Semiconductor device

Abstract

To improve reliability of a drive circuit.SOLUTION: A semiconductor device comprises a second high-resistance drain region 432 (or first high-resistance drain region 431) formed in an oxide semiconductor layer which overlaps a drain electrode layer 405b (and source electrode layer 405a). By forming the second high-resistance drain region 432, a structure where conductivity can be gradually varied from the drain electrode layer to the second high-resistance drain region 432 and a channel formation region. Accordingly, a structure can be achieved where locally high electric field is prevented from being applied because the high-resistance drain region serves as a buffer even when high electric field is applied between the gate electrode layer 401 and the drain electrode layer 405b when the drain electrode layer 405b is connected to wiring for supplying high power supply potential VDD to be operated thereby to achieve improved breakdown voltage of a transistor.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a semiconductor device including an oxide semiconductor and a manufacturing method thereof.

[0002] In this specification, a semiconductor device is a device that can function by utilizing semiconductor characteristics. This generally refers to electro-optical devices such as display devices, semiconductor circuits, and electronic devices. be. [Background technology]

[0003] Metal oxides having light transmitting properties are used in semiconductor devices. For example, indium oxide Conductive metal oxides such as indium tin oxide (ITO) (hereafter referred to as oxide conductors) are used in liquid crystal displays. It is used as a transparent electrode material required for display devices such as displays.

[0004] In addition, metal oxides that have light-transmitting properties are attracting attention as materials that exhibit semiconductor properties. For example, In-Ga-Zn-O oxides are required for display devices such as liquid crystal displays. It is expected that this technology will be applied to semiconductor materials that are used in thin film transistors (TFTs). It is expected that this technology will be applied to the channel layer of a FT (fiber-transistor-type thin-film transistor).

[0005] TFTs that use metal oxides with semiconducting properties (hereinafter referred to as oxide semiconductors) can be used at low temperatures. Therefore, it is possible to manufacture alumina, which is used in display devices, etc. There is growing expectation that this material will replace or surpass rufus silicon.

[0006] By constructing a TFT using a transparent oxide conductor and an oxide semiconductor, It is possible to fabricate a TFT having light-transmitting properties (see, for example, Non-Patent Document 1).

[0007] In addition, TFTs that use oxide semiconductors for the channel layer have high field effect mobility. The TFT can also be used to configure a driving circuit for a display device or the like (for example, (See Patent Document 2). [Prior art documents] [Non-patent literature]

[0008] [Non-Patent Document 1] Tetsuo Nozawa, "Transparent Circuits," Nikkei Electronics, August 27, 2007 (no. 959), pp. 39-52 [Non-Patent Document 2] T.Osada, and 8 others, SID '09 DIGEST, pp.184-187(2009) Summary of the Invention [Problem to be solved by the invention]

[0009] An object of one embodiment of the present invention is to reduce manufacturing costs of a semiconductor device.

[0010] An object of one embodiment of the present invention is to improve the aperture ratio of a semiconductor device.

[0011] An object of one embodiment of the present invention is to improve the resolution of an image displayed on a display portion of a semiconductor device. do.

[0012] An object of one embodiment of the present invention is to provide a semiconductor device capable of high-speed operation. [Means for solving the problem]

[0013] One embodiment of the present invention is a display device having a driver circuit portion and a display portion (also referred to as a pixel portion) over the same substrate. The driver circuit portion includes a source electrode (also called a source electrode layer) and a drain electrode (a drain electrode The metal layer is made of a metal, and the channel layer is made of an oxide semiconductor. A thin film transistor for a driving circuit and wiring for a driving circuit made of metal are included, The display unit includes a source electrode layer and a drain electrode layer made of an oxide conductor and a semiconductor A pixel thin film transistor having a layer made of an oxide semiconductor and a pixel having a layer made of an oxide conductor. The semiconductor device has a display portion wiring configured as above.

[0014] As a thin-film transistor for pixels and a thin-film transistor for driving circuits, A staggered thin film transistor is used. The pixel thin film transistor has a source electrode layer and a drain electrode layer. A bottom-gate type (inverted coplanar type, bottom contact type) with an oxide semiconductor layer overlapping the gate electrode layer The driver circuit thin-film transistor is an oxide thin-film transistor. A source electrode layer and a drain electrode layer overlapping the semiconductor layer, A bottom-gate type in which an oxide insulating film is provided in contact with an oxide semiconductor layer in a region between the oxide semiconductor layer and an electrode layer. (channel etch type) thin film transistor.

[0015] In addition, Non-Patent Document 1 does not disclose a specific process for manufacturing a TFT and other elements constituting a semiconductor device. The structure of the capacitors (for example, the capacitor elements) is not disclosed. There is also no description of fabricating a TFT having light-transmitting properties.

[0016] The semiconductor device according to one embodiment of the present invention includes a driver circuit having a TFT for a driver circuit on the same substrate. A display section having a path section and a pixel TFT is manufactured. Costs can be reduced.

[0017] In addition, in the semiconductor device of one embodiment of the present invention, a source electrode and a drain electrode are formed of an oxide A pixel TFT made of a conductor and having a semiconductor layer made of an oxide semiconductor. and a display wiring made of an oxide conductor. The region in which the pixel TFT and the display wiring are formed is used as the display region of the pixel portion. Therefore, the aperture ratio of the semiconductor device can be improved.

[0018] In addition, in the semiconductor device of one embodiment of the present invention, a source electrode and a drain electrode are formed of an oxide A pixel TFT made of a conductor and having a semiconductor layer made of an oxide semiconductor. and a display wiring made of an oxide conductor. Therefore, the pixel size can be designed without being limited by the size of the pixel TFT. Therefore, an image displayed on a display portion of the semiconductor device can be made higher in definition.

[0019] In the semiconductor device of one embodiment of the present invention, a source electrode and a drain electrode are formed of gold in a driver circuit portion. A TFT for a driving circuit, the TFT being made of a metal and the channel layer being made of an oxide semiconductor. and a driver circuit wiring made of metal. The driving circuit is composed of a TFT that exhibits high field effect mobility and low resistance wiring. Therefore, the semiconductor device can be a semiconductor device capable of high speed operation.

[0020] The oxide semiconductor used in this specification is InMO3(ZnO). m (m>0) A thin film is formed on the oxide semiconductor layer, and a thin film transistor is fabricated using the thin film as an oxide semiconductor layer. In addition, M is one or more metal elements selected from Ga, Fe, Ni, Mn, and Co. Indicates a metal element. For example, M can be Ga, Ga and Ni, or Ga and Ni. In some cases, the oxide semiconductor may contain the above-mentioned metal elements other than Ga, such as Fe. In addition to the metal elements contained as M, Fe, Ni and other transition metals are included as impurity elements. In the present specification, the term "In" refers to a transition metal oxide. MO3(ZnO) m In the oxide semiconductor layer with a structure represented by (m>0), M is Ga The oxide semiconductor with the structure containing In-Ga-Zn-O is called the In-Ga-Zn-O oxide semiconductor, and the thin film of the In-Ga-Zn-O oxide semiconductor is called the In-Ga-Zn-O oxide semiconductor. It is also called n-Ga-Zn-O type non-single crystal film.

[0021] In addition to the above, metal oxides that can be used for the oxide semiconductor layer include In-Sn-Zn-O In-Al-Zn-O, Sn-Ga-Zn-O, Al-Ga-Zn-O, Sn -Al-Zn-O series, In-Zn-O series, Sn-Zn-O series, Al-Zn-O series, In- Metal oxides of O, Sn-O, and Zn-O can be used. The oxide semiconductor layer made of such a material may contain silicon oxide.

[0022] In the manufacturing process of the semiconductor device, nitrogen or a rare gas (such as argon or helium) is used. The oxide semiconductor layer is subjected to heat treatment under an inert gas atmosphere or reduced pressure. The semiconductor layer is made oxygen-deficient to reduce resistance (i.e., N-type). - (e.g., acidification), then By forming an oxide insulating film in contact with the oxide semiconductor layer, the oxide semiconductor layer is It is preferable to make the silicon-rich state high resistance (i.e. I-type). It is possible to manufacture and provide a semiconductor device having a thin film transistor with good properties and high reliability. It becomes possible.

[0023] The above heat treatment is carried out under an inert gas atmosphere of nitrogen or rare gas (argon, helium, etc.). or heat treatment under reduced pressure at 350° C. or higher, preferably 400° C. or higher but lower than the strain point of the substrate. The oxide semiconductor layer is dehydrated or dehydrogenated by this heat treatment, and the oxide semiconductor Impurities containing hydrogen atoms, such as water, contained in the layer are reduced.

[0024] The heat treatment for dehydration or dehydrogenation is performed on the oxide semiconductor after dehydration or dehydrogenation. Even when the layer was measured by TDS up to 450°C, two peaks of water were observed, at least at 300°C. It is preferable to set the heat treatment conditions so that one peak that appears in the vicinity is not detected. For a thin film transistor using an oxide semiconductor layer that has been dehydrated or dehydrogenated under Even if the TDS measurement is performed up to 450°C, the water peak appears at least at around 300°C. Not detected.

[0025] The oxide semiconductor layer was cooled in the same furnace as that used for the dehydration or dehydrogenation by exposing it to the atmosphere. The oxide semiconductor layer is cooled so as not to be exposed to water or hydrogen, and Dehydration or dehydrogenation is performed to reduce the resistance of the I-type oxide semiconductor layer, i.e., to make it N-type (N - , N + After that, the oxide semiconductor layer is made high-resistance and made I-type again to fabricate a thin-film transistor. By forming a stator, the threshold voltage value of the thin film transistor can be made positive, so-called A normally-off switching element can be realized. The gate voltage of the thin-film transistor is 0V. It is desirable for the display device to have a channel formed with a positive threshold voltage as close as possible to In addition, if the threshold voltage of a thin-film transistor is negative, even if the gate voltage is 0V, Current flows between the source and drain electrodes, which is called a normally-on state. In active matrix display devices, the electrical characteristics of thin film transistors that make up the circuits The electrical characteristics of thin film transistors are important, and they affect the performance of the display device. Among the electrical characteristics, the threshold voltage (Vth) is important. If the threshold voltage is high or the threshold voltage is negative, the circuit cannot control it. It is difficult to obtain a high threshold voltage for thin-film transistors with a large absolute value of the threshold voltage. In this case, the switching function of the TFT cannot be achieved when the driving voltage is low. In the case of an n-channel thin-film transistor, the gate voltage is positive. A transistor in which a channel is formed and drain current begins to flow only when a voltage is applied. It is desirable to have transistors in which the channel does not form unless the driving voltage is high, and transistors in which the channel does not form unless the driving voltage is negative. A transistor in which a channel is formed and a drain current flows even in this state is a thin-film transistor used in circuits. It is not suitable as a transistor.

[0026] In addition, cooling after heating may be performed after changing the gas used for heating to a different gas. For example, the furnace can be used to purify the high-purity uranium dioxide without exposing it to the atmosphere in the same furnace where the dehydration or dehydrogenation was performed. Oxygen gas or N2O gas, ultra-dry air (dew point below -40℃, preferably below -60℃) Cooling can also be performed by filling the container with water (below).

[0027] The heat treatment for dehydration or dehydrogenation reduces impurities containing hydrogen atoms such as water in the film. After cooling, place in a moisture-free atmosphere (dew point below -40°C, preferably below -60°C). The electrical characteristics of thin film transistors are improved by using an oxide semiconductor film that has been slowly cooled (or cooled) at room temperature. This will also realize a thin-film transistor that is both easy to mass-produce and has high performance.

[0028] In this specification, under an inert gas atmosphere of nitrogen or rare gas (argon, helium, etc.), Alternatively, the heat treatment under reduced pressure is called a heat treatment for dehydration or dehydrogenation. The term "dehydrogenation" refers only to the process of desorption of hydrogen as H2 by this heat treatment. For convenience, this term is used to refer to the elimination of H, OH, etc. Let us assume that.

[0029] As described above, when heat treatment for dehydration or dehydrogenation is performed, the oxide semiconductor layer becomes oxygen-deficient and has low resistance, i.e., becomes N-type (N - Therefore, the resistance is reduced. By forming the drain electrode layer over the oxide semiconductor layer, the region overlapping with the drain electrode layer is made of oxide. It can be formed as a high resistivity drain region (also called HRD region) that is depleted of electrons. .

[0030] The carrier concentration of the high-resistance drain region is 1×10 17 / cm 3 Within the above range, At least the carrier concentration in the channel formation region (1×10 17 / cm 3 (less than 1000m) The carrier concentration in this specification is determined by Hall effect measurement at room temperature. Refers to the concentration value.

[0031] Thereafter, at least a part of the dehydrated or dehydrogenated oxide semiconductor layer is brought into an oxygen-excess state. By this, the resistance is increased, that is, the I-type is formed, and a channel formation region is formed. The treatment for making a part of the dehydrogenated oxide semiconductor layer into an oxygen-excess state can be carried out by the following method. The oxide insulating layer in contact with the dehydrated or dehydrogenated oxide semiconductor layer is The insulating film is formed by sputtering or is in contact with the dehydrated or dehydrogenated oxide semiconductor layer. In the above, an oxide insulating film is formed and then subjected to heat treatment or dehydration or dehydrogenation. An oxide insulating film is formed so as to be in contact with the oxide semiconductor layer, and then heat treatment is performed in an atmosphere containing oxygen. or an oxide insulating film is provided so as to be in contact with the dehydrated or dehydrogenated oxide semiconductor layer. After forming the film, the film is heated in an inert gas atmosphere and then cooled in an oxygen atmosphere. or after forming an oxide insulating film in contact with the dehydrated or dehydrogenated oxide semiconductor layer. Then, the mixture is heated in an inert gas atmosphere and then dried in ultra-dry air (dew point of -40°C or less, preferably - Cool the material at a temperature below 60°C.

[0032] In addition, at least a part of the dehydrated or dehydrogenated oxide semiconductor layer (gate electrode (gate By selectively creating an oxygen-excess state in the area (the area overlapping the electrode layer), the resistance is increased, i.e. This allows the formation of a channel formation region. For example, a metal electrode such as Ti is placed on a dehydrated or dehydrogenated oxide semiconductor layer. and forming a source electrode layer and a drain electrode layer that do not overlap the source electrode layer and the drain electrode layer. The exposed region can be selectively made into an oxygen-excessive state to form a channel formation region. When the oxygen-excess state is selectively created, a first high-resistance drain region overlapping the source electrode layer and A second high-resistance drain region overlapping the drain electrode layer is formed, and the first high-resistance drain The region between the drain region and the second high-resistance drain region is the channel formation region. A panel formation region is formed in a self-aligned manner between the source electrode layer and the drain electrode layer.

[0033] This allows the fabrication of a semiconductor device having thin film transistors with good electrical characteristics and high reliability. It will be possible to provide such information.

[0034] Note that a high-resistance drain electrode layer (and a source electrode layer) is formed in the oxide semiconductor layer overlapping the drain electrode layer (and the source electrode layer). By forming the drain region, the reliability of the driving circuit can be improved. In the above, a high-resistance drain region is formed, so that the high-resistance drain region is separated from the drain electrode layer. It is possible to provide a structure in which the conductivity can be changed stepwise over the channel formation region. Therefore, the drain electrode layer is connected to a wiring that supplies a high power supply potential VDD. In this case, even if a high electric field is applied between the gate electrode layer and the drain electrode layer, a high resistance drain region is formed. This acts as a buffer to prevent localized high electric fields from being applied, improving the breakdown voltage of the transistor. It is possible.

[0035] In addition, a high resistance drain electrode layer (and a source electrode layer) is formed in the oxide semiconductor layer overlapping the drain electrode layer (and the source electrode layer). By forming a drain region, leakage in the channel formation region when forming a driver circuit is prevented. Specifically, the drain current can be reduced by forming a high-resistance drain region. The drain electrode layer and the source electrode layer are connected to each other as a leakage current path of the transistor. Drain electrode layer, high-resistance drain region on the drain electrode layer side, channel formation region, source electrode The high-resistance drain region on the side of the gate electrode is followed by the source electrode layer. The leakage current that flows from the drain electrode layer to the channel formation region when the transistor is off It is possible to concentrate the high-resistance gate insulating layer near the interface between the channel forming region and the gate insulating layer. The back channel portion (a part of the surface of the channel formation region that is away from the gate electrode layer) This can reduce the leakage current in the

[0036] A first high-resistance drain region overlapping the source electrode layer and a second high-resistance drain region overlapping the drain electrode layer. By forming the high-resistance drain region so that it overlaps with the gate electrode layer, The electric field intensity in the vicinity of the end portion of the drain electrode layer can be reduced.

[0037] Therefore, one embodiment of the configuration of the present invention disclosed in this specification is a gate electrode layer on an insulating surface. a gate insulating layer on the gate electrode layer; an oxide semiconductor layer on the gate insulating layer; A source electrode layer and a drain electrode layer are formed on the insulating layer, a gate insulating layer, an oxide semiconductor layer, a source electrode layer, and a drain electrode layer. a protective insulating layer over the drain electrode layer and in contact with a part of the oxide semiconductor layer, The compound semiconductor layer includes at least a channel forming region, a source electrode layer, or a drain electrode layer. and a high-resistance drain region overlapping any one of the layers.

[0038] In the above configuration, the carrier concentration of the high-resistance drain region is 1×10 17 / cm 3 The above The carrier concentration of the channel formation region is within the range of 1×10 17 / cm 3 less than ) and the high resistance drain region is formed in a self-aligned manner. This determines the length of the channel formation region (channel length L).

[0039] In one embodiment of the configuration of the present invention disclosed in this specification, a first thin film transistor is provided on the same substrate. a pixel portion having a first thin film transistor and a driver circuit having a second thin film transistor, The transistor has a gate electrode layer on a substrate, a gate insulating layer on the gate electrode layer, and a gate insulating layer on the gate electrode layer. a source electrode layer and a drain electrode layer on the gate insulating layer; An oxide semiconductor layer overlapping the electrode layer, a protective insulating layer in contact with the oxide semiconductor layer, and a a pixel electrode layer on the first thin film transistor; a gate electrode layer of the first thin film transistor; a gate insulating layer; The semiconductor layer, the source electrode layer, the drain electrode layer, the protective insulating layer, and the pixel electrode layer have light-transmitting properties. The source electrode layer and the drain electrode layer of the second thin film transistor are The source electrode layer and the drain electrode layer of the first thin film transistor are made of different materials. The semiconductor device is made of a conductive material having a lower resistance than the electrode layer and the drain electrode layer.

[0040] In the above-mentioned configuration, a capacitance section is further provided on the same substrate, and the capacitance section includes a capacitance wiring and The capacitor electrode overlaps with the capacitor wiring, and the capacitor wiring and the capacitor electrode are transparent. The wiring overlaps the capacitance electrode via an insulating layer, which acts as a dielectric, for example, a gate insulating layer, and the gate insulating layer is formed. Since the edge layer also has light-transmitting properties, the capacitance portion also has light-transmitting properties.

[0041] In the above structure, the oxide semiconductor layer of the second thin film transistor is a channel forming region having a thickness smaller than that of a region overlapping with the drain electrode layer, A conductive layer is provided on the semiconductor device via a protective insulating layer.

[0042] In the above structure, the source electrode layer and the drain electrode layer of the second thin film transistor are A film mainly composed of an element selected from the group consisting of Al, Cr, Cu, Ta, Ti, Mo, and W, or is made up of a laminated film that combines these.

[0043] In the above structure, the source electrode layer, the drain electrode layer, and The pixel electrode layer is made of indium oxide, mixed oxide of indium and tin, or mixed oxide of indium and zinc. The gate electrode layer of the first thin film transistor, the source electrode layer, The electrode layer, drain electrode layer, pixel electrode layer, or other electrode layers included in the pixel portion, and other The thickness of the wiring layer is 30 nm or more and 200 nm or less, and the wiring layer is transparent to visible light. In this case, a film thickness that is transparent or semi-transparent may be selected.

[0044] In addition, one embodiment of the configuration of the present invention disclosed in this specification is a first A gate electrode layer and a second gate electrode layer are formed, and the first gate electrode layer and the second gate electrode layer are A gate insulating layer is formed on the electrode layer, and a first solenoid is formed on the gate insulating layer so as to overlap the first gate electrode layer. a first source electrode layer and a first drain electrode layer on the gate insulating layer; A first oxide semiconductor layer overlapping a portion of the first source electrode layer and a portion of the first drain electrode layer. a second oxide semiconductor layer overlapping the first gate electrode layer; and The oxide semiconductor layer and the second oxide semiconductor layer are dehydrated or dehydrogenated, and after the dehydration or dehydrogenation, A second source electrode layer and a second drain electrode layer are formed on the second oxide semiconductor layer without exposing the second oxide semiconductor layer to air. A drain electrode layer is formed to prevent water, hydrogen, etc. from entering the first oxide semiconductor layer and the second oxide semiconductor layer. The second oxide semiconductor layer is formed on a part of a top surface thereof, a side surface thereof, and a first oxide semiconductor layer. forming an oxide insulating layer in contact with an upper surface of the first oxide semiconductor layer; a pixel electrode layer electrically connected to the second oxide layer or the first source electrode layer; The present invention relates to a method for manufacturing a semiconductor device, which includes forming a conductive layer overlapping a compound semiconductor layer.

[0045] In the above structure, the second source electrode layer and the second drain electrode layer are made of Al, A film mainly composed of an element selected from Cr, Cu, Ta, Ti, Mo, and W, or The first source electrode layer and the first drain electrode layer are laminated films. The electrode layer and the pixel electrode layer are made of indium oxide, an indium oxide tin oxide alloy, or indium oxide. The zinc oxide alloy is zinc oxide or zinc oxide.

[0046] In this specification, the term "continuous processing" refers to a process that includes a first processing step of performing a heat treatment, a second processing step of performing a film formation by a sputtering method, or the like. During the series of processes up to the second processing step, the substrate to be processed is not exposed to a contaminated atmosphere such as air. To prevent this, always keep the equipment in a vacuum or in an inert gas atmosphere (nitrogen or rare gas). It means that the material is placed in a controlled atmosphere. It is possible to perform processing such as film formation while preventing re-adhesion of water and the like onto the substrate to be processed.

[0047] To carry out a series of processes from the first processing step to the second processing step in the same chamber is considered to be within the scope of continuous processing in this specification.

[0048] In addition, a series of processes from the first process to the second process are carried out in different chambers. In this case, after the first processing step is completed, the substrate is transported between chambers without being exposed to the atmosphere. In this specification, the term "sequential treatment" also includes a case where a first treatment is performed after the first treatment.

[0049] Between the first and second processing steps, a substrate transfer step, an alignment step, and a slow cooling step are performed. or a step of heating or cooling the substrate to a temperature required for the second step. However, such a process is considered to be within the scope of the continuous process in this specification.

[0050] However, the first step involves processes that use liquids, such as cleaning, wet etching, and resist formation. If the first processing step is between the second processing step, it does not fall within the scope of continuous processing as used herein. Let's say that's not the case.

[0051] The ordinal numbers such as 1st and 2nd are used for convenience and do not indicate the order of steps or stacking. In addition, the specific names used in this specification are not intended to identify the invention. This does not indicate the

[0052] In addition to liquid crystal display devices, display devices having a driving circuit include light-emitting devices using light-emitting elements. display devices, and display devices also called electronic paper using electrophoretic display elements. .

[0053] The liquid crystal display device is not particularly limited, and may be a TN liquid crystal, an IPS liquid crystal, an OCB liquid crystal, an STN liquid crystal, or the like. crystal, VA liquid crystal, ECB type liquid crystal, GH liquid crystal, polymer dispersed liquid crystal, discotic liquid crystal, etc. Among them, a normally black type liquid crystal panel, for example, a vertical alignment ( It is preferable to use a liquid crystal display device of a transmission type adopting a vertical alignment (VA) mode. There are several examples of this, such as MVA (Multi-Domain Verification). tical Alignment) mode, PVA(Patterned Vertic) mode Alignment mode, ASV mode, etc. can be used. The pixel is divided into multiple subpixels, and the opposing substrate is located at the center of each subpixel. By providing a convex portion in a certain area, one pixel is made into a multi-domain pixel. By providing a convex portion on the opposing substrate located at the center of each subpixel, one pixel is divided into alignment regions. The driving method that divides the display into multiple domains to achieve a wide viewing angle is called sub-pixel driving. The convex portions may be provided on either or both of the opposing substrate and the element substrate, and may be arranged radially. It aligns the liquid crystal molecules and improves the alignment control force.

[0054] In addition, the top surface of the liquid crystal driving electrode, i.e., the pixel electrode, is shaped like a comb or zigzag to reduce the voltage. The directions may be diversified. Also, one pixel may be made into a multi-domain by using optical alignment. Good too.

[0055] In addition, since thin-film transistors are easily damaged by static electricity, etc., For the line, a protection circuit for protecting the thin film transistor in the pixel area can be provided on the same substrate. The protection circuit is preferably configured using a nonlinear element using an oxide semiconductor. stomach.

[0056] In a light-emitting display device using a light-emitting element, a pixel portion has a plurality of thin film transistors. In the elemental portion, the gate electrode of a thin film transistor and the source wiring of another transistor, The light emitting device has a portion for connecting a drain wiring. In the driving circuit, the gate electrode of the thin film transistor and the source The semiconductor device has a portion for connecting a wiring or a drain wiring. Effect of the Invention

[0057] In a pixel portion of a display device according to one embodiment of the present invention, a light-transmitting In order to achieve high-definition images, the number of scanning lines is increased. Even if the element dimensions are miniaturized, a high aperture ratio can be achieved. Since the components are made of a transparent film, one pixel is divided into multiple subpixels to achieve a wide viewing angle. Even if the pixel is divided into sub-pixels, a high aperture ratio can be achieved.

[0058] In addition, a light-transmitting thin film transistor is provided in the pixel portion, and a different structure is provided on the same substrate as the pixel portion. A driving circuit having a thin film transistor of this structure is also provided, which can reduce manufacturing costs. [Brief description of the drawings]

[0059] [Figure 1] 1A to 1C are cross-sectional views showing a process of one embodiment of the present invention. [Diagram 2] 1A and 1B are cross-sectional views and a plan view illustrating one embodiment of the present invention. [Diagram 3] FIG. 1 is a cross-sectional view showing one embodiment of the present invention. [Figure 4] FIG. 2 is a plan view of a pixel illustrating one embodiment of the present invention. [Diagram 5] FIG. 1 is a cross-sectional view showing one embodiment of the present invention. [Figure 6] FIG. 1 is a cross-sectional view showing one embodiment of the present invention. [Figure 7] 1A to 1C are cross-sectional views showing a process of one embodiment of the present invention. [Figure 8] 1A and 1B are cross-sectional views and a plan view illustrating one embodiment of the present invention. [Figure 9] 1A to 1C are cross-sectional views showing a process of one embodiment of the present invention. [Figure 10] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 11]1A to 1C are diagrams illustrating a semiconductor device. [Figure 12] 1A and 1B are diagrams illustrating a pixel equivalent circuit of a semiconductor device. [Figure 13] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 14] FIG. 1 is a block diagram illustrating a semiconductor device. [Figure 15] 1A and 1B are circuit diagrams and a timing chart of a signal line driver circuit. [Figure 16] FIG. 1 is a circuit diagram showing a configuration of a shift register. [Figure 17] 4A and 4B are a timing chart and a circuit diagram illustrating the operation of a shift register. [Figure 18] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 19] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 20] FIG. 1 is an external view showing an example of an electronic book. [Figure 21] FIG. 1 is an external view showing an example of a television device and a digital photo frame. [Figure 22] FIG. 1 is an external view showing an example of a gaming machine. [Diagram 23] FIG. 1 is an external view showing an example of a portable computer and a mobile phone. [Figure 24] 1A to 1C are diagrams illustrating a semiconductor device. [Diagram 25] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 26] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 27] 1A to 1C are circuit diagrams of a semiconductor device. [Figure 28] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 29] 1A to 1C are diagrams illustrating a semiconductor device. [Diagram 30] 1A to 1C are diagrams illustrating a semiconductor device. [Diagram 31] 1A to 1C are circuit diagrams of a semiconductor device. [Diagram 32] 1A to 1C are diagrams illustrating a semiconductor device. [Diagram 33] 1A to 1C are diagrams illustrating a semiconductor device. [Diagram 34] 1A to 1C are diagrams illustrating a semiconductor device. [Diagram 35] 1A to 1C are diagrams illustrating a semiconductor device. [Diagram 36] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 37] 1A to 1C are diagrams illustrating a semiconductor device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0060] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the following description, and various modifications in form and details are possible by those skilled in the art. The present invention is not limited to the description of the following embodiments. It is not something that can be done.

[0061] (Embodiment 1) A semiconductor device and a method for manufacturing the semiconductor device will be described with reference to FIGS. 1 shows an example of a cross-sectional structure of two thin film transistors having different structures manufactured over the same substrate. The thin film transistor 470 shown in FIG. 2A is a bottom gate transistor called a channel etch type. The thin-film transistor 460 is a bottom-contact type (also called an inverted coplanar type). This is one of the bottom gate structures known as bottom gate structures.

[0062] FIG. 2B1 is a plan view of a channel-etched thin-film transistor 470 arranged in a driving circuit. 2A is a cross-sectional view taken along line C1-C2 in FIG. 2B1. (C) is a cross-sectional view taken along line C3-C4 in FIG. 2(B1).

[0063] The thin film transistor 470 arranged in the driving circuit is a channel-etch type thin film transistor. A gate electrode layer 401 and a first gate insulating layer 40 are formed on a substrate 400 having an insulating surface. 2a, the second gate insulating layer 402b, at least the channel forming region 434, the first high resistance An oxide semiconductor layer having a drain region 431 and a second high-resistance drain region 432. The thin film transistor 47 includes a source electrode layer 405a and a drain electrode layer 405b. An oxide insulating layer 407 is provided to cover the first insulating film 400 and to be in contact with a channel formation region 434 .

[0064] A first high-resistance drain region 431 is formed in a self-aligned manner in contact with the lower surface of the source electrode layer 405a. A second high-resistance drain region is formed in contact with the lower surface of the drain electrode layer 405b. The channel forming region 434 is formed in a self-aligned manner. 407, and the first high-resistance drain region 431 and the second high-resistance drain region 432 The first high-resistance drain region 431 and the second high-resistance drain region 432 are thinner than the first high-resistance drain region 431 and the second high-resistance drain region 432. The high-resistance drain region 432 has a higher resistance than the high-resistance drain region 432 (I-type region).

[0065] In addition, the thin film transistor 470 includes a source electrode layer 405a and The drain electrode layer 405b is preferably made of a metal material.

[0066] In addition, in a driving circuit formed on the same substrate as the pixel portion of a liquid crystal display device, an inverter circuit Thin-film transistors that compose logic gates such as gates, NAND circuits, NOR circuits, and latch circuits. Thin film transistors that compose analog circuits such as transistors, sense amplifiers, constant voltage generators, and VCOs. A transistor is a transistor in which only positive or only negative polarity is applied between the source and drain electrodes. Therefore, the width of the second high-resistance drain region 432, which is required to withstand a certain voltage, is set to be smaller than that of the first high-resistance drain region 432. The width of the first high-resistance drain region 431 may be designed to be wider than that of the first high-resistance drain region 432. The width of the first and second high-resistance drain regions 432 overlapping with the gate electrode layer may be increased.

[0067] In addition, the thin film transistor 470 arranged in the driving circuit is a thin film transistor with a single gate structure. Although the above description is based on a transistor, a multi-gate transistor having multiple channel formation regions may be used as necessary. A thin film transistor having the above structure can also be formed.

[0068] In addition, a conductive layer 406 is provided so as to overlap the channel forming region 434. By electrically connecting the gate electrode layer 401 and the conductive layer 402 to each other and setting them at the same potential, the gate electrode layer 401 and the conductive layer 4 A gate voltage can be applied from above and below the oxide semiconductor layer disposed between the gate electrodes 06. In addition, the gate electrode layer 401 and the conductive layer 406 are set to different potentials. For example, the conductive layer 406 is set to a fixed potential. When the voltage is set to GND or 0V, the electrical characteristics of the TFT, such as the threshold voltage, can be controlled. That is, the gate electrode layer 401 can function as a first gate electrode layer, and the conductive The layer 406 functions as a second gate electrode layer to form a four-terminal thin film transistor 470. The semiconductor device can be used as a thin film transistor.

[0069] In addition, a protective insulating layer 408 and a planarizing insulating layer 409 are provided between the conductive layer 406 and the oxide insulating layer 407. 09 and stacked together.

[0070] The protective insulating layer 408 is formed by insulating the first gate insulating layer 402 below the protective insulating layer 408. a or a base insulating film. H - In particular, the protective insulating layer 40 It is effective to use a silicon nitride film as the first gate insulating layer 402a in contact with the gate insulating film 8 or the insulating film serving as the base. It is effective.

[0071] FIG. 2B2 shows a bottom-contact type thin film transistor 460 disposed in a pixel. 2(B2) is a cross-sectional view taken along line D1-D2 in FIG. FIG. 2C is a cross-sectional view taken along line D3-D4 in FIG. 2B2.

[0072] The thin film transistor 460 disposed in the pixel is a bottom contact type thin film transistor. A gate electrode layer 451, a first gate insulating layer 402, and a second gate insulating layer 403 are formed on a substrate 400 having an insulating surface. a, the second gate insulating layer 402b, the oxide semiconductor layer 454 including a channel formation region, The thin film transistor 460 includes a source electrode layer 455a and a drain electrode layer 455b. an oxide insulating layer 407 which covers the oxide semiconductor layer 454 and is in contact with a top surface and a side surface of the oxide semiconductor layer 454 is provided. There are.

[0073] However, liquid crystal display devices are driven by alternating current to prevent deterioration of the liquid crystal. By this operation, the polarity of the signal potential applied to the pixel electrode layer is changed to positive or negative at regular intervals. The TFT connected to the pixel electrode layer has a pair of electrodes that alternate between the source electrode layer and the drain electrode layer. In this specification, for convenience, one electrode of the thin film transistor of the pixel is The first electrode is called the source electrode layer and the other electrode is called the drain electrode layer. In this case, one electrode alternately functions as a source electrode layer and a drain electrode layer. In order to reduce the current, the width of the gate electrode layer of the thin film transistor 460 arranged in the pixel is driven The width of the gate electrode layer of the thin film transistor 470 in the circuit may be narrower than that of the gate electrode layer of the thin film transistor 470 in the circuit. In order to reduce the current, the gate electrode layer of the thin film transistor 460 arranged in the pixel is The insulating layer may be designed so as not to overlap with the electrode layer or the drain electrode layer.

[0074] In addition, the thin film transistor 460 disposed in the pixel is a thin film transistor having a single gate structure. However, if necessary, a multi-gate structure having a plurality of channel forming regions may be used. A thin film transistor having the above structure can also be formed.

[0075] In addition, the oxide semiconductor layer 454 is formed by removing impurities such as water after the oxide semiconductor film is formed. Heat treatment (dehydration or dehydrogenation) is performed to reduce the amount of hydrogen. After performing heat treatment for dehydrogenation or dehydrogenation and slow cooling, Reducing the carrier concentration in the oxide semiconductor layer by forming a thin film or the like is effective in thin-film transistors. This leads to improved electrical characteristics and reliability of the capacitor 460.

[0076] Note that the oxide semiconductor layer 454 is a gate insulating layer between the source electrode layer 455a and the drain electrode layer 455b. The oxide semiconductor layer 454 is formed above and partially overlaps the gate electrode layer 451. and overlap with each other via a first gate insulating layer 402a and a second gate insulating layer 402b. The channel formation region of the thin film transistor 460 arranged in the pixel is the oxide semiconductor layer 454 Among them, the side surface of the source electrode layer 455a and the drain electrode layer 455b facing the side surface The region sandwiched between the side surface and the second gate insulating layer 402b, i.e., the region in contact with the second gate insulating layer 402b and the gate electrode layer 4 This is the area that overlaps with 51.

[0077] In addition, the thin film transistor 460 is a light-transmitting thin film transistor having a high aperture ratio. In order to realize a display device having a transparent insulating film, the source electrode layer 455a and the drain electrode layer 455b are A conductive film having optical properties is used.

[0078] In addition, a gate electrode layer 451 of the thin film transistor 460 is also formed using a light-transmitting conductive film.

[0079] In addition, the pixel in which the thin film transistor 460 is disposed is provided with a pixel electrode layer 456 or other The electrode layer (such as the capacitance electrode layer) and other wiring layers (such as the capacitance wiring layer) are transparent to visible light. A display device having a high aperture ratio is realized by using a conductive film having optical properties. The insulating layer 402a, the second gate insulating layer 402b, and the oxide insulating layer 407 are also transparent to visible light. It is preferable to use a film having optical properties.

[0080] In this specification, a film that is transparent to visible light has a visible light transmittance of 75 to 100 %, and if the film is conductive, it is also called a transparent conductive film. An electrode layer, a source electrode layer, a drain electrode layer, a pixel electrode layer, or other electrode layers, etc. As the metal oxide applied to the wiring layer, a conductive film that is semitransparent to visible light may be used. Translucent to visible light means that the visible light transmittance is 50 to 75%.

[0081] Hereinafter, referring to FIG. 1(A) to FIG. 1(F) and FIG. 2(B), a thin film transistor 4 The manufacturing process of the thin film transistor 70 and the thin film transistor 460 will be described.

[0082] First, a light-transmitting conductive film is formed on a substrate 400 having an insulating surface, and then a first photo Gate electrode layers 401 and 451 are formed by a lithography process. The first photolithography process is performed using the same material having the same light-transmitting properties as the first electrode layers 401 and 451. In addition, when capacitance is required not only for the pixel section but also for the drive circuit, A capacitance wiring layer is also formed on the driving circuit. The resist mask is formed by the inkjet method. If the resist mask is formed by the inkjet method, a photomask is not required. This reduces manufacturing costs.

[0083] There is no significant limitation on the substrate that can be used for the substrate 400 having an insulating surface. In any case, it is necessary for the insulating surface to have sufficient heat resistance to withstand subsequent heat treatment. The substrate 400 is made of glass such as barium borosilicate glass or aluminoborosilicate glass. A substrate can be used.

[0084] In addition, the above-mentioned substrate 400 has a distortion point of 730°C or higher when the temperature of the subsequent heat treatment is high. The substrate 400 may be made of, for example, aluminosilicate glass. Glass materials such as quartz, aluminoborosilicate glass, and barium borosilicate glass are used. In addition, by containing more barium oxide (BaO) than boron oxide, Therefore, glass substrates containing more BaO than B2O3 are used. It is preferable to use:

[0085] Instead of the substrate 400, an insulating substrate such as a ceramic substrate, a quartz substrate, or a sapphire substrate may be used. A substrate made of an insulating material may be used. Alternatively, crystallized glass or the like may be used.

[0086] In addition, an insulating film serving as a base film may be provided between the substrate 400 and the gate electrode layers 401 and 451. The undercoat film has a function of preventing the diffusion of impurity elements from the substrate 400. A stack of one or more films selected from a silicon oxide film, a silicon nitride oxide film, and a silicon oxynitride film. It can be formed in a layer structure.

[0087] The gate electrode layers 401 and 451 are made of a conductive material that is transparent to visible light, for example. In-Sn-Zn-O system, In-Al-Zn-O system, Sn-Ga-Zn-O system, Al-G a-Zn-O series, Sn-Al-Zn-O series, In-Zn-O series, Sn-Zn-O series, Al -Zn-O, In-O, Sn-O, and Zn-O metal oxides can be used. The thickness of the gate electrode layer 401 is appropriately selected within the range of 50 nm to 300 nm. The metal oxide film formation method used for 51 is the sputtering method or vacuum deposition method (electron beam deposition method, etc.) ) or arc discharge ion plating or spraying. Also, sputtering is used. When using a SiO2 target, the film is formed using a target containing 2% by weight or more and 10% by weight or less of SiO2. SiO x (X>0) and execute it in a later step. It is preferable to suppress crystallization during the heat treatment for dehydration or dehydrogenation. I wish.

[0088] Next, a gate insulating layer is formed on the gate electrode layers 401 and 451 .

[0089] The gate insulating layer is a silicon oxide layer, a nitride layer, etc., formed by plasma CVD or sputtering. The silicon layer, the silicon oxynitride layer, or the silicon nitride oxide layer can be formed as a single layer or a stacked layer. For example, a film is formed by plasma CVD using SiH4, oxygen, and nitrogen as the deposition gas. A silicon nitride layer may be formed.

[0090] In this embodiment, a first gate insulating layer 402a having a thickness of 50 nm or more and 200 nm or less, A second gate insulating layer 402b having a thickness of 50 nm to 300 nm is a stacked gate insulating layer. The first gate insulating layer 402a is a silicon nitride film or a nitride oxide film having a thickness of 100 nm. A silicon film is used as the second gate insulating layer 402b. A silicon oxide film having a thickness of 100 nm is used as the second gate insulating layer 402b. A bare membrane is used.

[0091] Next, a light-transmitting conductive film is formed over the second gate insulating layer 402b, and then a second A source electrode layer 455a and a drain electrode layer 455b are formed by a photolithography process. The conductive film having light-transmitting properties is formed by sputtering or vacuum deposition. The method uses a deposition method (such as electron beam deposition), an arc discharge ion plating method, and a spray method. The conductive film is made of a conductive material that is transparent to visible light, such as In-S n-Zn-O system, In-Al-Zn-O system, Sn-Ga-Zn-O system, Al-Ga-Zn -O series, Sn-Al-Zn-O series, In-Zn-O series, Sn-Zn-O series, Al-Zn- Metal oxides of O, In-O, Sn-O, and Zn-O can be used. The thickness is appropriately selected within the range of 50 nm to 300 nm. In addition, when using a sputtering method, The film is formed using a target containing 2% to 10% by weight of SiO2, and has translucency. The conductive film is coated with SiO, which inhibits crystallization. x (X>0) is included to facilitate the dehydration or It is preferable to suppress crystallization during the heat treatment for dehydrogenation.

[0092] Note that a resist pattern for forming the source electrode layer 455a and the drain electrode layer 455b was used. The resist mask may be formed by an ink-jet method. This eliminates the need for a photomask, thereby reducing manufacturing costs.

[0093] Next, the second gate insulating layer 402b, the source electrode layer 455a, and the drain electrode layer 45 An oxide semiconductor film having a thickness of 2 nm to 200 nm is formed on the oxide semiconductor film. Even if heat treatment for dehydration or dehydrogenation is performed after the formation of the oxide semiconductor layer, the oxide semiconductor layer does not become amorphous. In order to achieve a desired state, the thickness of the oxide semiconductor film is preferably as thin as 50 nm or less. By making the oxide semiconductor layer thin, crystallization can be prevented when heat treatment is performed after the oxide semiconductor layer is formed. It can be suppressed.

[0094] Note that before the oxide semiconductor film is formed by a sputtering method, argon gas is introduced to the plasma The reverse sputtering is performed to generate a gallium oxide, and the gallium oxide adhering to the surface of the second gate insulating layer 402b is removed. It is preferable to remove aluminum by reverse sputtering without applying voltage to the target side. In a nitrogen atmosphere, a voltage is applied to the substrate side using an RF power source to form plasma near the substrate. This is a method for modifying the surface. Note that nitrogen, helium, oxygen, etc. can be used instead of argon atmosphere. It may be used.

[0095] The oxide semiconductor film is an In-Ga-Zn-O non-single crystal film, an In-Sn-Zn-O film, or an In -Al-Zn-O system, Sn-Ga-Zn-O system, Al-Ga-Zn-O system, Sn-Al- Zn-O series, In-Zn-O series, Sn-Zn-O series, Al-Zn-O series, In-O series, S In this embodiment, an In-Ga-Zn The film is formed by sputtering using a -O-based oxide semiconductor target. , in a rare gas (typically argon) atmosphere, in an oxygen atmosphere, or in a rare gas (typically argon) atmosphere. The deposition can be carried out under an atmosphere of SiO2 and oxygen. The oxide semiconductor film was formed by using a target containing 2% by weight or more and 10% by weight or less. SiO inhibits crystallization x (X>0) is included for the dehydration or dehydrogenation in the subsequent process. It is preferable to suppress crystallization during the heat treatment for the purpose of the above.

[0096] Next, the oxide semiconductor film is formed into an island-shaped oxide semiconductor layer by a third photolithography process. Note that an oxide semiconductor layer overlapping the source electrode layer 455a and the drain electrode layer 455b is In order to obtain a conductor layer, the source electrode layer 455a and The materials and etching conditions are adjusted so that the drain electrode layer 455b and the drain electrode layer 455c are not removed. In addition, a resist mask for forming an island-shaped oxide semiconductor layer is formed by ink jet printing. If the resist mask is formed by the ink-jet method, the photomask Since no additional heat is used, the manufacturing cost can be reduced.

[0097] Next, the oxide semiconductor layer is dehydrated or dehydrogenated. The temperature of the heat treatment in step 1 is 350° C. or higher and lower than the distortion point of the substrate, preferably 400° C. or higher and The substrate is introduced into an electric furnace, which is a type of heat treatment device, and the temperature is set to be below the distortion point of the substrate. After the oxide semiconductor layer was subjected to heat treatment in a nitrogen atmosphere, the substrate was exposed to the air. By preventing the oxide semiconductor layers 403 and 404 from being mixed with water or hydrogen again, In this embodiment, the oxide semiconductor layer is dehydrated or dehydrated. The same furnace is used to heat the material from the temperature T at which oxidation takes place to a temperature that is sufficient to prevent water from entering again. In general, the temperature is gradually cooled in a nitrogen atmosphere until it drops by 100°C below the heating temperature T. The dehydrogenation is not limited to a nitrogen atmosphere, but may be performed in a rare gas atmosphere such as helium, neon, or argon. The dehydration or dehydrogenation may be carried out under air or reduced pressure.

[0098] In the first heat treatment, nitrogen or a rare gas such as helium, neon, or argon is used. It is preferable that the nitrogen gas introduced into the heat treatment device does not contain water, hydrogen, etc. Or the purity of rare gases such as helium, neon, and argon must be 6N (99.9999%) or higher. Preferably, the concentration of impurities is 7N (99.99999%) or more (i.e., the impurity concentration is 1 ppm or less, It is preferable to keep the concentration of the ion exchange resin at 0.1 ppm or less.

[0099] Depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, the oxide semiconductor layer may be crystallized and microcrystalline. In some cases, the film may be a crystalline or polycrystalline film.

[0100] The first heat treatment of the oxide semiconductor layer is performed before the oxide semiconductor layer is processed into an island-shaped oxide semiconductor layer. In that case, after the first heat treatment, the substrate is taken out of the heat treatment device and A photolithography process is carried out.

[0101] In addition, before the formation of the oxide semiconductor film, an inert gas atmosphere (nitrogen, helium, neon, Heat treatment (400℃ or higher) in an oxygen atmosphere or reduced pressure (argon, etc.) 100 ℃) to remove impurities such as hydrogen and water contained in the gate insulating layer.

[0102] Next, a metal conductive film is formed on the second gate insulating layer 402b, and then a fourth photolithography is performed. A resist mask 436 is formed by a lithography process, and selective etching is performed to form a metal electrode. The pole layer 435 is formed (see FIG. 1(C)). The material of the metal conductive film is Al, Cr, C An element selected from U, Ta, Ti, Mo, and W, or an alloy containing the above elements; There are alloys that combine the above elements.

[0103] The metal conductive film may be a titanium layer, an aluminum layer on the titanium layer, and a titanium layer on the aluminum layer. A laminated three-layer structure, or an aluminum layer on a molybdenum layer and the aluminum It is preferable to form a three-layer laminate structure in which a molybdenum layer is laminated on a metal conductive film. The insulating film may have a single layer structure, a two-layer structure, or a laminated structure of four or more layers.

[0104] Note that the oxide semiconductor layer 453 and the source electrode layer 455a were formed in the fourth photolithography process. In order to selectively remove the metal conductive film overlapping the drain electrode layer 455b, During the etching, the oxide semiconductor layer 453, the source electrode layer 455a, and the drain electrode The materials and etching conditions are appropriately adjusted so that the layer 455b is not removed. In addition, a resist mask 436 for forming a metal electrode layer 435 is formed by an inkjet method. If the resist mask 436 is formed by an ink-jet method, a photomask may be used. This reduces the manufacturing cost.

[0105] Next, the resist mask 436 is removed, and the resist is removed by a fifth photolithography process. A mask 437 is formed and selectively etched to remove the source electrode layer 405a and the drain electrode layer 405b. A second electrode layer 405b is formed (see FIG. 1(D)). In the example, the oxide semiconductor layer 403 is only partially etched, and a groove (depression) is formed. This becomes a semiconductor layer 433. In addition, a resist for forming a groove (a depression) in the oxide semiconductor layer is The mask 437 may be formed by an ink-jet method. When the film is formed by the injection method, no photomask is used, and therefore the manufacturing cost can be reduced.

[0106] Next, the resist mask 437 is removed, and a thin film is formed in contact with the top surface and the side surface of the oxide semiconductor layer 453. The oxide insulating layer 407 which serves as a protective insulating film in contact with the groove (depression) of the oxide semiconductor layer 433 is formed. Complete.

[0107] The oxide insulating layer 407 has a thickness of at least 1 nm and is formed by an oxide method such as a sputtering method. The insulating layer 407 can be formed by using an appropriate method that does not allow impurities such as water and hydrogen to be mixed in. In this embodiment, a silicon oxide film having a thickness of 300 nm is used as the oxide insulating layer 407. The substrate temperature during film formation should be between room temperature and 300°C. In this embodiment, the temperature is set to 100° C. Gas (typically argon) atmosphere, oxygen atmosphere, or rare gas (typically argon) atmosphere The target can be a silicon oxide target. A get or silicon target can be used. For example, a silicon target can be used to Silicon oxide can be formed by sputtering in an oxygen and nitrogen atmosphere. An oxide insulating layer formed in contact with an oxide semiconductor layer whose resistance has been reduced by hydration or dehydrogenation 407 is water, hydrogen ions, and OH -It does not contain impurities containing hydrogen atoms such as An inorganic insulating film is used to block external penetration. Typical examples are silicon oxide and nitride films. A silicon oxide film, an aluminum oxide film, an aluminum oxynitride film, or the like is used.

[0108] Next, a second heat treatment (preferably a second heat treatment) is performed under an inert gas atmosphere or an oxygen gas atmosphere. 00°C or higher and 400°C or lower, for example, 250°C or higher and 350°C or lower (see Figure 1(E)). For example, the second heat treatment is performed at 250° C. for 1 hour in a nitrogen atmosphere. When the oxide semiconductor layer 453 is heated, the grooves of the oxide semiconductor layer 433 and the top and side surfaces of the oxide semiconductor layer 453 are insulated from the oxide. It is heated in contact with edge layer 407 .

[0109] Through the above steps, the oxide semiconductor film after deposition is dehydrated or dehydrogenated. After the heat treatment for reducing the resistance, a part of the oxide semiconductor film is selectively As a result, the channel formation region 434 overlapping with the gate electrode layer 401 has an I-type structure. A first high-resistance drain region 431 overlapping the source electrode layer 405a and a drain electrode A second high-resistance drain region 432 overlapping the layer 405b is formed in a self-aligned manner. The oxide semiconductor layer 453 is entirely i-type, and the oxide semiconductor layer 4 The number is 54.

[0110] Note that the oxide semiconductor layer overlapping with the drain electrode layer 405b (and the source electrode layer 405a) In the above, the second high-resistance drain region 432 (or the first high-resistance drain region 431) is By forming the second insulating film, the reliability of the driving circuit can be improved. By forming the high-resistance drain region 432, a second high-resistance drain is formed from the drain electrode layer. The structure is such that the conductivity can be changed stepwise from the region 432 to the channel formation region. Therefore, the drain electrode layer 405b can be connected to a wiring for supplying a high power supply potential VDD. When the gate electrode layer 401 and the drain electrode layer 405b are connected to each other for operation, a high voltage is applied between the gate electrode layer 401 and the drain electrode layer 405b. Even if a high electric field is applied, the high-resistance drain region acts as a buffer to prevent a local high electric field from being applied. This allows the transistor to have an improved breakdown voltage.

[0111] In addition, the oxide semiconductor layer overlapping with the drain electrode layer 405b (and the source electrode layer 405a) In the above, the second high-resistance drain region 432 (or the first high-resistance drain region 431) is By forming the insulating layer 434, it is possible to reduce the leakage current in the channel forming region 434. .

[0112] Next, a protective insulating layer 408 is formed over the oxide insulating layer 407 (see FIG. 1F). In this embodiment, the silicon nitride film is formed by RF sputtering. Since the protective insulating layer 408 has good adhesion, it is preferable as a method for forming the protective insulating layer 408. , hydrogen ions, OH - It does not contain impurities containing hydrogen atoms such as The inorganic insulating film used is a silicon nitride film, an aluminum nitride film, a silicon oxide nitride film, and a silicon nitride film. Of course, the protective insulating layer 408 is a light-transmitting insulating film. This is the veneer.

[0113] The protective insulating layer 408 is formed by insulating the first gate insulating layer 402 below the protective insulating layer 408. a) or in contact with the insulating film serving as the base. , hydrogen ions, OH -It blocks the intrusion of impurities containing hydrogen atoms such as In particular, the first gate insulating layer 402a in contact with the protective insulating layer 408 or the insulating film serving as the base It is effective to use a silicon nitride film. By providing such a silicon nitride film, the reliability of the display device is improved.

[0114] Next, a planarization insulating layer 409 is formed over the protective insulating layer 408. Examples of resins include polyimide, acrylic resin, benzocyclobutene resin, polyamide, and epoxy resin. In addition to the above organic materials, low dielectric constant organic materials such as cellulose, etc. can be used. Dielectric constant material (low-k material), siloxane resin, PSG (phosphorus glass), BPSG (phosphorus In addition, the insulating film formed from these materials can be used in multiple layers. The planarization insulating layer 409 may be formed by stacking several layers.

[0115] Siloxane-based resin is a type of Si-OS formed using siloxane-based materials as starting materials. The siloxane resin corresponds to a resin containing an i bond. In addition, the organic group may have a fluoro group.

[0116] The method for forming the planarization insulating layer 409 is not particularly limited. Depending on the material, it may be formed by sputtering, SO G method, spin coating, dip, spray coating, droplet ejection method (inkjet method, screen Printing methods such as inkjet printing, offset printing, doctor knife, roll coater, curtain Tools such as a spool coater or a knife coater can be used.

[0117] Next, a sixth photolithography step is performed to form a resist mask, and a planarization insulating layer 4 09, the protective insulating layer 408 and the oxide insulating layer 407 are etched to form the drain electrode layer 4 A contact hole is formed that reaches the gate electrode 55b. Contact holes reaching the electrode layers 401 and 451 are also formed. A resist mask for forming a contact hole reaching b is formed by the inkjet method. If the resist mask is formed by the inkjet method, no photomask is required. This allows for reduced manufacturing costs.

[0118] Next, after removing the resist mask, a light-transmitting conductive film is formed. The conductive film material is indium oxide or a mixed oxide of indium and tin (ITO). The conductive film having a light-transmitting property is formed by using a sputtering method, a vacuum deposition method, or the like. As another material, nitrogen-doped Al-Zn-O-based non-single crystal film, i.e. Al-Zn-ON Zn-O non-single crystal film containing nitrogen, i.e. Zn-ON non-single crystal film or nitrogen-containing Sn-Zn-O-based non-single crystal film, i.e. Sn-Zn-ON-based non-single crystal film The composition ratio (atomic %) of zinc in the Al-Zn-ON non-single crystal film is as follows: The composition ratio (atomic %) of aluminum in the non-single crystal film is 47 atomic % or less, and is larger than that in the non-single crystal film. The composition ratio (atomic %) of aluminum in the crystalline film is the same as the composition ratio (atomic %) of nitrogen in the non-single crystalline film. Etching of such materials is carried out with solutions based on hydrochloric acid. ITO etching tends to leave residue, so we used an indium tin oxide (ITO) etching process to improve the etching processability. Mixed oxides of zinc and dium may also be used.

[0119] The composition ratio of the light-transmitting conductive film is expressed in atomic percent. (EPMA:Electron Probe X-ray MicroAnalyzer ) will be used for the evaluation.

[0120] Next, a seventh photolithography step is performed to form a resist mask and to form a Then, unnecessary portions are removed to form a pixel electrode layer 456 and a conductive layer 406 (see FIG. 2(A)). ).

[0121] Through the above steps, the thin film transistor 470 and the thin film transistor 471 are formed on the same substrate using seven masks. The film transistor 460 can be fabricated separately for the driver circuit or pixel portion. In addition, the first gate insulating layer 402a and the second gate insulating layer 402b are used as dielectrics to form a capacitance. The storage capacitor formed by the wiring layer and the capacitor electrode can also be formed on the same substrate. The pixel section is constructed by arranging transistors 460 and storage capacitors in a matrix corresponding to each pixel. A driver circuit having a thin film transistor 470 is arranged around the pixel portion. The present invention can be used as one of the substrates for manufacturing an active matrix type display device. For the sake of convenience, in this specification, such a substrate is called an active matrix substrate.

[0122] Note that the pixel electrode layer 456 is formed by removing the planarization insulating layer 409, the protective insulating layer 408, and the oxide insulating layer The capacitor is electrically connected to the capacitor electrode layer through a contact hole formed in 407. The drain electrode layer is formed of the same light-transmitting material and in the same process as the drain electrode layer 455b. This can be done.

[0123] The conductive layer 406 is provided so as to overlap with the channel formation region 434 of the oxide semiconductor layer. The bias-thermal stress test (BT) is used to check the reliability of thin-film transistors. In the test, the threshold voltage of the thin film transistor 470 before and after the BT test was In addition, the conductive layer 406 has a potential equal to that of the gate electrode layer 401. It may be the same or different and may also function as the second gate electrode layer. The potential of the conductive layer 406 may be GND, 0 V, or may be in a floating state. .

[0124] In addition, a resist mask for forming the pixel electrode layer 456 is formed by an ink-jet method. If the resist mask is formed by the inkjet method, a photomask is not required. , manufacturing costs can be reduced.

[0125] (Embodiment 2) In this embodiment mode, the active matrix substrate shown in Embodiment 1 is used to An example of manufacturing a liquid crystal display device of a matrix type will be described.

[0126] An example of the cross-sectional structure of an active matrix substrate is shown in FIG. A part of the top view is shown, and the cross section taken along the dashed line A1-A2 in FIG. 4 corresponds to A1-A in FIG. 2, and the cross section taken along the dashed line B1-B2 in FIG. 4 corresponds to B1-B2 in FIG. 3(A). In the pixel layout shown in FIG. 4, the source layer overlapping the oxide semiconductor layer The upper surface shape of the electrode layer is U-shaped or C-shaped, which is different from that of the first embodiment. Not limited.

[0127] In the first embodiment, the thin film transistors of the driver circuit and the thin film transistors of the pixel section are formed on the same substrate. In the present embodiment, in addition to the thin film transistors, a storage capacitor, a gate The terminals of the gate and source lines are also shown in the figures. The manufacturing process can be the same as that shown in the first embodiment, and the number of photomasks can be reduced. In addition, the display area of ​​the pixel portion can be manufactured without increasing the number of steps. In the portion where the gate wiring, the source wiring, and the capacitance wiring layer are all made of a conductive material having light transmission properties. The film is used to achieve a high aperture ratio. The wiring layer uses metal wiring to reduce the wiring resistance.

[0128] In FIG. 3A, a thin film transistor 210 is a channel etched thin film transistor disposed in a driving circuit. The thin film transistor 227 is electrically connected to the pixel electrode layer 227. Reference numeral 20 denotes a bottom-contact type thin film transistor provided in a pixel portion.

[0129] In this embodiment, the thin film transistor 220 formed above the substrate 200 is The same structure as the thin film transistor 460 of the first embodiment is used.

[0130] A layer formed of the same material and process as the gate electrode layer of the thin film transistor 220. The capacitor wiring layer 230 is made of a first gate insulating layer 202a and a second gate insulating layer 202b, which are dielectrics. The insulating layer 202b overlaps with the capacitance electrode 231 to form a storage capacitor. The thin film transistor 220 has a source electrode layer or a drain electrode layer having the same light-transmitting property as the thin film transistor 220. Therefore, the thin film transistor 220 has a light-transmitting property. In addition, each storage capacitor is transparent, which improves the aperture ratio. can be done.

[0131] It is important for the storage capacitor to have light transmittance in order to improve the aperture ratio. In the following small LCD panels, the number of gate wirings is increased to improve the resolution of the displayed image. Even if the pixel size is reduced to achieve high resolution, a high aperture ratio can be achieved. By using a film having light transmitting properties as the constituent members of the thin film transistor 220 and the storage capacitor, To achieve a wide viewing angle, a high aperture ratio is achieved even when one pixel is divided into multiple sub-pixels. That is, even if a group of thin film transistors is arranged at high density, a large aperture ratio can be obtained. For example, two to four pixels can be arranged in one pixel, and a sufficient area can be secured for the display area. When the device has four sub-pixels and a storage capacitor, the thin film transistor is transparent. In addition, each storage capacitor is transparent, so that the aperture ratio can be improved. do.

[0132] The storage capacitor is provided below the pixel electrode layer 227, and the capacitor electrode 231 is disposed below the pixel electrode layer 227. 27.

[0133] In this embodiment, a storage capacitor is formed using a capacitor electrode 231 and a capacitor wiring layer 230. However, the structure for forming the storage capacitor is not particularly limited. For example, The pixel electrode layer is not provided with a gate wiring of an adjacent pixel, a planarizing insulating layer, a protective insulating layer, and A storage capacitor may be formed by overlapping the first gate insulating layer and the second gate insulating layer therebetween.

[0134] FIG. 4 shows a contact hole for electrically connecting the capacitance electrode 231 to the pixel electrode layer 227. The contact hole 224 is connected to the drain of the thin film transistor 220. The contact hole 225 is for electrically connecting the gate electrode layer and the pixel electrode layer 227. Therefore, the contact holes can be formed without increasing the number of steps. 224 can be formed.

[0135] In addition, the gate wiring, source wiring, and capacitance wiring layer are provided in multiple lines according to the pixel density. In the terminal section, a first terminal electrode having the same potential as the gate line, a source line a second terminal electrode having the same potential as the capacitance wiring layer, a third terminal electrode having the same potential as the capacitance wiring layer, etc. are arranged in a row. The number of each terminal electrode may be any number. The implementer should make the appropriate decision.

[0136] In the terminal portion, the first terminal electrode having the same potential as the gate line is formed of the same light-transmitting material as the pixel electrode layer 227. The first terminal electrode can be formed of a material having a good thermal conductivity. The contact hole is electrically connected to the gate wiring. The pin electrically connects the drain electrode layer of the thin film transistor 220 and the pixel electrode layer 227. The same photomask as that used for the contact holes for connecting the semiconductor substrate to the semiconductor substrate is used to form the planarizing insulating layer 204 and the protective insulating layer 205. The border layer 203, the oxide insulating layer 216, the second gate insulating layer 202b, and the first gate insulating layer 202c. Layer 202a is formed by selectively etching.

[0137] The gate electrode layer of the thin film transistor 210 disposed in the driving circuit is an oxide semiconductor layer Alternatively, the conductive layer 217 may be electrically connected to the conductive layer 217 provided above the conductive layer 217. , electrically connects the drain electrode layer of the thin film transistor 220 and the pixel electrode layer 227 The same photomask as that for the contact holes for the planarization insulating layer 204 and the protective insulating layer 2 03, the oxide insulating layer 216, the second gate insulating layer 202b, and the first gate insulating layer 20 2a is selectively etched to form a contact hole. The conductive layer 217 is electrically connected to the gate electrode layer of the thin film transistor 210 disposed in the driving circuit. Connect emotionally.

[0138] In addition, the second terminal electrode 235, which has the same potential as the source line 234 of the driving circuit, is connected to the pixel electrode layer 22. The second terminal electrode 235 can be formed of the same light-transmitting material as the source electrode 7. The source line is electrically connected to the source electrode via a contact hole that reaches the line 234. The wiring 234 is a metal wiring, and is made of the same material as the source electrode layer of the thin film transistor 210. They are formed in the process and have the same potential.

[0139] The third terminal electrode having the same potential as the capacitance wiring layer 230 has the same light-transmitting property as the pixel electrode layer 227. In addition, the contact hole reaching the capacitance wiring layer 230 can be formed of a material having the above-mentioned properties. The contact hole 22 is for electrically connecting the capacitance electrode 231 to the pixel electrode layer 227. It can be formed using the same photomask and process as in 4.

[0140] In addition, when an active matrix type liquid crystal display device is manufactured, A liquid crystal layer is provided between the substrate and the opposing substrate on which the opposing electrode is provided, and an active matrix The substrate and the counter substrate are fixed together. The counter electrode is electrically connected to the counter substrate. A common electrode is provided on the active matrix substrate, and a fourth terminal is electrically connected to the common electrode. The fourth terminal electrode is provided on the terminal portion. The fourth terminal electrode is connected to the common electrode at a fixed potential, for example, GND, 0 The fourth terminal electrode is a terminal for setting the pixel electrode layer 227 and the like. The insulating layer may be made of a material having the following properties:

[0141] In addition, the source electrode layer of the thin film transistor 220 and the source electrode layer of the thin film transistor 210 The configuration for electrically connecting the source of the thin film transistor 220 is not particularly limited. A connection electrode that connects the electrode layer and the source electrode layer of the thin film transistor 210 is formed on the pixel electrode layer 227. In addition, in the portion other than the display region, the thin film transistor 2 may be formed in the same process. The source electrode layer of the thin film transistor 20 and the source electrode layer of the thin film transistor 210 are overlapped in contact with each other. This is also fine.

[0142] The cross-sectional structure of the gate wiring layer 232 of the driving circuit is shown in FIG. Since this embodiment is an example of a small liquid crystal display panel of 10 inches or less, the gate wiring layer of the driving circuit is The gate electrode layer 232 is made of the same light-transmitting material as the gate electrode layer of the thin film transistor 220. do.

[0143] Also, a gate electrode layer, a source electrode layer, a drain electrode layer, a pixel electrode layer, or other electrodes If the same material is used for the layers and other wiring layers, common sputter targets and common manufacturing equipment can be used. The cost of the material and the etchant (or This reduces the cost of etching gas, resulting in reduced manufacturing costs. It is possible.

[0144] In the structure of FIG. 3A, a photosensitive resin material is used as the planarization insulating layer 204. In this case, the step of forming a resist mask can be omitted.

[0145] FIG. 3(B) shows a cross-sectional structure that is partially different from that shown in FIG. 3(A). Since the same as A) except that the planarization insulating layer 204 is not present, the same parts are designated by the same reference numerals. In FIG. 3B, a protective insulating layer 203 is in contact with the protective insulating layer 203. The pixel electrode layer 227, the conductive layer 217, and the second terminal electrode 235 are formed.

[0146] When the structure in FIG. 3B is used, the step of forming the planarization insulating layer 204 can be omitted.

[0147] This embodiment mode can be freely combined with the first embodiment mode.

[0148] (Embodiment 3) In this embodiment, the size of the liquid crystal display panel exceeds 10 inches, and is 60 inches or even When using a 120-inch display, the wiring resistance of the light-transmitting wiring may become a problem. An example in which a part of the gate wiring is made into a metal wiring to reduce the wiring resistance will be shown.

[0149] In FIG. 5(A), the same reference numerals are used for the same parts as in FIG. 3(A), and detailed explanations of the same parts will be omitted. Omitted.

[0150] FIG. 5A shows a gate wiring of a driving circuit made of metal, and a thin film transistor 210 In this example, the gate electrode layer is formed in contact with a wiring having the same light-transmitting property as the gate electrode layer. Therefore, the number of photomasks increases compared to the first embodiment.

[0151] First, a layer capable of withstanding a first heat treatment for dehydration or dehydrogenation is formed on the substrate 200. A heat-resistant conductive material film (thickness: 100 nm or more and 500 nm or less) is formed.

[0152] In this embodiment, a tungsten film with a thickness of 370 nm and a tantalum nitride film with a thickness of 50 nm are used. Here, the conductive film is a laminate of a tantalum nitride film and a tungsten film. It is not limited, and an element selected from Ta, W, Ti, Mo, Al, Cu, or the above-mentioned elements An alloy film having the above-mentioned elements as components, an alloy film having the above-mentioned elements as components, The heat-resistant conductive material film is not limited to a single layer containing the above-mentioned elements, and may be a bilayer. A stack of more than one layer may be used.

[0153] A metal wiring is formed by a first photolithography process, and a first metal wiring layer 236 and a second The metal wiring layer 237 is formed. The tungsten film and the tantalum nitride film are etched using I CP (Inductively Coupled Plasma) It is recommended to use the etching method. The ICP etching method is used, and the etching conditions (coil type The amount of power applied to the electrode, the amount of power applied to the electrode on the substrate side, the electrode temperature on the substrate side, etc. By appropriately adjusting the thickness, the film can be etched into a desired tapered shape. The metal wiring layer 236 and the second metal wiring layer 237 are tapered to be in contact with each other. This can reduce defects in the formation of a light-transmitting conductive film.

[0154] Next, a light-transmitting conductive film is formed, and then a gate is formed by a second photolithography process. a gate wiring layer 238, a gate electrode layer of the thin film transistor 210, a gate The light-transmitting conductive film is transparent to visible light as described in Embodiment 1. A light-transmitting conductive material is used.

[0155] Depending on the material of the conductive film having light transmission properties, the first metal wiring layer 236 or the second metal wiring layer 237 may be The surface of the metal wiring layer 237 in contact with the gate wiring layer 238 is oxidized by a subsequent heat treatment or the like. Since the contact resistance may be increased due to the formation of the second metal wiring layer 237, the second metal wiring layer 237 is It is preferable to use a metal nitride film that prevents oxidation of the line layer 236 .

[0156] Next, a gate insulating layer, an oxide semiconductor layer, and the like are formed in the same steps as those in the first embodiment. In this process, an active matrix substrate is manufactured according to the first embodiment.

[0157] In this embodiment, after the planarization insulating layer 204 is formed, the terminal This shows an example of selectively removing the planarizing insulating layer in the terminal area. It is preferable not to do this in order to ensure a good connection with the FPC.

[0158] In FIG. 5A, the second terminal electrode 235 is formed on the protective insulating layer 203. 5(A) shows the gate wiring layer 238 overlapping a part of the second metal wiring layer 237. As a gate wiring layer covering the entire first metal wiring layer 236 and the second metal wiring layer 237, That is, the first metal wiring layer 236 and the second metal wiring layer 237 are formed to provide a gate wiring with low resistance. The wiring can be called an auxiliary wiring for improving resistance.

[0159] In the terminal section, a first terminal electrode having the same potential as the gate wiring is provided on the protective insulating layer 203. The wiring from the terminal portion is also made of metal. Formed by wiring.

[0160] In addition, the gate wiring and capacitance wiring in the non-display area are made of metal in order to reduce the wiring resistance. The wiring, that is, the first metal wiring layer 236 and the second metal wiring layer 237 are used as auxiliary wiring. It is also possible.

[0161] FIG. 5(B) shows a cross-sectional structure that is partially different from that shown in FIG. 5(A). A) is the same as A, except that the material of the gate electrode layer of the thin film transistor in the driver circuit is different. Therefore, the same reference numerals are used for the same parts, and detailed explanations of the same parts are omitted.

[0162] FIG. 5B shows an example in which the gate electrode layer of the thin film transistor of the driver circuit is formed of metal wiring. In the driver circuit, the material for the gate electrode layer is not limited to a light-transmitting material.

[0163] In FIG. 5B, a thin film transistor 240 disposed in the driving circuit is formed by the first metal wiring layer A gate electrode layer is formed by laminating a second metal wiring layer 241 on the first metal wiring layer 242. The wiring layer 242 can be formed using the same material and process as the first metal wiring layer 236. The second metal wiring layer 241 is formed of the same material and in the same process as the second metal wiring layer 237. It can be achieved.

[0164] In addition, when the gate electrode layer of the thin film transistor 240 is electrically connected to the conductive layer 217, The second metal wiring layer 241 for preventing oxidation of the first metal wiring layer 242 is a metal nitride film. It is preferred.

[0165] In this embodiment, metal wiring is used as part of the wiring of the drive circuit to reduce the wiring resistance. As the size of LCD panels exceeds 10 inches, 60 inches, and even 120 inches, Even in the case of using a switch, high definition display image and a high aperture ratio can be maintained.

[0166] (Embodiment 4) In this embodiment, a configuration of a storage capacitor different from that of the second embodiment is shown in FIG. FIG. 6(B) shows the same as FIG. 3(A) except for the configuration of the storage capacitor. Therefore, the same reference numerals are used for the same parts, and detailed explanations of the same parts are omitted. 1A shows the cross-sectional structure of a thin film transistor 220 and a storage capacitor disposed in a pixel portion.

[0167] FIG. 6A shows a dielectric layer including an oxide insulating layer 216, a protective insulating layer 203, and a planarizing insulating layer 20. 4, the pixel electrode layer 227 and the capacitance wiring layer 250 overlapping the pixel electrode layer 227 form a storage capacitor. The capacitance wiring layer 250 is connected to the thin film transistor 220 disposed in the pixel. Since the source electrode layer is formed of the same material and in the same process as the source electrode layer, It is laid out so as not to overlap with the source wiring layer of the resistor 220.

[0168] In the storage capacitor shown in FIG. 6A, a pair of electrodes and a dielectric material are transparent, and the entire storage capacitor The body is translucent.

[0169] FIG. 6B shows an example of a storage capacitor configuration different from that shown in FIG. 6A. Since this is the same as 3(A) except for the difference in the storage capacitance, the same symbols are used for the same parts. Detailed explanations of the same parts will be omitted.

[0170] FIG. 6B shows a structure in which the dielectric is a first gate insulating layer 202a and a second gate insulating layer 202b. The capacitance wiring layer 230 and the oxide semiconductor layer 252 and the capacitance In this example, a storage capacitor is formed by stacking the oxide semiconductor layer 252 and the electrode 231. The electrode 231 is laminated on the electrode 231 and functions as one electrode of the storage capacitor. The electrode 231 has the same light-transmitting property as the source electrode layer or the drain electrode layer of the thin film transistor 220. The capacitor wiring layer 230 is formed in the same process as the thin film transistor 2. Since the gate electrode layer 20 is formed of the same material and in the same process, the thin film transistor The layout is such that it does not overlap with the gate wiring layer of the resistor 220.

[0171] In addition, the capacitance electrode 231 is electrically connected to the pixel electrode layer 227 .

[0172] The storage capacitor shown in FIG. 6B also has a pair of electrodes and a dielectric material that are transparent, and the entire storage capacitor The body is translucent.

[0173] The storage capacitor shown in FIG. 6(A) and FIG. 6(B) has a light-transmitting property, and the number of gate wirings is In order to increase the resolution of displayed images, it is necessary to increase the capacity of the display even if the pixel size is reduced. It is possible to obtain a high aperture ratio.

[0174] This embodiment mode can be freely combined with other embodiment modes.

[0175] (Embodiment 5) In this embodiment mode, an example in which the first heat treatment is different from that in the first embodiment mode is shown in FIGS. 7 and 8 are the same as Figs. 1 and 2 except for some differences in the process. The same reference numerals are used and detailed explanations of the same parts are omitted.

[0176] First, according to the first embodiment, a conductive film having a light-transmitting property is formed on a substrate 400 having an insulating surface. After the formation, the gate electrode layers 401 and 451 are formed by a first photolithography process. do.

[0177] Next, a first gate insulating layer 402a and a second gate insulating layer 402b are formed on the gate electrode layers 401 and 451. A stack of edge layers 402b is formed.

[0178] Next, a light-transmitting conductive film is formed over the second gate insulating layer 402b, and then a second A source electrode layer 455a and a drain electrode layer 455b are formed by a photolithography process. (See FIG. 7(A)). Note that FIG. 7(A) is the same as FIG. 1(A).

[0179] Next, the second gate insulating layer 402b, the source electrode layer 455a, and the drain electrode layer 45 An oxide semiconductor film having a thickness of 2 nm to 200 nm is formed on 5b. The steps are the same as those in the first embodiment.

[0180] Next, the oxide semiconductor film is dehydrated or dehydrated under an inert gas atmosphere or under reduced pressure. The temperature of the first heat treatment for dehydration or dehydrogenation is 350° C. or higher and The temperature is set to be lower than the strain point of the plate, preferably at least 400° C. and lower than the strain point of the substrate. The substrate is placed in an electric furnace, which is one of the treatment apparatuses, and the oxide semiconductor film is heated in a nitrogen atmosphere. After the heat treatment, the substrate is not exposed to the air to prevent water and hydrogen from entering the oxide semiconductor film. This prevents the re-mixing of oxygen and reduces the resistance of the oxide semiconductor film, i.e., makes it an N-type (N - , N + After that, high-purity oxygen gas, high-purity N2O gas, or ultra-dry gas are added to the same furnace. Cooling is performed by introducing air (dew point below -40°C, preferably below -60°C). Oxygen gas Alternatively, it is preferable that the N2O gas does not contain water, hydrogen, etc. The purity of the oxygen gas or N2O gas introduced into the or 7N (99.99999%) or more (i.e., impurity concentration in oxygen gas or N2O gas) It is preferable to set the content of the EDTA to 1 ppm or less, and preferably 0.1 ppm or less.

[0181] After the first heat treatment for dehydration or dehydrogenation, the temperature is preferably 200° C. or higher and 400° C. or lower. Or at temperatures between 200°C and 300°C in an oxygen gas atmosphere, an N2O gas atmosphere, or Heat treatment is performed in an ultra-dry air atmosphere (dew point below -40°C, preferably below -60°C). You may go.

[0182] By going through the above steps, the entire oxide semiconductor layer is made into an oxygen-excess state, and thus a high resistance It converts it into type I, that is, into an antagonistic type.

[0183] As a result, the reliability of the thin film transistor to be formed later can be improved.

[0184] Next, the oxide semiconductor film is subjected to a photolithography process to form an island-shaped oxide semiconductor layer. The resulting semiconductor layer is processed into compound semiconductor layers 457 and 458 (see FIG. 7B).

[0185] Note that in this embodiment, an example in which dehydration or dehydrogenation is performed after the oxide semiconductor film is formed will be described. However, the first heat treatment of the oxide semiconductor layer is not particularly limited, and the oxide semiconductor layer is formed into an island-shaped oxide semiconductor layer. Alternatively, the oxide semiconductor film may be processed into a desired shape.

[0186] In addition, the oxide semiconductor film may be dehydrated or dehydrogenated under an inert gas atmosphere or reduced pressure. After cooling under an inert gas atmosphere, island-shaped oxide layers are formed by a photolithography process. Then, the oxide semiconductor layers 457 and 458 are processed into the oxide semiconductor layers 457 and 458. ℃ or less, preferably 200℃ to 300℃ in an oxygen gas atmosphere or N2O gas atmosphere. In a dry atmosphere or in an ultra-dry air atmosphere (dew point below -40°C, preferably below -60°C) Heat treatment at room temperature may be performed.

[0187] In addition, before the formation of the oxide semiconductor film, an inert gas atmosphere (nitrogen, helium, neon, Argon, etc.) under oxygen atmosphere, ultra-dry air (dew point below -40℃, preferably below -60℃ Heat treatment (400°C or higher but below the distortion point of the substrate) is performed in a low-pressure or low-temperature atmosphere. Impurities such as hydrogen and water contained in the gate insulating layer may be removed.

[0188] Next, a metal conductive film is formed on the second gate insulating layer 402b, and then a fourth photolithography is performed. A resist mask 436 is formed by a lithography process, and selective etching is performed to form a metal electrode. The pole layer 435 is formed (see FIG. 7(C)).

[0189] Next, the resist mask 436 is removed, and the resist is removed by a fifth photolithography process. A mask 437 is formed and selectively etched to remove the source electrode layer 405a and the drain electrode layer 405b. A second electrode layer 405b is formed (see FIG. 7(D)). In the oxide semiconductor layer, only a part of the oxide semiconductor layer is etched, and a groove (depression) is formed. This results in layer 459.

[0190] Next, the resist mask 437 is removed, and a thin film is formed in contact with the top surface and the side surface of the oxide semiconductor layer 458. The oxide insulating layer 407 which serves as a protective insulating film in contact with the groove (depression) of the oxide semiconductor layer 459 is formed. Complete.

[0191] Then, place the specimen in an inert gas atmosphere, oxygen gas atmosphere, or ultra-dry air (dew point below -40°C). A second heat treatment is performed under an atmosphere (preferably 200° C. to 40° C., preferably −60° C. or lower). 0°C or less, for example, 250°C to 350°C (see FIG. 7(E)). For example, nitrogen A second heat treatment is carried out at 250° C. for 1 hour in an atmosphere.

[0192] Next, a protective insulating layer 408 is formed over the oxide insulating layer 407 (see FIG. 7F).

[0193] Next, a planarization insulating layer 409 is formed over the protective insulating layer 408 .

[0194] Next, a sixth photolithography step is performed to form a resist mask, and a planarization insulating layer 4 09, the protective insulating layer 408 and the oxide insulating layer 407 are etched to form the drain electrode layer 4 A contact hole reaching 55b is formed.

[0195] Next, after removing the resist mask, a light-transmitting conductive film is formed.

[0196] Next, a seventh photolithography step is performed to form a resist mask and to form a Then, unnecessary portions are removed to form a pixel electrode layer 456 and a conductive layer 406 (see FIG. 8(A)). ).

[0197] Through the above steps, the thin film transistor 471 and the thin film transistor 472 are formed on the same substrate using seven masks. The film transistor 461 can be fabricated separately for the driver circuit or pixel portion. In addition, the first gate insulating layer 402a and the second gate insulating layer 402b are used as dielectrics to form a capacitance. The storage capacitor formed by the wiring layer and the capacitor electrode can also be formed on the same substrate. Transistor 461 and the holding capacitance are arranged in a matrix corresponding to individual pixels to form a pixel portion, and a driving circuit having a thin film transistor 471 is arranged around the pixel portion, whereby one substrate for manufacturing an active matrix type display device can be obtained. By arranging a driving circuit having a thin film transistor 471 around the pixel portion formed by arranging transistor 461 and the holding capacitance in a matrix corresponding to individual pixels, one substrate for manufacturing an active matrix type display device can be obtained. It can be used as one substrate for manufacturing an active matrix type display device.

[0198] By providing the conductive layer 406 at a position overlapping the channel formation region of the oxide semiconductor layer 459, in the bias - thermal stress test (BT test) for examining the reliability of the thin film transistor, the change amount of the threshold voltage of the thin film transistor 471 before and after the BT test can be reduced. In the bias - thermal stress test (BT test) for examining the reliability of the thin film transistor, the change amount of the threshold voltage of the thin film transistor 471 before and after the BT test can be reduced. The potential of the conductive layer 406 may be the same as that of the gate electrode layer 401, or different, and it can also function as a second gate electrode layer. Moreover, the potential of the conductive layer 406 may be GND, 0V, or in a floating state. The potential of the conductive layer 406 may be the same as that of the gate electrode layer 401, or different, and it can also function as a second gate electrode layer. Moreover, the potential of the conductive layer 406 may be GND, 0V, or in a floating state.

[0199] FIG. 8(B1) is a plan view of the channel - etched type thin film transistor 471 arranged in the driving circuit, and FIG. 8(A) is a cross - sectional view taken along line C1 - C2 of FIG. 8(B1). FIG. 8(C) is a cross - sectional view taken along line C3 - C4 of FIG. 8(B1). Moreover, FIG. 8(B2) is a plan view of the bottom - contact type thin film transistor 461 arranged in the pixel, and FIG. 8(A) is a cross - sectional view taken along line D1 - D2 of FIG. 8(B2). FIG. 8(C) is a cross - sectional view taken along line D3 - D4 of FIG. 8(B2). FIG. 8(A) is a cross - sectional view taken along line D1 - D2 of FIG. 8(B2). Moreover, FIG. 8(C) is a cross - sectional view taken along line D3 - D4 of FIG. 8(B2).

[0200] This embodiment can be freely combined with other embodiments.

[0201] (Embodiment 6) In this embodiment, an example of a process with fewer process steps and fewer photomasks than in Embodiment 1 is shown in the figure. 9(A) to 9(E). FIG. 9(A) to FIG. 9(E) are the same as FIG. 1 and FIG. 2. Since the same parts are the same except for the different points, the same reference numerals are used for the same parts, and detailed explanations of the same parts will be omitted. is omitted.

[0202] First, according to the first embodiment, a conductive film having a light-transmitting property is formed on a substrate 400 having an insulating surface. After the formation, the gate electrode layers 401 and 451 are formed by a first photolithography process. do.

[0203] Next, a first gate insulating layer 402a and a second gate insulating layer 402b are formed on the gate electrode layers 401 and 451. A stack of edge layers 402b is formed.

[0204] Next, a light-transmitting conductive film is formed over the second gate insulating layer 402b, and then a second A source electrode layer 455a and a drain electrode layer 455b are formed by a photolithography process. (See FIG. 9(A)). Note that FIG. 9(A) is the same as FIG. 1(A).

[0205] Next, the second gate insulating layer 402b, the source electrode layer 455a, and the drain electrode layer 45 An oxide semiconductor film having a thickness of 2 nm to 200 nm is formed over 5b. The target was an oxide semiconductor target containing In, Ga, and Zn (In-Ga- Zn-O oxide semiconductor target (In2O3:Ga2O3:ZnO=1:1:1 model) The distance between the substrate and the target was 170 mm, the pressure was 0.4 Pa, and the DC power supply 0.5kW, oxygen only, argon only, or argon and oxygen atmosphere By using a pulsed direct current (DC) power supply, dust can be reduced and the film thickness distribution can be made uniform. This is preferable because

[0206] Next, the oxide semiconductor film is formed into an island-shaped oxide semiconductor layer by a third photolithography process. To process.

[0207] Next, the oxide semiconductor layer is dehydrated or dehydrogenated. The temperature of the heat treatment in step 1 is 350° C. or higher and lower than the distortion point of the substrate, preferably 400° C. or higher. The substrate is introduced into an electric furnace, which is a type of heat treatment device, and the temperature is set to be below the distortion point of the substrate. After the oxide semiconductor layer was subjected to heat treatment in a nitrogen atmosphere, the substrate was exposed to the air. By preventing the oxide semiconductor layers 403 and 404 from being mixed with water or hydrogen again, 53 is obtained (see FIG. 9(B)). Note that the steps up to this point are the same as those in the first embodiment.

[0208] Next, a metal conductive film is formed on the second gate insulating layer 402b, and then a fourth photolithography is performed. A resist mask 441 is formed by a lithography process, and selective etching is performed to form a source An electrode layer 405a and a drain electrode layer 405b are formed (see FIG. 9C). To perform etching, an alkaline etchant is used to obtain the state shown in Figure 9(C). The materials for the metal conductive film are Al, Cr, Cu, Ta, Ti, Mo, and W. An element selected from the above, or an alloy containing the above elements, or a combination of the above elements In this embodiment, the metal conductive film is a 50 mm thick film obtained by sputtering. A Ti film having a thickness of 400 nm or more is used.

[0209] A Ti film was used as the metal conductive film, and an ammonia hydrogen peroxide mixture (ammonia hydrogen peroxide) was used as the alkaline etchant. By using a hydrogen peroxide solution, ammonia water, and water (5:2:2), the metal conductive film can be selectively removed. The oxide semiconductor layer made of an In-Ga-Zn-O-based oxide semiconductor can be left behind. can.

[0210] Next, the oxide semiconductor layer is partly thinned by using the resist mask 441 to form a groove. An oxide semiconductor layer 433 having a recess (see FIG. 9D) is formed. During the etching, the thickness of the oxide semiconductor layer 453 is reduced, and the oxide semiconductor layer 44 is thinned. Therefore, in the oxide semiconductor layer 453, the source electrode layer 405a and the drain electrode The thickness of the region between the layers 405b and the thickness of the oxide semiconductor layer 442 are approximately the same. The thin film transistor functions as a switching element without forming a groove (concave portion) in the oxide semiconductor layer. In the case where the etching function is to be performed, the etching is not particularly required. In this case, the thickness of the oxide semiconductor layer 453 does not become thin, and the thin film transistor is the same as that in the first embodiment. A transistor 460 is formed.

[0211] Next, the resist mask 441 is removed, and a thin film is formed in contact with the upper surface and the side surface of the oxide semiconductor layer 442. The oxide insulating layer 407 which serves as a protective insulating film in contact with the groove (depression) of the oxide semiconductor layer 433 is formed. Complete.

[0212] Next, a second heat treatment (preferably a second heat treatment) is performed under an inert gas atmosphere or an oxygen gas atmosphere. 00°C or higher and 400°C or lower, for example, 250°C or higher and 350°C or lower) (see FIG. 9(E)). .

[0213] Through the above steps, the oxide semiconductor film after deposition is dehydrated or dehydrogenated. The heat treatment is carried out to reduce the resistance and selectively put a part into an oxygen-excess state. The channel forming region 434 overlapping with the gate electrode layer 401 is I-shaped, and the source electrode layer 4 A first high-resistance drain region 431 overlapping the drain electrode layer 405a and a second high-resistance drain region 432 overlapping the drain electrode layer 405b. The gate electrode layer 451 is formed in a self-aligned manner with the high resistance drain region 432 of the second gate electrode 451. The channel formation region 443 overlapping with the first and second electrodes 441 has an I-type shape as a whole.

[0214] Through the above steps, the thin film transistor 470 and the thin film transistor 440 are formed on the same substrate. Here, the oxide semiconductor layer 453 is the same as the oxide semiconductor layer 453 in Embodiment 1. In the case of the same film thickness, the thin film transistor 440 obtained in this embodiment has a The oxide semiconductor layer 442 can be made thinner than the thin film transistor 460 of the first embodiment. The oxide semiconductor layer preferably has a thickness of 50 nm or less in order to maintain an amorphous state. In particular, in the channel-etch type thin film transistor 470, the etching shown in FIG. It is preferable that the thickness of the channel forming region 433 after etching is 30 nm or less. The channel forming region 443 of the thin film transistor 440 is formed by etching as shown in FIG. The film thickness of the thin film transistor is 30 nm or less. The film thickness of the channel forming regions 443 and 434 of the transistors 440 and 470 is set to 5 nm or more and 20 nm or less. The following applies.

[0215] In addition, the channel width of the final thin-film transistor is between 0.5 μm and 10 μm. It is preferable to set the above.

[0216] Subsequent steps are similar to those in Embodiment 1, in which a protective insulating layer 408 and a planarizing insulating layer 409 are formed. Then, a contact hole reaching the drain electrode layer 455b is formed, and the pixel electrode layer 456 is Then, a conductive layer 406 is formed.

[0217] Through the above steps, six photomasks are used to form thin film transistors 470 on the same substrate. and the thin film transistor 440 is separately manufactured in the driver circuit or pixel portion. It is possible to allocate transistors with optimal structures on the same substrate without increasing the number of processes. Various circuits can be configured using this.

[0218] This embodiment mode can be freely combined with other embodiment modes.

[0219] (Embodiment 7) A thin film transistor is manufactured, and the thin film transistor is used in a pixel portion and further in a driver circuit. It is possible to manufacture a semiconductor device (also called a display device) having a display function. A part or the whole of a driver circuit having a transistor is formed on the same substrate as the pixel portion, A stem-on panel can be formed.

[0220] The display device includes a display element. The display element may be a liquid crystal element (also called a liquid crystal display element), a light-emitting A light-emitting element (also called a light-emitting display element) can be used. A light-emitting element is a light-emitting element that emits light by applying a current or a voltage. This category includes elements whose brightness is controlled by a specific factor, such as inorganic EL (Electroluminescent) devices. Also, electronic ink, etc. A display medium whose contrast changes due to an electrical effect, such as a liquid crystal display, can also be used.

[0221] The display device includes a panel in which a display element is sealed, and a controller for the panel. and a module in which an IC or the like including the above is mounted. In the process, the element substrate, which corresponds to a form before the display element is completed, is used to transmit the current to the display element. The element substrate is provided with a means for supplying a voltage to each of the pixels of the display element. The electrode may be formed only, or the conductive film that will become the pixel electrode may be formed after the conductive film is formed. The state may be before etching to form pixel electrodes, or any other state may be used. Fits.

[0222] In this specification, the term "display device" refers to an image display device, a display device, or an optical device. Also refers to connectors, such as FPC (Flexible Printed Circuit). inted circuit) or TAB (Tape Automated Bon ding tape or TCP (Tape Carrier Package) is used. Modules with printed wiring boards attached to the ends of TAB tape or TCP or the display element is mounted with an IC (integrated circuit) by the COG (Chip On Glass) method. The display device also includes all modules in which a display circuit (or other circuit) is directly mounted.

[0223] The appearance and cross section of a liquid crystal display panel, which is one embodiment of a semiconductor device, will be described with reference to FIG. 10(A1) and 10(A2) show thin film transistors 4010 and 4011 and a liquid crystal display. The element 4013 is disposed between the first substrate 4001 and the second substrate 4006 by a sealant 4005. FIG. 10(B) is a plan view of the panel sealed by the This corresponds to the cross-sectional view at MN.

[0224] A pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. In this manner, a sealant 4005 is provided. A second substrate 4006 is provided on the path 4004. The line driver circuit 4004 is made up of a first substrate 4001, a sealant 4005, and a second substrate 4006. The liquid crystal layer 4008 is sealed together with the first substrate 4001. In a region different from the region surrounded by the material 4005, a single crystal is formed on a separately prepared substrate. A signal line driver circuit 4003 formed of a semiconductor film or a polycrystalline semiconductor film is mounted.

[0225] The method of connecting the separately formed drive circuit is not particularly limited, and may be a COG method, A wire bonding method, a TAB method, or the like can be used. FIG. 10A shows an example of mounting a signal line driver circuit 4003 by the COG method. This is an example in which a signal line driver circuit 4003 is mounted by the TAB method.

[0226] A pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. In FIG. 10B, the thin film transistor included in the pixel portion 4002 is A transistor 4010 and a thin film transistor 4011 included in the scanning line driver circuit 4004 A protective insulating layer 4020 is provided on the thin film transistors 4010 and 4011. An edge layer 4021 is provided.

[0227] The thin film transistors 4010 and 4011 each include the oxide semiconductor layer described in any of Embodiments 1 to 6. Thin film transistors with high reliability, including thin film transistors for driving circuits, can be used. The transistor 4011 may be the thin film transistor 470, 210, or 471, as the thin film transistor 4010 for the pixel, the thin film transistors 460, 220 In this embodiment, thin film transistors 4010 and 461 can be used. 011 is an n-channel thin film transistor.

[0228] The oxide semiconductor layer of the thin film transistor 4011 for the driver circuit is A conductive layer 4040 is provided in a position overlapping with the channel formation region. By providing the gate insulating film at a position overlapping the channel formation region of the nitride semiconductor layer, In addition, the amount of change in the threshold voltage of the thin film transistor 4011 can be reduced. The conductive layer 4040 may have the same potential as the gate electrode layer of the thin film transistor 4011. The conductive layer may be different from the first gate electrode layer and may function as the second gate electrode layer. The potential of 4040 may be GND, 0V, or may be in a floating state.

[0229] In addition, a pixel electrode layer 4030 of the liquid crystal element 4013 is connected to the thin film transistor 4010. The counter electrode layer 4031 of the liquid crystal element 4013 is electrically connected to the second substrate 40. 06. A pixel electrode layer 4030, a counter electrode layer 4031, and a liquid crystal layer 4008 are formed on the liquid crystal layer 4006. The overlapping portion corresponds to a liquid crystal element 4013. The electrode layer 4031 is provided with insulating layers 4032 and 4033 which function as alignment films. A liquid crystal layer 4008 is sandwiched between insulating layers 4032 and 4033 .

[0230] The first substrate 4001 and the second substrate 4006 may be light-transmitting substrates. Glass, ceramics, and plastics can be used. , FRP (Fiberglass-Reinforced Plastics) board, PV F (polyvinyl fluoride) film, polyester film, or acrylic resin film A film can be used.

[0231] Also, 4035 is a columnar spacer obtained by selectively etching the insulating film. In order to control the distance (cell gap) between the pixel electrode layer 4030 and the counter electrode layer 4031 A spherical spacer may be used. is electrically connected to a common potential line provided on the same substrate as the thin film transistor 4010. The common connection portion is used to connect the counter electrode layer 40 to the conductive particles disposed between the pair of substrates. The conductive particles can electrically connect the sealing material 40 to the common potential line. Included in 05.

[0232] Alternatively, a liquid crystal that exhibits a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases. When the temperature of cholesteric liquid crystal is increased, the phase immediately transitions from the cholesteric phase to the isotropic phase. The blue phase appears in a relatively narrow temperature range, so it is necessary to improve the temperature range. In order to improve the liquid crystal layer 4008, a liquid crystal composition containing 5% by weight or more of chiral agent is used. The liquid crystal composition containing the liquid crystal exhibiting the blue phase and the chiral agent has a response speed of 1 msec. c or less, it is optically isotropic so no alignment treatment is required, and it has low viewing angle dependency.

[0233] In addition to the transmission type liquid crystal display device, the present invention can also be applied to a semi-transmission type liquid crystal display device.

[0234] In addition, in liquid crystal display devices, a polarizing plate is provided on the outer side (the viewing side) of the substrate, and a colored layer (color In this example, the polarizing plate is placed on the inner side of the substrate. The laminated structure of the polarizing plate and the colored layer is not limited to the embodiment, and the polarizing plate may be provided in the same manner. The color layer may be appropriately set depending on the material and manufacturing process conditions of the color layer. A light-shielding film that functions as a light-shielding matrix may be provided.

[0235] The thin film transistors 4010 and 4011 are provided with an oxide semiconductor layer including a channel formation region. A protective insulating layer 4020 is formed in contact with the insulating film 4020. The oxide insulating layer 407 may be formed using a material and a method similar to those of the oxide insulating layer 407. In order to reduce the surface irregularities, the insulating layer 4021 is covered with the insulating layer 4021, which functions as a planarizing insulating film. Here, the protective insulating layer 4020 is formed by a sputtering method according to the first embodiment. A silicon oxide film is formed.

[0236] In addition, a protective insulating layer is formed on the protective insulating layer 4020. The protective insulating layer 408 may be formed using a material and a method similar to those of the protective insulating layer 408 described above. As the layer, a silicon nitride film is formed by RF sputtering.

[0237] The insulating layer 4021 can be formed using a material and a method similar to those of the planarization insulating layer 409 described in Embodiment 1. The material may be polyimide, acrylic resin, benzocyclobutene resin, polyamide, etc. Organic materials having heat resistance, such as epoxy resin, can be used. In addition to the above materials, low-k materials, siloxane resins, and PSG (phosphor glass) are also available. , BPSG (borophosphorus glass), etc. can be used. The insulating layer 4021 may be formed by stacking a plurality of insulating films.

[0238] Siloxane-based resin is a type of Si-OS formed using siloxane-based materials as starting materials. The siloxane resin corresponds to a resin containing an i bond. In addition, the organic group may have a fluoro group.

[0239] The method for forming the insulating layer 4021 is not particularly limited, and may be a sputtering method, an SOG method, or the like, depending on the material. , spin coating, dip coating, spray coating, droplet ejection method (inkjet method, screen Printing, offset printing, etc.) Roll coating method, curtain coating method, knife coating method The baking process of the insulating layer 4021 and the annealing process of the oxide semiconductor layer can be used. By using the same as the mold, a semiconductor device can be manufactured efficiently.

[0240] The pixel electrode layer 4030 and the counter electrode layer 4031 are made of indium oxide containing tungsten oxide. , indium zinc oxide with tungsten oxide, indium oxide with titanium oxide, Indium Tin Oxide with Titanium Dioxide, Indium Tin Oxide (ITO), Indium Zinc Conductive, light-transmitting oxides, such as indium tin oxide doped with silicon oxide Materials can be used.

[0241] The pixel electrode layer 4030 and the counter electrode layer 4031 are made of a conductive polymer. The conductive composition may be used to form the conductive film. The pixel electrode thus fabricated has a sheet resistance of 10,000 Ω / □ or less and a light transmittance of 550 nm. It is preferable that the sheet resistance is lower. It is preferable that the resistivity of the conductive polymer contained in the conductive composition is 0.1 Ω·cm or less. .

[0242] As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. For example, polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene or or a derivative thereof, or a copolymer of two or more of these.

[0243] A signal line driver circuit 4003 and a scanning line driver circuit 4004 or a pixel section 4 Various signals and potentials are applied to 002 via FPC4018.

[0244] The connection terminal electrode 4015 is made of the same conductive film as the pixel electrode layer 4030 of the liquid crystal element 4013. The terminal electrode 4016 is formed from the source electrode layer and the drain electrode layer of the thin film transistor 4011. The gate electrode layer is formed of the same conductive film.

[0245] The connection terminal electrode 4015 is connected to a terminal of the FPC 4018 via an anisotropic conductive film 4019. The electrodes are electrically connected to each other.

[0246] In FIG. 10, a signal line driver circuit 4003 is formed separately and mounted on a first substrate 4001. The present invention is not limited to this configuration. Only a part of the line driver circuit may be separately formed and mounted.

[0247] FIG. 19 shows a semiconductor device using a TFT substrate 2600 fabricated by the fabrication method disclosed in this specification. 1 shows an example in which a liquid crystal display module is configured as a semiconductor device.

[0248] FIG. 19 shows an example of a liquid crystal display module, in which a TFT substrate 2600 and an opposing substrate 2601 are connected. The substrate 2602 is fixed to the substrate 2601 by a bonding material 2602, and a pixel portion 2603 including a TFT and the like and a liquid crystal layer are disposed between the substrate 2601 and the substrate 2602. A display element 2604 and a colored layer 2605 are provided to form a display area. is necessary for color display, and in the case of the RGB method, it corresponds to each color of red, green, and blue. A colored layer is provided corresponding to each pixel. On the outside, a polarizing plate 2606, a polarizing plate 2607, and a diffusion plate 2613 are arranged. It is composed of a cathode ray tube 2610 and a reflector 2611, and a circuit board 2612 is a flexible wiring board. A wiring board 2609 is connected to the wiring circuit section 2608 of the TFT board 2600, and the controller The LCD has external circuits such as a filter circuit and a power supply circuit. The layers may be laminated with a retardation plate interposed therebetween.

[0249] The LCD module is available in TN (Twisted Nematic) mode, IPS (In-plane Switching) mode, n-Plane-Switching mode, FFS (Fringe Field Switching) switching mode, MVA (Multi-domain Vertical A alignment) mode, PVA(Patterned Vertical Alignment) mode nment) mode, ASM(Axially Symmetric aligned Micro-cell mode, OCB (Optically Compensated Birefringence mode, FLC (Ferroelectric Liquid uid Crystal) mode, AFLC(AntiFerroelectric L iquid Crystal mode etc. can be used.

[0250] By the above steps, a highly reliable liquid crystal display panel can be manufactured as a semiconductor device. do.

[0251] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0252] (Embodiment 8) An example of electronic paper will be shown as one mode of a semiconductor device.

[0253] Electronic paper that uses switching elements and elements electrically connected to drive electronic ink Electronic paper is also called an electrophoretic display. It is known to be as easy to read as paper, consumes less power than other display devices, and is thin and light. This has the advantage that it is possible to

[0254] Electrophoretic displays can take a variety of forms, but the first particle has a positive charge. A microcapsule containing a negatively charged second particle and a negatively charged second particle is immersed in a solvent or solute. By applying an electric field to the microcapsules, The particles in the capsule are moved in opposite directions to each other, and only the color of the particles that have gathered on one side is displayed. The first particles or the second particles contain a dye, and in the absence of an electric field, The first particles and the second particles are different in color (colorless). (including

[0255] Thus, electrophoretic displays operate in such a way that materials with high dielectric constants migrate to areas of high electric field. This is a display that utilizes the so-called dielectrophoretic effect. Therefore, no polarizing plate is required for the liquid crystal display device.

[0256] The microcapsules dispersed in a solvent are called electronic ink. The electronic ink can be printed on surfaces such as glass, plastic, fabric, and paper. A color display is also possible by using a color filter or particles having a pigment.

[0257] In addition, the above microphone is appropriately placed on the active matrix substrate so as to be sandwiched between two electrodes. By arranging multiple microcapsules, an active matrix display device is completed. Display can be achieved by applying an electric field to the cell. An active matrix substrate obtained by using transistors can be used.

[0258] The first particles and the second particles in the microcapsules are made of a conductive material, an insulating material, Semiconductor materials, magnetic materials, liquid crystal materials, ferroelectric materials, electroluminescent materials, A material selected from the group consisting of magnetochromic material, magnetophoretic material, and a composite material thereof. Just use it.

[0259] FIG. 18 shows an active matrix type electronic paper as an example of a semiconductor device. The thin film transistor 581 used in the device is the thin film transistor shown in the embodiment mode 1. The thin film transistor can be fabricated in the same manner as the conventional thin film transistor, and is highly reliable, including an oxide semiconductor layer. The thin film transistors shown in any of the embodiments 2 to 6 may be used as the thin film transistor 581 in this embodiment. It can also be applied.

[0260] The electronic paper in FIG. 18 is an example of a display device that uses the twisting ball display method. The spherical display method is an electrode layer that uses spherical particles painted in black and white as display elements. A potential difference is applied between the first electrode layer and the second electrode layer. This is a method of displaying images by controlling the orientation of spherical particles through the generation of light.

[0261] The thin film transistor 581 formed on the substrate 580 is a bottom-gate thin film transistor. The substrate 580 and the substrate 596 are covered with an insulating film 583 that is in contact with the semiconductor layer. The first electrode layer is formed by a source electrode layer or a drain electrode layer of the thin film transistor 581 sealed between the first electrode layer and the second electrode layer. The electrode layer 587 is in contact with the insulating film 583 and the insulating layer 585 through an opening formed therein, and is electrically connected. Between the first electrode layer 587 and the second electrode layer 588 formed on the substrate 596 The spherical particle 589 includes a black region 590a and a white region 590b. The periphery of the shaped particle 589 is filled with a filler 595 such as a resin. The first electrode layer 586 corresponds to a first electrode, and the second electrode layer 588 corresponds to a common electrode. It is electrically connected to a common potential line provided on the same substrate as the membrane transistor 581. The second electrode layer is connected to the conductive particles disposed between the substrates 580 and 596 by using the connection. 588 can be electrically connected to a common potential line.

[0262] Also, instead of the element using the twist ball, an electrophoretic element can be used. A transparent liquid is enclosed in a 1 mm diameter tube containing positively charged white particles and negatively charged black particles. Microcapsules with a size of about 0 μm to 200 μm are used. The microcapsules placed between the first and second electrode layers are subjected to an electric field. When the light is turned on, the white particles and black particles move in opposite directions, resulting in a white or black display. A display element that applies this principle is an electrophoretic display element. The device is generally called electronic paper. Electrophoretic display elements are liquid crystal display elements. Because it has a higher reflectivity than the children, auxiliary lights are not required, and it consumes less power and is dim. The display can be recognized even in a place where the power is not supplied to the display. Even if the display is turned on, it is possible to hold the image once it has been displayed, so the display can be connected to a semiconductor device with a power supply. When a display device (also referred to simply as a display device or a semiconductor device equipped with a display device) is cut, Even if there is a problem, it is possible to store the displayed image.

[0263] Through the above steps, electronic paper having high reliability as a semiconductor device can be manufactured. .

[0264] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0265] (Embodiment 9) An example of a light-emitting display device is shown as a semiconductor device. is shown using a light-emitting element that uses electroluminescence. The light-emitting element that uses the light-emitting material is classified into two types according to whether the light-emitting material is an organic compound or an inorganic compound. Generally, the former is called an organic EL element and the latter an inorganic EL element.

[0266] In an organic EL element, electrons and holes are released from a pair of electrodes by applying a voltage to the light-emitting element. are injected into layers containing light-emitting organic compounds, causing a current to flow. The rears (electrons and holes) recombine to form an excited state in the light-emitting organic compound. When the excited state returns to the ground state, light is emitted. Such a light-emitting element is called a current-excitation type light-emitting element.

[0267] Inorganic EL elements are divided into dispersion-type inorganic EL elements and thin-film-type inorganic EL elements according to their element structure. Dispersion-type inorganic EL elements have a light-emitting layer in which particles of a light-emitting material are dispersed in a binder. The emission mechanism is a donor-acceptor reaction that utilizes the donor and acceptor levels. Thin-film inorganic EL elements are made by sandwiching a light-emitting layer between dielectric layers. The structure is sandwiched between electrodes, and the light emission mechanism utilizes the inner shell electron transition of metal ions. In this example, the light-emitting element is an organic EL element. do.

[0268] FIG. 12 shows an example of a pixel configuration to which digital time gray scale driving can be applied as an example of a semiconductor device. This is a diagram.

[0269] The configuration of a pixel to which digital time gray scale driving can be applied and the operation of the pixel will be described. The figure shows an n-channel transistor that uses an oxide semiconductor layer as a channel formation region in one pixel. Here is an example of using two of them.

[0270] The pixel 6400 includes a switching transistor 6401 and a light-emitting element driving transistor 6 The transistor 402 has a light emitting element 6404 and a capacitor element 6403. The gate of the gate electrode of the gate electrode 6401 is connected to the scanning line 6406, and the first electrode (the source electrode and the drain electrode) One of the electrodes) is connected to a signal line 6405, and the second electrode (the source electrode and the drain electrode) is connected to a signal line 6405. The other end of the transistor 6402 is connected to the gate of the light-emitting element driving transistor 6402. The transistor 6402 has a gate connected to a power supply line 6407 via a capacitor element 6403. The first electrode is connected to a power line 6407, and the second electrode is the first electrode (pixel The second electrode of the light emitting element 6404 corresponds to a common electrode 6408. The common electrode 6408 is electrically connected to a common potential line formed on the same substrate.

[0271] A low power supply potential is set to the second electrode (common electrode 6408) of the light emitting element 6404. Note that the low power supply potential is a low power supply potential with respect to the high power supply potential set to the power supply line 6407. Potential < High power supply potential. For example, GND, 0V, etc. are set as low power supply potential. The potential difference between the high power supply potential and the low power supply potential is applied to the light emitting element 6404. In order to make the light emitting element 6404 emit light by passing a current through the light emitting element 6404, a high power supply potential and the low power supply potential is set to be equal to or higher than the forward threshold voltage of the light emitting element 6404. Each potential is set.

[0272] The capacitor 6403 is substituted for the gate capacitance of the light-emitting element driving transistor 6402. It is possible to omit it. Regarding the gate capacitance of the light-emitting element driving transistor 6402 A capacitance may be formed between the channel region and the gate electrode.

[0273] In the case of a voltage input voltage driving method, the gate of the light emitting element driving transistor 6402 In the test, the light emitting element driving transistor 6402 is either fully turned on or fully turned off. In other words, the light emitting element driving transistor 6402 is inputted with a video signal that is in the state of The light emitting element driving transistor 6402 is operated in the linear region. Therefore, a voltage higher than the voltage of the power supply line 6407 is applied to the gate of the light emitting element driving transistor 6402. The signal line 6405 is connected to the power supply line voltage + transistor for driving the light emitting element. Apply a voltage equal to or higher than the Vth of 6402.

[0274] In addition, when analog gray scale driving is performed instead of digital time gray scale driving, the input of the signal is different. By doing so, the same pixel configuration as in FIG. 12 can be used.

[0275] When analog gradation driving is performed, a light emitting element is connected to the gate of the light emitting element driving transistor 6402. Apply the forward voltage of 6404 + a voltage equal to or higher than the Vth of the light emitting element driving transistor 6402 The forward voltage of the light emitting element 6404 refers to a voltage for achieving a desired luminance. At least it is larger than the forward threshold voltage. By inputting a video signal that operates in the saturation region, a current flows through the light emitting element 6404. In order to operate the light emitting element driving transistor 6402 in a saturation region, The potential of the power source line 6407 is set higher than the gate potential of the light emitting element driving transistor 6402. By converting the video signal into an analog signal, a current corresponding to the video signal is supplied to the light emitting element 6404. It is possible to perform analog gray scale driving.

[0276] Note that the pixel configuration shown in FIG. 12 is not limited to this. For example, A switch, a resistive element, a capacitive element, a transistor, a logic circuit, or the like may be added.

[0277] Next, the configuration of the light emitting element will be described with reference to FIG. The cross-sectional structure of a pixel will be described using an example in which FT is n-type. (C) TFTs 7001 and 7011 which are TFTs for driving light emitting elements used in the semiconductor device The thin film transistor 7021 can be manufactured in the same manner as the thin film transistor arranged in the pixel shown in the embodiment mode 1. In addition, the thin film transistor according to the embodiment 2 to 5 has high reliability and includes an oxide semiconductor layer. The thin film transistors arranged in the pixel indicated by 6 are designated as TFTs 7001, 7011, and 7021. It can also be applied.

[0278] The light emitting element only needs to have at least one of the anode and cathode transparent in order to extract light. Then, a thin film transistor and a light emitting element are formed on the substrate, and light is taken from the surface opposite to the substrate. Top emission, bottom emission, and side emission. There are light-emitting elements with a double-sided emission structure that emits light from the side of the pixel. The present invention can also be applied to optical elements.

[0279] A light emitting element having a top emission structure will be described with reference to FIG.

[0280] In FIG. 13(A), the TFT 7001, which is a driving TFT arranged in a pixel, is an n-type light-emitting element. This figure shows a cross-sectional view of a pixel when light emitted from the electrode 7002 exits to the anode 7005 side. 13(A) shows a cathode 7003 of a light-emitting element 7002 and a driving TFT arranged in a pixel. A TFT 7001 is electrically connected to a cathode 7003, a light-emitting layer 7004 is formed on the cathode 7003, and an anode 7005 is formed on the anode 7006. 005 are laminated in order. The cathode 7003 has a small work function and reflects light. Various conductive materials can be used. For example, Ca, Al, MgAg, Al Li, etc. are preferable. The light-emitting layer 7004 may be composed of a single layer or a plurality of layers. It may be constructed in a laminated manner. If it is constructed in multiple layers, the An electron injection layer, an electron transport layer, a light-emitting layer, a hole transport layer, and a hole injection layer are stacked on the electrode 7003 in this order. It is not necessary to provide all of these layers. The anode 7005 is a light-transmitting conductive The material may be indium oxide, tungsten oxide, or other suitable materials. Indium zinc oxide containing titanium oxide, Indium oxide containing titanium oxide Indium tin oxide, Indium tin oxide, Indium zinc oxide, Silicon oxide added A light-transmitting conductive film such as indium tin oxide may also be used.

[0281] In addition, a partition wall is formed between the cathode 7003 and the cathode 7008 of the adjacent pixel, covering the ends of each. The partition wall 7009 is made of polyimide, acrylic resin, polyamide, or epoxy. The partition wall 7009 is formed using an organic resin film such as a resin film, an inorganic insulating film, or polysiloxane. In particular, a photosensitive resin material is used, and the side surface of the partition wall 7009 is formed with a continuous curvature. It is preferable to form the partition 7009 so as to have an inclined surface. In this case, the step of forming a resist mask can be omitted.

[0282] The region where the light-emitting layer 7004 is sandwiched between the cathode 7003 and the anode 7005 constitutes the light-emitting element 7002. In the case of the pixel shown in FIG. 13A, the light emitted from the light emitting element 7002 is The light is emitted toward the anode 7005 as indicated by the mark.

[0283] Next, a light emitting element having a bottom emission structure will be described with reference to FIG. The TFT 7011 is an n-type, and the light emitted from the light-emitting element 7012 is emitted toward the cathode 7013. FIG. 13B shows a cross-sectional view of a pixel in the case where a light-emitting element driving TFT 7011 and a A cathode 7013 of the light-emitting element 7012 is formed on the conductive film 7017 having a light-transmitting property and is electrically connected to the light-emitting element 7012. A light-emitting layer 7014 and an anode 7015 are laminated in this order on the cathode 7013. In addition, when the anode 7015 has a light-transmitting property, a light reflecting or blocking layer is provided so as to cover the anode. A shielding film 7016 for shielding the cathode 7013 may be formed. As in the case of the first embodiment, various conductive materials having a small work function can be used. However, the thickness of the film is set to a level that allows light to pass through (preferably, about 5 nm to 30 nm). For example, an aluminum film having a thickness of 20 nm can be used as the cathode 7013. The light-emitting layer 7014 may be composed of a single layer as in FIG. 13(A) or may be composed of multiple layers. The anode 7015 is a light-transmitting layer. Although not necessary, the insulating film 11 may be formed using a light-transmitting conductive material as in FIG. 13(A). The shielding film 7016 can be made of, for example, a metal that reflects light. The material is not limited to a metal film, and for example, a resin to which a black pigment is added may be used.

[0284] The region where the light-emitting layer 7014 is sandwiched between the cathode 7013 and the anode 7015 is the light-emitting element 7012. In the case of the pixel shown in FIG. 13B, the light emitted from the light-emitting element 7012 corresponds to The light is emitted toward the cathode 7013 as shown by the arrow.

[0285] In addition, between the conductive film 7017 and the conductive film 7018 of the adjacent pixel, A partition 7019 is provided. The partition 7019 is made of polyimide, acrylic resin, polyamide, epoxy, etc. The partition wall 70 is formed using an organic resin film such as an alkoxy resin, an inorganic insulating film, or polysiloxane. 19 is made of a photosensitive resin material, and the side of the partition 7019 is formed with a continuous curvature. It is preferable to form the partition wall 7019 so as to have an inclined surface. When the material is used, the step of forming a resist mask can be omitted.

[0286] Next, a light emitting element having a dual emission structure will be described with reference to FIG. In the example, a light-transmitting conductive film 702 electrically connected to a light-emitting element driving TFT 7021 is A cathode 7023 of a light-emitting element 7022 is formed on the substrate 701, and a light-emitting layer 7023 is formed on the cathode 7023. 13(A) and an anode 7025 are laminated in this order. Similarly, various conductive materials with small work functions can be used. The thickness of the cathode 702 is set to a level that allows light to pass through. For example, an Al film having a thickness of 20 nm is used as the cathode 702. 3. The light-emitting layer 7024 can be formed of a single It may be configured as a layer or as a laminate of a plurality of layers. The anode 7025 is formed using a light-transmitting conductive material, similarly to FIG. This can be done.

[0287] In addition, between the conductive film 7027 and the conductive film 7028 of the adjacent pixel, A partition 7029 is provided. The partition 7029 is made of polyimide, acrylic resin, polyamide, or epoxy. The partition wall 70 is formed using an organic resin film such as an alkoxy resin, an inorganic insulating film, or polysiloxane. 29 is made of a photosensitive resin material, and the side of the partition 7029 is formed with a continuous curvature. It is preferable to form the partition wall 7029 so as to have an inclined surface. When the material is used, the step of forming a resist mask can be omitted.

[0288] The overlapping portion of the cathode 7023, the light-emitting layer 7024, and the anode 7025 constitutes the light-emitting element 70. In the case of the pixel shown in FIG. 13C, the light emitted from the light emitting element 7022 is is emitted toward both the anode 7025 side and the cathode 7023 side as indicated by the arrows.

[0289] Although the organic EL element has been described as the light-emitting element here, inorganic EL elements can also be used as the light-emitting element. It is also possible to provide an L element.

[0290] In addition, a thin film transistor (a TFT for driving a light-emitting element) that controls the driving of the light-emitting element and a light-emitting element In the above example, the current control TFT is electrically connected between the driving TFT and the light emitting element. The configuration may be such that FT is connected.

[0291] The semiconductor device is not limited to the configuration shown in FIG. 13, and may be any of the configurations disclosed in this specification. Various modifications based on the technical concept are possible.

[0292] Next, the appearance and structure of a light-emitting display panel (also called a light-emitting panel) which corresponds to one embodiment of a semiconductor device will be described. The cross section will be described with reference to FIG. 11. FIG. 11(A) shows a thin film formed on a first substrate. A panel in which the film transistor and the light emitting element are sealed between the second substrate and the film transistor and the light emitting element by a sealant. 11(B) is a plan view of the above-mentioned embodiment, and FIG. 11(B) is a cross-sectional view taken along line HI of FIG. 11(A).

[0293] A pixel portion 4502, a signal line driver circuit 4503a, and a signal line driver circuit 4504 are provided on a first substrate 4501. A sealant 4505 is formed to surround the gate driver circuits 4504a and 4504b. In addition, a pixel portion 4502, signal line driver circuits 4503a and 4503b, and A second substrate 4506 is provided on the scanning line driver circuits 4504a and 4504b. The pixel portion 4502, the signal line driver circuits 4503a and 4503b, and the scanning line driver circuit 45 4504a and 4504b are a first substrate 4501, a sealant 4505, and a second substrate 4506. The filling material 4507 is sealed with the sealing material 4507. Highly sealed protective film with little outgassing (lamination film, UV curable resin film) It is preferable to package (enclose) the package in a material such as a film or a cover material.

[0294] A pixel portion 4502, a signal line driver circuit 4503a, and a fourth 503b and the scanning line driver circuits 4504a and 4504b each have a plurality of thin film transistors. In FIG. 11B, a thin film transistor 4510 included in a pixel portion 4502 and a signal 45, a thin film transistor 4509 included in a line driver circuit 4503a is illustrated.

[0295] The thin film transistors 4509 and 4510 each include the oxide semiconductor layer described in any of Embodiments 1 to 6. A highly reliable thin film transistor including a thin film transistor arranged in a driving circuit can be applied. The transistor 4509 can be the thin film transistor 470 described in any of Embodiments 1 to 5. 210, 240, 471, the thin film transistor 4510 arranged in the pixel is a thin film transistor In this embodiment, a thin film The transistors 4509 and 4510 are n-channel thin film transistors.

[0296] The oxide semiconductor layer of the thin film transistor 4509 for the driver circuit is formed over the insulating layer 4544. A conductive layer 4540 is provided in a position overlapping with the channel forming region. By providing the MOSFET in a position overlapping the channel formation region of the semiconductor layer, It is possible to reduce the amount of change in the threshold voltage of the thin film transistor 4509. The potential of the gate electrode layer 4540 may be the same as that of the gate electrode layer of the thin film transistor 4509 or may be different. The conductive layer 4 may be formed of a conductive material and may function as a second gate electrode layer. The potential of 540 may be GND, 0V, or may be in a floating state.

[0297] On the thin film transistors 4509 and 4510, a protective insulating film including a channel formation region is formed. An insulating layer 4543 is formed in contact with the semiconductor layer. The oxide insulating layer 407 may be formed using a material and a method similar to those of the oxide insulating layer 407. In order to reduce the surface unevenness of the substrate, the substrate is covered with an insulating layer 4545 which functions as a planarizing insulating film. Here, a silicon oxide film is formed as the insulating layer by sputtering in accordance with the first embodiment. Form.

[0298] In addition, a protective insulating layer 4547 is formed over the insulating layer 4543. The protective insulating layer 4547 is The protective insulating layer 408 may be formed using a material and a method similar to those of the protective insulating layer 408 described in Embodiment 1. As the protective insulating layer 4547, a silicon nitride film is formed by an RF sputtering method.

[0299] The insulating layer 4545 can be formed using a material and a method similar to those of the planarization insulating layer 409 described in Embodiment 1. Here, the insulating layer 4545 is formed using an acrylic resin.

[0300] In addition, 4511 corresponds to a light-emitting element, and a first electrode which is a pixel electrode of the light-emitting element 4511 is The layer 4517 is electrically connected to the source electrode layer or the drain electrode layer of the thin film transistor 4510. The light-emitting element 4511 is configured as a first electrode layer 4517, an electroluminescent layer The light emitting element 4512 and the second electrode layer 4513 are stacked together, but the structure is not limited to the one shown in the figure. The configuration of the light emitting element 4511 can be changed appropriately according to the direction of the light extracted from the element 4511. It is possible.

[0301] The partition wall 4520 is formed using an organic resin film, an inorganic insulating film, or polysiloxane. An opening is formed on the first electrode layer 4517 using a photosensitive material, and the sidewall of the opening is It is preferable to form the inclined surface so as to have a continuous curvature.

[0302] The electroluminescent layer 4512 may be composed of a single layer or a plurality of layers may be laminated. It doesn't matter whether it is done or not.

[0303] In order to prevent oxygen, hydrogen, water, carbon dioxide, etc. from entering the light emitting element 4511, the second electrode layer 4 A protective film may be formed on the insulating film 513 and the partition wall 4520. The protective film may be a silicon nitride film, a nitride It is possible to form a silicon oxide film, a DLC film, etc.

[0304] In addition, signal line driver circuits 4503a and 4503b, scanning line driver circuits 4504a and 4504b Various signals and potentials applied to the pixel portion 4502 are It is supplied by b.

[0305] The connection terminal electrode 4515 is formed of the same conductive film as the first electrode layer 4517 of the light-emitting element 4511. The terminal electrode 4516 is formed of a source electrode layer and The drain electrode layer is formed from the same conductive film as the drain electrode layer.

[0306] The connection terminal electrode 4515 is connected to the terminal of the FPC 4518a via the anisotropic conductive film 4519. The electrodes are electrically connected to each other.

[0307] The second substrate located in the direction in which light is extracted from the light emitting element 4511 must be transparent. In that case, use a glass plate, a plastic plate, a polyester film or an acrylic plate. A light-transmitting material such as a film is used.

[0308] In addition, filler 4507 can be inert gas such as nitrogen or argon, or ultraviolet-curing resin. It can be made of resin or thermosetting resin, and is suitable for PVC (polyvinyl chloride), acrylic resin, etc. Epoxy resin, silicone resin, PVB (polyvinyl butyral) or EVA (copolymer of ethylene and vinyl acetate) can be used. Nitrogen may be used as the material.

[0309] If necessary, a polarizing plate or a circular polarizing plate (including an elliptical polarizing plate) may be provided on the light-emitting surface of the light-emitting element. Optical films such as retardation plates (λ / 4 plates, λ / 2 plates) and color filters may be provided as appropriate. In addition, the polarizing plate or the circular polarizing plate may be provided with an anti-reflection film. Anti-glare treatment can be applied to diffuse reflected light and reduce glare.

[0310] In addition, only or a part of the signal line driver circuit, or only or a part of the scanning line driver circuit may be separated. The structure is not limited to that shown in FIG.

[0311] Through the above steps, a highly reliable light-emitting display device (display panel) can be manufactured as a semiconductor device. It is possible.

[0312] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0313] (Embodiment 10) In this embodiment, at least a part of the driver circuit and a thin film transistor to be disposed in the pixel portion are formed on the same substrate. An example of fabricating a transistor will be described below.

[0314] The thin film transistor to be disposed in the pixel portion is the thin film transistor according to the first embodiment, the fifth embodiment, or the fifth embodiment. The thin film transistors shown in any of the embodiments 1 to 6 are n-channel Since the driver circuit is a TFT, the driver circuit can be configured with n-channel TFTs. A part of the path is formed on the same substrate as the thin film transistor of the pixel portion.

[0315] An example of a block diagram of an active matrix display device is shown in FIG. A pixel portion 5301, a first scanning line driver circuit 5302, a second scanning line driver circuit 5303, and a third scanning line driver circuit 5304 are provided on a substrate 5300. The pixel portion 5301 includes a signal line driver circuit 5303 and a signal line driver circuit 5304. is arranged extending from a signal line driver circuit 5304, and a plurality of scanning lines are arranged in a first scanning line driver circuit The first scanning line driver circuit 5302 and the second scanning line driver circuit 5303 are arranged to extend from each other. At the intersections of the signal lines and the display elements, pixels each having a display element are arranged in a matrix. In addition, the substrate 5300 of the display device is a flexible printed circuit (FPC). A timing control circuit 5305 (controller, control I / F) is connected to the timing control circuit 5305 via a connection part such as a C).

[0316] In FIG. 14A, a first scanning line driver circuit 5302, a second scanning line driver circuit 5303, a signal The signal line driver circuit 5304 is formed on the same substrate 5300 as the pixel portion 5301. This reduces the number of external components such as drive circuits, and therefore reduces costs. In addition, when a driving circuit is provided outside the substrate 5300, the wiring is extended to provide a connection portion. The number of connections can be reduced, and the reliability and yield can be improved.

[0317] The timing control circuit 5305 is, for example, A start signal (GSP1) for the first scanning line driver circuit (also called a start pulse) A clock signal (GCK1) for the scan line driver circuit is supplied to the timing control circuit 530. 5 is a second scanning line driver circuit 5303, for example, a second scanning line driver circuit The signal line supplies the clock signal (GSP2) for the scanning line driver circuit and the clock signal (GCK2) for the scanning line driver circuit. A start signal (SSP) for the signal line driver circuit and a clock for the signal line driver circuit are input to the driver circuit 5304. Clock signal (SCK), data for video signal (DATA) (also simply called video signal), Each clock signal is a multiple of the clock signal (LAT) with different periods. It may be a clock signal or may be supplied together with an inverted clock signal (CKB). The first scanning line driver circuit 5302 and the second scanning line driver circuit 53 It is possible to omit either 03 or 04.

[0318] In FIG. 14B, a first scanning line driver circuit 5302 and a second scanning line driver circuit 5303 are shown. A signal line driver circuit 5304 is formed on the same substrate 5300 as the pixel portion 5301. shows a structure in which the semiconductor device is formed on a separate substrate.

[0319] The thin film transistors described in Embodiments 1 to 6 are n-channel TFTs. 5(A) and 15(B) show the configuration and operation of a signal line driver circuit configured with n-channel TFTs. An example will be given below.

[0320] The signal line driver circuit includes a shift register 5601 and a switching circuit 5602 . The switching circuit 5602 includes switching circuits 5602_1 to 5602_N (N is a natural number). The switching circuits 5602_1 to 5602_N each have a A plurality of thin film transistors 5603_1 to 5603_k (k is a natural number) are provided. The thin film transistors 5603_1 to 5603_k are N-channel TFTs. An example will be explained.

[0321] The connection relationship of the signal line driver circuit will be described using the switching circuit 5602_1 as an example. The first terminals of the thin film transistors 5603_1 to 5603_k are respectively connected to the wiring 5604_1 The second terminals of the thin film transistors 5603_1 to 5603_k are connected to are connected to the signal lines S1 to Sk, respectively. The gate of k is connected to the wiring 5605_1.

[0322] The shift register 5601 sequentially outputs H level (H signal) to the wirings 5605_1 to 5605_N. , or high power supply potential level), and the switching circuits 5602_1 to 56 It has the function of selecting 02_N in sequence.

[0323] The switching circuit 5602_1 controls the conduction state (first terminal) between the wiring 5604_1 and the signal line S1. The function of controlling the potential of the wiring 5604_1 to the signal line S1 In this manner, the switching circuit 5602_1 has a function of controlling whether or not to supply the Similarly, the thin film transistors 5603_2 to 5603_3 function as selectors. _k control the conduction state between the wirings 5604_2 to 5604_k and the signal lines S2 to Sk, respectively. That is, the function of supplying the potentials of the wirings 5604_2 to 5604_k to the signal lines S2 to Sk. In this manner, each of the thin film transistors 5603_1 to 5603_k has a switching function. It functions as a switch.

[0324] In addition, the wirings 5604_1 to 5604_k each carry video signal data (DATA). The video signal data (DATA) is an analog signal corresponding to the image information or image signal. This is often a signal that

[0325] Next, the operation of the signal line driver circuit of FIG. 15(A) will be described with reference to the timing chart of FIG. 15(B). FIG. 15B shows signals Sout_1 to Sout_N and An example of Vdata_1 to Vdata_k is shown. These are examples of output signals of the shift register 5601, and signals Vdata_1 to Vdata _k are examples of signals input to the wirings 5604_1 to 5604_k, respectively. One operation period of the signal line driving circuit corresponds to one gate selection period in the display device. The selection period is divided into periods T1 to TN, for example. This is a period for writing video signal data (DATA) to the pixels belonging to the selected row. be.

[0326] In the drawings of the present embodiment, the signal waveforms of the components are not rounded for clarity. Therefore, the scale may not necessarily be limited to the actual scale. It should be noted that

[0327] During the period T1 to the period TN, the shift register 5601 outputs an H-level signal to the wiring 560 For example, in the period T1, the shift registers 5 601 outputs a high-level signal to the wiring 5605_1. Since 5603_1 to 5603_k are turned on, wiring 5604_1 to 5604_k and signal At this time, the wirings 5604_1 to 5604_k are in a conductive state. Data(S1)~Data(Sk) are input. Data(S1)~Data(Sk ) belong to a selected row via thin film transistors 5603_1 to 5603_k. In this way, during the periods T1 to TN, Then, the video signal data (DATA) is sent to the pixels in the selected row in order of k columns. It will be written.

[0328] As described above, video signal data (DATA) is written to the pixels in multiple columns. This makes it possible to reduce the number of video signal data (DATA) or the number of wirings. This reduces the number of connections to external circuits. By writing directly to the memory, the writing time can be increased, and the writing This can prevent under-crowding.

[0329] The shift register 5601 and the switching circuit 5602 may be the same as those in the first embodiment. A circuit constituted by the thin film transistor shown in the sixth embodiment can be used.

[0330] Regarding one form of a shift register used as a part of a scanning line driver circuit and / or a signal line driver circuit, This will be described with reference to FIG. 14 and FIG. 15.

[0331] The scanning line driving circuit has a shift register. In some cases, it may also have a level shifter, a buffer, etc. In the scanning line driver circuit, a clock signal is input to the shift register. The selection signal is generated by inputting the clock (CLK) and start pulse signal (SP). The generated selection signal is buffered and amplified in a buffer and then supplied to the corresponding scan line. The gate electrodes of the transistors of the pixels for one line are connected to the scanning line. Since the transistors of the pixels in one line must be turned on simultaneously, The capacitor used is capable of carrying a large current.

[0332] Regarding one form of a shift register used as a part of a scanning line driver circuit and / or a signal line driver circuit, This will be described with reference to FIG. 16 and FIG. 17.

[0333] Regarding the shift registers of the scanning line driver circuit and the signal line driver circuit, refer to FIG. 16 and FIG. 17. The shift register includes a first pulse output circuit 10_1 to an Nth pulse output circuit 10_2. The path 10_N (N is a natural number equal to or greater than 3) is shown in FIG. 16(A). The first pulse output circuit 10_1 to the N-th pulse output circuit 10_N of the shift register shown in FIG. A first clock signal CK1 is output from a first wiring 11, a second clock signal CK2 is output from a second wiring 12, a third clock signal CK2 from the third wiring 13; a fourth clock signal CK3 from the fourth wiring 14; The clock signal CK4 is supplied to the first pulse output circuit 10_1. A start pulse SP1 (first start pulse) is input from line 15. In the subsequent n-th pulse output circuit 10_n (n is a natural number between 2 and N), A signal from the pulse output circuit (called the previous stage signal OUT(n-1)) is input. In the pulse output circuit 10_1, a signal from the third pulse output circuit 10_3, which is two stages behind, is Similarly, in the n-th pulse output circuit 10_n of the second stage or later, the The signal from the pulse output circuit 10_(n+2) (hereafter referred to as the next-stage signal OUT(n+2) Therefore, the pulse output circuit of each stage outputs the pulse of the following stage and / or the two stages before it. The first output signal OUT(1)(SR) to OUT(N)( SR), and second output signals OUT(1) to OUT(N) are output to be input to another circuit, etc. However, as shown in FIG. 16(A), the last two stages of the shift register have Since the stage signal OUT(n+2) is not input, for example, a second start pulse In this case, a first start pulse SP2 and a second start pulse SP3 may be input.

[0334] The clock signal (CK) goes between H and L levels (L signal, low power supply potential) at regular intervals. Here, the first clock signal (CK1) to the second clock signal (CK2) are The four clock signals (CK4) are delayed by 1 / 4 of a period in sequence (i.e., 90 degrees from each other). In this embodiment, the first clock signal (CK1) to the fourth clock signal (CK2) are The clock signal (CK4) is used to control the driving of the pulse output circuit. The signal may be called GCK or SCK depending on the drive circuit to which it is input. I will explain as K.

[0335] FIG. 16B shows one of the pulse output circuits 10_n shown in FIG. 16A. The input terminal 21, the second input terminal 22, and the third input terminal 23 are connected to the first wiring 11 to the fourth wiring 12. For example, in FIG. 16(A), the first pad The pulse output circuit 10_1 has a first input terminal 21 electrically connected to a first wiring 11, The second input terminal 22 is electrically connected to the second wiring 12, and the third input terminal 23 is electrically connected to the third wiring 13. The second pulse output circuit 10_2 is electrically connected to the first input The terminal 21 is electrically connected to the second wiring 12, and the second input terminal 22 is electrically connected to the third wiring 13. The third input terminal 23 is electrically connected to the fourth wiring 14 .

[0336] Each of the first pulse output circuit 10_1 to the N-th pulse output circuit 10_N has a first input terminal a first input terminal 21, a second input terminal 22, a third input terminal 23, a fourth input terminal 24, a fifth input terminal The input terminal 25, the first output terminal 26, and the second output terminal 27 (see FIG. 16(B)). In the first pulse output circuit 10_1, a first clock signal is input to a first input terminal 21. A first clock signal CK1 is input to the first input terminal 22, a second clock signal CK2 is input to the third input terminal 23, and a third clock signal CK3 is input to the second input terminal 24. A third clock signal CK3 is input to the input terminal 23 of the second clock CLK1, and a start signal CK4 is input to the fourth input terminal 24 of the third clock CLK2. A pulse is input, the next stage signal OUT(3) is input to the fifth input terminal 25, and the first output A first output signal OUT(1)(SR) is output from a terminal 26, and a second output signal OUT(1)(SR) is output from a second output terminal 27. The second output signal OUT(1) is output.

[0337] The first pulse output circuit 10_1 to the N-th pulse output circuit 10_N are each a three-terminal thin-film transistor. In addition to TFTs (also called Thin Film Transistors), The four-terminal thin film transistor described in the above embodiment can be used. 1 shows a symbol of the four-terminal thin film transistor 28 described in the above embodiment. The symbol of the thin film transistor 28 shown in FIG. 16(C) corresponds to any one of the first to fifth embodiments. This term refers to the four-terminal thin-film transistor described above, and will be used below in the drawings, etc. In this specification, a thin film transistor has two gate electrodes via a semiconductor layer. In this case, the gate electrode below the semiconductor layer is called the lower gate electrode, and the gate electrode above the semiconductor layer is called the upper gate electrode. The gate electrode of the thin film transistor 28 is also called the upper gate electrode. A first control signal G1 is input to the gate electrode of the upper side of the gate electrode and a second control signal G2 is input to the gate electrode of the upper side of the gate electrode. It is an element that can perform electrical control between the In terminal and the Out terminal.

[0338] When an oxide semiconductor is used for a semiconductor layer including a channel formation region of a thin film transistor, The threshold voltage may shift to the negative or positive side depending on the process. Therefore, in a thin film transistor in which an oxide semiconductor is used for a semiconductor layer including a channel formation region, A configuration capable of controlling the threshold voltage is preferable. The threshold voltage of the thin film transistor 28 is determined by forming gate insulating films above and below the channel forming region of the thin film transistor 28. By providing a gate electrode through the gate electrode and controlling the potential of the upper and / or lower gate electrodes, Therefore, it is possible to control the temperature to a desired value.

[0339] Next, an example of a specific circuit configuration of the pulse output circuit shown in FIG. This is explained in (D).

[0340] The first pulse output circuit shown in FIG. 16(D) includes a first transistor 31 to a thirteenth transistor. The first input terminal 21 to the fifth input terminal 25 have a transistor 43. In addition, a power supply line 51 to which a first high power supply potential VDD is supplied and a power supply line 52 to which a second high power supply potential VCC is supplied are provided. A power supply line 52 to which a low power supply potential VSS is supplied, and a power supply line 53 to which a low power supply potential VSS is supplied, A signal or a power supply potential is supplied to the 31st to 13th transistors 43. A signal or the like is output to the first output terminal 26 and the second output terminal 27. The magnitude relationship of the power supply potentials of the power supply lines is as follows: the first power supply potential VDD is equal to or higher than the second power supply potential VCC. The second power supply potential VCC is a potential higher than the third power supply potential VSS. The first clock signal (CK1) to the fourth clock signal (CK4) go to the H level at regular intervals. The signal alternates between high and low levels. When it is high, it is VDD, and when it is low, it is VSS. It is assumed that the potential VDD of the power supply line 51 is higher than the potential VCC of the power supply line 52. This allows the potential applied to the gate electrode of a transistor to be reduced without affecting its operation. This can reduce the threshold voltage shift of the transistor and suppress degradation. As shown in FIG. 16D, the first transistor 31 to the thirteenth transistor The first transistor 31, the sixth transistor 36 to the ninth transistor 43 are For the transistor 39, it is preferable to use the four-terminal thin film transistor 28 shown in FIG. The first transistor 31 and the sixth to ninth transistors 36 to 39 are preferably The potential of the node to which either the source or drain electrode is connected is determined by the potential of the gate electrode. A transistor that is switched by a control signal input to its gate electrode. The response to the control signal is fast (the rise of the on-current is steep), which allows for pulse output. This is a transistor that can reduce malfunction of the circuit. By using the four-terminal thin film transistor 28, the threshold voltage can be controlled. In this way, it is possible to provide a pulse output circuit that can further reduce malfunctions. The first control signal G1 and the second control signal G2 are the same control signal, but different control signals may be used. The configuration may be such that the information is input.

[0341] In FIG. 16D, the first transistor 31 has a first terminal electrically connected to the power supply line 51. a second terminal electrically connected to a first terminal of a ninth transistor 39; The electrodes (lower gate electrode and upper gate electrode) are electrically connected to the fourth input terminal 24. The second transistor 32 has a first terminal electrically connected to the power supply line 53 and a second terminal The gate electrode is electrically connected to the first terminal of the ninth transistor 39 and the gate electrode is electrically connected to the first terminal of the fourth transistor 39. The third transistor 33 is electrically connected to the gate electrode of the first terminal The terminal is electrically connected to the first input terminal 21 and the second terminal is electrically connected to the first output terminal 26. The fourth transistor 34 has a first terminal electrically connected to the power supply line 53. The second terminal is electrically connected to the first output terminal 26. The fifth transistor 35 , the first terminal is electrically connected to the power supply line 53, and the second terminal is connected to the gate of the second transistor 32. and the gate electrode of the fourth transistor 34, the gate electrode of which is electrically connected to the fourth The sixth transistor 36 has a first terminal electrically connected to the input terminal 24 of the power supply The second terminal is electrically connected to the gate electrode of the second transistor 32 and the fourth The gate electrode of the transistor 34 is electrically connected to the gate electrode of the gate electrode (the lower gate electrode and The upper gate electrode of the seventh transistor is electrically connected to the fifth input terminal 25. The first terminal of the transistor 37 is electrically connected to the power supply line 52, and the second terminal of the transistor 37 is electrically connected to the eighth transistor 33. 8, and a gate electrode (a lower gate electrode and an upper gate electrode ) is electrically connected to the third input terminal 23. The eighth transistor 38 has a first terminal The electrode is connected to the gate electrode of the second transistor 32 and the gate electrode of the fourth transistor 34. The gate electrodes (the lower gate electrode and the upper gate electrode) are electrically connected to the second input terminal. The ninth transistor 39 has a first terminal electrically connected to the first transistor 22. a second terminal of the second transistor 31 and a second terminal of the second transistor 32; The terminals are the gate electrode of the third transistor 33 and the gate electrode of the tenth transistor 40. The gate electrodes (lower gate electrode and upper gate electrode) are electrically connected to the power supply line 5 The tenth transistor 40 has a first terminal electrically connected to the first input terminal 2. 21, the second terminal is electrically connected to the second output terminal 27, and the gate voltage The terminal of the eleventh transistor 39 is electrically connected to the second terminal of the ninth transistor 39. The first terminal of the power supply 41 is electrically connected to the power supply line 53, and the second terminal of the power supply 41 is electrically connected to the second output terminal 27. The gate electrodes of the second transistor 32 and the fourth transistor 33 are electrically connected to each other. The twelfth transistor 42 is electrically connected to the gate electrode of the first transistor 34. The terminal is electrically connected to the power supply line 53, and the second terminal is electrically connected to the second output terminal 27. The gate electrode of the seventh transistor 37 (the lower gate electrode and the upper gate electrode) The thirteenth transistor 43 has a first terminal electrically connected to the power supply line 53, the second terminal is electrically connected to the first output terminal 26, and the gate voltage The electrodes are connected to the gate electrodes (lower gate electrode and upper gate electrode) of the seventh transistor 37. are electrically connected.

[0342] In FIG. 16D, the gate electrode of the third transistor 33 and the gate electrode of the tenth transistor 4 The connection point of the gate electrode of transistor 0 and the second terminal of transistor 939 is referred to as node A. In addition, the gate electrode of the second transistor 32, the gate electrode of the fourth transistor 34, the second terminal of the fifth transistor 35, the second terminal of the sixth transistor 36, the second terminal of the eighth transistor The connection point of the first terminal of the transistor 38 and the gate electrode of the eleventh transistor 41 is node B. (See FIG. 17(A)).

[0343] FIG. 17A shows the pulse output circuit described in FIG. 16D as a first pulse output circuit 10_ 1, the first input terminal 21 to the fifth input terminal 25 and the first output terminal 26 and a signal input to or output from a second output terminal 27.

[0344] Specifically, a first clock signal CK1 is input to the first input terminal 21, and A second clock signal CK2 is input to the third input terminal 22, and a third clock signal CK3 is input to the third input terminal 23. A start pulse (SP1) is input to the fourth input terminal 24, and a fifth The next stage signal OUT(3) is input to the first input terminal 25, and the first output terminal 26 outputs the first output The signal OUT(1) (SR) is output, and the second output signal OUT( 1) is output.

[0345] A thin film transistor is defined as a transistor having at least three elements including a gate, a drain, and a source. A semiconductor device has a terminal and a channel region formed in a region overlapping with the gate. By controlling the gate potential, the drain and source are connected via the channel region. The current flowing between the source and drain can be controlled by the thin film transistor. Which is the source and which is the drain depends on the transistor structure and operating conditions, etc. Therefore, the regions that function as the source and drain are In some cases, the term "source" or "drain" is not used. In such cases, for example, They may be written as terminal or second terminal.

[0346] In FIG. 16(D) and FIG. 17(A), node A is put into a floating state, and the boot A capacitor may be provided separately to perform a strap operation. To achieve this, a capacitor having one electrode electrically connected to the node B may be provided separately.

[0347] Here, the timing of the shift register having a plurality of pulse output circuits shown in FIG. A shift register is a scanning line driver circuit. In this case, the period 61 in FIG. 17(B) corresponds to a vertical blanking period, and the period 62 corresponds to a gate selection period. do.

[0348] As shown in FIG. 17A, the ninth transistor in which the second power supply potential VCC is applied to the gate electrode By providing the transistor 39, the following can be achieved before and after the bootstrap operation: The advantages are as follows:

[0349] In the absence of the ninth transistor 39, the gate electrode of which is applied with the second power supply potential VCC, When the potential of the node A rises due to the base strap operation, the second transistor 31 The potential of the source terminal rises and becomes higher than the first power supply potential VDD. Then, the source of the first transistor 31 is switched to the first terminal side, that is, the power supply line 51 side. Therefore, in the first transistor 31, between the gate and the source, between the gate and the drain In both cases, a large bias voltage is applied, which places a large stress on the transistor. Therefore, the ninth power supply potential VCC is applied to the gate electrode. By providing the transistor 39, the voltage of the node A is increased by the bootstrap operation. The potential of the second terminal of the first transistor 31 is increased, but the potential of the second terminal of the first transistor 31 is not increased. That is, by providing the ninth transistor 39, It is possible to reduce the value of the negative bias voltage applied between the gate and source of the transistor 31. Therefore, by using the circuit configuration of this embodiment, the first transistor 31 The negative bias voltage applied between the gate and source can also be reduced, reducing the stress-induced Deterioration of the first transistor 31 can be suppressed.

[0350] The ninth transistor 39 is provided at a position corresponding to the second gate of the first transistor 31. A terminal is connected between the terminal and the gate of the third transistor 33 via a first terminal and a second terminal. In addition, in the present embodiment, a system having a plurality of pulse output circuits may be provided. In the case of a soft register, the signal line driver circuit has more stages than the scan line driver circuit. The resistor 39 may be omitted, which has the advantage of reducing the number of transistors.

[0351] Note that the semiconductor layers of the first to thirteenth transistors 31 to 43 are made of oxide semiconductor. By using a conductor, the off-current of the thin film transistor is reduced, and the on-current and Because it is possible to increase the field effect mobility and reduce the degree of degradation. In addition, a transistor using an oxide semiconductor can be used. Compared to transistors using amorphous silicon, a higher potential is applied to the gate electrode. Therefore, the degree of deterioration of the transistor due to the second power supply potential VCC is small. The same operation can be obtained by supplying the first power supply potential VDD to the power supply line, and the wiring between the circuits is Since the number of power supply lines can be reduced, the circuit can be made more compact.

[0352] The gate electrodes (lower gate electrode and upper gate electrode) of the seventh transistor 37 a clock signal provided by the third input terminal 23 to the gate of the eighth transistor 38; The input electrodes (lower gate electrode and upper gate electrode) are supplied with a second input terminal 22. The clock signal is applied to the gate electrode of the seventh transistor 37 (the lower gate electrode and the upper gate electrode). A clock signal is supplied to the gate electrode of the eighth transistor by the second input terminal 22. The gate electrodes of the gate electrodes of the first input terminal 23 are connected to the gate electrodes of the second input terminal 23. Therefore, the same effect can be obtained by switching the wiring so that the clock signal is supplied. At this time, in the shift register shown in FIG. The seventh transistor 37 is turned off and the eighth transistor 38 is turned on. The transistor 38 is on, then the seventh transistor 37 is off, and the eighth transistor By turning off the input terminal 38, the second input terminal 22 and the third input terminal 23 are The voltage drop at node B is generated by the gate of the seventh transistor 37. due to a drop in the potential of the gate electrode of the eighth transistor 38 and a drop in the potential of the gate electrode of the eighth transistor 39. On the other hand, when the shift register shown in FIG. 17(A) is As described above, the seventh transistor 37 and the eighth transistor 38 are both in an on state, and The seventh transistor 37 is on and the eighth transistor 38 is off. Then, the seventh By turning off the transistor 37 and the eighth transistor 38, The potential of the node B caused by the potential of the second input terminal 22 and the third input terminal 23 decreasing The decrease in the potential of the gate electrode of the eighth transistor 38 is reduced to one time. Therefore, the gate electrode of the seventh transistor 37 (the lower gate electrode and the upper A clock signal CK3 is supplied to the gate electrode of the eighth transistor from the third input terminal 23. The gate electrodes (lower gate electrode and upper gate electrode) of the transistor 38 are connected to the second input terminal 2. It is preferable that the clock signal CK2 is supplied from the This is because the number of times the potential of the node B changes is reduced, and noise can also be reduced.

[0353] In this manner, the potentials of the first output terminal 26 and the second output terminal 27 are maintained at the L level. By configuring the node B to periodically receive a high-level signal during the period, the pulse output This makes it possible to suppress malfunction of the power circuit.

[0354] This embodiment mode can be freely combined with other embodiment modes.

[0355] (Embodiment 11) The semiconductor device disclosed in this specification can be applied as electronic paper. Par can be used in any electronic device that displays information. For example, electronic paper can be used for electronic books, posters, train rides, etc. It can be used for in-car advertising, display on various cards such as credit cards, etc. An example of an electronic device is shown in Figure 20.

[0356] FIG. 20 shows an electronic book 2700. For example, the electronic book 2700 includes a housing 2701. The housing 2701 and the housing 2703 are The opening and closing operations are performed by using the shaft portion 2711 as an axis. With this configuration, it becomes possible to operate like a paper book.

[0357] A display unit 2705 is incorporated in the housing 2701, and a display unit 2707 is incorporated in the housing 2703. The display unit 2705 and the display unit 2707 are configured to display a continuous screen. Alternatively, a different screen may be displayed. For example, a text is displayed on the right display (display 2705 in FIG. 20) and An image can be displayed on the display unit 2707 in FIG.

[0358] FIG. 20 shows an example in which the housing 2701 is provided with an operation unit. 701, a power supply 2721, operation keys 2723, a speaker 2725, etc. The operation keys 2723 can be used to turn pages. The configuration may include a display board, a pointing device, etc. On the front side, there is a terminal for external connection (earphone terminal, USB terminal, or AC adapter and USB cable). A terminal that can be connected to various cables such as a USB cable, a recording medium insertion section, etc. Furthermore, the electronic book 2700 may be configured to have a function as an electronic dictionary. Good too.

[0359] The electronic book 2700 may be configured to transmit and receive information wirelessly. The desired book data can be purchased and downloaded from the electronic book server. is also possible.

[0360] (Embodiment 12) The semiconductor device disclosed in this specification can be applied to various electronic devices (including game machines). The electronic device can be, for example, a television device (television or television receivers), computer monitors, digital cameras, digital video cameras cameras, digital photo frames, mobile phones (also called mobile phones or mobile phone devices), (c) Portable game machines, personal digital assistants, audio playback devices, large game machines such as pachinko machines, etc. Some examples include:

[0361] FIG. 21A shows a television device 9600. The television device 9600 includes A display portion 9603 is incorporated in the housing 9601. In addition, in this example, the housing 9601 is supported by a stand 9605. This shows the configuration.

[0362] The television device 9600 can be operated using an operation switch on the housing 9601 or a separate remote control. This can be done by the remote control operation device 9610. The channel and volume can be controlled by the 9609, and the display 9603 shows In addition, the remote control unit 9610 can control the video. A display portion 9607 for displaying information output from 9610 may be provided.

[0363] The television device 9600 includes a receiver and a modem. It can receive more general television broadcasts, and can also be connected to a modem via wired or wireless connection. By connecting to a network, communication can be one-way (sender to receiver) or two-way. It is also possible to communicate information (between a sender and a receiver, or between receivers).

[0364] FIG. 21B shows a digital photo frame 9700. The display frame 9700 includes a display unit 9703 built into a housing 9701. 03 is capable of displaying various images, such as images taken with a digital camera. By displaying image data, it can function like a normal photo frame.

[0365] The Digital Photo Frame 9700 is equipped with an operation unit, external connection terminals (USB terminal, US A terminal that can be connected to various cables such as B cable, etc., and a recording medium insertion section, etc. These components may be installed on the same surface as the display unit, but they may be installed on the side or back. It is preferable to have a digital photo frame with a built-in memory card because it improves the design. A memory that stores image data taken with a digital camera is inserted into the body insertion section. The captured image data can be displayed on the display portion 9703 .

[0366] The digital photo frame 9700 may also be configured to transmit and receive information wirelessly. It is also possible to wirelessly import and display desired image data.

[0367] FIG. 22(A) shows a portable gaming machine, which is composed of two housings, a housing 9881 and a housing 9891. The housing 9881 is connected to a connector 9893 so as to be openable and closable. A display unit 9883 is incorporated in the housing 9891. The portable gaming machine shown in FIG. 22(A) also includes a speaker unit 9884 and a recording medium insertion unit 988. 6, LED lamp 9890, input means (operation keys 9885, connection terminals 9887, sensors 9 888 (force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, Chemicals, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration 9889) equipped with a microphone, etc. Of course, the configuration of the portable gaming machine is not limited to the above, and may be at least as described in the present specification. The present invention is not limited to the above, and may be applied to any configuration having the semiconductor device disclosed in the above and other auxiliary equipment. The portable game machine shown in FIG. 22(A) can be used to play a game recorded on a recording medium. The function of reading out the program or data and displaying it on the display unit, and wireless communication with other portable gaming machines The portable gaming machine shown in FIG. 22(A) has the following functions: The functions are not limited to these, and various functions can be provided.

[0368] FIG. 22(B) shows a slot machine 9900, which is a large-scale gaming machine. The slot machine 9900 includes a display unit 9903 built into a housing 9901. The 9900 also has other controls such as a start lever and stop switch, and a coin slot. , speakers, etc. Of course, the configuration of the slot machine 9900 is the same as that described above. There is no limitation, and any configuration including at least the semiconductor device disclosed in this specification may be used. Other auxiliary equipment may be provided as appropriate.

[0369] FIG. 23A is a perspective view showing an example of a portable computer.

[0370] The portable computer of FIG. 23(A) has an upper housing 9301 and a lower housing 9302 connected to each other. The hinge unit is closed to form an upper housing 9301 having a display unit 9303 and a keyboard. The lower housing 9302 having the base 9304 can be stacked on top of each other, making it easy to carry. This is convenient, and when the user wants to type on the keyboard, the hinge unit needs to be opened. The user can perform input operations by looking at the display portion 9303.

[0371] The lower housing 9302 also includes a keyboard 9304 and a pointing device for inputting data. If the display portion 9303 is a touch panel, Input operations can be performed by touching the screen. The lower housing 9302 has a computing function unit such as a disk. It has an external connection port 9305 into which a communication cable conforming to the communication standard of .

[0372] The upper housing 9301 further includes a display unit 93 that can be slid and stored inside the upper housing 9301. 07, it is possible to realize a wide display screen. The orientation of the display of the 9307 can be adjusted by the user. In this case, input operations can be performed by touching a part of the retractable display unit.

[0373] The display unit 9303 or the foldable display unit 9307 may be a liquid crystal display panel, an organic light emitting element, or The display device uses an image display device such as a light-emitting display panel using inorganic light-emitting elements.

[0374] The portable computer shown in FIG. 23A is configured with a receiver and the like, and is also a television. It is possible to receive broadcasts and display images on the display unit or the display unit. The hinge unit connecting the display unit 9301 and the lower housing 9302 is closed. 7. Slide the screen to expose the entire screen, and adjust the screen angle to watch TV broadcasts. In this case, the hinge unit can be opened to display the display unit 9303. Furthermore, it only activates the circuits that display TV broadcasts, so it consumes minimal power. This is useful for portable computers with limited battery capacity. do.

[0375] FIG. 23(B) shows a portable electronic device that can be worn on the user's arm like a wristwatch. FIG. 13 is a perspective view showing an example of a story.

[0376] This mobile phone is a main body having at least a communication device having a telephone function and a battery. A band part 9204 for attaching the body to the arm, and a fastening state of the band part 9204 to the arm are adjusted. The device is made up of an adjustment unit 9205 for adjusting the temperature, a display unit 9201, a speaker 9207, and a microphone 9208. It has been made.

[0377] The main body also has an operation switch 9203, which serves as a power input switch and a display switching switch. In addition to the switch and the imaging start command switch, for example, when you press the button, the Internet program Each function can be associated with another function, such as

[0378] Input operations of this mobile phone are performed by touching the display portion 9201 with a finger or an input pen, or by operating the mobile phone. This is done by operating a switch 9203 or by inputting voice into a microphone 9208. 23(B) shows a display button 9202 displayed on a display unit 9201. Input can be made by touching the screen with a finger or other object.

[0379] The main body also includes an imaging device that converts the subject image formed through the photographic lens into an electronic image signal. The camera unit 9206 has a step. Note that the camera unit does not necessarily have to be provided.

[0380] The mobile phone shown in FIG. 23(B) is configured with a television broadcast receiver and the like. It can receive TV broadcasts and display the images on the display unit 9201, and can also store data in memory, etc. It is possible to record television broadcasts in memory by using a storage device. The mobile phone shown in B) may have a function capable of collecting location information such as GPS.

[0381] The display unit 9201 is a light-emitting display panel such as a liquid crystal display panel, an organic light-emitting element, or an inorganic light-emitting element. The mobile phone shown in FIG. 23(B) is small and lightweight. Therefore, the battery capacity is limited, and the display device used for the display portion 9201 is a low-power display device. It is preferable to use a force actuable panel.

[0382] Although FIG. 23B illustrates an electronic device that is worn on the arm, the electronic device is not limited to this. It is sufficient that the device has a shape that can be carried around.

[0383] (Embodiment 13) In this embodiment mode, the thin film transistor shown in any of the first to sixth embodiments is used as one mode of a semiconductor device. An example of a display device having a star will be described with reference to FIGS. An example of a liquid crystal display device using a liquid crystal element as an element will be described with reference to FIGS. The TFTs 628 and 629 used in the liquid crystal display devices of FIGS. The thin film transistor shown in FIG. 6 can be applied to the thin film transistor according to the first embodiment, the fifth embodiment, or the sixth embodiment. A thin film transistor having high electrical characteristics and high reliability can be manufactured in the same manner as in the process shown in the sixth embodiment. be.

[0384] First, we will explain the VA (Vertical Alignment) type liquid crystal display device. VA type is a type of method for controlling the arrangement of liquid crystal molecules in a liquid crystal display panel. In a liquid crystal display device, when no voltage is applied, the liquid crystal molecules are oriented vertically to the panel surface. In this embodiment, a pixel is divided into several regions (sub-pixels). The liquid crystal molecules are tilted in a different direction in each cell. In the following explanation, multi-domain design is considered. A liquid crystal display device in which this has been considered will now be described.

[0385] 25 and 26 show a pixel electrode and a counter electrode, respectively. FIG. 2 is a plan view of the substrate side on which electrodes are formed, showing a cross-sectional structure corresponding to a cutting line EF shown in the figure. FIG. 24 shows the structure. FIG. 26 shows a plan view of the substrate on which the counter electrode is formed. The following description will be given with reference to these figures.

[0386] FIG. 24 shows a TFT 628, a pixel electrode layer 624 connected thereto, and a storage capacitor 630. The substrate 600 on which the counter electrode layer 640 and the like are formed is laminated on the counter substrate 601. 4 shows the state in which liquid crystal has been injected.

[0387] A colored film 636 and a counter electrode layer 640 are formed on the counter substrate 601. On the pixel electrode layer 624, an alignment film 648 is formed. An alignment film 646 is also formed on the counter electrode layer 640 and the protrusions 644. A liquid crystal layer 650 is formed between opposing substrates 601 .

[0388] On the substrate 600, a TFT 628, a pixel electrode layer 624 connected thereto, and a storage capacitor 6 The pixel electrode layer 624 includes a TFT 628, a wiring 616, and a storage capacitor 630. 30, an insulating film 620 and an insulating film 621 covering the insulating film 620 and the insulating film 621. The TFT 6 is connected to the wiring 618 through a contact hole 623 that penetrates the TFT 6 The thin film transistors shown in any of the embodiments 1 to 6 can be appropriately used for the transistor 28. The storage capacitor 630 is formed by forming a first capacitance wiring 602 of the TFT 628 at the same time. 04, a first gate insulating film 606a, a second gate insulating film 606b, and wiring 616, 6 It is composed of a second capacitance wiring 617 formed at the same time as 18 .

[0389] The pixel electrode layer 624, the liquid crystal layer 650, and the counter electrode layer 640 are overlapped to form a liquid crystal element. It has been made.

[0390] 25 shows a planar structure on a substrate 600. The pixel electrode layer 624 is made of the material shown in the first embodiment. The pixel electrode layer 624 is formed using a slit 625. The slit 625 is formed by This is to control the crystal orientation.

[0391] The TFT 629 and the pixel electrode layer 626 and the storage capacitor 631 connected thereto shown in FIG. The TFT 628, the pixel electrode layer 624, and the storage capacitor portion 630 can be formed in the same manner. Both the TFT 628 and the TFT 629 are connected to the wiring 616. The pixel of the panel is composed of pixel electrode layer 624 and pixel electrode layer 626. The pixel electrode layer 624 and the pixel electrode layer 626 are sub-pixels.

[0392] 26 shows the planar structure of the opposing substrate side. The opposing electrode layer 640 is the same as the pixel electrode layer 624. On the counter electrode layer 640, a protrusion for controlling the alignment of the liquid crystal is formed. In addition, in FIG. 26, the pixel electrode layer 624 formed on the substrate 600 is The counter electrode layer 640, the pixel electrode layer 624, and the pixel electrode layer 626 are indicated by dashed lines. The pole layers 626 are shown arranged one on top of the other.

[0393] The equivalent circuit of this pixel structure is shown in Figure 27. TFT628 and TFT629 both have gate The line 602 is connected to the wiring 616. In this case, the capacitance wiring 604 and the capacitance wiring 605 are connected to each other. By making the positions different, the operations of the liquid crystal elements 651 and 652 can be made different. That is, the potentials of the capacitance wiring 604 and the capacitance wiring 605 are individually controlled. The orientation of the liquid crystal is precisely controlled to widen the viewing angle.

[0394] When a voltage is applied to the pixel electrode layer 624 having the slit 625, The slit 625 and the protrusion on the opposing substrate 601 side cause distortion of the electric field (diagonal electric field). By arranging the 644 in an alternating pattern, a diagonal electric field is effectively generated, and the liquid crystal By controlling the orientation, the direction in which the liquid crystal is oriented can be made to differ depending on the location. The viewing angle of the LCD panel is expanded by creating a multi-domain structure.

[0395] Next, a VA type liquid crystal display device different from the above will be described with reference to FIGS. 28 to 31. do.

[0396] 28 and 29 show the pixel structure of a VA type liquid crystal display panel. FIG. 28 shows a cross-sectional structure corresponding to the cutting line YZ shown in the figure.

[0397] In this pixel structure, one pixel has multiple pixel electrodes, each of which is connected to a TFT. Each TFT is configured to be driven by a different gate signal. That is, in a pixel with a multi-domain design, the signals applied to each pixel electrode are independent. The control circuit has a configuration in which the

[0398] The pixel electrode layer 624 penetrates the insulating film 620, the insulating film 621, and the insulating film 622. In the contact hole 623, the wiring 618 is connected to the TFT 628. The electrode layer 626 is a contact hole that penetrates the insulating film 620, the insulating film 621, and the insulating film 622. In the contact hole 627, the wiring 619 is connected to the TFT 629. Different gate signals are applied to the gate wiring 602 of the TFT 628 and the gate wiring 603 of the TFT 629. On the other hand, the wiring 616 that functions as a data line is It is commonly used in the TFT628 and TFT629. The thin film transistors shown in the first to sixth embodiments can be used as appropriate. A first gate insulating film 606a is formed on the gate wiring 602, the gate wiring 603 and the capacitance wiring 690. A gate insulating film 606b is formed.

[0399] The pixel electrode layer 624 and the pixel electrode layer 626 have different shapes, and the pixel electrode layer 624 and the pixel electrode layer 626 are V-shaped. A pixel electrode layer 626 is formed so as to surround the outside of the pixel electrode layer 624. By applying different voltages to the electrode layer 626 to the TFTs 628 and 629, The equivalent circuit of this pixel structure is shown in Figure 31. The TFT 629 is connected to the gate wiring 603. The TFT 628 and the TFT 629 are both connected to the wiring 616. By applying different gate signals to the gate wiring 603, the liquid crystal element 651 and the liquid crystal element 652 are operated. In other words, the operation of the TFT628 and TFT629 can be controlled separately. By controlling the liquid crystal orientation of the liquid crystal elements 651 and 652, the viewing angle can be precisely controlled. You can widen the corners.

[0400] A colored film 636 and a counter electrode layer 640 are formed on the counter substrate 601. A flattening film 637 is formed between the electrode layer 636 and the counter electrode layer 640 to prevent the alignment of the liquid crystal from being disturbed. FIG. 30 shows the planar structure of the opposing substrate side. The opposing electrode layer 640 is shared between different pixels. The electrode is connected to the substrate, and has a slit 641 formed therein. The element electrode layer 624 and the slits 625 on the pixel electrode layer 626 side are arranged so as to interdigitate with each other. By doing so, it is possible to effectively generate an oblique electric field and control the alignment of the liquid crystal. This allows the orientation direction of the liquid crystal to vary depending on the location, thereby widening the viewing angle. In addition, in FIG. 30, the pixel electrode layer 624 and the pixel electrode layer 626 formed on the substrate 600 are indicated by dashed lines. , the counter electrode layer 640, the pixel electrode layer 624, and the pixel electrode layer 626 are arranged to overlap each other. It shows how it is placed.

[0401] An alignment film 648 is formed on the pixel electrode layer 624 and the pixel electrode layer 626. An alignment film 646 is also formed on the layer 640. The pixel electrode layer 624, the liquid crystal layer 650, and the counter electrode layer 640 are formed. The pixel electrode layer 626 and the liquid crystal layer 627 are overlapped to form a first liquid crystal element. The layer 650 and the counter electrode layer 640 overlap each other to form a second liquid crystal element. The pixel structure of the display panel described in FIG. 28 to FIG. 31 has a first liquid crystal element and a second liquid crystal element in one pixel. The display has a multi-domain structure in which crystal elements are provided.

[0402] Next, we will explain the in-plane switching type liquid crystal display device. In the in-plane switching type, This method applies an electric field in the horizontal direction to drive the liquid crystal and express gradation. If this is done, the viewing angle can be expanded to approximately 180 degrees. A liquid crystal display device to be used will be described.

[0403] FIG. 32 shows a structure in which an electrode layer 607, a TFT 628, and a pixel electrode layer 624 connected to the TFT 628 are formed. The substrate 600 and the opposing substrate 601 are overlapped and liquid crystal is injected. A colored film 636, a planarizing film 637, etc. are formed on the opposing substrate 601. The electrode layer is on the substrate 600 side, and is not provided on the opposing substrate 601 side. A liquid crystal layer 650 is disposed between the substrate 600 and the opposing substrate 601 via an alignment film 646 and an alignment film 648. has been formed.

[0404] On the substrate 600, an electrode layer 607, a capacitance wiring 604 connected to the electrode layer 607, and a T The capacitance wiring 604 is formed at the same time as the gate wiring 602 of the TFT 628. The TFT 628 can be formed using the thin film transistor shown in any one of the first to fifth embodiments. The electrode layer 607 may be the pixel electrode layer described in any of the embodiments 1 to 6. The electrode layer 607 may be formed of a similar material. A first gate insulating film 606a is formed on the electrode layer 607 and the capacitor wiring 604. Then, a second gate insulating film 606b is formed.

[0405] The wiring 616 and the wiring 618 of the TFT 628 are connected to the first gate insulating film 606a and the second gate insulating film 606b. The wiring 616 is formed on the insulating film 606b. It is a data line that extends in one direction, and at the same time, it is the source region or drain of the TFT628. The wiring 618 is connected to the source and drain regions. This is the other electrode of the drain, and is a wiring connected to the pixel electrode layer 624.

[0406] An insulating film 620 and an insulating film 621 are formed over the wiring 616 and the wiring 618. On the insulating film 620, a wiring is formed through a contact hole 623 formed in the insulating film 620. A pixel electrode layer 624 is formed to connect to the line 618. The pixel electrode layer 624 is the same as that of the first embodiment. It is formed using the same material as the pixel electrodes shown in .

[0407] In this manner, the TFT 628 and the pixel electrode layer 624 connected thereto are formed on the substrate 600. The storage capacitor is formed between the electrode layer 607 and the pixel electrode layer 624.

[0408] 33 is a plan view showing the configuration of a pixel electrode. The surface structure is shown in Figure 32. The pixel electrode layer 624 is provided with a slit 625. The liquid crystal alignment layer 625 is for controlling the alignment of the liquid crystal. In this case, the electric field is applied to the electrode layer 607 and The first gate electrode layer 607 is located between the pixel electrode layer 624 and the pixel electrode layer 624. A first gate insulating film 606a and a second gate insulating film 606b are formed. The thickness of the first gate insulating film 606a and the second gate insulating film 606b is 50 to 200 nm, and Since the thickness of the liquid crystal layer is sufficiently thin compared to the thickness of the liquid crystal layer, which is m, the An electric field is generated in the direction parallel to the substrate. This electric field controls the alignment of the liquid crystal. The liquid crystal molecules are rotated horizontally using an electric field in the direction. In this case, the liquid crystal molecules are in any state. Because it is horizontal, the viewing angle has little effect on contrast and other aspects. In addition, since the electrode layer 607 and the pixel electrode layer 624 are both light-transmitting electrodes, the aperture ratio can be improved.

[0409] Next, another example of a liquid crystal display device of the lateral electric field type will be described.

[0410] Figures 34 and 35 show the pixel structure of an IPS type liquid crystal display device. Figure 35 is a plan view. The cross-sectional structure corresponding to the section line VW shown in the figure is shown in FIG. The following description will be given with reference to these two figures.

[0411] FIG. 34 shows a substrate 600 on which a TFT 628 and a pixel electrode layer 624 connected thereto are formed, The opposing substrate 601 is overlapped and liquid crystal is injected. A color film 636, a flattening film 637, etc. are formed on the opposing substrate 601 side. Between the substrate 600 and the counter substrate 601, an alignment film 646 and an alignment film 64 A liquid crystal layer 650 is formed via the substrate 8 .

[0412] A common potential line 609 and a TFT 628 are formed on the substrate 600. 9 can be formed simultaneously with the gate wiring 602 of the TFT 628. For this, the thin film transistor described in any of Embodiments 1 to 6 can be applied.

[0413] The wiring 616 and the wiring 618 of the TFT 628 are connected to the first gate insulating film 606a and the second gate insulating film 606b. The wiring 616 is formed on the insulating film 606b. It is a data line that extends in one direction, and at the same time, it is the source region or drain of the TFT628. The wiring 618 is connected to the source and drain regions. This is the other electrode of the drain, and is a wiring connected to the pixel electrode layer 624.

[0414] An insulating film 620 and an insulating film 621 are formed over the wiring 616 and the wiring 618. On the insulating films 620 and 621, a contact hole 623 is formed in the insulating films 620 and 621. A pixel electrode layer 624 is formed on the substrate 611 and connected to the wiring 618. The pixel electrode layer is formed using the same material as that shown in the first to sixth embodiments. As shown in the figure, the pixel electrode layer 624 generates a horizontal electric field together with the comb-shaped electrode formed at the same time as the common potential line 609. The comb-tooth portion of the pixel electrode layer 624 is formed to be the same as the common potential line 609. The electrodes are formed so as to interdigitate with the comb-shaped electrodes formed at the time.

[0415] When an electric field is generated between the potential applied to the pixel electrode layer 624 and the potential of the common potential line 609, The orientation of the liquid crystal is controlled by this electric field. Rotate the molecules horizontally. In this case, the liquid crystal molecules are horizontal in any state, so the viewing angle This has little effect on contrast, etc., and results in a wider viewing angle.

[0416] In this manner, the TFT 628 and the pixel electrode layer 624 connected thereto are formed on the substrate 600. The storage capacitor is formed by a first gate insulating film 606 between a common potential line 609 and a capacitor electrode 615. a, a second gate insulating film 606b is provided, thereby forming a capacitance electrode 615 and a pixel. The electrode layers 624 are connected via contact holes 633 .

[0417] Next, a configuration of a TN type liquid crystal display device will be described.

[0418] Figures 36 and 37 show the pixel structure of a TN type liquid crystal display device. Figure 37 is a plan view. The cross-sectional structure corresponding to the cutting line KL shown in the figure is shown in FIG. The following description will be given with reference to these two figures.

[0419] The pixel electrode layer 624 is formed by contact holes 623 and wirings formed in the insulating films 620 and 621. The wiring 616, which functions as a data line, is connected to the TFT 628 via the T The TFT 628 is connected to any one of the TFTs shown in the first to sixth embodiments. can be applied.

[0420] The pixel electrode layer 624 is formed using the pixel electrode layer 456 described in Embodiment 1. The gate wiring 604 can be formed simultaneously with the gate wiring 602 of the TFT 628. A first gate insulating film 606a and a second gate insulating film 606b are formed on the wiring 602 and the capacitance wiring 604. The storage capacitor is formed by forming a first gate between the capacitor wiring 604 and the capacitor electrode 615. The capacitor electrode 615 is formed via a first gate insulating film 606a and a second gate insulating film 606b. and the pixel electrode layer 624 are connected via a contact hole 633 .

[0421] A colored film 636 and a counter electrode layer 640 are formed on the counter substrate 601. A flattening film 637 is formed between the electrode layer 636 and the counter electrode layer 640 to prevent the alignment of the liquid crystal from being disturbed. The liquid crystal layer 650 is provided between the pixel electrode layer 624 and the counter electrode layer 640 with an alignment film 648 and an alignment layer 649. It is formed through a membrane 646 .

[0422] The pixel electrode layer 624, the liquid crystal layer 650, and the counter electrode layer 640 are overlapped to form a liquid crystal element. It has been made.

[0423] The colored film 636 may be formed on the substrate 600 side. A polarizing plate is attached to the surface opposite to the surface on which the transistors are formed, and a counter substrate 601 A polarizing plate can be attached to the surface opposite to the surface on which the counter electrode layer 640 is formed. do.

[0424] Through the above steps, a liquid crystal display device can be manufactured as a display device. The liquid crystal display device has a high aperture ratio. [Explanation of symbols]

[0425] 10 Pulse output circuit 11 Wiring 12 Wiring 13 Wiring 14 Wiring 15 Wiring 21 Input terminal 22 Input terminal 23 Input terminal 24 Input terminals 25 Input terminal 26 Output terminal 27 Output terminal 28 Thin-film transistor 31 Transistor 32 Transistor 33 Transistor 34 Transistor 35 Transistor 36 Transistor 37 Transistor 38 Transistor 39 Transistor 40 Transistor 41 Transistor 42 Transistor 43 Transistor 51 Power line 52 Power line 53 Power line 61 period 62 period 200 boards 203 Protective insulation layer 204 Planarizing insulating layer 210 Thin-film transistor 216 Oxide insulating layer 217 Conductive Layer 220 Thin-film transistor 224 Contact Hole 225 Contact Hole 227 Pixel electrode layer 230 Capacitive wiring layer 231 Capacitive electrode 232 Gate wiring layer 234 Source wiring 235 Terminal electrode 236 Metal wiring layer 237 Metal wiring layer 238 Gate wiring layer 240 Thin-film transistor 241 Metal wiring layer 242 Metal wiring layer 250 capacitive wiring layer 252 Oxide semiconductor layer 400 Substrates 401 Gate electrode layer 402a first gate insulating layer 402b Second gate insulating layer 403 Oxide semiconductor layer 405a Source electrode layer 405b Drain electrode layer 406 Conductive Layer 407 Oxide insulating layer 408 Protective insulation layer 409 Planarizing Insulation Layer 431 First high-resistance drain region 432 Second high-resistance drain region 433 Oxide Semiconductor Layer 434 Channel formation region 435 Metal electrode layer 436 Resist Mask 437 Resist Mask 451 Gate electrode layer 453 Oxide Semiconductor Layer 454 Channel forming region 455a Source electrode layer 455b Drain electrode layer 456 Pixel electrode layer 457 Oxide Semiconductor Layer 458 Oxide Semiconductor Layer 459 Oxide Semiconductor Layer 460 Thin Film Transistor 461 Thin-film transistor 470 Thin Film Transistor 471 Thin-film transistor 580 Substrate 581 Thin Film Transistor 583 Insulating Film 585 Insulation Layer 587 Electrode layer 588 Electrode layer 589 Spherical particles 590a black area 590b White area 595 Filling material 596 Board 600 Substrates 601 Opposing substrate 602 Gate wiring 603 Gate wiring 604 Capacitance wiring 605 Capacitance wiring 606a First gate insulating film 606b Second gate insulating film 607 Electrode layer 609 Common potential line 615 Capacitive electrode 616 Wiring 617 Capacitance wiring 618 Wiring 619 Wiring 620 Insulating film 621 Insulating film 622 Insulating film 623 Contact Hole 624 Pixel electrode layer 625 Slit 626 Pixel electrode layer 627 Contact Hole 628 TFT 629 TFT 630 Holding capacity section 631 Holding capacity section 633 Contact Hole 636 Colored film 637 Planarization film 640 Counter electrode layer 641 Slit 644 Protrusion 646 Orientation Film 648 Orientation Film 650 Liquid crystal layer 651 Liquid crystal element 652 Liquid crystal element 690 Capacitance wiring 2600 TFT substrate 2601 Opposing substrate 2602 Sealing material 2603 Pixel section 2604 Display element 2605 Colored layer 2606 Polarizing plate 2607 Polarizing plate 2608 Wiring circuit section 2609 Flexible wiring board 2610 cold cathode tube 2611 Reflector 2612 Circuit Board 2613 Diffuser 2700 e-books 2701 Case 2703 Case 2705 ​​Display section 2707 Display section 2711 Shaft 2721 Power supply 2723 Operation key 2725 Speaker 4001 Substrate 4002 Pixel section 4003 Signal line driver circuit 4004 Scanning line driver circuit 4005 Sealing material 4006 Substrate 4008 Liquid crystal layer 4010 Thin film transistor 4011 Thin film transistor 4013 Liquid crystal element 4015 Connection terminal electrode 4016 Terminal electrode 4018 FPC 4019 Anisotropic conductive film 4020 Insulation layer 4021 Insulation layer 4030 Pixel electrode layer 4031 Counter electrode layer 4032 Insulation layer 4040 Conductive layer 4501 Board 4502 Pixel section 4503a, 4503b Signal line driver circuit 4504a, 4504b Scanning line driver circuit 4505 Sealing material 4506 Board 4507 Filling material 4509 Thin-film transistor 4510 Thin-film transistor 4511 Light emitting element 4512 Electroluminescent layer 4513 Electrode layer 4515 Connection terminal electrode 4516 Terminal electrode 4517 Electrode layer 4518a, 4518b FPC 4519 Anisotropic conductive film 4520 Bulkhead 4540 Conductive layer 4544 Insulation layer 5300 Board 5301 Pixel unit 5302 Scanning line driver circuit 5303 Scanning line driver circuit 5304 Signal line driver circuit 5305 Timing Control Circuit 5601 Shift Register 5602 Switching Circuit 5603 Thin Film Transistor 5604 Wiring 5605 Wiring 6400 pixels 6401 Switching transistor 6402 Light emitting device driving transistor 6403 Capacitor 6404 Light emitting element 6405 Signal Line 6406 scan lines 6407 Power line 6408 Common electrode 7001 TFT 7002 Light emitting element 7003 Cathode 7004 Light-emitting layer 7005 Anode 7008 Cathode 7009 Bulkhead 7011 Light emitting element driving TFT 7012 Light emitting element 7013 Cathode 7014 Light-emitting layer 7015 Anode 7016 Shielding membrane 7017 Conductive film 7018 Conductive film 7019 Bulkhead 7021 Light-emitting element driving TFT 7022 Light emitting element 7023 Cathode 7024 Light-emitting layer 7025 Anode 7027 Conductive film 7028 Conductive film 7029 Bulkhead 9201 Display section 9202 Display button 9203 Operation switch 9205 Adjustment part 9206 Camera Department 9207 Speaker 9208 Mike 9301 Upper housing 9302 Lower housing 9303 Display section 9304 Keyboard 9305 External connection port 9306 Pointing Device 9307 Display section 9600 Television Equipment 9601 Case 9603 Display section 9605 Stand 9607 Display section 9609 Operation key 9610 Remote control device 9700 Digital Photo Frame 9701 Case 9703 Display section 9881 Case 9882 Display section 9883 Display section 9884 Speaker section 9885 Operation key 9886 Recording medium insertion section 9887 Connection terminal 9888 Sensor 9889 Microphone 9890 LED Lamp 9891 Case 9893 Connection section 9900 Slot Machine 9901 Case 9903 Display Department

Claims

[Claim 1] A pixel portion having a first thin film transistor and a driver circuit having a second thin film transistor are provided over the same substrate, the first thin film transistor includes a gate electrode layer over a substrate, a gate insulating layer over the gate electrode layer, a source electrode layer and a drain electrode layer over the gate insulating layer, an oxide semiconductor layer over the gate insulating layer and overlapping with the source electrode layer and the drain electrode layer, and a protective insulating layer in contact with the oxide semiconductor layer; A pixel electrode layer is provided on the protective insulating layer, each of the gate electrode layer, the gate insulating layer, the oxide semiconductor layer, the source electrode layer, the drain electrode layer, the protective insulating layer, and the pixel electrode layer of the first thin film transistor has a light-transmitting property; a source electrode layer and a drain electrode layer of the second thin film transistor are made of a different material from the source electrode layer and the drain electrode layer of the first thin film transistor and are made of a conductive material having a lower resistance than the source electrode layer and the drain electrode layer of the first thin film transistor.

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