Semiconductor device and manufacturing method thereof

Abstract

To provide a manufacturing method of a semiconductor device that improves a yield.SOLUTION: A manufacturing method of a semiconductor device includes the steps of: forming a second silicon carbide layer which has different first conductive type impurity density from a first silicon carbide layer and has a first thickness D2 in a first region on an upper surface of the first conductive type first silicon carbide layer; forming a second conductive type third silicon carbide layer which has a thickness D4 in a second region of the upper surface; forming a fourth silicon carbide layer which has lower first conductive type impurity density than the second silicon carbide layer and a thickness D1 on the first silicon carbide layer; measuring the second thickness D3 of the second silicon carbide layer and the thickness D1 of the fourth silicon carbide layer in the direction from the first silicon carbide layer toward the fourth silicon carbide layer after forming the fourth silicon carbide layer; and forming a trench with a predetermined depth, penetrating through the fourth silicon carbide layer and reaching the third silicon carbide layer on the basis of the thickness D1 of the fourth silicon carbide layer, the first thickness D2 and the second thickness D3 of the second silicon carbide layer, and the thickness D4 of the third silicon carbide layer.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] 1. Field of the Invention The present invention relates to a semiconductor device and a manufacturing method thereof. [Background technology]

[0002] SiC (silicon carbide) is expected to be a material for next-generation semiconductor devices. Compared to Si (silicon), silicon carbide has about three times the band gap, about ten times the breakdown electric field strength, and about three times the thermal conductivity. Therefore, by using SiC, it is possible to realize semiconductor devices that are low-loss and capable of operating at high temperatures. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2019-004010 A [Patent Document 2] JP 2017-050516 A Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a semiconductor device and a manufacturing method thereof with improved yield. [Means for solving the problem]

[0005] A method for manufacturing a semiconductor device according to an embodiment includes the steps of: forming a second silicon carbide layer having a first thickness D2 and a first conductivity type impurity density different from that of the first silicon carbide layer in a first region on an upper surface of a first silicon carbide layer of a first conductivity type; forming a third silicon carbide layer of a second conductivity type and a thickness D4 in a second region on the upper surface; and forming a fourth silicon carbide layer having a first conductivity type impurity concentration lower than that of the second silicon carbide layer and a thickness D1 on the first silicon carbide layer. the step of measuring a second film thickness D3 of the second silicon carbide layer and a film thickness D1 of the fourth silicon carbide layer in a direction from the first silicon carbide layer to the fourth silicon carbide layer after the fourth silicon carbide layer is formed; and the step of forming a trench of a predetermined depth that penetrates the fourth silicon carbide layer and reaches the third silicon carbide layer based on the film thickness D1 of the fourth silicon carbide layer, the first film thickness D2 and the second film thickness D3 of the second silicon carbide layer, and the film thickness D4 of the third silicon carbide layer. [Brief description of the drawings]

[0006] [Figure 1] 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment. [Diagram 2] FIG. 4 is a schematic diagram showing an example of a location where a first region is disposed. [Diagram 3] 2A to 2C are schematic cross-sectional views showing a manufacturing process of the semiconductor device according to the first embodiment. [Figure 4] FIG. 11 is a schematic cross-sectional view of a semiconductor device according to a second embodiment. [Diagram 5] 5A to 5C are schematic cross-sectional views showing a manufacturing process of the semiconductor device according to the second embodiment. [Figure 6] FIG. 11 is a schematic cross-sectional view of a semiconductor device according to a third embodiment. [Figure 7] 10A to 10C are schematic cross-sectional views showing a manufacturing process of the semiconductor device according to the third embodiment. [Figure 8] FIG. 13 is a schematic cross-sectional view of a semiconductor device according to a fourth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the following description, the same members are designated by the same reference numerals, and the description of members that have already been described will be omitted as appropriate.

[0008] In the following description, n + , n, n - And, p + , p, p - When the notations are used, these notations indicate the relative high and low impurity concentrations in each conductivity type. + has a relatively higher n-type impurity concentration than n, - indicates that the n-type impurity concentration is relatively lower than that of n. + has a relatively higher p-type impurity concentration than p, - indicates that the p-type impurity concentration is relatively lower than that of p. + type, n - The types are simply n-type and p-type. + type, p - The type is sometimes simply referred to as p-type.

[0009] The impurity concentration can be measured by CV measurement (capacitance measurement). The impurity concentration can also be measured by, for example, SIMS (Secondary Ion Mass Spectrometry). The relative level of the impurity concentration can also be determined from the level of the carrier concentration obtained by, for example, SCM (Scanning Capacitance Microscopy). The distance, such as the depth, of the impurity region can be obtained by, for example, SIMS. The distance, such as the width and depth of the impurity region can also be obtained from, for example, an SCM image.

[0010] Hereinafter, the first conductivity type will be referred to as n-type, and the second conductivity type will be referred to as p-type.

[0011] In this specification, in order to indicate the positional relationship of parts, etc., the upward direction of the drawing is described as "upper" and the downward direction of the drawing is described as "lower." In this specification, the concepts of "upper" and "lower" are not necessarily terms that indicate a relationship with the direction of gravity.

[0012] (First embodiment) The method for manufacturing a semiconductor substrate of this embodiment includes the steps of: forming a second silicon carbide layer having a first thickness D2 and a first conductivity type impurity density different from that of the first silicon carbide layer in a first region on the upper surface of a first silicon carbide layer of a first conductivity type; forming a third silicon carbide layer of the second conductivity type and having a thickness D4 in a second region on the upper surface; and forming a fourth silicon carbide layer having a first conductivity type impurity concentration lower than that of the second silicon carbide layer and having a thickness D1 on the first silicon carbide layer. the step of measuring a second film thickness D3 of the second silicon carbide layer and a film thickness D1 of the fourth silicon carbide layer in a direction from the first silicon carbide layer to the fourth silicon carbide layer after the fourth silicon carbide layer is formed; and the step of forming a trench of a predetermined depth that penetrates the fourth silicon carbide layer and reaches the third silicon carbide layer based on the film thickness D1 of the fourth silicon carbide layer, the first film thickness D2 and the second film thickness D3 of the second silicon carbide layer, and the film thickness D4 of the third silicon carbide layer.

[0013] FIG. 1 is a schematic cross-sectional view of a semiconductor device 100 according to the present embodiment.

[0014] The semiconductor device 100 comprises a first electrode 60, a silicon carbide substrate 2, a first silicon carbide layer 4, a second silicon carbide layer 20, a third silicon carbide layer 22, a fourth silicon carbide layer 24, a fifth silicon carbide layer 26, a sixth silicon carbide layer 28, a trench 70, a first insulating film 72, a second insulating film 74, a second electrode 62, and a third electrode 64.

[0015] The semiconductor device 100 of this embodiment is a trench-type metal insulator semiconductor field effect transistor (MISFET). Note that a metal oxide semiconductor field effect transistor (MOSFET) is a type of MISFET.

[0016] Here, an X direction, a Y direction perpendicular to the X direction, and a Z direction perpendicular to the X direction and the Y direction are defined. The first electrode 60, the silicon carbide substrate 2, the first silicon carbide layer 4, the fourth silicon carbide layer 24, and the third electrode 64 are provided parallel to each other in the XY plane. The Z direction is parallel to the direction in which the first electrode 60, the silicon carbide substrate 2, the first silicon carbide layer 4, the fourth silicon carbide layer 24, and the third electrode 64 are stacked. The Z direction is parallel to the direction from the first electrode 60 to the third electrode 64.

[0017] n + The silicon carbide substrate 2 is doped with n-type impurities at a concentration of, for example, 1×10 18 atoms / cm 3 More than 1×10 19 atoms / cm 3 Here, the n-type impurity is, for example, N (nitrogen). However, the n-type impurity may be, for example, P (phosphorus). The n-type impurity may be, for example, both N (nitrogen) and P (phosphorus). The silicon carbide substrate 2 is, for example, a hexagonal SiC substrate (n + The silicon carbide substrate 2 is a substrate that functions as, for example, the drain of a MISFET.

[0018] n - A first silicon carbide layer 4 having an n-type impurity is provided on a silicon carbide substrate 2. The first silicon carbide layer 4 is doped with an n-type impurity of, for example, 1×10 15 atoms / cm 3 5×10 or more 16 atoms / cm 3 The following is included. The film thickness of the first silicon carbide layer 4 is, for example, 4 μm or more and 50 μm or less. The first silicon carbide layer 4 is, for example, a silicon carbide layer formed on the silicon carbide substrate 2 by epitaxial growth using a CVD method (Chemical Vapor Deposition method). The first silicon carbide layer 4 is, for example, a layer that functions as a drift layer of a MISFET.

[0019] The first silicon carbide layer 4 has a first surface 6 and a second surface 8. The second surface 8 is provided on the side opposite to the first surface 6. The second surface 8 is in contact with, for example, the silicon carbide substrate 2. The first surface 6 is an example of an upper surface.

[0020] The n-type second silicon carbide layer 20 is provided in the first region 10 of the first surface 6. The n-type impurity concentration of the second silicon carbide layer 20 is different from the n-type impurity concentration of the first silicon carbide layer 4. However, when the second silicon carbide layer 20 is used as a current diffusion layer of a MOSFET, the n-type impurity concentration of the second silicon carbide layer 20 is preferably higher than the n-type impurity concentration of the first silicon carbide layer 4. Hereinafter, the description will be given assuming that the n-type impurity concentration of the second silicon carbide layer 20 is higher than the n-type impurity concentration of the first silicon carbide layer 4. The second silicon carbide layer 20 contains, for example, 5×10 n-type impurities. 16 atoms / cm 3 5×10 or more 17 atoms / cm 3 The following is included. The film thickness of the second silicon carbide layer 20 is, for example, 0.2 μm or more and 1.0 μm or less. The second silicon carbide layer 20 is a CV measurement base doped layer used for CV measurement of the impurity concentration, which will be described later. The second silicon carbide layer 20 is formed, for example, by ion implantation of n-type impurities into the first region 10 using a patterned hard mask or the like (not shown). Here, as the hard mask, for example, a silicon oxide film or a silicon nitride film is preferably used.

[0021] Fig. 2 is a schematic diagram showing an example of a location where the first region 10 is arranged. Fig. 2(a) is a schematic top view of a wafer 200 on which the semiconductor device 100 of this embodiment is manufactured. The semiconductor device 100 is provided on a semiconductor chip 150. The semiconductor chip 150 is obtained by dicing the wafer 200.

[0022] The TEG (Test Element Group) region (TEG chip) 10b is an example of a region in which the first region 10 is arranged. The TEG region 10b4 is provided at the edge of the wafer surface of the wafer 200. The TEG region 10b1, the TEG region 10b2, and the TEG region 10b3 are provided in a portion of the wafer surface of the wafer 200 closer to the center than the TEG region 10b4. The TEG region is a region in which a test chip formed on the wafer 200 is provided in order to evaluate a semiconductor process or a semiconductor device. The size of the TEG region 10b may be appropriately changed according to the width of a CV measurement probe R described later.

[0023] The dicing region (scribe lane) 10c is another example of a region in which the first region 10 is arranged. The dicing region 10c is provided between the respective semiconductor chips 150. The dicing region 10c is a region that is cut by a dicing blade or the like during dicing. Note that the size of the dicing region (scribe lane) 10c may be appropriately changed in accordance with the width of the CV measurement probe R described later.

[0024] FIG. 2(b) is a diagram showing another example of the region where the first region 10 is arranged. Here, FIG. 2(b) shows a semiconductor chip 180 as an example. FIG. 2(b) is a schematic top view of the semiconductor chip 180. A peripheral region 92 is provided around the device region (active region) 90. The peripheral region 92 is another example of the region where the first region 10 is arranged. Note that the size of the peripheral region 92 may be appropriately changed in accordance with the width of the CV measurement probe R described later.

[0025] The location where the first region 10 is arranged is not limited to the above location.

[0026] The p-type third silicon carbide layer 22 is provided in the second region 12 of the first surface 6. The third silicon carbide layer 22 is a layer provided at a location where the bottom of the trench 70 is to be provided in order to alleviate the electric field at the bottom of the trench 70, which will be described later. The third silicon carbide layer 22 is doped with a p-type impurity of, for example, 5×10 16atoms / cm 3 5×10 or more 17 atoms / cm 3 The following is included. The film thickness of the third silicon carbide layer 22 is, for example, 0.2 μm or more and 1.0 μm or less. The p-type impurity is, for example, Al (aluminum). The third silicon carbide layer 22 is formed by ion implantation into the second region 12 using, for example, a patterned hard mask not shown. Note that in FIG. 1, the length in the X direction of the first region 10 and the length in the X direction of the second region 12 are illustrated as being approximately the same. However, the length in the X direction of the first region 10 may be changed as appropriate in accordance with the width of a CV measurement probe R described later.

[0027] n - The fourth silicon carbide layer 24 of the type is provided on the first silicon carbide layer 4, the second silicon carbide layer 20, and the third silicon carbide layer 22. The fourth silicon carbide layer 24 is a layer formed on the first silicon carbide layer 4, the second silicon carbide layer 20, and the third silicon carbide layer 22 after the second silicon carbide layer 20 and the third silicon carbide layer 22 are formed. The fourth silicon carbide layer 24 is a layer that functions as a drift layer of a MISFET, for example. The fourth silicon carbide layer 24 is doped with an n-type impurity of 1×10 15 atoms / cm 3 5×10 or more 16 atoms / cm 3 The n-type impurity concentration of the fourth silicon carbide layer 24 is lower than the n-type impurity concentration of the second silicon carbide layer 20. The film thickness of the fourth silicon carbide layer 24 is, for example, not less than 0.5 μm and not more than 2 μm.

[0028] The p-type fifth silicon carbide layer 26 is provided on the fourth silicon carbide layer 24. The fifth silicon carbide layer 26 functions as a base of the MISFET. A fifth silicon carbide layer 26a and a fifth silicon carbide layer 26b are illustrated in FIG.

[0029] The n-type sixth silicon carbide layer 28 is provided on the fifth silicon carbide layer 26. The sixth silicon carbide layer 28 functions as a contact layer of the MISFET. In FIG. 1, the sixth silicon carbide layer 28a and the sixth silicon carbide layer 28b are illustrated.

[0030] The trench 70 reaches the third silicon carbide layer 22 from the fourth silicon carbide layer 24. The bottom of the trench 70 is provided in the third silicon carbide layer 22.

[0031] The first insulating film 72 is provided on the inner wall of the trench 70. The first insulating film 72 is a gate insulating film of the MOSFET. The first insulating film 72 includes an insulator such as silicon oxide.

[0032] The second electrode 62 is provided in the trench 70 so as to face the fifth silicon carbide layer 26 via the first insulating film 72. The second electrode 62 is a gate electrode of the MISFET. The second electrode 62 includes a conductive material such as conductive polysilicon containing impurities.

[0033] The second insulating film 74 is provided on the second electrode 62. The second insulating film 74 includes an insulator such as silicon oxide.

[0034] The first electrode 60 is provided under the silicon carbide substrate 2. The first electrode 60 is in contact with the silicon carbide substrate 2. The first electrode 60 includes, for example, a metal or a metal semiconductor compound. The first electrode 60 includes, for example, NiSi (nickel silicide), Ti (titanium), Ni (nickel), Ag (silver), or Au (gold). The first electrode 60 is a drain electrode of the MISFET.

[0035] The third electrode 64 is provided on the fourth silicon carbide layer 24, the fifth silicon carbide layer 26, the sixth silicon carbide layer 28, and the second insulating film 74. The third electrode 64 is in contact with, for example, the fourth silicon carbide layer 24, the fifth silicon carbide layer 26, the sixth silicon carbide layer 28, and the second insulating film 74. The third electrode 64 has, for example, a stacked structure of Ti (titanium) and Al (aluminum). The third electrode 64 may contain a metal silicide such as NiSi in a portion in contact with the fourth silicon carbide layer 24, the fifth silicon carbide layer 26, and the sixth silicon carbide layer 28.

[0036] 3A to 3C are schematic cross-sectional views showing the manufacturing process of the semiconductor device 100 of this embodiment.

[0037] First, in FIG. 3(a), n - A first silicon carbide layer 4 of the mold is formed by epitaxial growth using a CVD method.

[0038] Next, an n-type second silicon carbide layer 20 is formed in the first region 10 of the first surface 6 of the first silicon carbide layer 4 by, for example, ion implantation using a patterned hard mask or the like (not shown). Here, the thickness of the second silicon carbide layer 20 in the depth direction (-z direction) is D2 (first thickness D2 of the second silicon carbide layer 20). The first thickness D2 of the second silicon carbide layer 20 can be obtained, for example, by performing a CV measurement on the second silicon carbide layer 20 after performing an activation annealing process of impurities described later. In addition, in the case of SiC, impurity elements are less likely to diffuse compared to Si. Therefore, in the case of SiC, diffusion of impurity elements hardly occurs under general activation annealing conditions of impurity elements. Therefore, when the second silicon carbide layer 20 is formed by ion implantation, there is almost no difference between the design value and the actual value of the thickness. Therefore, the design value may be adopted as the first thickness D2.

[0039] Also, a p-type third silicon carbide layer 22 is formed in the second region 12 of the first surface 6 of the first silicon carbide layer 4 by ion implantation using a patterned hard mask or the like (not shown). The thickness of the third silicon carbide layer 22 in the depth direction (-z direction) is D4. Here, the third silicon carbide layer 22 is formed by ion implantation. As described above, in the case of SiC, impurity elements are less likely to diffuse compared to Si. Therefore, in the case of SiC, diffusion of impurity elements hardly occurs under general activation annealing conditions for impurity elements. Therefore, when the third silicon carbide layer 22 is formed by ion implantation, there is almost no difference between the design value and the actual measured value of the thickness. Therefore, the design value of the thickness of the third silicon carbide layer 22 can be adopted as the thickness D4. (FIG. 3(a)).

[0040] Next, on the first silicon carbide layer 4, the second silicon carbide layer 20 and the third silicon carbide layer 22, - A fourth silicon carbide layer 24 of the mold is formed by epitaxial growth using a CVD method.

[0041] The formation of the fourth silicon carbide layer 24 will be described. The silicon carbide substrate 2, the first silicon carbide layer 4, the second silicon carbide layer 20 and the third silicon carbide layer 22 are placed in an epitaxial growth furnace (not shown). Next, H 2 The first surface 6 is heated in a hydrogen gas atmosphere to a temperature of, for example, 1500° C. or more and 1700° C. or less. 2 The second silicon carbide layer 20 is etched and cleaned with a vacuum. This etching reduces the film thickness of the second silicon carbide layer 20 from D2 to D3 (second film thickness D3 of the second silicon carbide layer 20). The difference between D2 and D3 is, for example, not less than 0.01 μm and not more than 0.2 μm. However, the difference between D2 and D3 is not limited to this.

[0042] Furthermore, the thickness of the third silicon carbide layer 22 also decreases from D4 due to the above-mentioned etching.

[0043] Next, H 2 In addition to hydrogen gas, SiC source gases, such as Si (silicon)-based gas and C (carbon)-based gas, and an n-type impurity gas, are introduced into an epitaxial growth furnace. Here, the Si (silicon)-based gas is, for example, SiH 4 (monosilane) gas. Also, the C (carbon) gas is, for example, C 3 H 8 (propane) gas. The n-type impurity gas is, for example, N 2 (Nitrogen) gas. The fourth silicon carbide layer 24 is formed by, for example, maintaining the temperature at 1500° C. or more and 1700° C. or less. Here, the fourth silicon carbide layer 24 has a film thickness D1 in the depth direction (z direction).

[0044] Here, H on the first side 6 2 The cleaning by etching and the formation of the fourth silicon carbide layer 24 are typically performed successively in the same epitaxial growth furnace.

[0045] Next, the CV measurement probe R is moved onto the fourth silicon carbide layer 24 on the second silicon carbide layer 20. Then, CV measurement is performed (FIG. 3(c)). Here, the CV measurement probe R used for the CV measurement may be of a contact type or a non-contact type. As a non-contact type CV measurement probe, for example, a CnCV230 device manufactured by SemilabSDI can be preferably used. Note that in FIG. 3, the length of the first region 10 in the X direction is illustrated as being approximately the same as the length of the second region 12 in the X direction. However, the length of the first region 10 in the X direction may be appropriately changed according to the width of the CV measurement probe R.

[0046] 3(d) shows the concentration distribution (profile) of the impurity concentration in the depth direction (-z direction) obtained by CV measurement. Using this concentration distribution, the thickness D1 of the fourth silicon carbide layer 24 and the second thickness D3 of the second silicon carbide layer 20 can be obtained. Here, for example, the n-type impurity concentration of the second silicon carbide layer 20 is higher than the n-type impurity concentration of the first silicon carbide layer 4 and the n-type impurity concentration of the fourth silicon carbide layer 24. Therefore, the portion at a depth where the n-type impurity concentration is higher can be set as the second thickness D3 of the second silicon carbide layer 20.

[0047] The amount by which the second silicon carbide layer 20 is etched is ((first film thickness D2 of the second silicon carbide layer 20)-(second film thickness D3 of the second silicon carbide layer 20)). Therefore, the amount by which the first surface 6 and the third silicon carbide layer 22 are etched can be set to ((first film thickness D2 of the second silicon carbide layer 20)-(second film thickness D3 of the second silicon carbide layer 20)).

[0048] Next, a fifth silicon carbide layer 26 is formed on the fourth silicon carbide layer 24 by ion implantation using a hard mask or the like (not shown). In addition, a sixth silicon carbide layer 28 is formed on the fifth silicon carbide layer 26 by ion implantation using a hard mask or the like (not shown) (FIG. 3(e)).

[0049] At this stage, for example, a p-type contact layer (not shown) may be formed, and an annealing process for activating impurities may be performed.

[0050] Next, for example by RIE (Reactive Ion Etching) method, a trench 70 of a predetermined depth is formed that penetrates the fourth silicon carbide layer 24 and reaches the third silicon carbide layer 22 based on the thickness D1 of the fourth silicon carbide layer 24, the first thickness D2 of the second silicon carbide layer 20, the second thickness D3 of the second silicon carbide layer 20, and the thickness D4 of the third silicon carbide layer.

[0051] Here, when the thickness of the third silicon carbide layer 22 is D4, the specified depth of the trench 70 is preferably determined based on (thickness D1 of the fourth silicon carbide layer)+((thickness D4 of the third silicon carbide layer)-((first thickness D2 of the second silicon carbide layer)-(second thickness D3 of the second silicon carbide layer))) / 2.

[0052] Next, the first insulating film 72, the second electrode 62, the second insulating film 74, the first electrode 60 and the third electrode 64 are formed as appropriate, thereby obtaining the semiconductor device 100 of this embodiment.

[0053] Next, the effects of this embodiment will be described.

[0054] In the trench-type MISFET, in order to alleviate the electric field at the bottom of the trench 70, it is conceivable to provide a p-type third silicon carbide layer 22 at the location where the bottom of the trench 70 is located.

[0055] However, after the third silicon carbide layer 22 is formed and before the fourth silicon carbide layer 24 is formed, the first silicon carbide layer 4, the second silicon carbide layer 20 and the third silicon carbide layer 22 are grown in the H 2 This H 2 The amount of etching by the gas and the film thickness of the fourth silicon carbide layer 24 vary depending on the state of the epitaxial growth furnace, the degree of warping of the substrate, and the like.

[0056] Therefore, when forming the trench 70, there are cases where the bottom of the trench 70 is not provided within the third silicon carbide layer 22. This causes a problem of a decrease in the yield of the semiconductor device.

[0057] Therefore, the method for manufacturing a semiconductor device according to the present embodiment includes the steps of: forming a second silicon carbide layer having a first thickness D2 and a first conductivity type impurity density different from that of the first silicon carbide layer in a first region on the upper surface of a first silicon carbide layer of a first conductivity type; forming a third silicon carbide layer of a second conductivity type and a thickness D4 in a second region on the upper surface; and forming a fourth silicon carbide layer having a first conductivity type impurity concentration lower than that of the second silicon carbide layer and a thickness D1 on the first silicon carbide layer. the step of measuring a second film thickness D3 of the second silicon carbide layer and a film thickness D1 of the fourth silicon carbide layer in a direction from the first silicon carbide layer to the fourth silicon carbide layer after the fourth silicon carbide layer is formed; and the step of forming a trench of a predetermined depth that penetrates the fourth silicon carbide layer and reaches the third silicon carbide layer based on the film thickness D1 of the fourth silicon carbide layer, the first film thickness D2 and the second film thickness D3 of the second silicon carbide layer, and the film thickness D4 of the third silicon carbide layer.

[0058] The above H 2 The amount of etching by the gas can be calculated in the manufacturing process of the semiconductor device by using the first thickness D2 and the second thickness D3 of the second silicon carbide layer. 2 The amount of etching by the gas can be reflected in the depth of the trench 70 to be formed, so that a method for manufacturing a semiconductor device with improved yield can be provided.

[0059] When the depth of trench 70 is determined based on (thickness D1 of the fourth silicon carbide layer)+((thickness D4 of the third silicon carbide layer)-((first thickness D2 of the second silicon carbide layer)-(second thickness D3 of the second silicon carbide layer))) / 2, the depth of trench 70 is controlled so that the bottom of trench 70 is located at the center of the third silicon carbide layer in the Z direction. This makes it possible to provide a manufacturing method for semiconductor devices with an even improved yield.

[0060] The first region 10 can be provided in the TEG region, the scribe lane, and the outer periphery region, because the influence on the characteristics of the device can be suppressed.

[0061] According to this embodiment, it is possible to provide a semiconductor device and a manufacturing method thereof with improved yield.

[0062] Second embodiment This embodiment differs from the first embodiment in that the first region is provided around the second region on the first surface. Here, description of the contents that overlap with the first embodiment will be omitted.

[0063] Fig. 4 is a schematic cross-sectional view of the semiconductor device 110 of this embodiment. Fig. 5 is a schematic cross-sectional view showing a manufacturing process of the semiconductor device of this embodiment.

[0064] The first region 10 is provided around the second region 12 so as to surround the second region 12. Therefore, the second silicon carbide layer 20 is provided around the third silicon carbide layer 22.

[0065] In other words, in the semiconductor device 110 of this embodiment, the first region 10 is also provided in the device region 90 (FIG. 2(b)). Therefore, in the semiconductor device 110 of this embodiment, the second silicon carbide layer 20 is also provided in the device region 90.

[0066] The second silicon carbide layer 20 functions as a current spreading layer, which makes it possible to further reduce the resistance component and the on-resistance of the semiconductor device.

[0067] Furthermore, the second silicon carbide layer 20 of the present embodiment is formed, for example, on the first silicon carbide layer 4 by epitaxial growth using a CVD method, similarly to the first silicon carbide layer 4. This makes it possible to reduce the number of ion implantation steps by one.

[0068] According to this embodiment, it is possible to provide a semiconductor device and a manufacturing method thereof with improved yield.

[0069] Third embodiment The present embodiment differs from the first and second embodiments in that the concentration distribution of the first conductivity type impurity in the second silicon carbide layer in the direction from the first silicon carbide layer toward the fourth silicon carbide layer has a plurality of peaks.

[0070] The semiconductor device of the present embodiment includes a first electrode, a silicon carbide substrate of a first conductivity type provided on the first electrode, a first silicon carbide layer of a first conductivity type provided on the silicon carbide substrate, a second silicon carbide layer provided in a first region on an upper surface of the first silicon carbide layer, the second silicon carbide layer having a higher first conductivity type impurity density than the first silicon carbide layer and having a concentration distribution of the first conductivity type impurity in a direction from the first electrode toward the first silicon carbide layer with a plurality of peaks, a third silicon carbide layer of a second conductivity type provided in a second region on the upper surface, and a third silicon carbide layer of a second conductivity type provided on the first silicon carbide layer. the sixth silicon carbide layer is provided on the fifth silicon carbide layer; a fourth silicon carbide layer having a lower concentration of first conductivity type impurities than the sixth silicon carbide layer; a fifth silicon carbide layer of a second conductivity type provided on the fourth silicon carbide layer; a sixth silicon carbide layer of the first conductivity type provided on the fifth silicon carbide layer; a trench penetrating the fourth silicon carbide layer to reach the third silicon carbide layer; a first insulating film provided in the trench; a second electrode provided in the trench to face the fifth silicon carbide layer via the first insulating film; a second insulating film provided on the second electrode; and a third electrode provided on the sixth silicon carbide layer and the second insulating film.

[0071] Here, the description of the contents overlapping with the first and second embodiments will be omitted.

[0072] FIG. 6 is a schematic cross-sectional view of the semiconductor device 120 of this embodiment. In FIG. 6, the second silicon carbide layer 20 is provided around the third silicon carbide layer 22, for example, in the same manner as the semiconductor device 110 of the second embodiment. The second silicon carbide layer 20 has an eighth silicon carbide layer 20a having a higher n-type impurity concentration than the first silicon carbide layer 4, a ninth silicon carbide layer 20b provided on the eighth silicon carbide layer 20a and having a lower n-type impurity concentration than the eighth silicon carbide layer 20a, and a tenth silicon carbide layer 20c provided on the ninth silicon carbide layer 20b and having a higher n-type impurity concentration than the ninth silicon carbide layer 20b and the fourth silicon carbide layer 24. For example, the thicknesses of the eighth silicon carbide layer 20a, the ninth silicon carbide layer 20b, and the tenth silicon carbide layer 20c are each about 0.1 μm. The eighth silicon carbide layer 20a and the tenth silicon carbide layer 20c have an n-type impurity concentration of, for example, 1×10 17 atoms / cm 3 The n-type impurity concentration of the ninth silicon carbide layer 20b is, for example, about 5×10 16 atoms / cm 3 That's about it.

[0073] 7A to 7C are schematic cross-sectional views showing the manufacturing process of the semiconductor device of the present embodiment. In Fig. 7D, the concentration distribution (profile) of the impurity concentration in the depth direction (-z direction) obtained by CV measurement has multiple peaks corresponding to the n-type impurity concentrations of the eighth silicon carbide layer 20a and the tenth silicon carbide layer 20c.

[0074] In this embodiment, the thickness of the second silicon carbide layer 20 can be estimated based on the impurity concentration distribution as shown in Fig. 7(d). Specifically, the thicknesses of the eighth silicon carbide layer 20a, the ninth silicon carbide layer 20b, and the tenth silicon carbide layer 20c are each about 0.1 µm. 2 The amount of etching by the gas can be known. For example, since it can be seen in FIG. 7(d) that the tenth silicon carbide layer 20c is etched by about half, the amount of etching can be estimated to be about 0.05 μm. In this way, the process of determining the film thickness of the second silicon carbide layer 20 before the formation of the fourth silicon carbide layer 24 can be simplified.

[0075] According to this embodiment, it is possible to provide a semiconductor device and a manufacturing method thereof with improved yield.

[0076] (Fourth embodiment) The semiconductor device of this embodiment differs from the semiconductor devices of the first to third embodiments in that it further includes a seventh silicon carbide layer 30 between the first silicon carbide layer 4 and the fourth silicon carbide layer 24, the seventh silicon carbide layer 30 having a higher first conductivity type impurity concentration than the first silicon carbide layer 4 and the fourth silicon carbide layer 24.

[0077] The method for manufacturing a semiconductor device of this embodiment differs from the methods for manufacturing semiconductor devices of the first to third embodiments in that it further includes a step of forming a seventh silicon carbide layer having a higher first conductivity type impurity concentration than the first silicon carbide layer and the fourth silicon carbide layer on the third silicon carbide layer after forming the third silicon carbide layer and before forming the fourth silicon carbide layer.

[0078] Here, the description of the contents overlapping with the first to third embodiments will be omitted.

[0079] FIG. 8 is a schematic cross-sectional view of a semiconductor device 130 of this embodiment.

[0080] The seventh silicon carbide layer 30 functions as a current spreading layer, which makes it possible to further reduce the resistance component and the on-resistance of the semiconductor device.

[0081] According to this embodiment, it is possible to provide a semiconductor device and a manufacturing method thereof with improved yield.

[0082] Although some embodiments and examples of the present invention have been described, these embodiments and examples are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims.

[0083] The above-described embodiment can be summarized as the following technical proposal. (Technical proposal 1) forming a second silicon carbide layer having a first conductivity type impurity density different from that of the first silicon carbide layer and having a first thickness D2 in a first region of an upper surface of a first silicon carbide layer of a first conductivity type; forming a third silicon carbide layer of a second conductivity type and having a thickness D4 in a second region of the upper surface; forming a fourth silicon carbide layer having a first conductivity type impurity concentration lower than that of the second silicon carbide layer and having a thickness D1 on the first silicon carbide layer; measuring a second thickness D3 of the second silicon carbide layer and a thickness D1 of the fourth silicon carbide layer in a direction from the first silicon carbide layer to the fourth silicon carbide layer after the fourth silicon carbide layer is formed; forming a trench of a predetermined depth that penetrates the fourth silicon carbide layer and reaches the third silicon carbide layer based on a thickness D1 of the fourth silicon carbide layer, a first thickness D2 and a second thickness D3 of the second silicon carbide layer, and a thickness D4 of the third silicon carbide layer; A method for manufacturing a semiconductor device comprising the steps of: (Technical proposal 2) (thickness D1 of the fourth silicon carbide layer)+((thickness D4 of the third silicon carbide layer)-((first thickness D2 of the second silicon carbide layer)-(second thickness D3 of the second silicon carbide layer))) / 2 forming a trench of the predetermined depth based on the A method for manufacturing a semiconductor device according to Technical Proposal 1. (Technical proposal 3) Prior to the step of forming a trench having a predetermined depth that penetrates the fourth silicon carbide layer and reaches the third silicon carbide layer based on a thickness D1 of the fourth silicon carbide layer, a first thickness D2 and a second thickness D3 of the second silicon carbide layer, and a thickness D4 of the third silicon carbide layer, forming a fifth silicon carbide layer of a second conductivity type on the fourth silicon carbide layer on the third silicon carbide layer; forming a sixth silicon carbide layer of a first conductivity type on the fifth silicon carbide layer; Further equipped with After the step of forming the trench of the predetermined depth, which penetrates the fourth silicon carbide layer and reaches the third silicon carbide layer, based on a thickness D1 of the fourth silicon carbide layer, a first thickness D2 and a second thickness D3 of the second silicon carbide layer, and a thickness D4 of the third silicon carbide layer, forming a first insulating film in the trench; forming a second electrode in the trench so as to face the fifth silicon carbide layer with the first insulating film interposed therebetween; forming a second insulating film on the second electrode; forming a first electrode under the first silicon carbide layer; forming a third electrode on the sixth silicon carbide layer; The method for manufacturing a semiconductor device according to Technical Scheme 1 or 2, further comprising: (Technical proposal 4) On the upper surface, the first region is provided around the second region. A method for manufacturing a semiconductor device according to any one of Technical Schemes 1 to 3. (Technical proposal 5) The first region is provided in a TEG region of the semiconductor device. A method for manufacturing a semiconductor device according to any one of Technical Schemes 1 to 4. (Technical proposal 6) the first region is provided in a scribe lane of the semiconductor device; A method for manufacturing a semiconductor device according to any one of Technical Schemes 1 to 4. (Technical proposal 7) The first region is provided in a peripheral region of the semiconductor device. A method for manufacturing a semiconductor device according to Technical Proposal 1. (Technical proposal 8) a concentration distribution of the first conductivity type impurity in the second silicon carbide layer in a direction from the first silicon carbide layer toward the fourth silicon carbide layer has a plurality of peaks; A method for manufacturing a semiconductor device according to any one of technical proposals 1 to 7. (Technical proposal 9) After forming the third silicon carbide layer and before forming the fourth silicon carbide layer, forming a seventh silicon carbide layer on the third silicon carbide layer, the seventh silicon carbide layer having a first conductivity type impurity concentration higher than the first silicon carbide layer and the fourth silicon carbide layer; A method for manufacturing a semiconductor device according to any one of technical proposals 1 to 7. (Technical proposal 10) A first electrode; a silicon carbide substrate of a first conductivity type provided on the first electrode; a first silicon carbide layer of a first conductivity type provided on the silicon carbide substrate; a second silicon carbide layer provided in a first region of an upper surface of the first silicon carbide layer and having a first conductivity type impurity density higher than that of the first silicon carbide layer; a third silicon carbide layer of a second conductivity type provided in a second region of the upper surface; a fourth silicon carbide layer provided on the first silicon carbide layer and having a first conductivity type impurity concentration lower than that of the second silicon carbide layer; a fifth silicon carbide layer of a second conductivity type provided on the fourth silicon carbide layer; a sixth silicon carbide layer of a first conductivity type provided on the fifth silicon carbide layer; a trench penetrating the fourth silicon carbide layer and reaching the third silicon carbide layer; A first insulating film provided in the trench; a second electrode provided in the trench so as to face the fifth silicon carbide layer with the first insulating film interposed therebetween; A second insulating film provided on the second electrode; a third electrode provided on the sixth silicon carbide layer and the second insulating film; A semiconductor device comprising: [Explanation of symbols]

[0084] 2: Silicon carbide substrate 4: First silicon carbide layer 6: 1st page 8:Second side 10: 1st area 10b :TEG area 10c: Dicing area 12:Second area 20: Second silicon carbide layer 20a: eighth silicon carbide layer 20b: 9th silicon carbide layer 20c: 10th silicon carbide layer 22: Third silicon carbide layer 24: Fourth silicon carbide layer 26: Fifth silicon carbide layer 28: Sixth silicon carbide layer 30: Seventh silicon carbide layer 60: 1st electrode 62: 2nd electrode 64:Third electrode 70: Trench 72: First insulating film 74: Second insulating film 90: Device area 92: Outer area 100: Semiconductor device 110: Semiconductor device 120: Semiconductor device 130: Semiconductor device 150: Semiconductor chips 180: Semiconductor chips 200: Wafer D1: Film thickness D2: First film thickness D3: Second film thickness D4: Film thickness R: CV measurement probe

Claims

1. forming a second silicon carbide layer having a first conductivity type impurity density different from that of the first silicon carbide layer and having a first thickness D2 in a first region of an upper surface of a first silicon carbide layer of a first conductivity type; forming a third silicon carbide layer of a second conductivity type and having a thickness D4 in a second region of the upper surface; forming a fourth silicon carbide layer on the first silicon carbide layer, the fourth silicon carbide layer having a first conductivity type impurity concentration lower than that of the second silicon carbide layer and having a thickness D1; measuring a second thickness D3 of the second silicon carbide layer and a thickness D1 of the fourth silicon carbide layer in a direction from the first silicon carbide layer to the fourth silicon carbide layer after the fourth silicon carbide layer is formed; forming a trench having a predetermined depth that penetrates the fourth silicon carbide layer and reaches the third silicon carbide layer based on a thickness D1 of the fourth silicon carbide layer, a first thickness D2 and a second thickness D3 of the second silicon carbide layer, and a thickness D4 of the third silicon carbide layer; A method for manufacturing a semiconductor device comprising the steps of:

2. (thickness D1 of the fourth silicon carbide layer)+((thickness D4 of the third silicon carbide layer)-((first thickness D2 of the second silicon carbide layer)-(second thickness D3 of the second silicon carbide layer))) / 2 forming a trench of the predetermined depth based on the The method for manufacturing a semiconductor device according to claim 1.

3. Prior to the step of forming a trench having a predetermined depth that penetrates the fourth silicon carbide layer and reaches the third silicon carbide layer based on a thickness D1 of the fourth silicon carbide layer, a first thickness D2 and a second thickness D3 of the second silicon carbide layer, and a thickness D4 of the third silicon carbide layer, forming a fifth silicon carbide layer of a second conductivity type on the fourth silicon carbide layer on the third silicon carbide layer; forming a sixth silicon carbide layer of a first conductivity type on the fifth silicon carbide layer; Further equipped with After the step of forming the trench having the predetermined depth, the trench penetrating the fourth silicon carbide layer and reaching the third silicon carbide layer based on a thickness D1 of the fourth silicon carbide layer, a first thickness D2 and a second thickness D3 of the second silicon carbide layer, and a thickness D4 of the third silicon carbide layer, forming a first insulating film in the trench; forming a second electrode in the trench so as to face the fifth silicon carbide layer with the first insulating film interposed therebetween; forming a second insulating film on the second electrode; forming a first electrode under the first silicon carbide layer; forming a third electrode on the sixth silicon carbide layer; The method for manufacturing a semiconductor device according to claim 1 , further comprising:

4. On the upper surface, the first region is provided around the second region. The method for manufacturing a semiconductor device according to claim 1.

5. The first region is provided in a TEG region of the semiconductor device. The method for manufacturing a semiconductor device according to claim 1.

6. the first region is provided in a scribe lane of the semiconductor device; The method for manufacturing a semiconductor device according to claim 1.

7. The first region is provided in a peripheral region of the semiconductor device. The method for manufacturing a semiconductor device according to claim 1.

8. a concentration distribution of a first conductivity type impurity in the second silicon carbide layer in a direction from the first silicon carbide layer toward the fourth silicon carbide layer has a plurality of peaks; 8. The method for manufacturing a semiconductor device according to claim 1.

9. After forming the third silicon carbide layer and before forming the fourth silicon carbide layer, forming a seventh silicon carbide layer having a first conductivity type impurity concentration higher than the first silicon carbide layer and the fourth silicon carbide layer on the third silicon carbide layer; 8. The method for manufacturing a semiconductor device according to claim 1.

Images