Semiconductor memory device

Abstract

To provide a semiconductor memory device capable of accelerating data reading.SOLUTION: A semiconductor memory device includes a sense amplifier unit having a first latch circuit and a second latch circuit and a third latch circuit electrically connected to the sense amplifier unit. A first read operation is performed according to a first command set, and a second read operation is performed according to a second command set. When the second command set is input at a first timing, a first data transfer operation is performed. When the second command set is input at a second timing earlier than the first timing, a second data transfer operation is performed. In the first data transfer operation, data of the first latch circuit is transferred to the second latch circuit according to the first read operation, and data of the second latch circuit is transferred to the third latch circuit. In the second data transfer operation, the data of the first latch circuit is transferred to the third latch circuit according to the first read operation.SELECTED DRAWING: Figure 24

Description

[Technical field]

[0001] The present embodiment relates to a semiconductor memory device. [Background technology]

[0002] A semiconductor memory device is known that includes a memory string and a plurality of first wirings electrically connected to the memory string, the memory string including a plurality of memory transistors connected in series, and gate electrodes of the plurality of memory transistors connected to the plurality of first wirings. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2023-12706 [Patent Document 2] JP 2022-174874 A Summary of the Invention [Problem to be solved by the invention]

[0004] A semiconductor memory device capable of reading data at high speed is provided. [Means for solving the problem]

[0005] A semiconductor memory device according to one embodiment includes a memory string having a plurality of memory transistors connected in series, a bit line connected to the memory string, a sense amplifier unit connected to the bit line and having a first latch circuit and a second latch circuit, and a third latch circuit electrically connected to the sense amplifier unit. A first read operation is performed in response to a first command set, and a second read operation is performed consecutively after the first read operation in response to a second command set. A first data transfer operation is performed when the second command set is input at a first timing. A second data transfer operation is performed when the second command set is input at a second timing prior to the first timing. The first data transfer operation transfers data held in the first latch circuit to the second latch circuit in response to the first read operation, and transfers data held in the second latch circuit to the third latch circuit. The second data transfer operation transfers data held in the first latch circuit to the third latch circuit in response to the first read operation. [Brief description of the drawings]

[0006] [Figure 1] 1 is a schematic block diagram showing a configuration of a memory system 10 according to a first embodiment. [Diagram 2] 1 is a schematic side view showing a configuration example of a memory system 10. FIG. [Diagram 3] 1 is a schematic plan view showing a configuration example of a memory system 10. FIG. [Figure 4] 1 is a schematic block diagram showing a configuration of a memory die MD according to a first embodiment. [Diagram 5] 2 is a schematic circuit diagram showing a configuration of a portion of a memory die MD. [Figure 6] 2 is a schematic circuit diagram showing a configuration of a portion of a memory die MD. [Figure 7] 2 is a schematic circuit diagram showing a configuration of a portion of a memory die MD. [Figure 8] 2 is a schematic circuit diagram showing a configuration of a portion of a memory die MD. [Figure 9]2 is a schematic circuit diagram showing a configuration of a portion of a memory die MD. [Figure 10] 2 is a schematic circuit diagram showing a configuration of a portion of a memory die MD. [Figure 11] 2 is a schematic circuit diagram showing a configuration of a portion of a memory die MD. [Figure 12] 1 is a schematic exploded perspective view showing a configuration example of a semiconductor memory device according to an embodiment of the present invention; [Figure 13] 2 is a schematic bottom view showing an example of the configuration of the chip CM. FIG. [Figure 14] 2 is a schematic cross-sectional view showing a configuration of a portion of a memory die MD. [Figure 15] 2 is a schematic cross-sectional view showing a configuration of a portion of a memory die MD. [Figure 16] 2 is a schematic bottom view showing a configuration of a portion of the chip CM. FIG. [Figure 17] 2 is a schematic cross-sectional view showing the configuration of a portion of the chip CM. [Figure 18] 2 is a schematic diagram for explaining data recorded in a memory cell MC. FIG. [Figure 19] 11 is a timing chart for explaining a read operation of a normal read and a first cache read. [Figure 20] 13 is a timing chart for explaining a read operation of a normal read and a second cache read. [Figure 21] 10 is a timing chart for explaining an operation upon reception of a command set CS. [Figure 22] 11 is a schematic cross-sectional view for explaining a read voltage supply operation. FIG. [Diagram 23] FIG. 11 is a waveform diagram for explaining a read operation of a first cache read. [Figure 24] FIG. 11 is a waveform diagram for explaining a read operation of a second cache read. [Diagram 25] 11 is a flowchart illustrating a data transfer operation. [Figure 26]13 is a timing chart for explaining a cache read operation in the comparative example and a second cache read operation in the first embodiment. [Figure 27] 13 is a timing chart for explaining a cache read operation in a comparative example and a first cache read operation in the first embodiment. [Figure 28] FIG. 11 is a waveform diagram for explaining a read operation of a second cache read in the second embodiment. [Figure 29] 13 is a timing chart for explaining a cache read operation in a comparative example and a second cache read operation in the second embodiment. [Diagram 30] 13 is a timing chart for explaining a cache read operation in a comparative example and a first cache read operation in the second embodiment. [Diagram 31] FIG. 13 is a waveform diagram for explaining a read operation of a connected read in the third embodiment. [Diagram 32] FIG. 13 is a diagram showing some waveforms in a read operation of a connected read in the third embodiment. [Diagram 33] 13 is a flowchart for explaining a read operation of linked reading in the third embodiment. [Diagram 34] FIG. 13 is a waveform diagram for explaining a read operation of a connected read in the fourth embodiment. [Diagram 35] FIG. 13 is a waveform diagram for explaining a modified example of a read operation of a connected read in the fourth embodiment. [Diagram 36] FIG. 13 is a waveform diagram for explaining a read operation of sequential reading in the fifth embodiment. [Figure 37] FIG. 25 is a waveform diagram showing a modified example of FIG. 24. [Figure 38] FIG. 32 is a waveform diagram showing a modification of FIG. 31. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Next, a semiconductor memory device according to an embodiment will be described in detail with reference to the drawings. Note that the following embodiment is merely an example, and is not intended to limit the present invention. Also, the following drawings are schematic, and for the sake of explanation, some configurations may be omitted. Also, parts common to multiple embodiments may be given the same reference numerals, and explanations may be omitted.

[0008] In addition, in this specification, the term "semiconductor memory device" may refer to a memory die, or may refer to a memory system including a controller die, such as a memory chip, a memory card, or an SSD (Solid State Drive). Furthermore, it may refer to a configuration including a host computer, such as a smartphone, a tablet terminal, or a personal computer.

[0009] In addition, in this specification, the term "control circuit" may refer to a peripheral circuit such as a sequencer provided on a memory die, or may refer to a controller die or controller chip connected to a memory die, or may refer to a configuration that includes both of these.

[0010] In addition, in this specification, when it is said that a first configuration is "electrically connected" to a second configuration, the first configuration may be directly connected to the second configuration, or the first configuration may be connected to the second configuration via wiring, a semiconductor member, a transistor, etc. For example, when three transistors are connected in series, the first transistor is "electrically connected" to the third transistor even if the second transistor is in an OFF state.

[0011] Furthermore, in this specification, when it is said that a first configuration is "connected between" a second configuration and a third configuration, it may mean that the first configuration, the second configuration, and the third configuration are connected in series, and that the second configuration is connected to the third configuration via the first configuration.

[0012] In addition, in this specification, when it is said that a circuit or the like "conducts" two wirings or the like, it may mean, for example, that the circuit or the like includes a transistor or the like, that the transistor or the like is provided in a current path between the two wirings, and that the transistor or the like is in an ON state.

[0013] In this specification, a predetermined direction parallel to the upper surface of the substrate is called the X direction, a direction parallel to the upper surface of the substrate and perpendicular to the X direction is called the Y direction, and a direction perpendicular to the upper surface of the substrate is called the Z direction.

[0014] In this specification, a direction along a predetermined plane may be referred to as a first direction, a direction along this predetermined plane that intersects with the first direction may be referred to as a second direction, and a direction that intersects with this predetermined plane may be referred to as a third direction. These first, second, and third directions may or may not correspond to any of the X, Y, and Z directions.

[0015] In this specification, expressions such as "upper" and "lower" are based on the substrate. For example, the direction away from the substrate along the Z direction is called "up," and the direction toward the substrate along the Z direction is called "down." Furthermore, when referring to a certain configuration, the lower surface or lower end refers to the surface or end of the configuration facing the substrate, and when referring to the upper surface or upper end, refers to the surface or end of the configuration facing away from the substrate. Furthermore, surfaces that intersect with the X or Y direction are called side surfaces, etc.

[0016] [First embodiment] [Memory System 10] FIG. 1 is a schematic block diagram showing the configuration of a memory system 10 according to the first embodiment.

[0017] The memory system 10 reads, writes, erases, etc. user data in response to a signal transmitted from a host computer 20. The memory system 10 is, for example, a memory chip, a memory card, an SSD, or other system capable of storing user data. The memory system 10 includes a plurality of memory dies MD and a controller die CD.

[0018] The memory die MD stores user data. The memory die MD includes a plurality of memory blocks BLK. Each memory block BLK includes a plurality of pages PG. The memory block BLK may be an execution unit of an erase operation. The page PG may be an execution unit of a read operation and a write operation.

[0019] 1, the controller die CD is connected to a plurality of memory dies MD and a host computer 20. The controller die CD includes, for example, a logical-physical conversion table 21, a FAT (File Allocation Table) 22, an erase count holding unit 23, an ECC circuit 24, and an MPU (Micro Processor Unit) 25.

[0020] The logical-physical conversion table 21 holds a logical address received from the host computer 20 in association with a physical address assigned to a page PG in the memory die MD. The logical-physical conversion table 21 is realized, for example, by a RAM (Random Access Memory) (not shown).

[0021] FAT22 holds FAT information indicating the state of each page PG. Such FAT information includes, for example, information indicating "valid", "invalid", and "erased". For example, a page PG that is "valid" stores valid data that is read in response to a command from the host computer 20. A page PG that is "invalid" stores invalid data that is not read in response to a command from the host computer 20. A page PG that is "erased" has not stored data since the erasure process was executed. FAT22 is realized, for example, by a RAM or the like (not shown).

[0022] The erase count holding unit 23 holds a physical address corresponding to the memory block BLK and the number of erase operations executed on the memory block BLK in association with each other. The erase count holding unit 23 is realized by, for example, a RAM (not shown) or the like.

[0023] The ECC circuit 24 detects errors in the data read from the memory die MD and corrects the data if possible.

[0024] The MPU 25 refers to the logical-physical conversion table 21, the FAT 22, the erase count holding unit 23, and the ECC circuit 24 to perform processes such as conversion between logical addresses and physical addresses, bit error detection / correction, garbage collection (compaction), and wear leveling.

[0025] Fig. 2 is a schematic side view showing a configuration example of the memory system 10 according to this embodiment. Fig. 3 is a schematic plan view showing the same configuration example. For convenience of explanation, some components are omitted in Figs. 2 and 3.

[0026] As shown in FIG. 2, the memory system 10 according to the present embodiment includes a mounting substrate MSB, a plurality of memory dies MD, and a controller die CD. A pad electrode Px is provided in an end region in the Y direction of the upper surface of the mounting substrate MSB. A region of the upper surface of the mounting substrate MSB other than the end region in the Y direction is bonded to the lower surface of the memory die MD via an adhesive or the like. The plurality of memory dies MD are stacked on the mounting substrate MSB. A pad electrode Px is provided in an end region in the Y direction of the upper surface of the memory die MD. A region of the upper surface of the memory die MD other than the end region in the Y direction is bonded to the lower surface of another memory die MD or the controller die CD via an adhesive or the like. The controller die CD is stacked on the memory die MD. A pad electrode Px is provided in an end region in the Y direction of the upper surface of the controller die CD.

[0027] 3, the mounting substrate MSB, the memory dies MD, and the controller die CD each include a plurality of pad electrodes Px arranged in the X direction. The pad electrodes Px provided on the mounting substrate MSB, the memory dies MD, and the controller die CD are connected to each other via bonding wires B.

[0028] 2 and 3 are merely examples, and the specific configuration can be adjusted as appropriate. For example, in the example shown in FIG. 2 and FIG. 3, a controller die CD is stacked on a plurality of memory dies MD. The memory die MD and the controller die CD are connected by a bonding wire B. The plurality of memory dies MD and the controller die CD are included in one package. However, the controller die CD may be included in a package separate from the memory die MD. The plurality of memory dies MD and the controller die CD may be connected to each other via a through electrode or the like, instead of the bonding wire B.

[0029] [Circuit configuration of memory die MD] Fig. 4 is a schematic block diagram showing the configuration of the memory die MD according to the first embodiment. Figs. 5 to 11 are schematic circuit diagrams showing the configuration of a portion of the memory die MD.

[0030] FIG. 4 illustrates a plurality of control terminals. These control terminals may be represented as control terminals corresponding to high active signals (positive logic signals). Furthermore, the control terminals may be represented as control terminals corresponding to low active signals (negative logic signals). Furthermore, the control terminals may be represented as control terminals corresponding to both high active signals and low active signals. In FIG. 4, the reference numerals of the control terminals corresponding to low active signals include an overline. In this specification, the reference numerals of the control terminals corresponding to low active signals include a slash (" / "). The description in FIG. 4 is an example, and the specific embodiment can be appropriately adjusted. For example, it is also possible to make some or all of the high active signals low active signals, and to make some or all of the low active signals high active signals.

[0031] 4, the memory die MD includes a memory cell array MCA and a peripheral circuit PC. The peripheral circuit PC includes a voltage generating circuit VG, a row decoder RD, a sense amplifier module SAM, and a sequencer SQC. The peripheral circuit PC also includes a cache memory CM, an address register ADR, a command register CMR, and a status register STR. The peripheral circuit PC also includes an input / output control circuit I / O and a logic circuit CTR.

[0032] [Circuit configuration of memory cell array MCA] 5, the memory cell array MCA includes a plurality of memory blocks BLK as described above. Each of the memory blocks BLK includes a plurality of string units SU. Each of the string units SU includes a plurality of memory strings MS. One end of each of the memory strings MS is connected to a peripheral circuit PC via a bit line BL. The other ends of each of the memory strings MS are connected to the peripheral circuit PC via a common source line SL.

[0033] The memory string MS includes a drain side select transistor STD, a plurality of memory cells MC (memory transistors), a source side select transistor STS, and a source side select transistor STSb. The drain side select transistor STD, the plurality of memory cells MC, the source side select transistor STS, and the source side select transistor STSb are connected in series between a bit line BL and a source line SL. Hereinafter, the drain side select transistor STD, the source side select transistor STS, and the source side select transistor STSb may be simply referred to as select transistors (STD, STS, STSb).

[0034] The memory cells MC are field-effect transistors. The memory cells MC include a semiconductor layer, a gate insulating film, and a gate electrode. The semiconductor layer functions as a channel region. The gate insulating film includes a charge storage film. The threshold voltage of the memory cells MC varies depending on the amount of charge in the charge storage film. The memory cells MC store one or more bits of data. A word line WL is connected to each of the gate electrodes of the memory cells MC corresponding to one memory string MS. Each of these word lines WL is commonly connected to all the memory strings MS in one memory block BLK.

[0035] The selection transistors (STD, STS, STSb) are field-effect transistors. The selection transistors (STD, STS, STSb) include a semiconductor layer, a gate insulating film, and a gate electrode. The semiconductor layer functions as a channel region. The gate electrodes of the selection transistors (STD, STS, STSb) are connected to selection gate lines (SGD, SGS, SGSb), respectively. One drain side selection gate line SGD is commonly connected to all memory strings MS in one string unit SU. One source side selection gate line SGS is commonly connected to all memory strings MS in one memory block BLK. One source side selection gate line SGSb is commonly connected to all memory strings MS in one memory block BLK.

[0036] [Circuit configuration of voltage generation circuit VG] The voltage generating circuit VG (FIG. 4) includes a plurality of voltage generating units vg1 to vg3, as shown in FIG. 6. The voltage generating units vg1 to vg3 generate voltages of a predetermined magnitude in a read operation, a write operation, and an erase operation, and supply the voltage to the voltage supply line L. VG (L VG1 ~L VG3 For example, the voltage generating unit vg1 outputs a program voltage used in a write operation. The voltage generating unit vg2 outputs a read pass voltage V READThe voltage generation unit vg1 outputs a write pass voltage used in a write operation. The voltage generation unit vg3 outputs a read voltage, which will be described later, in a read operation. The voltage generation unit vg3 outputs a verify voltage, which will be described later, in a write operation. The voltage generation units vg1 to vg3 may be, for example, boost circuits such as charge pump circuits, or step-down circuits such as regulators. These step-down circuits and step-up circuits are connected to the voltage supply line L P The voltage supply line L P is the power supply voltage V CC or ground voltage V SS (Figure 4) are provided. These voltage supply lines L P is connected to, for example, the pad electrode Px described with reference to Figures 2 and 3. The operating voltage output from the voltage generating circuit VG is adjusted appropriately in accordance with a control signal from the sequencer SQC.

[0037] The charge pump circuit 32 (FIG. 7) in the voltage generating circuit VG includes a voltage output circuit 32a, a voltage dividing circuit 32b, and a comparator 32c. The voltage output circuit 32a is connected to a voltage supply line L VG Voltage V OUT The voltage divider circuit 32b outputs the voltage supply line L VG The comparator 32c is connected to the voltage V OUT ´ and the reference voltage V REF The feedback signal FB is output to the voltage output circuit 32a in accordance with the magnitude relationship between the input voltage FB and the output voltage FB.

[0038] 8, the voltage output circuit 32a includes a plurality of transistors 32a2a and 32a2b. The plurality of transistors 32a2a and 32a2b are connected to a voltage supply line L VG and voltage supply line L P The voltage supply line L shown in the figure is alternately connected between P is the power supply voltage V CCis supplied. The gate electrodes of the plurality of transistors 32a2a and 32a2b connected in series are connected to the drain electrodes of the respective transistors and the capacitor 32a3. The voltage output circuit 32a further includes an AND circuit 32a4, a level shifter 32a5a, and a level shifter 32a5b. The AND circuit 32a4 outputs a logical sum of the clock signal CLK and the feedback signal FB. The level shifter 32a5a boosts and outputs the output signal of the AND circuit 32a4. The output terminal of the level shifter 32a5a is connected to the gate electrode of the transistor 32a2a via the capacitor 32a3. The level shifter 32a5b boosts and outputs the inverted signal of the output signal of the AND circuit 32a4. The output terminal of the level shifter 32a5b is connected to the gate electrode of the transistor 32a2b via the capacitor 32a3.

[0039] When the feedback signal FB is in the “H” state, the AND circuit 32a4 outputs the clock signal CLK. VG From voltage supply line L P Electrons are transferred to the voltage supply line L VG On the other hand, when the feedback signal FB is in the "L" state, the clock signal CLK is not output from the AND circuit 32a4. VG The voltage at does not increase.

[0040] 7, the voltage dividing circuit 32b includes a resistive element 32b2 and a variable resistive element 32b4. The resistive element 32b2 is connected to the voltage supply line L VG and the voltage division terminal 32b1. The variable resistance element 32b4 is connected between the voltage division terminal 32b1 and the voltage supply line L P This voltage supply line L P The ground voltage V SS The resistance value of the variable resistance element 32b4 is supplied with the operating voltage control signal V CTRL Therefore, the voltage V of the voltage dividing terminal 32b1 OUT The magnitude of the operating voltage control signal V CTRL It can be adjusted according to the requirements.

[0041] 9, the variable resistance element 32b4 includes a plurality of current paths 32b5. The plurality of current paths 32b5 are connected to the voltage division terminal 32b1 and the voltage supply line L P The current paths 32b5 each include a resistor element 32b6 and a transistor 32b7 connected in series. The resistor elements 32b6 in the current paths 32b5 may have different resistance values. The gate electrodes of the transistors 32b7 are connected in parallel to the operation voltage control signal V CTRL Different bits of the first and second inputs are input to the variable resistance element 32b4. The variable resistance element 32b4 may have a current path 32b8 that does not include the transistor 32b7.

[0042] 7, the comparator 32c outputs a feedback signal FB. The feedback signal FB is, for example, a voltage V OUT ´ is the reference voltage V REF The feedback signal FB is in the “L” state when the voltage V OUT ´ is the reference voltage V REF If it is smaller than this, it will be in the “H” state.

[0043] [Circuit configuration of row decoder RD] As shown in FIG. 6, the row decoder RD includes a block decoder BLKD, a word line decoder WLD, a driver circuit DRV, and an address decoder (not shown).

[0044] The block decoder BLKD includes a plurality of block decode units blkd. The plurality of block decode units blkd correspond to a plurality of memory blocks BLK in the memory cell array MCA. The block decode unit blkd includes a plurality of transistors T BLK A plurality of transistors T BLK corresponds to a plurality of word lines WL in the memory block BLK. BLK is, for example, a field effect NMOS transistor. BLK The drain electrode of the transistor T is connected to the word line WL.BLK The source electrode of the transistor T is connected to the wiring CG. The wiring CG is connected to all the block decode units blkd in the block decoder BLKD. BLK The gate electrodes of the transistors T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14, T15, T16, T17, T18, T20, T21, T22, T30, T41, T19, T22, T31, T42, T19, T23, T18, T24, T19, T25, T30, T41, T19, T26, T18, T27, T31, T42, T19, T28, T19, T29, T30, T41, T19, T21, T31, T42, T19, T22, T19, T23, T31, T42, T19, T24, T18, T25, T31, T42, T19, T BLK is connected to.

[0045] In a read operation, a write operation, etc., for example, the voltage of one signal line BLKSEL corresponding to a block address in the address register ADR (FIG. 4) is in the “H” state, and the voltages of the other signal lines BLKSEL are in the “L” state. For example, a predetermined driving voltage having a positive magnitude is supplied to one signal line BLKSEL, and a ground voltage V SS As a result, all word lines WL in one memory block BLK corresponding to this block address are electrically connected to all wirings CG, and all word lines WL in the other memory blocks BLK are in a floating state.

[0046] The word line decoder WLD includes a plurality of word line decode units wld. The plurality of word line decode units wld correspond to a plurality of memory cells MC in the memory string MS. In the illustrated example, the word line decode unit wld includes two transistors T WLS ,T WLU The transistor T WLS ,T WLU is, for example, a field effect NMOS transistor. WLS ,T WLU The drain electrode of the transistor T is connected to the wiring CG. WLS The source electrode of the wiring CG S Transistor T WLU The source electrode of the wiring CG U Transistor T WLS The gate electrode of the signal line WLSELS Transistor T WLU The gate electrode of the signal line WLSEL U Signal line WLSEL is connected to S is one of the transistors T included in each word line decode unit wld. WLS A plurality of signal lines WLSEL are provided corresponding to the U The other transistor T included in each word line decode unit wld WLU A plurality of such sensors are provided corresponding to the number of sensors.

[0047] In a read operation, a write operation, etc., for example, a signal line WLSEL corresponding to one word line decode unit wld corresponding to a page address in the address register ADR (FIG. 4) is S The voltage of the WLSEL U The voltage of the signal line WLSEL corresponding to the other word line decode units wld is in the “L” state. S The voltage of the WLSEL U The voltage of the wiring CG S The selected word line WL S A voltage corresponding to the wiring CG U The unselected word lines WL U As a result, a voltage corresponding to the selected word line WL is supplied to one word line WL corresponding to the page address. S In addition, a voltage corresponding to the unselected word line WL is supplied to the other word lines WL. U A voltage corresponding to

[0048] The driver circuit DRV is, for example, a transistor T DRV1 ~T DRV6 The transistor T DRV1 ~T DRV6 is, for example, a field effect NMOS transistor. DRV1 ~T DRV4 The drain electrode of the S Transistor TDRV5 ,T DRV6 The drain electrode of the U Transistor T DRV1 The source electrode of the voltage supply line L VG1 , and is connected to the output terminal of the voltage generating unit vg1 via the transistor T DRV2 ,T DRV5 The source electrode of the voltage supply line L VG2 , and is connected to the output terminal of the voltage generating unit vg2 via the transistor T DRV3 The source electrode of the voltage supply line L VG3 , and is connected to the output terminal of the voltage generating unit vg3 via the transistor T DRV4 ,T DRV6 The source electrode of the voltage supply line L P 2 and 3. DRV1 ~T DRV6 The gate electrodes of these transistors are connected to signal lines VSEL1 to VSEL6, respectively.

[0049] In the read operation, write operation, etc., for example, the wiring CG S The voltage of one of the signal lines VSEL1 to VSEL4 corresponding to the wiring CG U The voltage of one of the two corresponding signal lines VSEL5 and VSEL6 goes to the "H" state, and the voltage of the other goes to the "L" state.

[0050] An address decoder (not shown) sequentially refers to the row address RA of the address register ADR (FIG. 4) in accordance with a control signal from the sequencer SQC (FIG. 4). The row address RA includes the above-mentioned block address and page address. The address decoder uses the above-mentioned signal lines BLKSEL and WLSEL S ,WLSEL U The voltage is controlled to be in the “H” or “L” state.

[0051] In the example of FIG. 6, the row decoder RD is provided with one block decode unit blkd for each memory block BLK. However, this configuration can be changed as appropriate. For example, one block decode unit blkd may be provided for two or more memory blocks BLK.

[0052] [Circuit configuration of the sense amplifier module SAM] The sense amplifier module SAM (FIG. 4) includes a plurality of sense amplifier units SAU, as shown in FIG. 10, for example. The plurality of sense amplifier units SAU correspond to a plurality of bit lines BL. Each of the sense amplifier units SAU includes a sense amplifier SA, a wiring LBUS, and latch circuits SDL, ADL, BDL, and CDL. A charging transistor 55 (FIG. 11) for precharging is connected to the wiring LBUS. The wiring LBUS is connected to a wiring DBUS via a switch transistor DSW.

[0053] 11, the sense amplifier SA includes a sense transistor 41. The sense transistor 41 discharges the charge on the line LBUS in response to the current flowing through the bit line BL. The source electrode of the sense transistor 41 is connected to the ground voltage V SS The sense node SEN is connected to a voltage supply line through which a voltage is supplied. The drain electrode is connected to the wiring LBUS via a switch transistor 42. The gate electrode is connected to the bit line BL via a sense node SEN, a discharge transistor 43, a node COM, a clamp transistor 44, and a voltage-resistant transistor 45. The sense node SEN is connected to an internal control signal line CLKSA via a capacitor 48.

[0054] The sense amplifier SA also includes a voltage transfer circuit. The voltage transfer circuit transfers the node COM and the sense node SEN to a voltage V DD The voltage supply line or voltage V SRCThe voltage transfer circuit selectively connects the node N1 to a voltage supply line to which voltage V is supplied. The voltage transfer circuit includes a node N1, a charging transistor 46, a charging transistor 49, a charging transistor 47, and a discharging transistor 50. The charging transistor 46 is connected between the node N1 and a sense node SEN. The charging transistor 49 is connected between the node N1 and a node COM. The charging transistor 47 is connected between the node N1 and a voltage V DD A discharge transistor 50 is connected between the node N1 and the voltage supply line to which the voltage V SRC The gate electrodes of the charge transistor 47 and the discharge transistor 50 are commonly connected to a node INV_S of the latch circuit SDL.

[0055] The sense transistor 41, the switch transistor 42, the discharge transistor 43, the clamp transistor 44, the charge transistor 46, the charge transistor 49, and the discharge transistor 50 are, for example, enhancement type NMOS transistors. The voltage-resistant transistor 45 is, for example, a depletion type NMOS transistor. The charge transistor 47 is, for example, a PMOS transistor.

[0056] Also, the gate electrode of the switch transistor 42 is connected to a signal line STB. The gate electrode of the discharge transistor 43 is connected to a signal line XXL. The gate electrode of the clamp transistor 44 is connected to a signal line BLC. The gate electrode of the voltage-resistant transistor 45 is connected to a signal line BLS. The gate electrode of the charge transistor 46 is connected to a signal line HLL. The gate electrode of the charge transistor 49 is connected to a signal line BLX. These signal lines STB, XXL, BLC, BLS, HLL, and BLX are connected to a sequencer SQC.

[0057] The latch circuit SDL includes nodes LAT_S and INV_S, an inverter 51, an inverter 52, a switch transistor 53, and a switch transistor 54. The inverter 51 includes an output terminal connected to the node LAT_S and an input terminal connected to the node INV_S. The inverter 52 includes an input terminal connected to the node LAT_S and an output terminal connected to the node INV_S. The switch transistor 53 is provided in a current path between the node LAT_S and a wiring LBUS. The switch transistor 54 is provided in a current path between the node INV_S and a wiring LBUS. The switch transistors 53 and 54 are, for example, NMOS transistors. The gate electrode of the switch transistor 53 is connected to the sequencer SQC via a signal line STL. The gate electrode of the switch transistor 54 is connected to the sequencer SQC via a signal line STI.

[0058] The latch circuits ADL, BDL, and CDL are configured in almost the same manner as the latch circuit SDL. However, as described above, the node INV_S of the latch circuit SDL is electrically connected to the gate electrodes of the charge transistor 47 and the discharge transistor 50 in the sense amplifier SA. The latch circuits ADL, BDL, and CDL differ from the latch circuit SDL in this respect.

[0059] The switch transistor DSW is, for example, an NMOS transistor. The switch transistor DSW is connected between the wiring LBUS and the wiring DBUS. The gate electrode of the switch transistor DSW is connected to the sequencer SQC via a signal line DBS.

[0060] As shown in FIG. 10, the above-mentioned signal lines STB, HLL, XXL, BLX, BLC, and BLS are commonly connected among all the sense amplifier units SAU included in the sense amplifier module SAM. DD The voltage supply line and voltage V SRCThe voltage supply lines to which the signal lines STI and STL of the latch circuit SDL are supplied are connected in common to all the sense amplifier units SAU included in the sense amplifier module SAM. Similarly, the signal lines ATI, ATL, BTI, BTL, CTI, and CTL corresponding to the signal lines STI and STL in the latch circuits ADL, BDL, and CDL are connected in common to all the sense amplifier units SAU included in the sense amplifier module SAM. Meanwhile, a plurality of the signal lines DBS are provided corresponding to all the sense amplifier units SAU included in the sense amplifier module SAM.

[0061] [Circuit configuration of cache memory CM] The cache memory CM (FIG. 4) includes a plurality of latch circuits XDL as shown in FIG 10. The plurality of latch circuits XDL are connected to the latch circuits in the sense amplifier module SAM via wiring DBUS.

[0062] The data DAT contained in these latch circuits XDL are sequentially transferred to the latch circuits in the sense amplifier module SAM during a write operation. Also, the data DAT contained in the latch circuits in the sense amplifier module SAM are sequentially transferred to the latch circuits XDL during a read operation. In general, when data transfer is performed using the wiring DBUS, the power supply voltage V CC The operating current I flows through the pad electrode Px to which CC Also, the data DAT contained in the latch circuit XDL is sequentially transferred to the input / output control circuit I / O via the bidirectional bus YIO during a data out operation.

[0063] In addition, a decode circuit and a switch circuit (not shown) are connected to the cache memory CM. The decode circuit decodes the column address CA held in the address register ADR. The switch circuit connects the latch circuit corresponding to the column address CA to the bidirectional bus YIO (FIG. 4) in response to the output signal of the decode circuit.

[0064] [Circuit configuration of sequencer SQC] The sequencer SQC (Figure 4) reads the command data D held in the command register CMR. CMD In accordance with the above, the sequencer SQC outputs internal control signals to the row decoder RD, the sense amplifier module SAM, and the voltage generating circuit VG. In addition, the sequencer SQC outputs status data D ST is output to the status register STR.

[0065] Moreover, the sequencer SQC generates a ready / busy signal RB and outputs it to a terminal RBn. The ready / busy signal RB is a signal that notifies the controller die CD whether it is in a ready state in which it can accept a command from the controller die CD, or in a busy state in which it cannot accept a command. During a period in which the voltage of the terminal RBn is in an “L” state (busy period), access to the memory die MD is basically prohibited. During a period in which the voltage of the terminal RBn is in an “H” state (ready period), access to the memory die MD is permitted. The terminal RBn is realized by, for example, the pad electrode Px described with reference to FIG. 2 and FIG. 3.

[0066] [Circuit configuration of input / output control circuit I / O] The input / output control circuit I / O includes data signal input / output terminals DQ0 to DQ7, toggle signal input / output terminals DQS, / DQS, a plurality of input circuits, a plurality of output circuits, a shift register, and a buffer circuit. The plurality of input circuits, the plurality of output circuits, the shift register, and the buffer circuit are each connected to a power supply voltage V CC and ground voltage V SS is connected to the terminal supplied with

[0067] Data signal input / output terminals DQ0 to DQ7, toggle signal input / output terminals DQS, / DQS, and power supply voltage V CC The terminals to which the data are supplied are realized by, for example, the pad electrodes Px described with reference to Figures 2 and 3. The data input via the data signal input / output terminals DQ0 to DQ7 is output from the buffer circuit to the cache memory CM, the address register ADR, or the command register CMR in response to an internal control signal from the logic circuit CTR. Also, the data output via the data signal input / output terminals DQ0 to DQ7 is input from the cache memory CM or the status register STR to the buffer circuit in response to an internal control signal from the logic circuit CTR.

[0068] The input circuits include, for example, a comparator connected to any one of the data signal input / output terminals DQ0 to DQ7 or both of the toggle signal input / output terminals DQS, / DQS. The output circuits include, for example, an OCD (Off Chip Driver) circuit connected to any one of the data signal input / output terminals DQ0 to DQ7 or either of the toggle signal input / output terminals DQS, / DQS.

[0069] [Circuit configuration of logic circuit CTR] The logic circuit CTR (FIG. 4) receives external control signals from the controller die CD via the external control terminals / CEn, CLE, ALE, / WE, RE, and / RE, and outputs internal control signals to the input / output control circuit I / O in response to the external control signals. Note that the external control terminals / CEn, CLE, ALE, / WE, RE, and / RE are realized by, for example, the pad electrodes Px described with reference to FIGS. 2 and 3.

[0070] [Memory die MD structure] 12 is a schematic exploded perspective view showing a configuration example of the semiconductor memory device according to the present embodiment. As shown in FIG. 12, the memory die MD includes a chip C on the memory cell array MCA side. M and the peripheral circuit PC side chip C P And, it is equipped with.

[0071] Chip C MA plurality of pad electrodes Px that can be connected to bonding wires (not shown) are provided on the upper surface of the chip C. M On the underside of I1 Also, chip C P On the upper surface of the I2 The following is Chip C M Regarding the multiple laminated electrodes P I1 The surface on which the pad electrodes Px are provided is called the front surface, and the surface on which the pad electrodes Px are provided is called the back surface. P Regarding the multiple laminated electrodes P I2 The surface on which the chip C is provided is called the front surface, and the surface opposite the front surface is called the back surface. P The surface of the chip C P The chip C is located above the back surface of the chip C. M The back side of the chip is C M The surface of the substrate is provided above the substrate.

[0072] Chip C M and Chip C P is Chip C M Surface and chip C P The surface of the laminated electrodes P I1 is a plurality of laminated electrodes P I2 , and a plurality of bonding electrodes P I2 The electrode is placed in a position where it can be attached to the I1 and the laminated electrode P I2 What is Chip C? M and Chip C P The laminate functions as a laminate electrode for bonding the two and electrically connecting them.

[0073] In the example of FIG. 12, chip C M The corners a1, a2, a3, and a4 of the chip C P These correspond to corners b1, b2, b3, and b4.

[0074] FIG. 13 shows chip C M FIG. 13 is a schematic bottom view showing a configuration example of the laminated electrode P I114 and 15 are schematic cross-sectional views showing a part of the configuration of the memory die MD. M FIG. 17 is a schematic bottom view showing a part of the configuration of the chip C. M 17 is a schematic cross-sectional view showing a part of the configuration of the semiconductor layer 120. Although Fig. 17 shows a YZ cross section, a structure similar to that of Fig. 17 is observed even when a cross section other than the YZ cross section along the central axis of the semiconductor layer 120 (for example, an XZ cross section) is observed.

[0075] [Chip C M Structure of In the example of FIG. 13, chip C M 13 includes four memory planes MPL0, MPL1, MPL2, and MPL3 aligned in the X direction. Each of the four memory planes MPL0 to MPL3 corresponds to a memory cell array MCA (FIG. 5). Each of the four memory planes MPL0 to MPL3 includes a plurality of memory blocks BLK aligned in the Y direction. In the example of FIG. 13, each of the plurality of memory blocks BLK includes hook-up regions R HU and a memory hole region R MH Also, the chip C M The peripheral region R is provided on one end side in the Y direction from the four memory planes MPL0 to MPL3. P Equipped with.

[0076] In the illustrated example, the hook-up region R HU is the memory cell array region R MCA However, this configuration is merely an example, and the specific configuration can be adjusted as appropriate. For example, the hook-up region R HU is the memory cell array region R MCA The hook-up region R may be provided at one end in the X direction, not at both ends in the X direction. HU is the memory cell array region R MCA Alternatively, the light source 10 may be provided at the center or near the center in the X direction.

[0077] Chip C M For example, as shown in FIG. SB and the substrate layer L SB A memory cell array layer L MCA and the memory cell array layer L MCA and a plurality of wiring layers CH, M0, M1, and MB provided below the wiring layers.

[0078] [Chip C M Base layer L SB Structure of For example, as shown in FIG. SB The memory cell array layer L MCA The semiconductor device comprises a conductive layer 100 provided on the upper surface of the substrate, an insulating layer 101 provided on the upper surface of the conductive layer 100, a back surface wiring layer MA provided on the upper surface of the insulating layer 101, and an insulating layer 102 provided on the upper surface of the back surface wiring layer MA.

[0079] The conductive layer 100 may include, for example, a semiconductor layer such as silicon (Si) doped with an N-type impurity such as phosphorus (P) or a P-type impurity such as boron (B), may include a metal such as tungsten (W), or may include a silicide such as tungsten silicide (WSi).

[0080] The conductive layer 100 functions as a part of the source line SL (FIG. 5). Four conductive layers 100 are provided corresponding to the four memory planes MPL0 to MPL3 (FIG. 13). Regions VZ not including the conductive layer 100 are provided at the ends of the memory planes MPL0 to MPL3 in the X and Y directions.

[0081] The insulating layer 101 includes, for example, silicon oxide (SiO2).

[0082] The back wiring layer MA includes a plurality of wirings ma. These wirings ma may include, for example, aluminum (Al).

[0083] Some of the multiple wirings ma function as part of the source lines SL (FIG. 5). Four of these wirings ma are provided corresponding to the four memory planes MPL0 to MPL3 (FIG. 13). Each of these wirings ma is electrically connected to the conductive layer 100.

[0084] In addition, some of the wirings ma function as pad electrodes Px. P The wiring ma is provided in the memory cell array layer L in the region VZ not including the conductive layer 100. MCA The wiring ma is connected to a via contact electrode CC in the insulating layer 102. A part of the wiring ma is exposed to the outside of the memory die MD through an opening TV provided in the insulating layer 102.

[0085] The insulating layer 102 is, for example, a passivation layer made of an insulating material such as polyimide.

[0086] [Chip C M The memory cell array layer L MCA Memory hole region R MH Structure in As described with reference to FIG. MCA 14, a plurality of memory blocks BLK arranged in the Y direction are provided. An inter-block insulating layer ST made of silicon oxide (SiO2) or the like is provided between two memory blocks BLK adjacent to each other in the Y direction.

[0087] 14, the memory block BLK includes a plurality of conductive layers 110 arranged in the Z direction and a plurality of semiconductor layers 120 extending in the Z direction. Also, as shown in FIG 17, a gate insulating film 130 is provided between each of the conductive layers 110 and the semiconductor layers 120.

[0088] The conductive layer 110 has a generally plate-like shape extending in the X direction. The conductive layer 110 may include a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). The conductive layer 110 may also include polycrystalline silicon containing impurities such as phosphorus (P) or boron (B). An interlayer insulating layer 111 such as silicon oxide (SiO2) is provided between the multiple conductive layers 110 arranged in the Z direction.

[0089] Of the multiple conductive layers 110, one or more conductive layers 110 located in the uppermost layer function as the gate electrode of the source side select transistor STS (FIG. 5) and the source side select gate line SGS (see FIG. 14). These multiple conductive layers 110 are electrically independent for each memory block BLK.

[0090] Further, a plurality of conductive layers 110 positioned below this function as gate electrodes and word lines WL of memory cells MC (FIG. 5). These plurality of conductive layers 110 are electrically independent for each memory block BLK.

[0091] In addition, one or more conductive layers 110 located below the above function as the gate electrode of the drain side select transistor STD and the drain side select gate line SGD. For example, as shown in FIG. 16, the width Y SGD is the width Y in the Y direction of the conductive layer 110 functioning as the word line WL. WL In addition, an insulating layer SHE such as silicon oxide (SiO2) is provided between two conductive layers 110 adjacent to each other in the Y direction.

[0092] The semiconductor layers 120 are arranged in a predetermined pattern in the X and Y directions, for example, as shown in FIG. 16. Each of the semiconductor layers 120 functions as a channel region of a plurality of memory cells MC and select transistors (STD, STS) included in one memory string MS (FIG. 12). The semiconductor layer 120 includes, for example, polycrystalline silicon (Si) or the like. The semiconductor layer 120 has a substantially cylindrical shape, and an insulating layer 125 such as silicon oxide is provided in the central portion. The outer peripheral surface of the semiconductor layer 120 is surrounded by a plurality of conductive layers 110, and faces these plurality of conductive layers 110.

[0093] Moreover, an impurity region (not shown) is provided at the upper end of the semiconductor layer 120. This impurity region is connected to the conductive layer 100 (see FIG. 14). This impurity region contains, for example, an N-type impurity such as phosphorus (P) or a P-type impurity such as boron (B).

[0094] In addition, an impurity region (not shown) is provided at the lower end of the semiconductor layer 120. This impurity region is connected to the bit line BL through a via contact electrode ch and a via contact electrode Vy. This impurity region contains an N-type impurity such as phosphorus (P).

[0095] The gate insulating film 130 has a substantially cylindrical shape covering the outer peripheral surface of the semiconductor layer 120, as shown in FIG. 16, for example. The gate insulating film 130 includes a tunnel insulating film 131, a charge storage film 132, and a block insulating film 133 stacked between the semiconductor layer 120 and the conductive layer 110, as shown in FIG. 17, for example. The tunnel insulating film 131 and the block insulating film 133 include, for example, silicon oxide (SiO2) or the like. The charge storage film 132 includes, for example, a film capable of storing charge, such as silicon nitride (SiN). The tunnel insulating film 131, the charge storage film 132, and the block insulating film 133 have a substantially cylindrical shape and extend in the Z direction along the outer peripheral surface of the semiconductor layer 120 except for the contact portion between the semiconductor layer 120 and the conductive layer 100.

[0096] 17 shows an example in which the gate insulating film 130 includes a charge storage film 132 such as silicon nitride. However, the gate insulating film 130 may include a floating gate such as polycrystalline silicon containing N-type or P-type impurities.

[0097] [Chip C M The memory cell array layer L MCA Hookup area R HU Structure in As shown in Figure 15, the hook-up area R HU A plurality of via contact electrodes CC are provided on the conductive layer 110. Each of the plurality of via contact electrodes CC extends in the Z direction and is connected to the conductive layer 110 at its upper end.

[0098] [Chip C M The memory cell array layer L MCA The surrounding area R P Structure in Surrounding area R P 14, a plurality of via contact electrodes CC are provided in correspondence with the pad electrodes Px. The upper ends of the plurality of via contact electrodes CC are connected to the pad electrodes Px.

[0099] [Chip C M [Structure of wiring layers CH, M0, M1, MB] The wiring layers CH, M0, M1, and MB include, for example, a memory cell array layer L MCA Internal configuration and chip C P The semiconductor device is electrically connected to at least one of the components.

[0100] The wiring layer CH includes a plurality of via contact electrodes ch as a plurality of wirings. The plurality of via contact electrodes ch may include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). The via contact electrodes ch are provided corresponding to the plurality of semiconductor layers 120 and are connected to the lower ends of the plurality of semiconductor layers 120.

[0101] The wiring layer M0 includes a plurality of wirings m0. The plurality of wirings m0 may include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as copper (Cu). Some of the plurality of wirings m0 function as bit lines BL. The bit lines BL are arranged in the X direction and extend in the Y direction, as shown in FIG. 16.

[0102] The wiring layer M1 includes a plurality of wirings m1, as shown in Fig. 14. The plurality of wirings m1 may include a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W).

[0103] The wiring layer MB is made up of a plurality of bonding electrodes P I1 These multiple laminated electrodes P I1 For example, the insulating film may include a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as copper (Cu).

[0104] [Chip C P Structure of Chip C P For example, as shown in FIG. 14, the semiconductor substrate 200 includes an electrode layer GC provided above the semiconductor substrate 200, and wiring layers D0, D1, D2, D3, D4, and DB provided above the electrode layer GC.

[0105] [Chip C P Structure of the semiconductor substrate 200 The semiconductor substrate 200 includes P-type silicon (Si) containing P-type impurities such as boron (B). On the surface of the semiconductor substrate 200, an N-type well region 200N containing N-type impurities such as phosphorus (P), a P-type well region 200P containing P-type impurities such as boron (B), a semiconductor substrate region 200S in which the N-type well region 200N and the P-type well region 200P are not provided, and an insulating region 200I are provided. The N-type well region 200N, the P-type well region 200P, and the semiconductor substrate region 200S each function as a part of a plurality of transistors Tr and a plurality of capacitors that configure the peripheral circuit PC.

[0106] [Chip C P [Structure of electrode layer GC] An electrode layer GC is provided on the upper surface of the semiconductor substrate 200 via an insulating layer 200G. The electrode layer GC includes a plurality of electrodes gc facing the surface of the semiconductor substrate 200. Furthermore, each region of the semiconductor substrate 200 and the plurality of electrodes gc included in the electrode layer GC are connected to a via contact electrode CSb.

[0107] The N-type well region 200N, the P-type well region 200P, and the semiconductor substrate region 200S of the semiconductor substrate 200 function as channel regions of a plurality of transistors Tr constituting the peripheral circuit PC, one electrode of a plurality of capacitors, and the like.

[0108] The electrodes gc included in the electrode layer GC function as gate electrodes of the transistors Tr constituting the peripheral circuit PC, the other electrodes of the capacitors, and the like.

[0109] The via contact electrode CSb extends in the Z direction, and its lower end is connected to the upper surface of the semiconductor substrate 200 or the electrode gc. An impurity region containing N-type impurities or P-type impurities is provided at the connection portion between the via contact electrode CSb and the semiconductor substrate 200. The via contact electrode CSb may include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W).

[0110] [Chip C P [Structure of wiring layers D0, D1, D2, D3, D4, DB] For example, as shown in FIG. 14, a plurality of wirings included in D0, D1, D2, D3, D4, and DB are, for example, a memory cell array layer L MCA Internal configuration and chip C P The semiconductor device is electrically connected to at least one of the components.

[0111] The wiring layers D0, D1, and D2 each include a plurality of wirings d0, d1, and d2. The plurality of wirings d0, d1, and d2 may include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W).

[0112] The wiring layers D3 and D4 include a plurality of wirings d3 and d4, respectively. The plurality of wirings d3 and d4 may include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as copper (Cu).

[0113] The wiring layer DB is made up of a plurality of bonding electrodes P I2 These multiple laminated electrodes P I2 For example, the insulating film may include a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as copper (Cu).

[0114] [Threshold voltage of memory cell MC] Next, the threshold voltage of the memory cell MC will be described with reference to Figure 18. Figure 18(a) is a schematic histogram for explaining the threshold voltage of the memory cell MC. The horizontal axis indicates the voltage of the word line WL, and the vertical axis indicates the number of memory cells MC. Figure 18(b) is an example of the threshold voltage of the memory cell MC and the data recorded in the memory cell MC.

[0115] As described above, the memory cell array MCA includes a plurality of memory cells MC. When a write operation is performed on these memory cells MC, the threshold voltages of these memory cells MC are controlled to a plurality of states. FIG. 18(a) shows the distribution of threshold voltages of memory cells MC controlled to eight states. For example, the threshold voltage of a memory cell MC controlled to state A is the read voltage V CGAR Larger, read voltage V CGBR The threshold voltages of all memory cells MC are smaller than the read pass voltage V READ Less than.

[0116] In this embodiment, 3-bit data is recorded in each memory cell MC by adjusting the memory cell MC to one of eight different states.

[0117] For example, the Er state corresponds to the lowest threshold voltage (threshold voltage of memory cells MC in an erased state). For example, data "111" is assigned to memory cells MC corresponding to the Er state.

[0118] The A state corresponds to a threshold voltage higher than the threshold voltage corresponding to the Er state. For example, data "110" is assigned to the memory cells MC corresponding to the A state.

[0119] Moreover, the B state corresponds to a threshold voltage higher than the threshold voltage corresponding to the above-mentioned A state. For example, data "100" is assigned to the memory cells MC corresponding to the B state.

[0120] Similarly, the C state to the G state in the figure correspond to threshold voltages higher than the threshold voltages corresponding to the B state to the F state. For example, data “000”, “010”, “011”, “001”, and “101” are assigned to the memory cells MC corresponding to these distributions.

[0121] In the case of the allocation illustrated in FIG. 18(b), the data of the lower bit (lower page: LP) is read at two read voltages V CGAR ,V CGER The data of the middle bit (Middle Page: MP) can be read at three read voltages V CGBR ,V CGDR ,V CGFR The data of the upper bit (UP: Upper Page) can be distinguished by two read voltages V CGCR ,V CGGRThis type of data allocation is sometimes called a 2-3-2 code. A method of reading out the lower page, middle page, and upper page is called a page read.

[0122] The number of bits of data recorded in the memory cells MC, the number of states, and the allocation of data to each state can be changed as appropriate.

[0123] [Read operation mode type] Next, the types of read operation modes according to this embodiment will be described. The types of read operation modes according to this embodiment include a normal read mode and a cache read mode. In addition, the types of cache read include a first cache read and a second cache read.

[0124] Fig. 19 is a timing chart for explaining the read operation of a normal read and a first cache read, and Fig. 20 is a timing chart for explaining the read operation of a normal read and a second cache read.

[0125] 19 and 20, "Read(N)" indicates a read operation of page N, "Read(N+1)" indicates a read operation of page N+1, and "Read(N+2)" indicates a read operation of page N+2. Here, N is an integer equal to or greater than 1. Furthermore, "Dout(N)" indicates a data-out operation of page N, "Dout(N+1)" indicates a data-out operation of page N+1, and "Dout(N+2)" indicates a data-out operation of page N+2. Furthermore, "ADD(N)" in the command set indicates address data D that identifies page N. ADD "ADD(N+1)" indicates that the page N+1 is included in the address data D ADD "ADD(N+2)" indicates that the page N+2 is included in the address data D ADD This indicates that it includes

[0126] [Normal lead mode] The normal read mode is a mode for executing a normal read read operation. As shown in Figures 19 and 20, in normal read, when the ready / busy signal RB is controlled to the "H" state (ready state), if a command set ("00h-ADD(N)-30h" in Figures 19 and 20) instructing a normal read is received from the controller die CD, a read operation (Read(N)) of page N is started and the ready / busy signal RB is controlled to the "L" state (busy state).

[0127] When a normal read operation (Read(N)) is performed in the memory cell array MCA, read data (read data of page N) is stored in the latch circuit SDL in the sense amplifier module SAM. The read data stored in the latch circuit SDL in the sense amplifier module SAM is transferred to the latch circuit XDL in the cache memory CM before the read operation is completed.

[0128] When a normal read operation (Read(N)) is completed in the memory cell array MCA, the ready / busy signal RB is controlled from the "L" state (busy state) to the "H" state (ready state), and the command set instructing a normal read or cache read becomes available for acceptance. In the normal read mode, the state of the ready / busy signal RB is consistent with "True busy." "True busy" indicates a state in which access to the sense amplifier module SAM is prohibited, or a write operation, read operation, erase operation, etc. is being performed on the memory cell array MCA.

[0129] [Cache read mode] The cache read mode is a mode in which a cache read operation is executed. There are two types of cache read: a first cache read in which a data transfer operation is executed after the cache read operation is completed, and a second cache read in which a data transfer operation is included in the cache read operation.

[0130] [First cache read] As shown in FIG. 19, in the first cache read, when the ready / busy signal RB is controlled to the “H” state (ready state), if a command set (“00h-ADD(N+1)-31h” in FIG. 19, hereinafter sometimes referred to as a cache read command) instructing a cache read is received, a read operation (Read(N+1)) of page N+1 is started, and the ready / busy signal RB is temporarily controlled from the “H” state (ready state) to the “L” state (busy state), and immediately controlled from the “L” state (busy state) to the “H” state (ready state). In this way, the ready / busy signal RB changes in the order of the “H” state, the “L” state, and the “H” state. Since the read data (read data of page N) is stored in the latch circuit XDL, no data transfer operation is required, and the ready / busy signal RB changes in a short time.

[0131] When the ready / busy signal RB is controlled to the “H” state (ready state), a command set instructing data out from the controller die CD (“05h-ADD(N)-E0h” in FIG. 19, hereinafter sometimes referred to as a data out command) is accepted. By accepting this command set, a data out operation Dout(N) of the read data (read data of page N) stored in the latch circuit XDL is started. In a cache read, the read operation (Read(N+1)) and the data out operation Dout(N) are executed in parallel. When the data out operation Dout(N) is completed, the next cache read command (“00h-ADD(N+2)-31h” in FIG. 19) is accepted.

[0132] In this way, when the ready / busy signal RB is controlled to the “H” state (ready state), it is possible to accept a cache read command as the next read operation (Read(N+2)) even if the cache read operation (Read(N+1)) has not been completed.

[0133] When a cache read command ("00h-ADD(N+2)-31h" in FIG. 19) is received from the controller die CD, the ready / busy signal RB is controlled to the "L" state (busy state). The timing at which the cache read command is received is after the specific timing TA. When the read operation (Read(N+1)) of page N+1 is completed, the read data of page N+1 is transferred to the latch circuit XDL. After the read data of page N+1 is transferred to the latch circuit XDL, the read operation (Read(N+2)) of page N+2 is started, and the ready / busy signal RB is controlled to the "H" state (ready state).

[0134] Specifically, when a read operation (Read(N+1)) of page N+1 is performed, read data (read data of page N+1) is stored in the latch circuit SDL in the sense amplifier module SAM. The read data stored in the latch circuit SDL in the sense amplifier module SAM is temporarily stored in the latch circuit ADL in the sense amplifier module SAM before the read operation is completed. The read data stored in the latch circuit ADL is transferred to the latch circuit XDL in the cache memory CM when the read operation of page N+1 is completed and the cache read command ("00h-ADD(N+2)-31h") is executed.

[0135] When the read operation (Read(N+2)) of page N+2 is started, the ready / busy signal RB returns to the “H” state (ready state). In the cache read mode, the state of the ready / busy signal RB does not match “True busy”.

[0136] Thereafter, by receiving a data out command ("05h-ADD(N+1)-E0h" in FIG. 19) from the controller die CD, a data out operation Dout(N+1) of the read data (read data of page N+1) stored in the latch circuit XDL is performed. Then, the read operation (Read(N+2)) and the data out operation Dout(N+1) are executed in parallel. When the data out operation Dout(N+1) is completed, the device becomes ready to accept a command ("3Fh" in FIG. 19) instructing the end of the cache read.

[0137] When a command ("3Fh" in FIG. 19) instructing the end of cache read is received from the controller die CD, the ready / busy signal RB is controlled to the "L" state (busy state). The timing at which the command instructing the end of cache read is received is after the specific timing TA. After the read operation (Read(N+2)) of page N+2 is completed, the read data of page N+2 is transferred to the latch circuit XDL.

[0138] Thereafter, by receiving a data out command ("05h-ADD(N+2)-E0h" in FIG. 19) from the controller die CD, a data out operation Dout(N+2) of the read data (read data of page N+2) stored in the latch circuit XDL is performed.

[0139] [Second cache read] 20, the read operation (Read(N+1)) of page N+1 and the data out operation (Dout(N)) of page N in the second cache read are the same as the read operation (Read(N+1)) of page N+1 and the data out operation (Dout(N)) of page N in the first cache read. Therefore, a duplicated description will be omitted.

[0140] When a cache read command ("00h-ADD(N+2)-31h" in FIG. 20) is received from the controller die CD, the ready / busy signal RB is controlled to the "L" state (busy state). The timing at which the cache read command is received is before the specific timing TA. Immediately after the read operation (Read(N+1)) of page N+1 is completed, the read operation (Read(N+2)) of page N+2 is started, and the ready / busy signal RB is controlled to the "H" state (ready state). In the second cache read, the timing at which the cache read command is received is before the specific timing TA, and before the read operation (Read(N+1)) of page N+1 is completed, the read data of page N+1 is transferred to the latch circuit XDL.

[0141] Specifically, a read operation (Read(N+1)) of page N+1 is performed, and read data (read data of page N+1) is stored in the latch circuit SDL in the sense amplifier module SAM. The read data stored in the latch circuit SDL in the sense amplifier module SAM is transferred to the latch circuit XDL in the cache memory CM before the read operation is completed. In this way, in the second cache read, the read data stored in the latch circuit SDL is transferred to the latch circuit XDL in the cache memory CM without passing through the latch circuit ADL.

[0142] When the read operation of page N+2 (Read(N+2)) starts, the ready / busy signal RB returns to the “H” state (ready state). As shown in Fig. 20, the read operation of page N+1 (Read(N+1)) and the read operation of page N+2 (Read(N+2)) are executed consecutively without any interval.

[0143] After that, by receiving a data out command ("05h-ADD(N+1)-E0h" in FIG. 20) from the controller die CD, a data out operation Dout(N+1) of the read data (read data of page N+1) stored in the latch circuit XDL is performed. Then, the read operation (Read(N+2)) and the data out operation Dout(N+1) are executed in parallel. When the data out operation Dout(N+1) is completed, the device becomes ready to accept a command ("3Fh" in FIG. 20) instructing the end of the next cache read.

[0144] When a command ("3Fh" in FIG. 20) instructing the end of cache read is received from the controller die CD, the ready / busy signal RB is controlled to the "L" state (busy state). The timing at which the command instructing the end of cache read is received is before the specific timing TA. Before the read operation of page N+2 is completed, the read data of page N+2 is transferred to the latch circuit XDL.

[0145] After that, by receiving a data out command ("05h-ADD(N+2)-E0h" in FIG. 20) from the controller die CD, a data out operation Dout(N+2) of the read data (read data of page N+2) stored in the latch circuit XDL is performed.

[0146] In this way, the data transfer speed of the interface between the controller die CD and the memory die MD is being increased, and the time of the data out operation Dout is being shortened. Therefore, the cache read command and the command instructing the end of the cache read are more likely to be accepted before the specific timing TA. In this case, as shown in FIG. 20, before the read operation of the cache read is completed, the read data is transferred from the latch circuit SDL to the latch circuit XDL. As a result, the total time of the read operations of the cache read that are executed consecutively can be shortened.

[0147] [Command set for read operation] Next, an operation upon receiving a command set for a read operation will be described with reference to FIG 21, which is a timing chart for explaining an operation upon receiving a command set CS.

[0148] In the following description, 8-bit data input to the eight data signal input / output terminals DQ0 to DQ7 may be expressed using two-digit hexadecimal numbers. For example, when "0,0,0,0,0,0,0,0,0" is input to the eight data signal input / output terminals DQ0 to DQ7, this data may be expressed as data 00h, etc. When "1,1,1,1,1,1,1,1" is input, this data may be expressed as data FFh, etc.

[0149] 21 illustrates an example of a command set CS input to the memory die MD during a cache read operation. This command set CS is the cache read command described above.

[0150] The command set CS includes data 00h, A101, A102, A103, A104, A105, and 31h. Among the data included in this command set CS, the data A101, A102, A103, A104, and A105 are designated as data D ADD This data is sometimes called D ADD is the data input to the address register ADR.

[0151] At timing t1, the controller die CD transmits command data D to the memory die MD. CMD As shown in FIG. 4, data 00h is input. That is, the voltage of the data signal input / output terminals DQ0 to DQ7 is set to "H" or "L" according to each bit of data 00h, "H" is input to the external control terminal CLE, and "L" is input to the external control terminal ALE. In this state, the external control terminal / WE is raised from "L" to "H". Data 00h is the command input at the start of a read operation.

[0152] At timing t2, the controller die CD transmits address data D to the memory die MD. ADD (FIG. 4) is input as data A101. That is, the voltage of the data signal input / output terminals DQ0 to DQ7 is set to "H" or "L" according to each bit of the data A101, "L" is input to the external control terminal CLE, and "H" is input to the external control terminal ALE. In this state, the external control terminal / WE is raised from "L" to "H". The data A101 is part of the column address CA.

[0153] At timing t3, the controller die CD transmits address data D to the memory die MD. ADD Data A102 is input as shown in FIG. 4. Data A102 is a part of the column address CA.

[0154] At timing t4, the controller die CD transmits address data D to the memory die MD. ADD Data A103 is input as (FIG. 4). Data A103 is a part of row address RA. Data A103 includes, for example, a block address and a page address. The block address is data that specifies a memory block BLK. The page address is data that specifies a string unit SU and a word line WL.

[0155] At timing t5, the controller die CD transmits address data D to the memory die MD. ADD (FIG. 4) Data A104 is input as the row address RA. Data A104 includes, for example, a block address and a page address.

[0156] At timing t6, the controller die CD transmits address data D to the memory die MD. ADDData A105 is input as (FIG. 4). The data A105 includes a chip address and a plane address. The chip address is data that identifies one of the multiple memory die MD controlled by the controller die CD. The plane address is data that identifies one of the multiple memory planes MPL0 to MPL3 controlled by the controller die CD.

[0157] At timing t7, the controller die CD transmits command data D to the memory die MD. CMD (FIG. 4) The data 31h is a command indicating that the input of the command set CS for the read operation has ended.

[0158] At timing t8, the voltage of the terminal RBn (ready / busy signal RB) changes from the “H” state to the “L” state, and access to the memory die MD is prohibited. Also, a read operation is executed in the memory die MD.

[0159] In the example of FIG. 21, data D in the command set CS ADD In each case, the data are A101, A102, A103, A104, and A105. However, this data D ADD does not mean the same address, but may be different addresses.

[0160] [Read voltage supply operation] Next, the read voltage supply operation for normal read and cache read will be described.

[0161] 22 is a schematic cross-sectional view for explaining the read voltage supply operation. Note that the read voltage supply operation described below is common to both normal read and cache read.

[0162] In the following description, the word line WL that is the object of the operation is referred to as the selected word line WL S and the other word lines WL are called unselected word lines WLU In the following description, the selected word line WL S An example of executing a read voltage supply operation to a memory cell connected to the selected page PG will be described below. In addition, in the following description, a configuration including such a plurality of selected memory cells MC may be referred to as a selected page PG.

[0163] In the read voltage supply operation, for example, a voltage V DD For example, the latch circuit SDL in FIG. 11 is caused to latch "H" and the states of the signal lines STB, XXL, BLC, BLS, HLL, and BLX are set to "L, L, H, H, H, H, H." This causes a voltage V DD Also, a voltage V SRC Supply voltage V SRC is the ground voltage V SS It can be larger than the ground voltage V SS It can be equal to the voltage V DD is the voltage V SRC Greater than.

[0164] In addition, in the read voltage supply operation, the drain side select gate line SGD is supplied with a voltage V SG Supply voltage V SG is the voltage V DD Also, the voltage V SG and voltage V DD The voltage difference between the drain side select transistor STD and the drain side select transistor STD is greater than the threshold voltage of the drain side select transistor STD. Therefore, an electron channel is formed in the channel region of the drain side select transistor STD, and a voltage V DD will be transferred.

[0165] In addition, in the read voltage supply operation, a voltage V SG Supply voltage V SG is the voltage V SRC Also, the voltage V SG and voltage VSRC The voltage difference between the source side select transistors STS and STSb and the threshold voltage V SRC will be transferred.

[0166] In addition, in the read voltage supply operation, the unselected word lines WL U The read pass voltage V READ Supply the read pass voltage V READ is the voltage V DD ,V SRC Also, the read pass voltage V READ and voltage V DD ,V SRC The voltage difference between the selected memory cell MC and the unselected memory cell MC is greater than the threshold voltage when the memory cell MC functions as an NMOS transistor, regardless of the data stored in the memory cell MC. Therefore, an electron channel is formed in the channel region of the unselected memory cell MC, and a voltage V DD ,V SRC will be transferred.

[0167] In addition, in the read voltage supply operation, the selected word line WL S Read voltage V CGR Supply the read voltage V CGR is the read pass voltage V READ The read voltage V CGR is the read voltage V CGAR ~V CGGR The read voltage V CGR and voltage V SRC The voltage difference between the read voltage V and the bit line BL is larger than the threshold voltage of the memory cell MC in which some data is stored. Therefore, the memory cell MC in which some data is stored is in the ON state. Therefore, a current flows through the bit line BL connected to such a memory cell MC. On the other hand, the read voltage V CGR and voltage V SRCThe voltage difference between the bit line BL and the threshold voltage of the memory cell MC in which some data is stored is smaller than the threshold voltage of the memory cell MC in which some data is stored. Therefore, the memory cell MC in which some data is stored is in the OFF state. Therefore, no current flows through the bit line BL connected to such a memory cell MC.

[0168] In addition, in the read voltage supply operation, the sense amplifier SA (FIG. 11) detects whether or not a current flows through the bit line BL, thereby detecting the ON / OFF state of the memory cell MC. Hereinafter, such an operation is called a "sense operation." In the sense operation, for example, a voltage V DD In the state where the sense amplifier unit SAU is supplying the signal lines STB, XXL, BLC, BLS, HLL, and BLX are set to "L, H, H, H, L, L". This allows the sense node SEN of the sense amplifier SA (FIG. 11) to be electrically connected to the bit line BL. After a certain period of time has elapsed, the signal lines STB, XXL, BLC, BLS, HLL, and BLX are set to "L, L, H, H, L, L". This allows the sense node SEN of the sense amplifier SA (FIG. 11) to be electrically disconnected from the bit line BL. After the sense operation is performed, the signal line STB is temporarily set to "H". This allows the sense transistor 41 to be electrically connected to the wiring LBUS (FIG. 11), and the charge of the wiring LBUS is discharged or maintained. Also, any one of the latch circuits (e.g., the latch circuit SDL) in the sense amplifier unit SAU is electrically connected to the wiring LBUS, and the data of the wiring LBUS is latched by this latch circuit.

[0169] In addition, in the read voltage supply operation, as necessary, arithmetic operations such as AND and OR are performed on the data indicating the state of the memory cell MC, thereby calculating the data recorded in the memory cell MC. This data is transferred to the latch circuit XDL (FIG. 10) in the cache memory CM via the wiring LBUS (FIG. 11), the switch transistor DSW, and the wiring DBUS.

[0170] [Cache read read operation] Next, a cache read operation according to the first embodiment will be described.

[0171] Fig. 23 is a waveform diagram for explaining a read operation of a first cache read, and Fig. 24 is a waveform diagram for explaining a read operation of a second cache read.

[0172] In the following explanation, data is assigned to each memory cell MC in the manner described with reference to Figure 18 (b), and an example will be described in which data is read from the lower page (LP) and middle page (MP).

[0173] 23 and 24, "tR" means a period during which a read operation is being performed. Also, "R" means a period during which the selected word line WL S The voltage of the selected word line WL is set to the first read voltage. S The period R is a period during which the voltage is set to the second (and third) read voltage. Also, "RR" means a period during which a recovery operation is performed during a read operation. In general, the period R is longer than the period RWL, and the period RR is shorter than the period R and the period RWL.

[0174] [First cache read operation] The read operation of the first cache read will be described with reference to FIG.

[0175] 23, timing t101 to timing t105 and timing t111 to timing t114 correspond to period R. Timing t105 to timing t107A, timing t114 to timing t116A, and timing t116A to timing t118 correspond to period RWL. Timing t107A to timing t109A and timing t118 to timing t120 correspond to period RR.

[0176] In FIG. 23, a plurality of operations executed from timing t103 to timing t107A and from timing t112 to timing t118 correspond to the read voltage supply operation described with reference to FIG. 22, respectively.

[0177] When starting a cache read operation, the controller die CD outputs a command set CS(1) that instructs the cache read operation to the memory die MD via the data signal input / output terminals DQ0 to DQ7. The command set CS(1) includes data 00h, ADD, and 31h, as shown in Fig. 20. Note that numbers are added to the command sets CS to distinguish between multiple command sets CS.

[0178] At timing t101, when the command set CS(1) is input, the data 00h and 31h of the command set CS(1) are converted into the command data D CMD The data D of the command set CS(1) is stored in the command register CMR as ADD is address data D ADD The address is stored in the address register ADR as the address.

[0179] In response to the input of the command set CS(1), the sequencer SQC controls the terminal RBn (ready / busy signal RB) to change from the “H” state to the “L” state. Accordingly, access to the memory die MD is prohibited. Also, a read operation is executed in the memory die MD. Also, at the point in time when the read operation is started, “True busy” changes from the “H” state to the “L” state.

[0180] At timing t102, the sequencer SQC controls the terminal RBn to change from the "L" state to the "H" state.

[0181] At timing t102, the unselected word line WL U Voltage of V SS Read pass voltage V READ Also, the drain side select gate line SGD is charged to V SG supplies.

[0182] Also, at timing t102, the controller die CD outputs a data out command to the memory die MD via the data signal input / output terminals DQ0 to DQ7. The data out command includes data 05h, ADD, and E0h, as shown in FIG.

[0183] Data 05h is the command data D input to the command register CMR. CMD This data 05h is input at the beginning of data out. Data D ADD is the data D of the cache read command. ADD The data E0h is the same as the command data D input to the command register CMR. CMD This data E0h is data indicating that the input of the data out command has ended.

[0184] At timing t103, the selected word line WL included in the selected memory block BLK S , the read voltage V CGER As a result, the memory cells MC corresponding to the Er state to the D state in FIG. 18(a) are turned on, and the memory cells MC corresponding to the E state to the G state are turned off.

[0185] Although not shown in FIG. 23, at timing t103, the voltage of the bit line BL included in the selected memory block BLK is set to the ground voltage V SS to voltage V DD At timing t103, the source line SL included in the selected memory block BLK is charged to a voltage V SRC supplies.

[0186] At timing t104, a sense operation ("sense" in FIG. 23) is performed. As a result, the sense amplifier SA outputs a read voltage V CGER The read data (E) corresponding to the bit line 114 is acquired. The read data (E) is held in the latch circuit SDL.

[0187] At timing t105, the selected word line WL S Read voltage V CGAR As a result, the memory cells MC corresponding to the Er state in FIG. 18(a) are turned on, and the memory cells MC corresponding to the A states to G states are turned off.

[0188] At timing t106A, a sense operation is performed. As a result, the sense amplifier SA is supplied with a read voltage V CGAR The sense amplifier SA performs a predetermined logical operation on the read data (E) and the read data (A). The latch circuit SDL holds the result (E&A) of this logical operation. The result (E&A) of this logical operation is the read data [LP] of the lower bit (lower page).

[0189] A recovery operation is performed from timing t107A to timing t109A. Timing t107A corresponds to the specific timing TA described with reference to FIG. 19. Therefore, if the cache read command (00h-ADD-31h) is not input by timing t107A, the transfer of read data (E&A) from the latch circuit SDL to the latch circuit XDL is not performed at timing t107A. Also, in the recovery operation, the charge pump circuit 32 (FIG. 7) is reset, and the selected word line WL S and unselected word lines WL U Stop the voltage generation to the selected word line WL S and unselected word lines WL U For example, the ground voltage V SS Converge to.

[0190] In FIG. 23, at timing t108A after timing t107A, a cache read command (00h-ADD-31h) is input as a command set CS(2). The read data (E&A) stored in the latch circuit SDL is then transferred to the latch circuit ADL at timing t109A. In FIG. 23, the transfer of the read data (E&A) from the latch circuit SDL to the latch circuit ADL is indicated as "SDL2ADL". The read data (E&A) stored in the latch circuit ADL is transferred to the latch circuit XDL at timing t111. In FIG. 23, the transfer of the read data (E&A) from the latch circuit ADL to the latch circuit XDL is indicated as "ADL2XDL". The power supply required for data transfer to the latch circuit XDL is prepared, for example, at timing t109A.

[0191] In addition, the sequencer SQC controls the terminal RBn (ready / busy signal RB) to change from the "H" state to the "L" state in response to the input of the command set CS(2) at timing t108A. Accordingly, access to the memory die MD is prohibited. In addition, at timing t108A, the unselected word line WL U The voltages are the read pass voltage V READ to ground voltage V SS After the read operation is completed, the selected word line WL S to ground voltage V SS , and a read operation is performed on the memory die MD.

[0192] At timing t111, the sequencer SQC controls the terminal RBn to change from the “L” state to the “H” state. Also, at timing t111, the unselected word line WL U Voltage of V SS Read pass voltage V READ Also, the drain side select gate line SGD is charged to V SG supplies.

[0193] Furthermore, at timing t111, the memory die MD receives a data-out command (05h-ADD-E0h) from the controller die CD via the data signal input / output terminals DQ0 to DQ7.

[0194] At timing t112, the selected word line WL included in the selected memory block BLK S , the read voltage V CGFR As a result, the memory cells MC corresponding to the Er state to the E state in FIG. 18(a) are turned on, and the memory cells MC corresponding to the F state to the G state are turned off.

[0195] Although not shown in FIG. 23, at timing t112, the voltage of the bit line BL included in the selected memory block BLK is set to the ground voltage V SS to voltage V DD At timing t112, the source line SL included in the selected memory block BLK is charged to a voltage V SRC supplies.

[0196] At timing t113, a sense operation is performed. As a result, the sense amplifier SA is supplied with a read voltage V CGFR The read data (F) corresponding to the input signal is acquired. The read data (F) is held in the latch circuit SDL.

[0197] At timing t114, the selected word line WL S Read voltage V CGDR As a result, the memory cells MC corresponding to the Er state to the C state in FIG. 18(a) are turned on, and the memory cells MC corresponding to the D state to the G state are turned off.

[0198] At timing t115, a sense operation is performed. As a result, the sense amplifier SA is supplied with a read voltage V CGDRThe sense amplifier SA obtains read data (D) corresponding to the read data (F) and the read data (D). The latch circuit SDL holds the result (F&D) of this logical operation.

[0199] At timing t116A, the selected word line WL S Read voltage V CGBR As a result, the memory cells MC corresponding to the Er state to the A state in FIG. 18(a) are turned on, and the memory cells MC corresponding to the B state to the G state are turned off.

[0200] At timing t117, a sense operation is performed. As a result, the sense amplifier SA is supplied with a read voltage V CGBR The sense amplifier SA performs a predetermined logical operation on the read data (F), read data (D), and read data (B). The latch circuit SDL holds the result of this logical operation (F, D&B). The result of this logical operation (F, D&B) is the read data [MP] of the middle bit (middle page).

[0201] A recovery operation is performed from timing t118 to timing t120. Timing t118 corresponds to the specific timing TA described with reference to FIG. 19. Therefore, if the cache read command CS(3) is not input by timing t118, the transfer of read data (F, D & B) from the latch circuit SDL to the latch circuit XDL is not performed at timing t120. Also, in the recovery operation, the charge pump circuit 32 (FIG. 7) is reset, and the selected word line WL S and unselected word lines WL U Stop the voltage output to the selected word line WL S and unselected word lines WL U For example, the ground voltage V SS Converge to.

[0202] In FIG. 23, at timing t119A after timing t118, a cache read command (00h-ADD-31h) is input. Then, the read data (F, D&B) stored in the latch circuit SDL is transferred to the latch circuit ADL at timing t120. Also, the read data (F, D&B) stored in the latch circuit ADL is transferred to the latch circuit XDL at timing t121. After that, although not shown in FIG. 23, the read data (F, D&B) stored in the latch circuit XDL is output to the controller die CD based on a data out operation.

[0203] [Second cache read operation] The read operation of the second cache read will be described with reference to FIG.

[0204] In FIG. 24, the operations from timing t103 to timing t107A and timing t112 to timing t118 correspond to the read voltage supply operation described with reference to FIG.

[0205] The operations from timing t101 to timing t105, timing t111 to timing t115, and timing t116A to timing t118 in FIG. 24 are similar to the operations described with reference to FIG. 23, and therefore will not be described again.

[0206] In Fig. 24, at timing t106B prior to timing t107A, a cache read command CS(2) is input. The read data (E&A) stored in the latch circuit SDL is then transferred to the latch circuit XDL at timing t111. In Fig. 24, the transfer of the read data (E&A) from the latch circuit SDL to the latch circuit XDL is represented as "SDL2XDL". Note that the power supply required for data transfer to the latch circuit XDL is prepared at, for example, timing t101.

[0207] A recovery operation is performed from timing t107A to timing t111. In the recovery operation, the charge pump circuit 32 (FIG. 7) is not reset, and the selected word line WL S and unselected word lines WL U At timing t107A, for example, the voltage supply from the charge pump circuit 32 is stopped by a switch circuit between the charge pump circuit 32 and the wiring CG, and an equalizer circuit (not shown) located downstream of the switch circuit is used to maintain the voltage generation to the selected word line WL S and unselected word lines WL U For example, the ground voltage V SS Converge to.

[0208] At timing t111, the equalizer circuit is closed, the switch circuit is opened, and the selected word line WL S and unselected word lines WL U In Fig. 24, the charge pump circuit 32 is not reset during the recovery operation.

[0209] The operations from timing t111 to timing t115 in FIG. 24 are similar to those described with reference to FIG. 23, and therefore will not be described again.

[0210] In FIG. 24, at timing t116B prior to timing t118, a cache read command CS(3) is input. Then, the read data (F&D&B) stored in the latch circuit SDL is transferred to the latch circuit XDL at timing t120. In FIG. 24, the transfer of the read data (F&D&B) from the latch circuit SDL to the latch circuit XDL is represented as "SDL2XDL". After that, although not shown in FIG. 24, the read data (F&D&B) stored in the latch circuit XDL is output to the controller die CD based on a data out operation.

[0211] [Data transfer operation] Next, the data transfer operation will be described with reference to FIG.

[0212] Fig. 25 is a flowchart for explaining the data transfer operation. The operations of steps S101 to S106 in Fig. 25 correspond to the operations of timing t107A to timing t111 and timing t118 to timing t121 in Fig. 23, and the operations of timing t106B to timing t111 and timing t116B to timing t121 in Fig. 24. In Fig. 25, the operations of steps S102 to S106 correspond to the data transfer operation.

[0213] For example, the read operation corresponding to the cache read command CS(1) is a read operation of page N, and the read operation corresponding to the cache read command CS(2) is a read operation of page N+1.

[0214] In step S101, when the memory die MD inputs a cache read command for page N+1 (see timing t108A in FIG. 23 and timing t106B in FIG. 24), in step S102, the memory die MD determines whether or not a read operation for page N is being executed. If a read operation for page N is being executed (YES in step S102), in step S103, the memory die MD determines whether or not the timing at which the cache read command for page N+1 was input is before the start of the recovery operation for the read operation for page N (before timing t107A in FIG. 23 and FIG. 24).

[0215] If the read operation of page N is not being executed (NO in step S102), or if the timing at which the cache read command of page N+1 is input is not before the start of the recovery operation of the read operation of page N (NO in step S103), in step S104, the memory die MD transfers the read data stored in the latch circuit SDL to the latch circuit ADL (step S104). This operation corresponds to the operation from timing t107A to timing t109A in FIG. 23. This operation corresponds to the operation from timing t109A to timing t110A in FIG. 23. In step S105, the read data stored in the latch circuit ADL is transferred to the latch circuit XDL. This operation corresponds to the operation from timing t110A to timing t111 in FIG. 23.

[0216] If the timing at which the cache read command for page N+1 is input is before the start of the recovery operation in the read operation for page N (YES in step S103), in step S106, the read data stored in the latch circuit SDL is transferred to the latch circuit XDL. This operation corresponds to the operations from timing t107A to timing t111 in FIG.

[0217] According to this configuration, when cache read operations are executed consecutively, the first cache read and the second cache read are automatically switched according to the timing of inputting the latter cache read command. Therefore, the data transfer operation is optimized according to the timing of inputting the latter cache read command. As a result, the interval between consecutively executed read operations can be shortened.

[0218] In addition, with the increase in the data transfer speed of the interface between the controller die CD and the memory die MD, the time of the data out operation Dout is being shortened. Even if the data out operation Dout ends early, a data transfer operation may be executed after the end of a read operation. The configuration according to the first embodiment is effective in solving the above problems. Furthermore, the configuration according to the first embodiment can be realized without using a special command set for optimizing the data transfer operation.

[0219] For example, a comparison between a cache read in a comparative example and a cache read in the first embodiment will be described. Fig. 26 is a timing chart for describing a cache read in the comparative example and a read operation of a second cache read in the first embodiment. Fig. 27 is a timing chart for describing a cache read in the comparative example and a read operation of a first cache read in the first embodiment.

[0220] As shown in Figures 26 and 27, when a cache read command is input, the ready / busy signal RB is controlled to change from the "H" state to the "L" state, and when read data is transferred to the latch circuit XDL, the ready / busy signal RB is controlled to change from the "L" state to the "H" state.

[0221] In FIG. 26, the upper diagram shows a case where cache read operations are continuously executed in the comparative example, and the lower diagram shows a case where second cache read operations are continuously executed in the first embodiment.

[0222] As shown in the upper diagram of FIG. 26, in the cache read in the comparative example, even if the timing of inputting the cache read command (00h-ADD(N+2)-31h) is before the specific timing TA, the data transfer operation from the latch circuit ADL to the latch circuit XDL is executed after the end of the cache read read operation (Read(N+1)). In this case, after the data transfer operation from the latch circuit ADL to the latch circuit XDL is executed, the read operation of the next cache read is started. On the other hand, as shown in the lower diagram of FIG. 26, in the second cache read in the first embodiment, if the timing of inputting the cache read command (00h-ADD(N+2)-31h) is before the specific timing TA, the data transfer operation from the latch circuit SDL to the latch circuit XDL is executed before the end of the cache read read operation (Read(N+1)). In this case, the read operation of the next cache read is started immediately after the end of the cache read read operation.

[0223] As shown in FIG. 26, the time from when the cache read command (00h-ADD(N+2)-31h) is input to when the data transfer operation to the latch circuit XDL is completed (the period during which the ready / busy signal RB is in the “L” state) is shorter for the second cache read in the first embodiment (lower diagram in FIG. 26) than for the cache read in the comparative example (upper diagram in FIG. 26).

[0224] In FIG. 27, the upper diagram shows a case where cache read operations are continuously executed in the comparative example, and the lower diagram shows a case where first cache read operations are continuously executed in the first embodiment.

[0225] As shown in the upper diagram of FIG. 27, in the cache read in the comparative example, if the timing of inputting the cache read command (00h-ADD(N+2)-31h) is after the specific timing TA, the data transfer operation from the latch circuit ADL to the latch circuit XDL is executed after the end of the cache read read operation (Read(N+1)). In this case, after the data transfer operation from the latch circuit ADL to the latch circuit XDL is executed, the read operation of the next cache read is started. Also, as shown in the lower diagram of FIG. 27, the first cache read in the first embodiment is similar to the cache read in the comparative example. That is, if the timing of inputting the cache read command (00h-ADD(N+2)-31h) is after the specific timing TA, the data transfer operation from the latch circuit ADL to the latch circuit XDL is executed after the end of the cache read read operation (Read(N+1)).

[0226] The time from when the cache read command (00h-ADD(N+2)-31h) is input to when the data transfer operation to the latch circuit XDL is completed (the period during which the ready / busy signal RB is in the “L” state) is the same for the cache read in the comparative example (upper diagram of FIG. 27) and the first cache read in the first embodiment (lower diagram of FIG. 27).

[0227] Furthermore, the time from when the cache read command (00h-ADD(N+2)-31h) is input to when the data transfer operation to the latch circuit XDL is completed (the period during which the ready / busy signal RB is in the "L" state) is longer for the first cache read in the first embodiment (lower diagram in FIG. 27) than for the second cache read in the first embodiment (lower diagram in FIG. 26). In other words, if the timing of inputting the cache read command (00h-ADD(N+2)-31h) is delayed, in the first embodiment, the period during which the ready / busy signal RB is in the "L" state immediately after inputting the cache read command (00h-ADD(N+2)-31h) becomes longer.

[0228] In contrast, in the cache read in the comparative example, the time is shorter when the cache read command (00h-ADD(N+2)-31h) is input late (upper diagram in FIG. 27) than when it is input early (upper diagram in FIG. 26). In other words, when the time to input the cache read command (00h-ADD(N+2)-31h) is delayed, the time during which the ready / busy signal RB is in the "L" state immediately after input of the cache read command (00h-ADD(N+2)-31h) becomes shorter in the comparative example.

[0229] [Second embodiment] Next, a cache read operation according to the second embodiment will be described.

[0230] FIG. 28 is a waveform diagram for explaining the read operation of the second cache read in the second embodiment. In the read operation of the second cache read described with reference to FIG. 24, the read data stored in the latch circuit SDL is directly transferred to the latch circuit XDL during the period RR of the recovery operation (see timing t107A to timing t111 and timing t118 to timing t121 in FIG. 24). In contrast, in the read operation of the second cache read shown in FIG. 28, the read data stored in the latch circuit SDL is transferred to the latch circuit ADL during the period RR of the recovery operation (see timing t208 to timing t209 and timing t217 to timing t218 in FIG. 28). At the beginning of the period R in the read operation of the next cache read, the read data stored in the latch circuit ADL is transferred to the latch circuit XDL (see timing t209 to timing t210 and timing t218 to timing t219 in FIG. 28).

[0231] Note that configurations other than those described above in the read operation of the second cache read shown in Fig. 28 are similar to the read operation of the second cache read described with reference to Fig. 24. That is, the operations from timing t201 to timing t208 and timing t210 to timing t217 in Fig. 28 are similar to the operations from timing t101 to timing t107A and timing t112 to timing t118 in Fig. 24. Therefore, overlapping descriptions will be omitted.

[0232] Although the first cache read in the second embodiment (a cache read command input after the specific timing TA) is not shown in Fig. 28, like the second cache read in the second embodiment (a cache read command input before the specific timing TA), during the period RR of the recovery operation, the read data stored in the latch circuit SDL is transferred to the latch circuit ADL, and at the beginning of the period R of the read operation of the next cache read, the read data stored in the latch circuit ADL is transferred to the latch circuit XDL. Details of the first cache read in the second embodiment will be described later (see Fig. 30).

[0233] Even with this configuration, when cache read operations are executed consecutively, the first cache read and the second cache read are automatically switched according to the timing of inputting the latter cache read command. Therefore, the data transfer operation is optimized according to the timing of inputting the latter cache read command. As a result, the interval between consecutively executed read operations can be shortened.

[0234] For example, a comparison between a cache read in a comparative example and a cache read in a second embodiment will be described. Fig. 29 is a timing chart for explaining a cache read in the comparative example and a read operation of a second cache read in the second embodiment. Fig. 30 is a timing chart for explaining a cache read in the comparative example and a read operation of a first cache read in the second embodiment.

[0235] As shown in Figures 29 and 30, when a cache read command is input, the ready / busy signal RB is controlled to change from the "H" state to the "L" state, and when read data is transferred to the latch circuit XDL, the ready / busy signal RB is controlled to change from the "L" state to the "H" state.

[0236] In FIG. 29, the upper diagram shows a case where cache read operations are continuously executed in the comparative example, and the lower diagram shows a case where second cache read operations are continuously executed in the second embodiment.

[0237] The cache read in the comparative example shown in the upper diagram of FIG. 29 is the same as the cache read in the comparative example shown in the upper diagram of FIG. 26. In this case, after the data transfer operation from the latch circuit ADL to the latch circuit XDL is executed, the read operation of the next cache read (Read(N+2)) is started. On the other hand, as shown in the lower diagram of FIG. 29, in the second cache read in the second embodiment, if the timing of inputting the cache read command (00h-ADD(N+2)-31h) is before the specific timing TA, the data transfer operation from the latch circuit SDL to the latch circuit ADL is executed before the end of the read operation of the cache read (Read(N+1)), and the read operation of the next cache read (Read(N+2)) is started immediately after the end of the read operation of the cache read (Read(N+1)). During the execution of the read operation of the cache read (Read(N+2)), the data transfer operation from the latch circuit ADL to the latch circuit XDL is executed.

[0238] As shown in FIG. 29, the time from when the cache read command (00h-ADD(N+2)-31h) is input to when the data transfer operation to the latch circuit XDL is completed (the period during which the ready / busy signal RB is in the “L” state) is the same for the cache read in the comparative example (upper diagram of FIG. 29) and the second cache read in the second embodiment (lower diagram of FIG. 29).

[0239] When a cache read operation (Read(N+2)) starts, the unselected word line WL U For the read pass voltage V READ is charged, and data is transferred from the latch circuit ADL to the latch circuit XDL. Therefore, as shown in FIG. CC The operating current I flows through the pad electrode Px to which CC This operating current I CC is the operating current I when a cache read operation (Read(N+1)) starts. CC Larger than.

[0240] In FIG. 30, the upper diagram shows a case where cache read operations are continuously executed in the comparative example, and the lower diagram shows a case where first cache read operations are continuously executed in the second embodiment.

[0241] The cache read in the comparative example shown in the upper diagram of FIG. 30 is the same as the cache read in the comparative example shown in the upper diagram of FIG. 27. In this case, after the data transfer operation from the latch circuit ADL to the latch circuit XDL is executed, the read operation of the next cache read (Read(N+2)) is started. On the other hand, as shown in the lower diagram of FIG. 30, in the first cache read in the second embodiment, if the timing of inputting the cache read command (00h-ADD(N+2)-31h) is after the specific timing TA, the data transfer operation from the latch circuit SDL to the latch circuit ADL is executed before the end of the read operation of the cache read (Read(N+1)), and the read operation of the next cache read (Read(N+2)) is started immediately after the end of the read operation of the cache read (Read(N+1)). During the execution of the read operation of the cache read (Read(N+2)), the data transfer operation from the latch circuit ADL to the latch circuit XDL is executed.

[0242] As shown in Figure 30, the time from when the cache read command (00h-ADD(N+2)-31h) is input to when the data transfer operation to the latch circuit XDL is completed (the period during which the ready / busy signal RB is in the "L" state) is the same for the cache read in the comparative example (upper diagram of Figure 30) and the first cache read in the second embodiment (lower diagram of Figure 30). Note that the above period for the first cache read in the second embodiment (lower diagram of Figure 30) is shorter than the above period for the second cache read in the second embodiment (lower diagram of Figure 29).

[0243] When a cache read operation (Read(N+2)) starts, the unselected word line WL U For the read pass voltage V READ is charged, and data is transferred from the latch circuit ADL to the latch circuit XDL. Therefore, as shown in FIG. CC The operating current I flows through the pad electrode Px to which CC This operating current I CCis the operating current I when a cache read operation (Read(N+1)) starts. CC Larger than.

[0244] [Third embodiment] Next, a read operation of the linked read according to the third embodiment will be described.

[0245] Fig. 31 is a waveform diagram for explaining the read operation of the linked read in the third embodiment. Fig. 32 is a diagram showing a part of the waveform in the read operation of the linked read in the third embodiment. Here, in the read operation of the linked read, when a specific condition is satisfied, the cache read read operations of the previous and next pages are linked.

[0246] In the following explanation, as in the case explained in Figure 31, data is assigned to each memory cell MC in the manner explained with reference to Figure 18 (b), and an example will be explained in which data is read from the lower page (LP), middle page (MP), upper page (UP), and lower page (LP).

[0247] When starting a read operation of the linked read, the controller die CD outputs a command set for instructing a read operation of the normal read to the memory die MD via the data signal input / output terminals DQ0 to DQ7. The command set includes data 00h, ADD, and 30h, as shown in FIG.

[0248] Data D ADD is assumed to be data that specifies, for example, the lower page (LP), memory block BLKx, word line WLm, and memory string MSa to be operated on.

[0249] At timing t301, when a command set is input, data 00h and 30h of the command set are input as command data D CMD The data of the command set is stored in the command register CMR as ADD is address data D ADDThe address is stored in the address register ADR as the address.

[0250] In response to the input of the command set, the sequencer SQC controls the terminal RBn (ready / busy signal RB) to change from the “H” state to the “L” state. Accordingly, access to the memory die MD is prohibited. Also, a read operation is executed in the memory die MD. Also, at the point in time when the read operation starts, “True busy” changes from the “H” state to the “L” state.

[0251] At timing t302, the unselected word line WL included in the selected memory block BLKx U Voltage of V SS Read pass voltage V READ Also, the drain side select gate line SGD (MSa) is charged to the voltage V SG supplies.

[0252] Here, all the unselected word lines WL included in the selected memory block BLKx U Read the pass voltage V READ When charging the power supply voltage V, a positive charge is supplied to the charge pump circuit 32 which functions as the voltage generating unit vg2 (FIG. 6) or supplies a voltage to the voltage generating unit vg2 (FIG. 6). As a result, as shown in FIG. CC The operating current I flows through the pad electrode Px to which CC increases.

[0253] At timing t303, the selected word line WL included in the selected memory block BLKx S , the read voltage V CGER As a result, the memory cells MC corresponding to the Er state to the D state in FIG. 18(a) are turned on, and the memory cells MC corresponding to the E state to the G state are turned off.

[0254] Although not shown in FIG. 31, at timing t303, the voltage of the bit line BL included in the selected memory block BLKx is set to the ground voltage V SSto voltage V DD At timing t303, the source line SL included in the selected memory block BLKx is charged to a voltage V SRC supplies.

[0255] Next, a sense operation ("sense" in FIG. 31) is performed. As a result, the sense amplifier SA is supplied with a read voltage V CGER The read data (E) corresponding to the power supply voltage V is obtained. This read data (E) is held in the latch circuit SDL. When a sense operation is performed, the amount of charge required to charge the sense node SEN increases. Then, as shown in FIG. 31, CC The operating current I flows through the pad electrode Px to which CC In the following, when performing a sense operation, the operating current I CC increases.

[0256] At timing t304, the selected word line WL S Read voltage V CGAR As a result, the memory cells MC corresponding to the Er state in FIG. 18(a) are turned on, and the memory cells MC corresponding to the A states to G states are turned off.

[0257] Next, a sense operation is performed. This causes the sense amplifier SA to supply the read voltage V CGAR The sense amplifier SA performs a predetermined logical operation on the read data (E) and the read data (A). The latch circuit SDL holds the result (E&A) of this logical operation. The result (E&A) of this logical operation is the read data [LP] of the lower bit (lower page).

[0258] At timing t305, the sequencer SQC controls the terminal RBn to change from the “L” state to the “H” state.

[0259] At timing t306, when a command set CS(1) instructing a cache read is input, data 00h and 31h of the command set CS(1) are input as command data D CMD The data D of the command set CS(1) is stored in the command register CMR as ADD is address data D ADD The address is stored in the address register ADR as the address.

[0260] Data D ADD is assumed to be data that specifies, for example, the middle page (MP), memory block BLKx, word line WLm, and memory string MSa that are the target of the operation.

[0261] In response to the input of the command set CS(1), the sequencer SQC controls the terminal RBn (ready / busy signal RB) to change from the “H” state to the “L” state. Accordingly, access to the memory die MD is prohibited. Also, a read operation is performed on the memory die MD.

[0262] At timing t307, the sequencer SQC controls the terminal RBn to change from the “L” state to the “H” state.

[0263] At timing t307, the unselected word line WL U Voltage of V SS Read pass voltage V READ Also, the drain side select gate line SGD (MSa) is charged to the voltage V SG This provides the power supply voltage V CC The operating current I flows through the pad electrode Px to which CC increases.

[0264] Also, at timing t307, the controller die CD outputs a data out command to the memory die MD via the data signal input / output terminals DQ0 to DQ7. The data out command includes data 05h, ADD, and E0h, as shown in FIG.

[0265] Data 05h is the command data D input to the command register CMR. CMD This data 05h is input at the beginning of data out. Data D ADD is the data D of the command set (00h-ADD-30h) that indicates a normal read. ADD The data E0h is the same as the command data D input to the command register CMR. CMD This data E0h is data indicating that the input of the data out command has ended. When the memory die MD inputs the data out command, the data out operation Dout(LP) (Dout(N-1) in FIG. 32) is started.

[0266] At timing t307, the selected word line WL included in the selected memory block BLKx S , the read voltage V CGFR As a result, the memory cells MC corresponding to the Er state to the E state in FIG. 18(a) are turned on, and the memory cells MC corresponding to the F state to the G state are turned off.

[0267] As shown in FIG. 32, at timing t307, the voltage of the bit line BL included in the selected memory block BLKx is set to the ground voltage V SS to voltage V DD At timing t307, the source line SL included in the selected memory block BLKx is charged to a voltage V SRC supplies.

[0268] Next, a sense operation is performed. This causes the sense amplifier SA to supply the read voltage V CGFR The read data (F) corresponding to the input signal is acquired. The read data (F) is held in the latch circuit SDL.

[0269] At timing t308, the selected word line WL S Read voltage V CGDRAs a result, the memory cells MC corresponding to the Er state to the C state in FIG. 18(a) are turned on, and the memory cells MC corresponding to the D state to the G state are turned off.

[0270] Next, a sense operation is performed. This causes the sense amplifier SA to supply the read voltage V CGDR The sense amplifier SA obtains read data (D) corresponding to the read data (F) and the read data (D). The latch circuit SDL holds the result (F&D) of this logical operation.

[0271] At timing t309, the selected word line WL S Read voltage V CGBR As a result, the memory cells MC corresponding to the Er state to the A state in FIG. 18(a) are turned on, and the memory cells MC corresponding to the B state to the G state are turned off.

[0272] Next, a sense operation is performed. This causes the sense amplifier SA to supply the read voltage V CGBR The sense amplifier SA performs a predetermined logical operation on the read data (F), read data (D), and read data (B). The latch circuit SDL holds the result of this logical operation (F&D&B). The result of this logical operation (F&D&B) is the read data [MP] of the middle bit (middle page).

[0273] 31 and 32, when the data out operation (Dout(LP) in FIG. 31, Dout(N-1) in FIG. 32) is completed, the next cache read command ("00h-ADD-31h" in FIG. 31 and FIG. 32) can be accepted. When the cache read command CS(2) is input, the sequencer SQC controls the terminal RBn from the "H" state to the "L" state.

[0274] Data D included in cache read command CS(2) ADDis assumed to be data that specifies, for example, the upper page (UP), memory block BLKx, word line WLm, and memory string MSa to be operated on.

[0275] In this case, the memory block BLKx, the word line WLm, and the memory string MSa are common to the middle page (page N in FIG. 32) and the upper page (page N+1 in FIG. 32). In this case, as shown in FIG. 31 and FIG. 32, the read operation of the middle page (page N in FIG. 32) and the read operation of the upper page (page N+1 in FIG. 32) are linked.

[0276] Specifically, as shown in FIG. 32, the period RR of the recovery operation of the middle page (page N in FIG. 32) is deleted, and the last period RWL of the middle page is linked to the first period R of the upper page. Note that the first period R of the upper page is linked to the period RWL of the middle page, so that the period R becomes the period RWL. In this way, by linking the middle page and the upper page, the time for the read operation is shortened. Also, by linking the middle page and the upper page, the unselected word lines WL U The read pass voltage V READ , the voltage V supplied to the drain side select gate line SGD (MSa) SG , the voltage V supplied to the source line SL SRC , and the voltage V supplied to the bit line BL DD is the ground voltage V SS Therefore, it is not necessary to discharge and charge these wirings, and the power supply voltage V CC The operating current I flows through the pad electrode Px to which CC is suppressed.

[0277] In addition, if the timing of inputting the cache read command CS(2) is later than the specific timing TA (timing t310 in FIG. 31 and FIG. 32), the read operation of the middle page (page N in FIG. 32) and the read operation of the upper page (page N+1 in FIG. 32) are not linked. In this case, at timing t310, a recovery operation (period RR) is performed, and during the recovery operation (period RR), a data transfer operation is performed from the latch circuit SDL to the latch circuit ADL. In addition, after the read operation of the upper page (page N+1 in FIG. 32) is completed, a data transfer operation is performed from the latch circuit ADL to the latch circuit XDL. The same applies to the case where the timing of inputting the cache read commands CS(3) and CS(4) is later than the specific timing TA (timings t312 and t314 in FIG. 31 and FIG. 32).

[0278] At timing t310, the sequencer SQC controls the terminal RBn to change from the "L" state to the "H" state. Although not shown in Figures 31 and 32, at timing t310, the read data (F&D&B) stored in the latch circuit SDL is transferred to the latch circuit ADL. Then, the read data (F&D&B) stored in the latch circuit ADL is transferred to the latch circuit XDL. Note that at timing t310, the read data (F&D&B) stored in the latch circuit SDL may be directly transferred to the latch circuit XDL.

[0279] At timing t310, the selected word line WL S , the read voltage V CGGR As a result, the memory cells MC corresponding to the Er state to the F state in FIG. 18(a) are turned on, and the memory cells MC corresponding to the G state are turned off.

[0280] In response to the memory die MD inputting a data out command, a data out operation Dout(MP) (Dout(N) in FIG. 32) is started.

[0281] Next, a sense operation is performed. This causes the sense amplifier SA to supply the read voltage V CGGR The read data (G) corresponding to the first bit is acquired. The read data (G) is held in the latch circuit SDL.

[0282] At timing t311, the selected word line WL S Read voltage V CGCR As a result, the memory cells MC corresponding to the Er state to the B state in FIG. 18(a) are turned on, and the memory cells MC corresponding to the C state to the G state are turned off.

[0283] Next, a sense operation is performed. This causes the sense amplifier SA to supply the read voltage V CGCR The sense amplifier SA performs a predetermined logical operation on the read data (G) and the read data (C). The latch circuit SDL holds the result (G&C) of this logical operation. The result (G&C) of this logical operation is the read data [UP] of the upper bit (upper page).

[0284] 31 and 32, when the data out operation (Dout(MP) in FIG. 31, Dout(N) in FIG. 32) is completed, the next cache read command ("00h-ADD-31h" in FIG. 31 and FIG. 32) can be accepted. When the cache read command CS(3) is input, the sequencer SQC controls the terminal RBn from the "H" state to the "L" state.

[0285] Data D included in cache read command CS(3) ADD is, for example, data specifying the lower page (LP), memory block BLKx, word line WLm, and memory string MSb to be operated on.

[0286] In this case, the upper page (page N+1 in FIG. 32) and the lower page (page N+2 in FIG. 32) share the same memory block BLKx and word line WLm. On the other hand, the memory string MSb of the lower page is different from the memory string MSa of the upper page. Even in this case, the read operation of the middle page (page N+1 in FIG. 32) and the read operation of the upper page (page N+2 in FIG. 32) are linked as shown in FIG. 31 and FIG. 32.

[0287] Specifically, as shown in FIG. 32, the period RR of the recovery operation of the upper page (page N+1 in FIG. 32) is deleted, and the last period RWL of the upper page and the first period R of the lower page are linked. Note that the first period R of the lower page is linked with the period RWL of the upper page, so that the period R becomes the period RWL. In this way, the upper page and the lower page are linked, thereby shortening the time of the read operation. Also, the unselected word lines WL U , it is no longer necessary to discharge and charge the source line SL and the bit line BL, and the power supply voltage V CC The operating current I flows through the pad electrode Px to which CC is suppressed.

[0288] As described above, since the memory string MSa of the upper page and the memory string MSb of the lower page are different, the memory string MS is switched. At timing t312, the voltage V SG is discharged, and the ground voltage V SS Then, the drain side select gate line SGD(MSb) corresponding to the address of the memory string MSb is lowered to the ground voltage V SS to voltage V SG It will be charged until

[0289] Also, at timing t312, the sequencer SQC controls the terminal RBn to change from the "L" state to the "H" state. Although not shown in Figures 31 and 32, at timing t312, the read data (G&C) stored in the latch circuit SDL is transferred to the latch circuit ADL. Then, the read data (G&C) stored in the latch circuit ADL is transferred to the latch circuit XDL. Note that at timing t312, the read data (G&C) stored in the latch circuit SDL may be transferred directly to the latch circuit XDL.

[0290] At timing t312, the selected word line WL included in the selected memory block BLKx S , the read voltage V CGER As a result, the memory cells MC corresponding to the Er state to the D state in FIG. 18(a) are turned on, and the memory cells MC corresponding to the E state are turned off.

[0291] In response to the memory die MD inputting a data out command, a data out operation Dout(UP) (Dout(N+1) in FIG. 32) is started.

[0292] Next, a sense operation is performed. This causes the sense amplifier SA to supply the read voltage V CGER The read data (E) corresponding to the bit line 114 is acquired. The read data (E) is held in the latch circuit SDL.

[0293] At timing t313, the selected word line WL S Read voltage V CGAR As a result, the memory cells MC corresponding to the Er state in FIG. 18(a) are turned on, and the memory cells MC corresponding to the A states to G states are turned off.

[0294] Next, a sense operation is performed. This causes the sense amplifier SA to supply the read voltage V CGARThe sense amplifier SA performs a predetermined logical operation on the read data (E) and the read data (A). The latch circuit SDL holds the result (E&A) of this logical operation. The result (E&A) of this logical operation is the read data [LP] of the lower bit (lower page).

[0295] 31 and 32, when the data out operation (Dout(UP) in FIG. 31, Dout(N+1) in FIG. 32) is completed, the next cache read command ("00h-ADD-31h" in FIG. 31 and FIG. 32) is ready to be accepted. When the cache read command CS(4) is input, the sequencer SQC controls the terminal RBn from the "H" state to the "L" state.

[0296] Data D included in cache read command CS(4) ADD is assumed to be data that specifies, for example, the middle page (MP), memory block BLKy, word line WLm, and memory string MSb that are the target of the operation.

[0297] Data D included in the above cache read command CS(3) ADD and the data D included in the next cache read command CS(4) ADD If the addresses of the memory block BLKx or the word line WLm are different, the read operation of page N+2 and the read operation of the next page are not linked. In this case, at timing t314, the unselected word line WL U Read pass voltage V READ , the voltage of the drain side select gate line SGD (MSb) V SG , the voltage V of the source line SL SRC , and the voltage V of the bit line BL DD are discharged, respectively.

[0298] Even if the addresses of the memory block BLKx and the word line WLm are the same, the read operation of the normal read and the read operation of the cache read are not linked.

[0299] FIG. 33 is a flowchart for explaining a read operation of the linked read in the third embodiment.

[0300] In step S201, the memory die MD inputs a cache read command for page N (see timing t306 in FIG. 31). In step S202, the memory die MD inputs a cache read command for page N+1 (see timing t309 in FIG. 31). In step S203A, the memory die MD determines whether or not a read operation for page N is being executed. If a read operation for page N is being executed (YES in step S203A), in step S203B, the memory die MD determines whether or not the timing at which the cache read command for page N+1 was input is before the start of the recovery operation of the read operation for page N (before timing t310 in FIG. 31 and FIG. 32).

[0301] If the timing at which the cache read command for page N+1 is input is before the start of the recovery operation in the read operation of page N (YES in step S203B), in step S204, the memory die MD determines whether the addresses of the memory blocks BLK of page N and page N+1 are the same.

[0302] If the addresses of the memory blocks BLK of page N and page N+1 are the same (YES in step S204), in step S205, the memory die MD determines whether the addresses of the word lines WL of page N and page N+1 are the same. If the addresses of the word lines WL of page N and page N+1 are the same (YES in step S205), in step S206, the memory die MD determines whether the addresses of the memory strings MS of page N and page N+1 are the same.

[0303] If the addresses of the memory strings MS of page N and page N+1 are the same (YES in step S206), in step S207, the memory die MD SWiring other than the selected word line (WL U , drain side select gate line SGD, source side select gate line SGS, source line SL, bit line BL) and maintains the voltage of those wirings. On the other hand, if the addresses of the memory strings MS of page N and page N+1 are different (NO in step S206), in step S208, the memory die MD discharges the selected word line WL S And wiring other than the drain side select gate line SGD (unselected word line WL U , source side select gate line SGS, source line SL, bit line BL) is not discharged, and the voltage of these wirings is maintained. S For the period RR, the read voltage supply operation is connected without executing the recovery operation (period RR).

[0304] If the read operation of page N is not being executed (NO in step S203A), if the timing of inputting the cache read command for page N+1 is not before the start of the recovery operation in the read operation of page N (NO in step S203B), if the addresses of the memory blocks BLK of page N and page N+1 are different (NO in step S204), or if the addresses of the word lines WL of page N and page N+1 are different (NO in step S205), in step S209, the memory die MD reads the selected word line WL S And all wiring including the drain side select gate line SGD (select word line WL S , unselected word lines WL U , the drain side select gate line SGD, the source side select gate line SGS, the source line SL, and the bit line BL) are discharged, and then the voltages of all the wirings are charged.

[0305] According to this configuration, when the cache read operation is executed continuously, if a specific condition (steps S203 to S206) is satisfied, the read operation of the previous and next pages is linked. Therefore, the period during which the cache read operation is executed can be shortened. In addition, it is no longer necessary to discharge and charge the specified wiring, and the power supply voltage V CCThe operating current I flows through the pad electrode Px to which CC is suppressed.

[0306] [Fourth embodiment] FIG. 34 is a waveform diagram for explaining a read operation of the connected read in the fourth embodiment.

[0307] In the read operation of the linked read according to the third embodiment, as shown in FIG. S Read voltage V CGFR ,V CGDR ,V CGBR ,V CGGR ,V CGCR ,V CGER ,V CGAR In contrast, in the linked read operation according to the fourth embodiment, as shown in FIG. S Read voltage V CGFR ,V CGDR ,V CGBR ,V CGCR ,V CGGR ,V CGER ,V CGAR The rest of the configuration is the same as that described with reference to Fig. 32, so a duplicated description will be omitted.

[0308] According to this configuration, the selected word line WL S Since the amount of transition of the read voltage level of the cache is reduced, the period during which the cache read operation is being performed can be shortened, and it is no longer necessary to discharge and charge the specified wiring, so that the power supply voltage V CC The operating current I flows through the pad electrode Px to which CC In addition, the read voltage level can be smoothly switched.

[0309] In FIG. 34, a reverse read (V CGFR ,V CGDR ,V CGBR) and a forward read (V CGCR ,V CGGR ), then perform a reverse read (V CGER ,V CGAR ) was performed. However, forward lead (V CGBR ,V CGDR ,V CGFR ) and perform a reverse read (V CGGR ,V CGCR ) and then perform a forward read (V CGAR ,V CGER ) can be executed.

[0310] FIG. 35 is a waveform diagram for explaining a modified example of the read operation of the linked read in the fourth embodiment. In FIG. CGBR ,V CGDR ,V CGFR ) and perform a reverse read (V CGGR ,V CGCR ) and then perform a forward read (V CGAR ,V CGER 35, in the modified example of the linked read read operation according to the fourth embodiment, the selected word line WL S Read voltage V CGBR ,V CGDR ,V CGFR ,V CGGR ,V CGCR ,V CGAR ,V CGER The other configurations are the same as those described with reference to Fig. 32 and Fig. 34, so a duplicated description will be omitted.

[0311] Even in this configuration, the selected word line WL S Since the amount of transition of the read voltage level of the cache is reduced, the period during which the cache read operation is being performed can be shortened, and it is no longer necessary to discharge and charge the specified wiring, so that the power supply voltage V CC The operating current I flows through the pad electrode Px to which CCIn addition, the read voltage level can be smoothly switched.

[0312] In the case of QLC (Quad Level Cell: 16-value data (4 bits) are recorded in a memory cell), for example, a reverse read may be performed, a forward read may be performed, a reverse read may be performed, and then a forward read may be performed. Alternatively, in the case of QLC, for example, a forward read may be performed, a reverse read may be performed, a forward read may be performed, and then a reverse read may be performed.

[0313] In addition, in the case of PLC (short for Penta Level Cell, which records 32 levels of data (5 bits) in a memory cell), for example, a reverse read may be performed, a forward read may be performed, a reverse read may be performed, a forward read may be performed, and then a reverse read may be performed. Or, in the case of PLC, for example, a forward read may be performed, a reverse read may be performed, a forward read may be performed, a reverse read may be performed, and then a forward read may be performed.

[0314] The case where reverse read and forward read are alternately performed has been described. S If the amount of transition in the level of the read voltage is reduced, it is not necessary to alternate between reverse read and forward read.

[0315] [Fifth embodiment] Next, a read operation of sequential read in the fifth embodiment will be described with reference to Fig. 36. A method of performing a read operation on the lower page, middle page, and upper page all at once is called sequential read.

[0316] 36 is a waveform diagram for explaining the read operation of sequential read in the fifth embodiment. Sequential read is a method of reading read data from a plurality of pages at once. As shown in FIG. 36, for example, when the selected word line WL SThe read voltage supplied to the CGAR ,V CGBR ,V CGCR ,V CGDR ,V CGER ,V CGFR ,V CGGR The read data of the lower page, the middle page, and the upper page are sequentially stored in the latch circuit XDL of the cache memory CM. Then, each time the read data is stored, the data is output.

[0317] In the example of FIG. 36, the memory block BLKx and word line WLm are common to the first and second sequential reads. On the other hand, the memory string MSa of the first sequential read and the memory string MSb of the second sequential read are different. In such a case, as shown in FIG. 36, the read operation of the first sequential read and the read operation of the second sequential read can be linked. In this case, the unselected word line WL U Read pass voltage V READ is connected without being discharged or charged. Meanwhile, the voltage V SG The battery is discharged and charged.

[0318] With this configuration as well, the period during which the sequential read operation is being performed can be shortened, and it is no longer necessary to discharge and charge the specified wiring, so that the power supply voltage V CC The operating current I flows through the pad electrode Px to which CC is suppressed.

[0319] In the sequential read in the fifth embodiment, a command set dedicated to sequential read (for example, 50h-00h-ADD-31h) is used to instruct the execution of the sequential read. In the command set dedicated to sequential read, a prefix command such as “50h” is added.

[0320] Although not shown, a data out operation Dout(N+1) of the read data stored in the latch circuit XDL is performed by receiving a data out command ("05h-ADD-E0h" in FIG. 19) from the controller die CD. In sequential read, the data out operation is performed in the order of, for example, the lower page (LP), the middle page (MP), and the upper page (UP).

[0321] Next, a modification of the first and second embodiments will be described with reference to FIG.

[0322] Fig. 37 is a waveform diagram showing a modification of Fig. 24. The configuration of Fig. 37 is basically the same as the configuration of Fig. 24. Therefore, duplicated explanations of the same configuration will be omitted.

[0323] Between timing t102 and timing t103, the selected word line WL included in the selected memory block BLK S The voltage of is the ground voltage V SS Read pass voltage V READ During the period from timing t102 to timing t103, the unselected word lines WL U The voltage of is the ground voltage V SS Read pass voltage V READ Charge until

[0324] During the period from timing t107A to timing t111, the selected word line WL S The read pass voltage V READ After supplying the ground voltage V SS The period from timing t107A to timing t111 is a period RR during which a recovery operation is performed. This period is also called a channel clean period. In addition, during the period from timing t107A to timing t111, the voltage of the unselected word line WL included in the selected memory block BLK is reduced to 0V. U The voltage of the read pass voltage V READ to ground voltage V SSThe selected word line WL S and unselected word lines WL U The timing of the discharges may be simultaneous.

[0325] From timing t112A to timing t112, the selected word line WL included in the selected memory block BLK S The voltage of is the ground voltage V SS Read pass voltage V READ In addition, from timing t112A to timing t112, the unselected word line WL U The voltage of is the ground voltage V SS Read pass voltage V READ Charge until

[0326] During the period from timing t118 to timing t120, the selected word line WL S The read pass voltage V READ After supplying the ground voltage V SS The period from timing t118 to timing t120 is a channel clean period. In addition, during the period from timing t118 to timing t120, the voltage of the unselected word line WL U The voltage of the read pass voltage V READ to ground voltage V SS Discharge until

[0327] Selected word line WL S and unselected word lines WL U A voltage having a waveform as shown in Fig. 37 may be supplied to the selected word line WL S and unselected word lines WL U The same applies to.

[0328] Next, modifications of the third and fourth embodiments will be described with reference to FIG.

[0329] Fig. 38 is a waveform diagram showing a modification of Fig. 31. The configuration of Fig. 38 is basically the same as the configuration of Fig. 31. Therefore, duplicated explanations of the same configuration will be omitted.

[0330] Between timing t302 and timing t303, the selected word line WL included in the selected memory block BLK S The voltage of is the ground voltage V SS Read pass voltage V READ During the period from timing t302 to timing t303, the unselected word lines WL U The voltage of is the ground voltage V SS Read pass voltage V READ Charge until

[0331] During the period from timing t305A to timing t305, the selected word line WL S The read pass voltage V READ After supplying the ground voltage V SS The period from timing t305A to timing t305 is a period RR during which a recovery operation is performed. This period is also called a channel clean period. In addition, during the period from timing t305A to timing t305, the voltage of the unselected word line WL included in the selected memory block BLK is U The voltage of the read pass voltage V READ to ground voltage V SS The selected word line WL S and unselected word lines WL U The timing of the discharges may be simultaneous.

[0332] In the period from timing t306 to timing t307, the period from timing t310A to timing t310, and the period from timing t312A to timing t312, the selected word line WL S The voltage of is the ground voltage V SS Read pass voltage V READDuring the period from timing t306 to timing t307, the unselected word lines WL U The voltage of is the ground voltage V SS Read pass voltage V READ Charge until

[0333] During the period from timing t314A to timing t314, the selected word line WL S The read pass voltage V READ After supplying the ground voltage V SS The period from timing t314A to timing t314 is a channel clean period. In addition, during the period from timing t314A to timing t314, the voltage of the unselected word line WL U The voltage of the read pass voltage V READ to ground voltage V SS Discharge until

[0334] Selected word line WL S and unselected word lines WL U A voltage having a waveform as shown in Fig. 38 may be supplied to the selected word line WL S and unselected word lines WL U The same applies to.

[0335] [Other embodiments] The semiconductor memory devices according to the first to fifth embodiments have been described above. However, the semiconductor memory devices described above are merely examples, and the operation, configuration, and the like can be adjusted as appropriate.

[0336] For example, in the semiconductor memory devices according to the first to fifth embodiments, 3-bit data is recorded in each memory cell MC as described with reference to Fig. 18. However, the data recorded in the memory cell MC may be 1 bit, 2 bits, 4 bits, or 5 bits or more.

[0337] In the above third to fifth embodiments, whether or not a linked read is executed is determined depending on whether or not the timing at which the cache read command CS is input is before the specific timing TA. However, the configuration may be such that the user can select whether or not to execute a linked read.

[0338] In this case, the SET FEATURE operation may be used to set whether or not to execute linked read. For example, in one mode (enable mode), whether or not to execute linked read is determined according to the timing at which the cache read command CS is input. In another mode (disable mode), linked read is not performed regardless of the timing at which the cache read command CS is input.

[0339] Also, a configuration may be made in which it is possible to specify whether or not to perform a concatenated read using a prefix command. A prefix command is a command added to the beginning of a normal command set. For example, in a command set (xxh-00h-ADD-31h), the prefix command is "xxh". In one mode (enable base mode), when a prefix command is added, a concatenated read is not performed, and when a prefix command is not added, a concatenated read is possible. In another mode (disable base mode), when a prefix command is added, a concatenated read is possible, and when a prefix command is not added, a concatenated read is not performed. The mode selection is set, for example, using a SET FEATURE operation.

[0340] In the first embodiment, the following configuration is disclosed. In response to a first command set, a first read operation is executed, and in response to a second command set, a second read operation is executed consecutively after the first read operation. When the second command set is input at a first timing, a first data transfer operation is executed, and when the second command set is input at a second timing prior to the first timing, a second data transfer operation is executed. The first data transfer operation transfers data held in a first latch circuit (e.g., latch circuit SDL) to the second latch circuit (e.g., latch circuit ADL) in response to the first read operation, and transfers the data held in the second latch circuit (e.g., latch circuit ADL) to the third latch circuit (e.g., latch circuit XDL). The second data transfer operation transfers the data held in the first latch circuit (e.g., latch circuit SDL) to the third latch circuit (e.g., latch circuit XDL) in response to the first read operation.

[0341] Here, the first command set corresponds to, for example, the command set CS(1) input at timing t101 in FIG. 23 and FIG. 24. The second command set corresponds to, for example, the command set CS(2) input at timing t108A in FIG. 23 or timing t106B in FIG. 24. The first read operation corresponds to, for example, the read operation executed at timing t102 to timing t109A in FIG. 23 or timing t102 to timing t111 in FIG. 24. The second read operation corresponds to, for example, the read operation executed at timing t111 to timing t120 in FIG. 23 and FIG. 24. The first timing corresponds to, for example, the timing t108A in FIG. 23. The second timing corresponds to, for example, the timing t106B in FIG. 24. As shown in FIG. 23 and FIG. 24, the second timing is a timing before the first timing. The first data transfer operation corresponds to, for example, the data transfer operation executed at timing t107A to timing t111 in FIG. 23. The second data transfer operation corresponds to, for example, the data transfer operation executed from timing t107A to timing t111 in Fig. 24. As shown in Fig. 23 and Fig. 24, the second data transfer operation has a shorter operation period than the first data transfer operation.

[0342] [others] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0343] 110: conductive layer, 120: semiconductor layer, 130: gate insulating film, WL: word line, WL S ...selected word line (conductive layer, selected conductive layer), WL U...unselected word line (unselected conductive layer), SGD...drain side select gate line (second conductive layer), MC...memory cell, MS...memory string, SU...string unit, BLK...memory block, MCA...memory cell array.

Claims

1. a memory string having a plurality of memory transistors connected in series; a bit line connected to the memory string; a first latch circuit and a second latch circuit sense amplifier unit connected to the bit line; a third latch circuit electrically connected to the sense amplifier unit; Equipped with A first read operation is performed in response to the first command set; A second read operation is performed consecutively after the first read operation in response to a second command set; executes a first data transfer operation when the second command set is input at a first timing; executing a second data transfer operation when the second command set is input at a second timing that is earlier than the first timing; the first data transfer operation includes transferring data held in the first latch circuit to the second latch circuit in response to the first read operation, and transferring the data held in the second latch circuit to the third latch circuit; The second data transfer operation transfers the data held in the first latch circuit to the third latch circuit in response to the first read operation. Semiconductor memory device.

2. a third read operation is performed before the first read operation in response to a third command set; performing a data out operation related to the third read operation in response to a fourth command set; The data out operation outputs data from the third latch circuit to an external device, After the data out operation, the second command set is accepted.

2. The semiconductor memory device according to claim 1.

3. The second data transfer operation is performed during a period in which the first read operation is being performed, and the second read operation is started immediately after the end of the first read operation.

3. The semiconductor memory device according to claim 2.

4. A ready / busy signal indicating whether or not a command set can be received is output. The second command set is input when the ready / busy signal is in a ready state to accept the command set.

2. The semiconductor memory device according to claim 1.

5. When the data is transferred to the third latch circuit, the ready / busy signal goes to the ready state.

5. The semiconductor memory device according to claim 4.

6. a plurality of conductive layers connected to gate electrodes of the plurality of memory transistors; In the first read operation and the second read operation, a read voltage is supplied to a selected conductive layer that is one of the plurality of conductive layers, and a read pass voltage higher than the read voltage is supplied to an unselected conductive layer different from the selected conductive layer; the first timing is a timing later than a third timing at which the read pass voltage starts to drop; The second timing is a timing prior to the third timing.

2. The semiconductor memory device according to claim 1.

7. a plurality of conductive layers connected to gate electrodes of the plurality of memory transistors; In the first read operation and the second read operation, a read voltage is supplied to a selected conductive layer that is one of the plurality of conductive layers, and then a read pass voltage that is greater than the read voltage is supplied to the selected conductive layer; the first timing is a timing after a fourth timing at which the voltage of the selected conductive layer starts to rise to the read pass voltage; The second timing is a timing prior to the fourth timing.

2. The semiconductor memory device according to claim 1.

8. a memory string having a plurality of memory transistors connected in series; a bit line connected to the memory string; a sense amplifier unit connected to the bit line and having a first latch circuit and a second latch circuit; a third latch circuit electrically connected to the sense amplifier unit; Equipped with A first read operation is performed in response to the first command set; A second read operation is performed consecutively after the first read operation in response to a second command set; executes a first data transfer operation when the second command set is input at a first timing; executing a second data transfer operation when the second command set is input at a second timing that is earlier than the first timing; the first data transfer operation transfers data held in the first latch circuit to the second latch circuit in response to the first read operation, and transfers the data held in the second latch circuit before the start of the second read operation to the third latch circuit; the second data transfer operation includes transferring the data held in the first latch circuit to the second latch circuit in response to the first read operation, and transferring the data held in the second latch circuit to the third latch circuit during execution of the second read operation; When the second data transfer operation is performed, the second read operation is started immediately after the first read operation is completed. Semiconductor memory device.

9. a memory string having a plurality of memory transistors connected in series; a plurality of conductive layers connected to gate electrodes of the plurality of memory transistors; Multiple memory blocks and Equipped with A first read operation is performed in response to the first command set; A second read operation is performed consecutively after the first read operation in response to a second command set; each of the first read operation and the second read operation includes a read voltage supply operation of supplying a read voltage to a selected conductive layer that is one of the plurality of conductive layers; When an address of the memory block and the selected conductive layer that are the operation target of the first read operation are the same as an address of the memory block and the selected conductive layer that are the operation target of the second read operation, the read voltage supply operation of the first read operation is coupled to the read voltage supply operation of the second read operation. Semiconductor memory device.

10. A read pass voltage supplied to an unselected conductive layer different from the selected conductive layer among the plurality of conductive layers is maintained during a period in which the first read operation and the second read operation are being performed.

10. The semiconductor memory device according to claim 9.

11. The memory string includes a select gate transistor connected in series with the plurality of memory transistors, a second conductive layer connected to a gate electrode of the select gate transistor; When an address of the second conductive layer that is the target of the first read operation is the same as an address of the second conductive layer that is the target of the second read operation, a voltage supplied to the second conductive layer is maintained during a period in which the first read operation and the second read operation are being performed.

10. The semiconductor memory device according to claim 9.

12. a source line connected to the other end of the memory string; The voltage supplied to the source line is maintained during the period in which the first read operation and the second read operation are being performed.

10. The semiconductor memory device according to claim 9.

13. a bit line connected to one end of the memory string; The voltage supplied to the bit line is maintained during the period in which the first read operation and the second read operation are being performed.

10. The semiconductor memory device according to claim 9.

14. In the first read operation, the read voltage changes from a high level to a low level; In the second read operation, the read voltage changes from a low level to a high level.

10. The semiconductor memory device according to claim 9.

15. In the first read operation, the read voltage changes from a low level to a high level; In the second read operation, the read voltage changes from a high level to a low level.

10. The semiconductor memory device according to claim 9.

16. The second command set is input at a timing during which the read voltage is supplied to the selected conductive layer.

11. The semiconductor memory device according to claim 10.

17. In the first read operation and the second read operation, the read voltage is supplied to the selective conductive layer, and then a read pass voltage is supplied to the selective conductive layer; The second command set is input at a timing before the read pass voltage is reached.

10. The semiconductor memory device according to claim 9.

18. The first command set and the second command set are related to a page read.

10. The semiconductor memory device according to claim 9.

19. the first command set and the second command set are for sequential read; 10. The semiconductor memory device according to claim 9.

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