Semiconductor device and manufacturing method therefor

Abstract

To provide a semiconductor device including an IGBT having an improved switching characteristic.SOLUTION: Inside a trench TR1 and a trench TR2 that are formed in a semiconductor substrate SUB of an active cell AC, a trench gate electrode GE and a trench emitter electrode EE are formed via a gate insulation film GI. In part of the semiconductor substrate SUB between the trench TR1 and the trench TR2, an n-type hole barrier region NHB is formed. In the hole barrier region NHB, a p-type base region PB is formed. In the base region PB, an n-type emitter region NE is formed. In part of the semiconductor substrate SUB of an inactive cell IAC, a p-type floating region PF is formed. The depth of the floating region PF is shorter than the depth of the trenches TR1, TR2 and is longer than the depth of the base region PB.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a gate electrode formed inside a trench and a manufacturing method thereof. [Background technology]

[0002] In recent years, semiconductor devices including power semiconductor elements such as IGBTs (Insulated Gate Bipolar Transistors) have come into widespread use. As an IGBT with low on-resistance, an IGBT having a structure in which a gate electrode is embedded inside a trench is known.

[0003] For example, Patent Document 1 discloses IGBTs with a GGEE structure and an EGE structure that utilize the IE (Injection Enhancement) effect. The IE effect is a technology that increases the concentration of charges accumulated in the drift region by making it difficult for holes to be discharged to the emitter wiring EW side when the IGBT is in the on state.

[0004] The "G" in the GGEE structure refers to a trench gate electrode that is embedded in the trench via a gate insulating film and is connected to a gate potential. The "E" in the GGEE structure refers to a trench emitter electrode that is embedded in the trench via a gate insulating film and is connected to an emitter potential. Therefore, the GGEE structure is a structure in which a pair of trench emitter electrodes are formed at a position some distance away from a pair of trench gate electrodes.

[0005] Patent Document 2 discloses an IGBT with a GGEEs structure in which the cell pitch of the GGEE structure is shrunk. In the GGEEs structure, the distance between a pair of trench emitter electrodes is made shorter than the distance between a pair of trench gate electrodes, and the trench emitter electrode and the base region are connected by the same hole. In other words, the "s" in the GGEEs structure means that the distance between a pair of trench emitter electrodes is shrunk. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] JP 2013-140885 A [Patent Document 2] JP 2017-157733 A Summary of the Invention [Problem to be solved by the invention]

[0007] IGBTs with the GGEE structure are used, for example, in inverters that require large currents. In this case, the saturation current density cannot be increased more than necessary in order to ensure the load short circuit resistance. In addition, the design of this IGBT focuses on lowering the on-voltage by promoting conductivity modulation without increasing the MOSFET (Metal Oxide Semiconductor Field Effect Transistor) components.

[0008] On the other hand, IGBTs for PFC (Power Factor Correction) are used in products such as air conditioners. For IGBTs for PFC, it is important to increase the switching speed and reduce switching losses. Also, since ensuring load short circuit resistance is not a high priority, it is possible to increase the saturation current density.

[0009] If IGBTs for PFC applications could be manufactured using the GGEE structure manufacturing process, it would be possible to shorten the development period, eliminate the need for new manufacturing equipment, and reduce manufacturing costs. In that case, it is necessary to design the IGBT so that the on-voltage is kept low while also increasing the switching speed and reducing switching losses.

[0010] A primary object of the present application is to provide a semiconductor device having an IGBT with improved switching characteristics. Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0011] A brief outline of a representative embodiment of the present invention will be described below.

[0012] A semiconductor device according to one embodiment includes a semiconductor substrate having a first conductivity type and a bottom surface opposite to the top surface, a first trench, a second trench, and a third trench each formed in the semiconductor substrate to reach a predetermined depth from the top surface of the semiconductor substrate, a trench gate electrode formed in the first trench via a first insulating film, a first trench emitter electrode formed in the second trench via a second insulating film, a second trench emitter electrode formed in the third trench via a third insulating film, a first hole barrier region of the first conductivity type formed in the semiconductor substrate between the first trench and the second trench, a first base region of a second conductivity type opposite to the first conductivity type formed in the first hole barrier region, and a gate electrode of the first trench. a first emitter region of the first conductivity type formed in a base region, a second hole barrier region of the first conductivity type formed in the semiconductor substrate between the first trench and the third trench, a second base region of the second conductivity type formed in the second hole barrier region, a second emitter region of the first conductivity type formed in the second base region, a first floating region of the second conductivity type formed in the semiconductor substrate located on one of both side surfaces of the second trench opposite to one side surface on which the first hole barrier region is formed, and a second floating region of the second conductivity type formed in the semiconductor substrate located on the other side surface of the third trench opposite to one side surface on which the second hole barrier region is formed. The depth of each of the first floating region and the second floating region from the top surface of the semiconductor substrate is shallower than the depths of each of the first trench, the second trench, and the third trench from the top surface of the semiconductor substrate and is deeper than the depths of each of the first base region and the second base region from the top surface of the semiconductor substrate.

[0013] A method for manufacturing a semiconductor device according to one embodiment includes the steps of: (a) preparing a semiconductor substrate of a first conductivity type having an upper surface and a lower surface opposite to the upper surface; (b) forming a first hole barrier region of the first conductivity type and a second hole barrier region of the first conductivity type in the semiconductor substrate on the upper surface side of the semiconductor substrate; (c) after the step (b), forming a first trench and a second trench in the semiconductor substrate so as to sandwich the first hole barrier region in a plan view, and forming a third trench in the semiconductor substrate so as to sandwich the second hole barrier region with the first trench in a plan view; (d) after the step (c), forming a first insulating film inside the first trench, forming a second insulating film inside the second trench, and forming a third insulating film inside the third trench; (e) after the step (d), forming a trench gate electrode inside the first trench via the first insulating film, and forming a gate electrode of the second trench via the second insulating film. forming a first trench emitter electrode inside the third trench via the third insulating film; (f) after the step (e), forming a first base region of a second conductivity type opposite to the first conductivity type in the first hole barrier region, forming a second base region of the second conductivity type in the second hole barrier region, forming a first floating region of the second conductivity type in the semiconductor substrate located on the other side of the second trench opposite to the one side on which the first hole barrier region is formed, and forming a second floating region of the second conductivity type in the semiconductor substrate located on the other side of the third trench opposite to the one side on which the second hole barrier region is formed; and (g) after the step (f), forming a first emitter region of the first conductivity type in the first base region, and forming a second emitter region of the first conductivity type in the second base region. The depth of each of the first floating region and the second floating region from the top surface of the semiconductor substrate is shallower than the depth of each of the first trench, the second trench, and the third trench from the top surface of the semiconductor substrate, and is deeper than the depth of each of the first base region and the second base region from the top surface of the semiconductor substrate.

[0014] A semiconductor device according to one embodiment includes an IGBT having a plurality of cells. Each of the plurality of cells includes a trench gate electrode, a first trench emitter electrode, and a second trench emitter electrode formed in an n-type semiconductor substrate, a p-type first base region formed in the semiconductor substrate between the trench gate electrode and the first trench emitter electrode, and a p-type second base region formed in the semiconductor substrate between the trench gate electrode and the second trench emitter electrode. A p-type floating region is formed in the semiconductor substrate between each of the plurality of cells. The depth of the floating region is shallower than the depth of each of the trench gate electrode, the first trench emitter electrode, and the second trench emitter electrode, and is deeper than the depth of each of the first base region and the second base region. Effect of the Invention

[0015] According to one embodiment, a semiconductor device having an IGBT with improved switching characteristics can be provided. [Brief description of the drawings]

[0016] [Figure 1] 1 is a plan view showing a semiconductor device in a first embodiment. [Diagram 2] 1 is a plan view showing a main part of a semiconductor device according to a first embodiment. [Diagram 3] 1 is a cross-sectional view showing a semiconductor device in a first embodiment. [Figure 4] 1 is a cross-sectional view showing a semiconductor device in a first embodiment. [Diagram 5] 1 is a cross-sectional view showing a main part of a semiconductor device according to a first embodiment. [Figure 6] 4 is a graph showing profiles of impurity concentrations of active cells and inactive cells in the first embodiment. [Figure 7] 1 is a cross-sectional view showing a main part of the structure of the first embodiment, the first study example, and the second study example. [Figure 8] 1 is a graph showing the performance of the first embodiment, study example 1, and study example 2. [Figure 9] 2A to 2C are cross-sectional views showing a manufacturing process of the semiconductor device in the first embodiment. [Figure 10] 10 is a cross-sectional view showing a manufacturing process following FIG. 9. [Figure 11] 11 is a cross-sectional view showing a manufacturing process following FIG. 10. [Figure 12] 12 is a cross-sectional view showing a manufacturing process following FIG. 11. [Figure 13] 13 is a cross-sectional view showing a manufacturing process following FIG. 12. [Figure 14] 14 is a cross-sectional view showing a manufacturing process following FIG. 13. [Figure 15] 15 is a cross-sectional view showing a manufacturing process following FIG. 14. [Figure 16] 16 is a cross-sectional view showing a manufacturing process following FIG. 15. [Figure 17] 17 is a cross-sectional view showing a manufacturing process following FIG. 16. [Figure 18] 18 is a cross-sectional view showing a manufacturing process following FIG. 17. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0017] Hereinafter, the embodiments will be described in detail with reference to the drawings. In all the drawings for explaining the embodiments, the same reference numerals are used for the members having the same functions, and the repeated explanations are omitted. In the following embodiments, the explanations of the same or similar parts will not be repeated as a rule unless it is particularly necessary.

[0018] In addition, the X-direction, Y-direction, and Z-direction described in this application intersect with each other and are perpendicular to each other. In this application, the Z-direction is described as the up-down direction, height direction, depth direction, or thickness direction of a structure. In addition, expressions such as "plan view" and "planar view" used in this application mean that a surface formed by the X-direction and the Y-direction is a "plane" and this "plane" is viewed from the Z-direction.

[0019] (Embodiment 1) <Structure of Semiconductor Device> The structure of a semiconductor device 100 according to the first embodiment will be described below with reference to FIGS.

[0020] Fig. 1 is a plan view showing a semiconductor chip that is a semiconductor device 100. As shown in Fig. 1, most of the semiconductor device 100 is covered with an emitter wiring EW. A gate wiring GW surrounds the emitter wiring EW in a plan view.

[0021] Although not shown here, the emitter wiring EW and the gate wiring GW are covered with a protective film such as a polyimide film. An opening is provided in a part of the protective film on the emitter wiring EW and the gate wiring GW, and the area exposed at the opening becomes the emitter pad EP and the gate pad GP. By connecting an external connection member to the emitter pad EP and the gate pad GP, the semiconductor device 100 is electrically connected to another semiconductor chip, a lead frame, a wiring board, or the like. The external connection member is, for example, a wire made of aluminum, gold, or copper, or a clip made of a copper plate.

[0022] FIG. 2 is a plan view of a main part corresponding to the region 1A shown in FIG. 1. The semiconductor device 100 includes an IGBT formed on a semiconductor substrate SUB. This IGBT is an IGBT with an EGE structure that utilizes the IE effect. The IGBT with the EGE structure has a plurality of active cells AC for performing the main operation of the IGBT, and a plurality of inactive cells IAC provided between each of the active cells AC. One active cell AC includes one trench gate electrode GE and two trench emitter electrodes EE. The active cells AC are adjacent to each other in the X direction. A p-type floating region PF is provided in the semiconductor substrate SUB located between each of the active cells AC.

[0023] 2, the trenches TR1, TR2 extend in the Y direction and are adjacent to each other in the X direction. The trenches TR1, TR2 are formed at the same pitch in the X direction. A trench gate electrode GE is formed inside the trench TR1 with a gate insulating film GI interposed therebetween. A trench emitter electrode EE is formed inside the trench TR2 with a gate insulating film GI interposed therebetween.

[0024] A p-type base region PB is formed in the semiconductor substrate SUB of the active cell AC. An n-type emitter region NE is formed in the base region PB. A floating region PF is formed in the semiconductor substrate SUB of the inactive cell IAC. The emitter region NE extends discontinuously in the Y direction while contacting the trench TR1, but the emitter region NE is not formed near the end of the trench TR1 (near the hole CH2).

[0025] A gate wiring GW is electrically connected to the trench gate electrode GE via a plug PG formed inside the hole CH2, and a gate potential is supplied to the IGBT when the IGBT is in operation. An emitter wiring EW is electrically connected to the trench emitter electrode EE, the base region PB, and the emitter region NE via a plug PG formed inside the hole CH1, and an emitter potential is supplied to the IGBT when the IGBT is in operation.

[0026] 3 is a cross-sectional view taken along line AA in FIG. 2. The semiconductor device 100 includes an n-type semiconductor substrate SUB having an upper surface and a lower surface opposite to the upper surface. The semiconductor substrate SUB is made of n-type silicon and has a low-concentration n-type drift region NV. Here, the n-type semiconductor substrate SUB itself constitutes the drift region NV. Note that the semiconductor substrate SUB may be a laminate of an n-type silicon substrate and an n-type silicon layer grown on the silicon substrate by epitaxial growth while introducing phosphorus (P). In this case, the n-type silicon layer having a lower impurity concentration than the n-type silicon substrate constitutes the drift region NV.

[0027] An n-type field stop region (impurity region) NS is formed on the lower surface of the semiconductor substrate SUB. The impurity concentration of the field stop region NS is higher than the impurity concentration of the drift region NV. The field stop region NS is provided to prevent a depletion layer extending from the pn junction on the upper surface side of the semiconductor substrate SUB from reaching the p-type collector region PC when the IGBT is turned off.

[0028] A p-type collector region (impurity region) PC is formed in the lower surface of the semiconductor substrate SUB. The collector region PC is located below the field stop region NS.

[0029] A collector electrode CE is formed on the lower surface of the semiconductor substrate SUB. The collector electrode CE is electrically connected to the collector region PC and supplies a collector potential to the collector region PC. The collector electrode CE is a single-layer metal film such as an Au film, a Ni film, a Ti film, or an AlSi film, or a laminated metal film in which these films are appropriately laminated.

[0030] The collector electrode CE, the collector region PC and the field stop region NS are formed over the entire semiconductor substrate SUB of the active cells AC and the inactive cells IAC.

[0031] In the semiconductor substrate SUB of the active cell AC, trenches TR1 and TR2 are formed so as to reach a predetermined depth from the upper surface of the semiconductor substrate SUB. The trenches TR1 and TR2 penetrate the emitter region NE, the base region PB, and the floating region PF, which will be described later. The depth of the trenches TR1 and TR2 is, for example, 2 μm or more and 6 μm or less.

[0032] A gate insulating film (insulating film) GI is formed inside the trenches TR1 and TR2. A trench gate electrode GE is formed inside the trench TR1 via the gate insulating film GI. A trench emitter electrode EE is formed inside the trench TR2 via the gate insulating film (insulating film) GI. The gate insulating film GI is an insulating film such as a silicon oxide film. The trench gate electrode GE and the trench emitter electrode EE are conductive films, such as a polycrystalline silicon film into which n-type impurities are introduced. The thickness of the gate insulating film GI is, for example, 70 nm or more and 150 nm or less.

[0033] In the active cell AC, an n-type hole barrier region (impurity region) NHB is formed in the semiconductor substrate SUB between the trenches TR1 and TR2 (between the trench gate electrode GE and the trench emitter electrode EE). The impurity concentration of the hole barrier region NHB is higher than the impurity concentration of the drift region NV and lower than the impurity concentration of the emitter region NE. The depth of the hole barrier region NHB from the upper surface of the semiconductor substrate SUB is deeper than the depths of the trenches TR1 and TR2 from the upper surface of the semiconductor substrate SUB. The hole barrier region NHB prevents holes from reaching the base region PB and being discharged during operation of the IGBT. That is, it functions as a barrier against holes.

[0034] A p-type base region (impurity region) PB is formed in the hole barrier region NHB. An n-type emitter region (impurity region) NE is formed in the p-type base region PB. The impurity concentration of the emitter region NE is higher than the impurity concentration of the drift region NV. The depth of the base region PB from the upper surface of the semiconductor substrate SUB is shallower than the depths of the trenches TR1 and TR2 from the upper surface of the semiconductor substrate SUB. The base region PB, which is in contact with the trench TR1 and located below the emitter region NE, is used as a channel region.

[0035] One active cell AC of the IGBT includes one trench TR1, two trenches TR2, each gate insulating film GI in each trench TR1, TR2, one trench gate electrode GE, two trench emitter electrodes EE, two hole barrier regions NHB, two base regions PB, two emitter regions NE, and a collector region PC.

[0036] On the upper surface side of the semiconductor substrate SUB, a p-type floating region (impurity region) PF is formed in the semiconductor substrate SUB between the active cells AC (in the semiconductor substrate SUB of the inactive cells IAC). The floating region PF is not electrically connected to the gate wiring GW and the emitter wiring EW, is not supplied with a potential, and is in an electrically floating state.

[0037] An interlayer insulating film IL is formed on the upper surface of the semiconductor substrate SUB of the active cells AC and the inactive cells IAC so as to cover the trenches TR1 and TR2. The interlayer insulating film IL is, for example, a silicon oxide film. The thickness of the interlayer insulating film IL is, for example, 600 nm or more and 1500 nm or less.

[0038] A hole CH1 is formed in the interlayer insulating film IL. The hole CH1 penetrates the interlayer insulating film IL to a position deeper than the emitter region NE, and is formed so as not to penetrate the base region PB. In other words, the hole CH1 includes an opening formed in the interlayer insulating film IL and a recess portion formed in the semiconductor substrate SUB so as to straddle between the trench emitter electrode EE and the emitter region NE. That is, the hole CH1 penetrates the interlayer insulating film IL and reaches the trench emitter electrode EE, the base region PB, and the emitter region NE. In other words, the hole CH1 is formed so as to overlap the trench emitter electrode EE, the base region PB, and the emitter region NE in a plan view.

[0039] A p-type high-concentration diffusion region (impurity region) PR is formed in the base region PB around the bottom of the hole CH1. The impurity concentration of the high-concentration diffusion region PR is higher than that of the base region PB. The high-concentration diffusion region PR is provided mainly to reduce the contact resistance with the plug PG and to prevent latch-up.

[0040] A plug PG is buried inside the hole CH1. The plug PG is in contact with the trench emitter electrode EE, the base region PB, the emitter region NE, and the high-concentration diffusion region PR. The plug PG includes a barrier metal film and a conductive film formed on the barrier metal film. The barrier metal film is, for example, a stacked film of a titanium film and a titanium nitride film formed on the titanium film. The conductive film is, for example, a tungsten film.

[0041] The interlayer insulating film IL recedes above the hole CH1. That is, the size of the opening of the hole CH1 located above the upper surface of the semiconductor substrate SUB is larger than the size of the opening of the hole CH1 located below the upper surface of the semiconductor substrate SUB. As a result, parts of the upper surfaces of the emitter region NE and the trench emitter electrode EE are exposed from the interlayer insulating film IL. Therefore, inside the hole CH1, the plug PG not only contacts the side surfaces of the emitter region NE and the trench emitter electrode EE, but also contacts parts of the upper surfaces of the emitter region NE and the trench emitter electrode EE. This makes it possible to reduce the contact resistance between the plug PG and the emitter region NE and the trench emitter electrode EE.

[0042] Although not shown here, a hole CH2 shown in FIG. 2 is also formed in the interlayer insulating film IL. The hole CH2 is formed so as to overlap the trench gate electrode GE in a plan view, and penetrates the interlayer insulating film IL to reach the trench gate electrode GE. A plug PG is also formed inside the hole CH2. The interlayer insulating film IL also recedes from above the hole CH2. That is, the size of the opening of the hole CH2 located above the upper surface of the semiconductor substrate SUB is larger than the size of the opening of the hole CH2 located below the upper surface of the semiconductor substrate SUB.

[0043] In addition, no holes such as holes CH1, CH2, etc. are formed in the interlayer insulating film IL located above the floating region PF.

[0044] An emitter wiring EW is formed on the interlayer insulating film IL. The emitter wiring EW is electrically connected to the trench emitter electrode EE, the base region PB, the emitter region NE, and the high-concentration diffusion region PR via the plug PG in the hole CH1, and supplies an emitter potential to these. Although not shown here, a gate wiring GW formed in the same manufacturing process as the emitter wiring EW is also formed on the interlayer insulating film IL. The gate wiring GW is electrically connected to the trench gate electrode GE via the plug PG in the hole CH2, and supplies a gate potential to the trench gate electrode GE.

[0045] The emitter wiring EW and the gate wiring GW include a barrier metal film and a conductive film formed on the barrier metal film. The barrier metal film is, for example, a TiW film. The conductive film is, for example, an aluminum alloy film to which copper or silicon is added. The aluminum alloy film is a main conductor film of the emitter wiring EW and the gate wiring GW, and is sufficiently thicker than the TiW film.

[0046] <Details of the impurity region around the trench> Fig. 4 shows only the trenches TR1 and TR2 and the main impurity regions around them in the cross-sectional structure of Fig. 3. Fig. 5 shows the cross-sectional direction of the impurity concentration profile Pac of the active cell AC and the impurity concentration profile Piac of the inactive cell IAC. Fig. 6 is a graph showing the impurity concentration profiles Pac and Piac shown in Fig. 5.

[0047] Hereinafter, a detailed relationship between one trench TR1 and two trenches TR2 included in one active cell AC and the impurity regions surrounding them will be described with reference to FIGS.

[0048] 4, trench TR1 has a side surface SS1, a side surface SS2 opposite to side surface SS1, and a bottom surface BS1 connecting side surface SS1 and side surface SS2. One trench TR2 has a side surface SS3, a side surface SS4 opposite to side surface SS3, and a bottom surface BS2 connecting side surface SS3 and side surface SS4. The other trench TR2 has a side surface SS5, a side surface SS6 opposite to side surface SS5, and a bottom surface BS3 connecting side surface SS5 and side surface SS6.

[0049] The trench TR1 and one trench TR2 are spaced apart from each other such that the side surface SS1 and the side surface SS4 are adjacent to each other. The trench TR1 and the other trench TR2 are spaced apart from each other such that the side surface SS2 and the side surface SS5 are adjacent to each other.

[0050] One hole barrier region NHB, one base region PB, and one emitter region NE are provided in the semiconductor substrate SUB between the side surface SS1 and the side surface SS4. One hole barrier region NHB is in contact with the side surface SS1, the side surface SS4, the bottom surface BS1, and the bottom surface BS2, but is not in contact with the side surface SS3. One base region PB is in contact with the side surface SS1 and the side surface SS4, but is not in contact with the bottom surface BS1 and the bottom surface BS2. One emitter region NE is in contact with the side surface SS1.

[0051] The other hole barrier region NHB, the other base region PB, and the other emitter region NE are provided in the semiconductor substrate SUB between the side surface SS2 and the side surface SS5. The other hole barrier region NHB is in contact with the side surface SS2, the side surface SS5, the bottom surface BS1, and the bottom surface BS3, but is not in contact with the side surface SS6. The other base region PB is in contact with the side surface SS2 and the side surface SS5, but is not in contact with the bottom surface BS1 and the bottom surface BS3. The other emitter region NE is in contact with the side surface SS2.

[0052] Each floating region PF is provided in the semiconductor substrate SUB between the side surface SS3 and the side surface SS6, and is in contact with the side surface SS3 and the side surface SS6 but not with the bottom surface BS2 and the bottom surface BS3.

[0053] As shown in FIG. 4, the depth Dpb of the base region PB from the upper surface of the semiconductor substrate SUB and the depth Dpf of the floating region PF from the upper surface of the semiconductor substrate SUB are shallower than the respective depths of the trenches TR1 and TR2 from the upper surface of the semiconductor substrate SUB.

[0054] 6, the floating region PF is formed to a position deeper than the base region PB. That is, the depth Dpf of the floating region PF is deeper than the depth Dpb of the base region PB. The impurity concentration of the floating region PF is effectively higher than the impurity concentration of the base region PB.

[0055] A hole barrier region NHB is formed in the semiconductor substrate SUB of the active cell AC, but an n-type impurity region with a higher concentration than the semiconductor substrate SUB (drift region NV), such as the hole barrier region NHB, is not formed in the semiconductor substrate SUB of the inactive cell IAC. In other words, in the active cell AC, the base region PB forms a pn junction with the hole barrier region NHB and the emitter region NE. In addition, in the inactive cell IAC, the floating region PF forms a pn junction with the semiconductor substrate SUB (drift region NV).

[0056] Since the p-type base region PB is formed in the n-type hole barrier region NHB, which has a higher impurity concentration than the semiconductor substrate SUB, the proportion of the p-type conductivity being cancelled out by the n-type conductivity is greater in the base region PB than in the floating region PF. Therefore, the impurity concentration of the base region PB formed in the hole barrier region NHB is effectively lower than the impurity concentration of the floating region PF. Also, the depth Dpb of the base region PB is shallower than the depth Dpf of the floating region PF.

[0057] <Study example and main features of the first embodiment> 7 and 8, the main features of the semiconductor device 100 of the first embodiment will be described below while comparing with the semiconductor devices of Study Examples 1 and 2 as necessary. The semiconductor devices of Study Examples 1 and 2 were studied by the inventors of the present application based on the techniques disclosed in Patent Documents 1 and 2. FIG. 8 is a graph showing turn-off waveforms of the first embodiment, Study Example 1, and Study Example 2.

[0058] Study example 1 refers to the technology of the GGEE structure in Patent Document 1 and the like. As shown in FIG. 7, a p-type impurity region PFa is formed in the semiconductor substrate SUB of the inactive cell IAC instead of the floating region PF of the first embodiment. The impurity region PFa is in an electrically floating state. The impurity region PFa is formed deeper than the floating region PF and is formed so as to cover the bottom surface (BS2, BS3) of the trench TR2.

[0059] In the study example 2, the impurity structure of the inactive cell IAC is the same as that of the active cell AC, except that there is no emitter region NE. As shown in Fig. 7, an n-type hole barrier region NHB is formed in the semiconductor substrate SUB of the inactive cell IAC, and a p-type impurity region PFb is formed in the hole barrier region NHB. The impurity region PFb is formed by the same manufacturing process as the base region PB, but the impurity region PFb is in an electrically floating state.

[0060] In an IGBT for PFC use, since ensuring load short circuit resistance is a low priority, it is possible to increase the saturation current density. To achieve this, it is necessary to increase the MOSFET components per unit area of ​​the IGBT. In the GGEE structure, the MOSFET components are configured on one side surface of each of the two trench gate electrodes GE. In the EGE structure of the first embodiment, the MOSFET components can be configured on both sides of one trench gate electrode GE. This allows the MOSFET components per unit area of ​​the IGBT to be increased.

[0061] In addition, in the GGEE structure, the distance between the trench gate electrode GE and the trench emitter electrode EE is relatively long, but the trenches TR1 and TR2 in the first embodiment are formed at the same pitch. In this respect, the MOSFET components per unit area of ​​the IGBT can be further increased.

[0062] In addition, the trench emitter electrode EE, the base region PB, the emitter region NE, and the emitter wiring EW are connected through a single hole CH1 (a single plug PG), which allows the IGBT to be miniaturized, thereby further increasing the MOSFET components per unit area of ​​the IGBT.

[0063] 2, the emitter region NE extends discontinuously in the Y direction while being in contact with the trench TR1, which increases the gate width of the MOSFET component, thereby enabling the saturation current density to be further increased.

[0064] However, increasing the MOSFET components increases the parasitic capacitance between the trench gate electrode GE and the drift region NV, decreasing the switching speed and increasing the switching loss. Therefore, by providing a floating region PF between each trench emitter electrode EE, holes injected from the lower surface of the semiconductor substrate SUB are accumulated.

[0065] Here, a parasitic PMOS is configured with the floating region PF as the source, the base region PB as the drain, the drift region NV and the hole barrier region NHB as the channel, and the trench emitter electrode EE at the emitter potential as the gate. When holes are sufficiently accumulated in the floating region PF and the potential becomes high, the parasitic PMOS turns on. Then, the holes move from the floating region PF to the base region PB and are automatically discharged to the emitter wiring EW. This makes it possible to suppress the decrease in switching speed and the increase in switching loss. In addition, the above function of the parasitic PMOS suppresses the potential fluctuation of the floating region PF, so that the potential of the trench gate electrode GE is stabilized and the switching loss during switching can be suppressed.

[0066] As shown in FIG. 7, in the study example 1, a relatively deep impurity region PFa is formed instead of the floating region PF. In this case, holes are accumulated in the impurity region PFa, but the depletion layer does not spread between the trench emitter electrode EE and the trench gate electrode GE until all the holes in the impurity region PFa are discharged. Therefore, as shown in FIG. 8, in the study example 1, the rise of the collector voltage Vc is delayed and the time when the collector current Ic flows is delayed compared to the first embodiment. That is, in the study example 1, the turn-off is delayed and the switching speed is reduced.

[0067] Furthermore, when the distance between the trench emitter electrode EE and the trench gate electrode GE is relatively long as in the GGEE structure, the breakdown voltage BVCES (the breakdown voltage between the collector region PC and the emitter region NE) decreases, and therefore a deep p-type impurity region such as the impurity region PFa is required. However, when a plurality of trenches TR1, TR2 are formed at the same pitch as in the first embodiment, the trench emitter electrodes EE of the emitter potential are uniformly arranged, and therefore there is no need to worry about a decrease in the breakdown voltage BVCES. Therefore, the depth of the floating region PF in the first embodiment may be shallower than the depth of the trench TR2.

[0068] The distance between two adjacent trenches TR2 (trench emitter electrodes EE) sandwiching the floating region PF may be narrower than the distance between the trench TR1 (trench gate electrode GE) and the trench TR2 (trench emitter electrode EE). This can increase the ratio of MOSFET components in the semiconductor device 100. This can reduce the on-voltage or improve the switching characteristics.

[0069] As shown in Fig. 7, in Study Example 2, a hole barrier region NHB is formed under the p-type impurity region PFb. In this case, holes injected from the lower surface of the semiconductor substrate SUB are blocked by the hole barrier region NHB, and as shown in Fig. 8, in Study Example 2, the rise of the collector voltage Vc is delayed and the time when the collector current Ic flows is delayed compared to the first embodiment. That is, in Study Example 2, the turn-off is delayed and the switching speed is reduced.

[0070] As described above, in the first embodiment, by applying an EGE type IGBT to the active cell AC and providing a floating region PF to the inactive cell IAC, it is possible to maintain a low on-voltage, increase the switching speed, and reduce switching loss. That is, according to the first embodiment, it is possible to provide a semiconductor device 100 including an IGBT with improved switching characteristics.

[0071] <Method of Manufacturing Semiconductor Device> Each manufacturing step included in the method for manufacturing the semiconductor device 100 according to the first embodiment will be described below with reference to FIGS.

[0072] 9, first, an n-type semiconductor substrate SUB having an upper surface and a lower surface is prepared. The semiconductor substrate SUB is made of silicon. As described above, the semiconductor substrate SUB may be a laminate of an n-type silicon substrate and an n-type silicon layer grown on the silicon substrate by epitaxial growth while introducing phosphorus (P).

[0073] Next, a hole barrier region NHB is selectively formed in the semiconductor substrate SUB on the upper surface side of the semiconductor substrate SUB by photolithography and ion implantation.

[0074] 10, trenches TR1 and TR2 are formed in the semiconductor substrate SUB such that a hole barrier region NHB is located between the trenches TR1 and TR2 on the upper surface side of the semiconductor substrate SUB. In other words, trenches TR1 and TR2 are formed in the semiconductor substrate SUB so as to sandwich the hole barrier region NHB in a plan view.

[0075] First, for example, a silicon oxide film is formed on the upper surface of the semiconductor substrate SUB by, for example, a CVD method. Next, a resist pattern having an opening is formed on the silicon oxide film. Next, the silicon oxide film is patterned by performing an anisotropic etching process using the resist pattern as a mask to form a hard mask HM. Next, the resist pattern is removed by an ashing process.

[0076] Next, an anisotropic etching process is performed using the hard mask HM as a mask to form trenches TR1 and TR2 in the semiconductor substrate SUB, each of which reaches a predetermined depth from the upper surface of the semiconductor substrate SUB. Thereafter, the hard mask HM is removed by wet etching using a solution containing, for example, hydrofluoric acid.

[0077] 11, a sacrificial oxide film IF1 is formed inside the trench TR1, inside the trench TR2, and on the upper surface of the semiconductor substrate SUB. This removes the damaged layer formed in the semiconductor substrate SUB. Thereafter, the sacrificial oxide film IF1 is removed by isotropic etching using a solution containing, for example, hydrofluoric acid.

[0078] The sacrificial oxide film IF1 is formed by subjecting the semiconductor substrate SUB to a heat treatment, which is performed, for example, at 1100° C. for 30 minutes to 60 minutes in an atmosphere filled with oxygen gas.

[0079] This heat treatment diffuses the impurities contained in the hole barrier region NHB. The depth of the hole barrier region NHB from the upper surface of the semiconductor substrate SUB becomes deeper than the depths of the trenches TR1 and TR2 from the upper surface of the semiconductor substrate SUB.

[0080] As shown in FIG. 12, a gate insulating film (insulating film) GI and a conductive film CF1 are formed inside the trenches TR1 and TR2.

[0081] First, a gate insulating film GI is formed inside the trenches TR1, TR2 and on the upper surface of the semiconductor substrate SUB by heat treatment using oxygen gas and hydrogen gas under conditions of, for example, 950° C. and 60 minutes.

[0082] Next, a conductive film CF1 is formed on the gate insulating film GI by, for example, a CVD method so as to fill the insides of the trenches TR1 and TR2 via the gate insulating film GI. The conductive film CF1 is, for example, a polycrystalline silicon film into which an n-type impurity is introduced.

[0083] As shown in FIG. 13, a trench gate electrode GE is formed inside a trench TR1 with a gate insulating film GI therebetween, and a trench emitter electrode EE is formed inside a trench TR2 with a gate insulating film GI therebetween.

[0084] First, the conductive film CF1 formed outside the trenches TR1 and TR2 is removed by anisotropic etching. The conductive film CF1 formed inside the trench TR1 is left as the trench gate electrode GE, and the conductive film CF1 formed inside the trench TR2 is left as the trench emitter electrode EE. Next, the gate insulating film GI formed outside the trenches TR1 and TR2 is removed by isotropic etching, anisotropic etching, or a combination of these.

[0085] As shown in FIG. 14, a p-type base region PB is formed in the hole barrier region NHB by ion implantation. At the same time, a p-type floating region PF is formed in the semiconductor substrate SUB located on the other side of the trench TR2 opposite to the side on which the hole barrier region NHB is formed. The p-type base region PB and the floating region PF may be formed by multiple ion implantations. By appropriately adjusting the implantation energy for each implantation, the floating region PF can be formed to a desired depth.

[0086] 4, a base region PB is formed in the semiconductor substrate SUB located between side SS1 and side SS4 and between side SS2 and side SS5, and a floating region PF is formed in the semiconductor substrate SUB located between side SS3 and side SS6. In other words, a base region PB is formed in the semiconductor substrate SUB of the active cell AC, and a floating region PF is formed in the semiconductor substrate SUB of the inactive cell IAC.

[0087] 15, an n-type emitter region NE is selectively formed in the base region PB by photolithography and ion implantation. Then, a heat treatment is performed to activate the impurities contained in the hole barrier region NHB, the floating region PF, the base region PB, and the emitter region NE. This heat treatment is performed in an atmosphere filled with an inert gas such as nitrogen gas under conditions of 900° C. or higher and 1000° C. or lower, and 30 seconds or higher and 50 seconds or lower.

[0088] At this point, the impurity concentration profile shown in FIG. 6 is formed. The hole barrier region NHB is formed in the semiconductor substrate SUB in which the base region PB is formed, but the semiconductor substrate SUB in which the floating region PF is formed does not have an n-type impurity region with a higher concentration than the semiconductor substrate SUB (drift region NV) such as the hole barrier region NHB. Therefore, the rate at which the p-type conductivity is cancelled out by the n-type conductivity is higher in the base region PB than in the floating region PF. Therefore, although the base region PB and the floating region PF are formed by the same ion implantation process, the impurity concentration of the base region PB is effectively lower than the impurity concentration of the floating region PF. In addition, the depth Dpb of the base region PB is shallower than the depth Dpf of the floating region PF.

[0089] 16, first, an interlayer insulating film IL is formed on the upper surface of the semiconductor substrate SUB by, for example, a CVD method so as to cover the trenches TR1 and TR2. The interlayer insulating film IL is, for example, a silicon oxide film.

[0090] Next, a hole CH1 is formed in the interlayer insulating film IL by photolithography and anisotropic etching. The hole CH1 reaches the trench emitter electrode EE, the base region PB, and the emitter region NE. Next, a p-type high concentration diffusion region PR is selectively formed in the base region PB located at the bottom of the hole CH1 by ion implantation.

[0091] Next, although not shown here, a hole CH2 reaching the trench gate electrode GE is formed in the interlayer insulating film IL by photolithography and anisotropic etching. Either the step of forming the hole CH1 or the step of forming the hole CH2 may be performed first.

[0092] Not only during the process of forming the holes CH1 and CH2, but also during the subsequent manufacturing processes, no holes are formed in the interlayer insulating film IL located above the floating region PF. Therefore, the floating region PF becomes a region to which no potential is supplied and is in an electrically floating state.

[0093] 17, the interlayer insulating film IL is set back by performing an isotropic etching process on the interlayer insulating film IL. As a result, the opening width of the hole CH1 located on the upper surface of the semiconductor substrate SUB becomes larger than the opening width of the hole CH1 located inside the semiconductor substrate SUB. Note that the interlayer insulating film IL of the hole CH2 is also set back by this isotropic etching process.

[0094] As shown in FIG. 18, a plug PG is formed inside the hole CH1, and an emitter wiring EW is formed on the interlayer insulating film IL.

[0095] First, a barrier metal film is formed inside the hole CH1 and on the interlayer insulating film IL. The barrier metal film can be formed by forming a titanium film inside the hole CH1 and on the interlayer insulating film IL by, for example, a sputtering method, and forming a titanium nitride film on the titanium film by, for example, a sputtering method. Next, a conductive film made of, for example, a tungsten film is formed on the barrier metal film by, for example, a CVD method so as to fill the inside of the hole CH1. Next, the conductive film and the barrier metal film formed outside the hole CH1 are removed by anisotropic etching. As a result, a plug PG is formed so as to fill the inside of the hole CH1. During these manufacturing steps, a plug PG is also formed inside the hole CH2.

[0096] Next, the emitter wiring EW is formed on the interlayer insulating film IL. First, a TiW film is formed on the interlayer insulating film IL by, for example, a sputtering method, and an aluminum alloy film is formed on the TiW film by, for example, a sputtering method. Next, the TiW film and the aluminum alloy film are patterned by photolithography technology and dry etching processing to form the emitter wiring EW. During these manufacturing steps, the gate wiring GW is also formed on the interlayer insulating film IL.

[0097] After that, the structure of FIG. 3 is obtained through the following manufacturing steps. First, the wafer is ground to be extremely thin as necessary. Next, ions are implanted from the lower surface of the semiconductor substrate SUB to form an n-type field stop region NS and a p-type collector region PC in the semiconductor substrate SUB. After these ion implantations, laser annealing is performed to activate the impurities contained in the field stop region NS and the collector region PC. Next, a metal film such as an Au film, Ni film, Ti film, or AlSi film is formed on the lower surface of the semiconductor substrate SUB by, for example, a sputtering method. This metal film becomes the collector electrode CE. The collector electrode CE may be a laminated film in which the above metal films are appropriately laminated.

[0098] In this way, according to the manufacturing method of the first embodiment, the semiconductor device 100 can be manufactured using the same manufacturing process as the manufacturing process for forming the IGBTs of the GGEE structure and the EGE structure as shown in Patent Document 1. This makes it possible to shorten the development period, eliminate the need for new manufacturing equipment, and reduce manufacturing costs.

[0099] Furthermore, according to the manufacturing method of the first embodiment, the floating region PF can be formed in the process of forming the base region PB. Therefore, the formation of the deep floating region shown in Patent Document 1 and the like can be omitted, and the manufacturing cost can be reduced accordingly.

[0100] Although the present invention has been specifically described based on the embodiments, the present invention is not limited to these embodiments and can be modified in various ways without departing from the gist of the present invention. [Explanation of symbols]

[0101] 100 Semiconductor device 1A area AC Active Cell BS1, BS2, BS3 Bottom of trench CE collector electrode CF1 n-type conductive film CH1, CH2 hole EE Trench emitter electrode EP Emitter Pad EW Emitter wiring GE Trench Gate Electrode GI Gate insulating film (insulating film) GP Gate Pad GW Gate wiring HM Hard Mask IAC Inactive Cell IF1 sacrificial oxide film IL Interlayer insulating film NE n-type emitter region NHB n-type hole barrier region NS n-type field stop region NV n-type drift region PB p-type base region PC p-type collector region PF p-type floating region PFa, PFb p-type impurity region PG plug PR p-type high concentration diffusion region SS1, SS2, SS3, SS4, SS5, SS6 Trench Sides SUB Semiconductor Substrate TR1, TR2 Trench

Claims

1. a semiconductor substrate of a first conductivity type having an upper surface and a lower surface opposite to the upper surface; a first trench, a second trench, and a third trench each formed in the semiconductor substrate so as to reach a predetermined depth from the top surface of the semiconductor substrate; a trench gate electrode formed inside the first trench via a first insulating film; a first trench emitter electrode formed inside the second trench via a second insulating film; a second trench emitter electrode formed inside the third trench via a third insulating film; a first hole barrier region of the first conductivity type formed in the semiconductor substrate between the first trench and the second trench; a first base region of a second conductivity type opposite to the first conductivity type formed in the first hole barrier region; a first emitter region of the first conductivity type formed in the first base region; a second hole barrier region of the first conductivity type formed in the semiconductor substrate between the first trench and the third trench; a second base region of the second conductivity type formed in the second hole barrier region; a second emitter region of the first conductivity type formed in the second base region; a first floating region of the second conductivity type formed in the semiconductor substrate, the first floating region being located on one of both side surfaces of the second trench, the other side surface being opposite to the side surface on which the first hole barrier region is formed; a second floating region of the second conductivity type formed in the semiconductor substrate, the second floating region being located on one of both side surfaces of the third trench, the other side surface being opposite to the one side surface on which the second hole barrier region is formed; Equipped with a depth of each of the first floating region and the second floating region from the top surface of the semiconductor substrate is shallower than a depth of each of the first trench, the second trench, and the third trench from the top surface of the semiconductor substrate, and is deeper than a depth of each of the first base region and the second base region from the top surface of the semiconductor substrate.

2. 2. The semiconductor device according to claim 1, a first floating region and a second floating region each having an impurity concentration higher than a first base region and a second base region;

3. 2. The semiconductor device according to claim 1, a depth of each of the first hole barrier region and the second hole barrier region from the top surface of the semiconductor substrate is deeper than a depth of each of the first trench, the second trench, and the third trench from the top surface of the semiconductor substrate.

4. 2. The semiconductor device according to claim 1, an interlayer insulating film formed on the upper surface of the semiconductor substrate so as to cover the first trench, the second trench, and the third trench; a first hole penetrating the interlayer insulating film and reaching the first trench emitter electrode, the first base region, and the first emitter region; a second hole that penetrates the interlayer insulating film and reaches the second trench emitter electrode, the second base region, and the second emitter region; a third hole penetrating the interlayer insulating film and reaching the trench gate electrode; a first plug formed inside the first hole; a second plug formed within the second hole; a third plug formed inside the third hole; an emitter wiring and a gate wiring formed on the interlayer insulating film; Further comprising: the first trench emitter electrode, the first base region, and the first emitter region are electrically connected to the emitter wiring via the first plug; the second trench emitter electrode, the second base region, and the second emitter region are electrically connected to the emitter wiring via the second plug; the trench gate electrode is electrically connected to the gate wiring via the third plug; The first floating region and the second floating region are each in an electrically floating state.

5. 5. The semiconductor device according to claim 4, a first floating region formed on the first insulating film and a second floating region formed on the second insulating film;

6. 2. The semiconductor device according to claim 1, the first trench, the second trench, and the third trench each extend in a first direction in a plan view and are adjacent to each other in a second direction perpendicular to the first direction; the first emitter region and the second emitter region extend discontinuously in the first direction while contacting the first trench.

7. 7. The semiconductor device according to claim 6, a collector region of the second conductivity type formed on the lower surface of the semiconductor substrate; Further comprising: an active cell of an IGBT includes the trench gate electrode, the first trench emitter electrode, the second trench emitter electrode, the first hole barrier region, the second hole barrier region, the first base region, the second base region, the first emitter region, the second emitter region, and the collector region.

8. 8. The semiconductor device according to claim 7, Further comprising a plurality of said active cells; The active cells are adjacent to each other in the second direction, A semiconductor device, wherein the first floating region or the second floating region is formed in the semiconductor substrate and positioned between the plurality of active cells.

9. 9. The semiconductor device according to claim 8, the first trench, the second trench and the third trench included in each of the plurality of active cells are formed at the same pitch in the second direction.

10. 2. The semiconductor device according to claim 1, The first floating region and the second floating region each form a pn junction with the semiconductor substrate.

11. 2. The semiconductor device according to claim 1, the other side surface of the second trench is not in contact with the first hole barrier region; the other side surface of the third trench is not in contact with the second hole barrier region.

12. (a) providing a semiconductor substrate of a first conductivity type having a top surface and a bottom surface opposite the top surface; (b) forming a first hole barrier region of the first conductivity type and a second hole barrier region of the first conductivity type on the top surface of the semiconductor substrate; (c) after the step (b), forming a first trench and a second trench in the semiconductor substrate so as to sandwich the first hole barrier region in a plan view, and forming a third trench in the semiconductor substrate so as to sandwich the second hole barrier region between the first trench and the third trench in a plan view; (d) after the step (c), forming a first insulating film inside the first trench, forming a second insulating film inside the second trench, and forming a third insulating film inside the third trench; (e) after the step (d), forming a trench gate electrode inside the first trench via the first insulating film, forming a first trench emitter electrode inside the second trench via the second insulating film, and forming a second trench emitter electrode inside the third trench via the third insulating film; (f) after the step (e), forming a first base region of a second conductivity type opposite to the first conductivity type in the first hole barrier region, forming a second base region of the second conductivity type in the second hole barrier region, forming a first floating region of the second conductivity type in the semiconductor substrate located on the other side of the second trench opposite to the one side on which the first hole barrier region is formed, and forming a second floating region of the second conductivity type in the semiconductor substrate located on the other side of the third trench opposite to the one side on which the second hole barrier region is formed; (g) after step (f), forming a first emitter region of the first conductivity type in the first base region and forming a second emitter region of the first conductivity type in the second base region; Equipped with A method for manufacturing a semiconductor device, wherein a depth of each of the first floating region and the second floating region from the top surface of the semiconductor substrate is shallower than a depth of each of the first trench, the second trench, and the third trench from the top surface of the semiconductor substrate, and is deeper than a depth of each of the first base region and the second base region from the top surface of the semiconductor substrate.

13. 13. The method of manufacturing a semiconductor device according to claim 12, A method for manufacturing a semiconductor device, wherein an impurity concentration of each of the first floating region and the second floating region is higher than an impurity concentration of each of the first base region and the second base region.

14. 12. The method of manufacturing a semiconductor device according to claim 11, (h) performing a heat treatment between the step (b) and the step (c); Further comprising: the first hole barrier region and the second hole barrier region are diffused by the heat treatment; after the step (c), a depth of each of the first hole barrier region and the second hole barrier region from the top surface of the semiconductor substrate is deeper than a depth of each of the first trench, the second trench, and the third trench from the top surface of the semiconductor substrate.

15. 12. The method of manufacturing a semiconductor device according to claim 11, (i) after the step (g), forming an interlayer insulating film on the top surface of the semiconductor substrate so as to cover the first trench, the second trench, and the third trench; (j) after the step (i), forming a first hole penetrating the interlayer insulating film and reaching the first trench emitter electrode, the first base region, and the first emitter region, and a second hole penetrating the interlayer insulating film and reaching the second trench emitter electrode, the second base region, and the second emitter region; (k) after the step (i), forming a third hole penetrating the interlayer insulating film and reaching the trench gate electrode; (l) after the step (k), forming a first plug in the first hole, forming a second plug in the second hole, and forming a third plug in the third hole; (m) after the step (l), forming an emitter wiring and a gate wiring on the interlayer insulating film; Further comprising: the first trench emitter electrode, the first base region, and the first emitter region are electrically connected to the emitter wiring via the first plug; the second trench emitter electrode, the second base region, and the second emitter region are electrically connected to the emitter wiring via the second plug; the trench gate electrode is electrically connected to the gate wiring via the third plug; The method for manufacturing a semiconductor device, wherein the first floating region and the second floating region are each in an electrically floating state.

16. A semiconductor device including an IGBT having a plurality of cells, Each of the plurality of cells comprises: a trench gate electrode, a first trench emitter electrode and a second trench emitter electrode formed on an n-type semiconductor substrate; a p-type first base region formed in the semiconductor substrate and located between the trench gate electrode and the first trench emitter electrode; a p-type second base region formed in the semiconductor substrate and located between the trench gate electrode and the second trench emitter electrode; having a p-type floating region is formed in the semiconductor substrate located between each of the plurality of cells; a depth of the floating region is shallower than a depth of each of the trench gate electrode, the first trench emitter electrode, and the second trench emitter electrode, and is deeper than a depth of each of the first base region and the second base region.

17. 17. The semiconductor device according to claim 16, Each of the plurality of cells comprises: a first emitter region of n-type formed in the first base region; a second emitter region of n-type formed in the second base region; a first n-type hole barrier region formed in the semiconductor substrate and located between the trench gate electrode and the first trench emitter electrode; a second n-type hole barrier region formed in the semiconductor substrate and located between the trench gate electrode and the second trench emitter electrode; Further comprising: the first base region is formed in the first hole barrier region; the second base region is formed in the second hole barrier region; an impurity concentration of each of the first hole barrier region and the second hole barrier region is higher than an impurity concentration of the semiconductor substrate; the first base region forms a pn junction with the first emitter region and the first hole barrier region; the second base region forms a pn junction with the second emitter region and the second hole barrier region; The floating region forms a pn junction with the semiconductor substrate.

18. 18. The semiconductor device according to claim 17, The semiconductor device, wherein the floating region has an impurity concentration higher than each of the first base region and the second base region.

19. 18. The semiconductor device according to claim 17, an interlayer insulating film formed on the semiconductor substrate so as to cover the trench gate electrode, the first trench emitter electrode, and the second trench emitter electrode; a first hole penetrating the interlayer insulating film and reaching the first trench emitter electrode, the first base region, and the first emitter region; a second hole penetrating the interlayer insulating film and reaching the second trench emitter electrode, the second base region, and the second emitter region; a third hole penetrating the interlayer insulating film and reaching the trench gate electrode; a first plug formed inside the first hole; a second plug formed within the second hole; a third plug formed inside the third hole; an emitter wiring and a gate wiring formed on the interlayer insulating film; Further comprising: the first trench emitter electrode, the first base region, and the first emitter region are electrically connected to the emitter wiring via the first plug; the second trench emitter electrode, the second base region, and the second emitter region are electrically connected to the emitter wiring via the second plug; the trench gate electrode is electrically connected to the gate wiring via the third plug; The first floating region and the second floating region are each in an electrically floating state.

20. 17. The semiconductor device according to claim 16, the trench gate electrode, the first trench emitter, and the second trench emitter included in each of the plurality of cells are formed at the same pitch.

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