Semiconductor device and display device

Abstract

To provide a semiconductor device or the like with a novel configuration capable of displaying images in reverse, provide a semiconductor device or the like having a novel configuration that can suppress deterioration of transistor characteristics, provide a semiconductor device or the like having a novel configuration capable of improving operating speed, and a semiconductor device or the like having a novel configuration capable of reducing dielectric breakdown of a transistor.SOLUTION: A circuit configuration is such that it is possible to switch between two operations, the first operation and the second operation, by switching the potential of a wiring, the scanning direction can be easily switched by switching between these two operations. The scanning direction can be switched.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] One embodiment of the present invention relates to a semiconductor device and an electronic device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field relates to an article, a method, or a manufacturing method. , process, machine, manufacture, or composition of matter Therefore, one embodiment of the present invention disclosed in the present specification more specifically relates to The technical fields include semiconductor devices, display devices, light-emitting devices, power storage devices, imaging devices, memory devices, The driving method thereof or the manufacturing method thereof can be given as an example.

[0003] In this specification, a semiconductor device is an element that can function by utilizing semiconductor characteristics. For example, semiconductor elements such as transistors and diodes are As another example, a circuit having a semiconductor element is a semiconductor device. As another example, a device including a circuit having a semiconductor element is a semiconductor device. . [Background technology]

[0004] In a semiconductor device having a display function, as typified by a television receiver, The display orientation is fixed.

[0005] A driver circuit for driving such a semiconductor device is equipped with a shift register. (See Patent Document 1). [Prior art documents] [Patent documents]

[0006] [Patent Document 1] US Patent Application Publication No. 2010 / 0201659 Summary of the Invention [Problem to be solved by the invention]

[0007] In recent years, with the spread of smartphones and other devices, semiconductor devices that display images upside down or leftside upside down have become common. It is required.

[0008] An object of one embodiment of the present invention is to provide a novel semiconductor device, a novel electronic device, or the like. do.

[0009] Another embodiment of the present invention is to provide a semiconductor device or the like having a novel structure capable of inverting display. Another object of one embodiment of the present invention is to suppress deterioration of transistor characteristics. Another object of the present invention is to provide a semiconductor device or the like having a novel structure. The object of the present invention is to provide a semiconductor device having a novel configuration capable of improving the operating speed. Another embodiment of the present invention is a novel method for reducing dielectric breakdown of a transistor. It is an object of the present invention to provide a semiconductor device or the like having such a structure.

[0010] Note that the problems of one embodiment of the present invention are not limited to the problems listed above. This does not preclude the existence of other issues. Other issues may be discussed in the following sections. Problems not mentioned in this section are problems that a person skilled in the art would understand in the specification or This can be derived from the descriptions in the drawings, etc., and can be extracted appropriately from these descriptions. One aspect of the present invention is to achieve at least one of the above-listed objects and / or other objects. This is intended to solve three problems. [Means for solving the problem]

[0011] One embodiment of the present invention includes first to ninth transistors, One of the drains of the first transistor is electrically connected to one of the source and drain of the second transistor. The other of the source and the drain of the first transistor is electrically connected to a first wiring. one of a source and a drain of the second transistor is electrically connected to a second wiring; The other of the source and the drain of the second transistor is electrically connected to a third wiring. Either the source or the drain of the third transistor is electrically connected to the gate of the first transistor. the other of the source and the drain of the third transistor is electrically connected to the third wiring. The source or drain of the fourth transistor is connected to the gate of the second transistor. the source of the fourth transistor is electrically connected to the gate of the third transistor The other of the drain and the source of the fifth transistor is electrically connected to a fourth wiring. One of the drains of the first transistor and the source of the second transistor is electrically connected to one of the drains of the fourth transistor. The other of the source and the drain of the fifth transistor is electrically connected to a third wiring. The gate of the fifth transistor is electrically connected to the gate of the first transistor. Either the source or the drain of the sixth transistor is electrically connected to the gate of the fourth transistor. The other of the source and the drain of the sixth transistor is electrically connected to the fifth wiring. The gate of the sixth transistor is electrically connected to the sixth wiring, and the gate of the seventh transistor is electrically connected to the sixth wiring. One of the source and drain of the fourth transistor is electrically connected to the gate of the fourth transistor. The other of the source and the drain of the seventh transistor is electrically connected to a seventh wiring. The gate of the seventh transistor is electrically connected to an eighth wiring. One of the source and drain of the first transistor is electrically connected to the gate of the eighth transistor. The other of the source and the drain of the transistor is electrically connected to a fifth wiring. The gate of the transistor is electrically connected to the ninth wiring, and the source of the ninth transistor is or one of the drains is electrically connected to the gate of the first transistor, The other of the source and drain of the ninth transistor is electrically connected to the seventh wiring. The gate of the transistor is electrically connected to the tenth wiring, and the fifth wiring is In the second operation, the first potential is applied to the first electrode. The seventh wiring has a function of transmitting either the first potential or the second potential. During the first operation, the other of the first potential or the second potential is transmitted, and during the second operation, A semiconductor device having a function of transmitting either a first potential or a second potential. It is a body device.

[0012] In one embodiment of the present invention, the first wiring has a function of transmitting a first clock signal. the sixth wiring has a function of transmitting a second clock signal; and the eighth wiring The line is preferably a semiconductor device capable of transmitting a third clock signal.

[0013] In one embodiment of the present invention, the second wiring has a function of transmitting an output signal, The 10th wire has a function of transmitting the output signal of the previous stage, and the 9th wire has a function of transmitting the output signal of the next stage. A semiconductor device capable of transmitting an output signal is preferred.

[0014] In one embodiment of the present invention, the fourth wiring has a function of transmitting a first potential, The third wiring is preferably a semiconductor device capable of transmitting the second potential.

[0015] In one embodiment of the present invention, a first capacitor is provided. One electrode of the first capacitor is the other of the first capacitance element is electrically connected to one of the source and drain of the transistor The electrode is preferably a semiconductor device electrically connected to the gate of the first transistor.

[0016] In one embodiment of the present invention, a second capacitor is provided. One electrode of the second capacitor is the other of the second capacitance element is electrically connected to one of the source and drain of the transistor The electrode of the second transistor is preferably electrically connected to the gate of the fourth transistor.

[0017] In one embodiment of the present invention, the first transistor has a W (W is a channel width) / L (L is a channel length It is preferable that the W / L of the second to ninth transistors is larger than that of the first to ninth transistors.

[0018] In one embodiment of the present invention, the sixth transistor has a W (W is a channel width) / L (L is a channel length The length of the semiconductor device is 0.8 to 1.2 times the W / L of the seventh transistor. Positioning is preferred.

[0019] In one embodiment of the present invention, the eighth transistor has a W (W is a channel width) / L (L is a channel length The length of the semiconductor device is 0.8 times or more and 1.2 times or less than the W / L of the ninth transistor. Positioning is preferred.

[0020] In one embodiment of the present invention, the first to ninth transistors each have an oxide semiconductor A semiconductor device having a conductor is preferred.

[0021] One embodiment of the present invention is a display module including the above semiconductor device and an FPC.

[0022] One embodiment of the present invention is a semiconductor device including the above-described semiconductor device or the above-described display module, a speaker, an operation button, and a and / or an antenna.

[0023] Note that another embodiment of the present invention will be described in the following embodiment and in the drawings. is written on the surface. Effect of the Invention

[0024] One embodiment of the present invention can provide a novel semiconductor device, a novel electronic device, or the like.

[0025] Another embodiment of the present invention is to provide a semiconductor device or the like having a novel structure capable of inverting display. Another embodiment of the present invention is a novel structure that can suppress deterioration of transistor characteristics. According to another embodiment of the present invention, a semiconductor device or the like having an improved operating speed can be provided. It is possible to provide a semiconductor device or the like having a novel configuration that can achieve the above object. According to one aspect of the present invention, there is provided a semiconductor device having a novel structure capable of reducing dielectric breakdown of a transistor. It is possible.

[0026] Note that the effects of one embodiment of the present invention are not limited to the effects listed above. This does not preclude the existence of other effects. Other effects are described below. The effects not mentioned in this section are obvious to those skilled in the art in the specification or the like. This can be derived from the descriptions in the drawings, etc., and can be extracted appropriately from these descriptions. In addition, one aspect of the present invention has at least one of the effects listed above and / or other effects. Therefore, one aspect of the present invention may have the above-listed effects. In some cases, it may have no effect. [Brief description of the drawings]

[0027] [Figure 1] FIG. 1 is a circuit diagram illustrating one embodiment of the present invention. [Diagram 2] 1 is a timing chart illustrating one embodiment of the present invention. [Diagram 3] 1 is a timing chart illustrating one embodiment of the present invention. [Figure 4] FIG. 1 is a circuit diagram illustrating one embodiment of the present invention. [Diagram 5] FIG. 1 is a circuit diagram illustrating one embodiment of the present invention. [Figure 6] FIG. 1 is a circuit diagram illustrating one embodiment of the present invention. [Figure 7] FIG. 1 is a circuit diagram illustrating one embodiment of the present invention. [Figure 8] FIG. 1 is a circuit diagram illustrating one embodiment of the present invention. [Figure 9] FIG. 1 is a circuit diagram illustrating one embodiment of the present invention. [Figure 10] FIG. 1 is a circuit diagram illustrating one embodiment of the present invention. [Figure 11] FIG. 1 is a circuit diagram illustrating one embodiment of the present invention. [Figure 12] FIG. 1 is a circuit diagram illustrating one embodiment of the present invention. [Figure 13] FIG. 1 is a circuit diagram illustrating one embodiment of the present invention. [Figure 14] FIG. 1 is a circuit diagram illustrating one embodiment of the present invention. [Figure 15] FIG. 1 is a circuit diagram illustrating one embodiment of the present invention. [Figure 16] FIG. 1 is a circuit diagram illustrating one embodiment of the present invention. [Figure 17]FIG. 1 is a circuit diagram illustrating one embodiment of the present invention. [Figure 18] FIG. 1 is a circuit diagram illustrating one embodiment of the present invention. [Figure 19] FIG. 1 is a circuit diagram illustrating one embodiment of the present invention. [Figure 20] FIG. 1 is a circuit diagram illustrating one embodiment of the present invention. [Figure 21] FIG. 1 is a circuit diagram illustrating one embodiment of the present invention. [Figure 22] 1 is a timing chart illustrating one embodiment of the present invention. [Figure 23] FIG. 1 is a circuit diagram illustrating one embodiment of the present invention. [Figure 24] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of the present invention. [Diagram 25] FIG. 1 is a cross-sectional view illustrating one embodiment of the present invention. [Figure 26] FIG. 1 is a cross-sectional view illustrating one embodiment of the present invention. [Figure 27] FIG. 1 is a cross-sectional view illustrating one embodiment of the present invention. [Figure 28] FIG. 1 is a top view illustrating one embodiment of the present invention. [Figure 29] FIG. 1 is a cross-sectional view illustrating one embodiment of the present invention. [Diagram 30] FIG. 1 is a projection view illustrating one embodiment of the present invention. [Diagram 31] FIG. 1 is a cross-sectional view illustrating one embodiment of the present invention. [Diagram 32] 1A to 1C are diagrams illustrating electronic devices according to one embodiment of the present invention. [Diagram 33] FIG. 1 is a layout diagram illustrating one embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0028] Hereinafter, an embodiment will be described with reference to the drawings. However, the embodiment may be different from the embodiment. The present invention can be implemented in any manner without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that various modifications may be made to the embodiments and details of the present invention. The present invention should not be construed as being limited to the description of the following embodiments.

[0029] In this specification, the ordinal numbers "first," "second," and "third" are used to refer to the mixture of elements. Therefore, it does not limit the number of components. In addition, the order of the components is not limited. The components referred to as "first" in the above may be included in other embodiments or in the claims. In addition, for example, the second component may be referred to as a "second" component in the present specification. A component referred to as "first" in one embodiment may be used in other embodiments or in particular It may be omitted in the claims.

[0030] In the drawings, elements that are the same or have similar functions, elements that are made of the same material, or In the following description, the same reference numerals may be used to denote elements or components formed at the same time, and repeated explanations thereof will be omitted. It may be omitted.

[0031] (Embodiment 1) The structure of a semiconductor device according to one embodiment of the present invention will be described with reference to FIG.

[0032] The semiconductor device illustrated in FIG. 1 includes a circuit 100. The circuit 100 controls the potential of a wiring 152. The circuit 100 may be called a logic circuit or a sequential circuit.

[0033] The circuit 100 performs a first operation by switching the potentials of the wirings 155 and 157 connected thereto. It is possible to switch between two actions, one for the first action and one for the second action. A semiconductor device having a circuit 100 capable of switching the scanning direction can be easily performed. The semiconductor device having a display function and capable of switching the scanning direction can be It is possible to perform a transfer display.

[0034] The circuit 100 includes transistors 101 to 109 and a capacitor 110. In the figure, the gate of the transistor 101 is indicated as a node ND1. The gate of transistor 4 is indicated as node ND2. Similarly, the gate of transistor 102 is indicated as node ND3. This indicates that.

[0035] The connections of the transistors 101 to 109 and the capacitor 110 will be described.

[0036] One of the source and the drain of the transistor 101 is connected to a wiring 151. The other of the source and the drain of the transistor 101 is connected to a wiring 152 .

[0037] One of the source and the drain of the transistor 102 is connected to the wiring 153. The other of the source and drain of the transistor 102 is connected to a wiring 152 .

[0038] The gate of the transistor 103 is connected to a node ND3. One of the source and drain of the transistor 103 is connected to the wiring 153. The other end of the rain is connected to a node ND1.

[0039] One of the source and the drain of the transistor 104 is connected to the wiring 154. The other of the source or drain of the transistor 104 is connected to a node ND3.

[0040] The gate of the transistor 105 is connected to the node ND1. One of the source and drain of the transistor 105 is connected to the wiring 153. The other end of the rain is connected to a node ND3.

[0041] The gate of the transistor 106 is connected to the wiring 156. One of the source and drain of the transistor 106 is connected to the wiring 155. The other input is connected to node ND2.

[0042] The gate of the transistor 107 is connected to the wiring 158. One of the source and drain of the transistor 107 is connected to the wiring 157. The other input is connected to node ND2.

[0043] The gate of the transistor 108 is connected to the wiring 159. One of the source and drain of the transistor 108 is connected to the wiring 155. The other input is connected to a node ND1.

[0044] The gate of the transistor 109 is connected to the wiring 160. One of the source and drain of the transistor 109 is connected to the wiring 157. The other input is connected to a node ND1.

[0045] A first electrode of the capacitance element 110 is connected to the node ND1. The pole is connected to a wire 152 .

[0046] It is preferable that the transistors 101 to 109 have the same polarity. Preferably, the transistors 101 to 109 are N-channel type. It is preferable that 01 to 109 are P-channel type. This simplifies the manufacturing process. This allows for an improvement in yield and / or a reduction in cost.

[0047] When the transistors 101 to 109 are N-channel type, the transistors 101 to 09 is a transistor having an oxide semiconductor in a channel formation region (OS transistor) The OS transistor can have an arsenic oxide (ATO) in the channel formation region. Higher mobility and extremely low off-state current than transistors using amorphous silicon Therefore, the sizes of the transistors 101 to 109 are reduced, and the nodes ND1 to ND2 are This makes it easier to maintain the potential at ND3.

[0048] The W (channel width) / L (channel length) of the transistor 101 is It is preferable that the W / L of the transistor 109 is larger than that of the transistor 109. Since the supply capacity can be increased, the rise time and fall time of the signal transmitted to the wiring 152 can be reduced. The fall time can be shortened.

[0049] When a transistor is composed of multiple transistors, the W / L is the sum of the W / L of multiple transistors. For example, When transistors are connected in parallel, W is the sum of the W of the multiple transistors, and L is the sum of the W of the multiple This is the average value of the transistor's L.

[0050] The W / L of transistor 106 is equal to or approximately equal to the W / L of transistor 107. Similarly, the W / L of transistor 108 is preferably equal to the W / L of transistor 109. It is preferable that the W / L ratio of the transistors is equal to or substantially equal to each other. The W / L of one transistor must be between 0.8 and 1.2 times the W / L of the other transistor. More preferably, the ratio is 0.9 to 1.1. Even when switching between the first operation and the second operation, the current supply capability is equal or approximately equal. Thus, the operation can be performed.

[0051] The signals or potentials of the wirings 151 to 160 and the nodes ND1 to ND3 will be described.

[0052] The wiring 151 has a function of transmitting a signal having a high level and a low level. As an example, the wiring 151 has a function of transmitting a clock signal. may be referred to as the first clock signal.

[0053] The wiring 152 has a function of transmitting a signal having a high level and a low level. As an example, the wiring 152 has a function of transmitting an output signal. It may be called a signal, a selection signal, or a pulse signal.

[0054] The wiring 153 has a function of transmitting a low-level potential. Then, the wiring 153 has a function of being set to the potential VL.

[0055] The wiring 154 has a function of transmitting a high-level potential. VL), the wiring 154 has a function of being set to a potential VH.

[0056] The wiring 155 has a function of transmitting a signal having a high level and a low level. As an example, the wiring 155 is set to a potential VH during the first operation and to a potential VH during the second operation. The potential VL is set at the potential VL.

[0057] The wiring 156 has a function of transmitting a signal having a high level and a low level. As an example, the wiring 156 has a function of transmitting a clock signal. The second clock signal is sometimes called the second clock signal. and the phase is different.

[0058] The wiring 157 has a function of transmitting a signal having a high level and a low level. As an example, the wiring 157 is set to a potential VL during the first operation and to a potential VL during the second operation. to a potential VH.

[0059] The wiring 158 has a function of transmitting a signal having a high level and a low level. As an example, the wiring 158 has a function of transmitting a clock signal. The third clock signal is sometimes called the third clock signal. The third clock signal is a clock signal that is generated by synchronizing the first clock signal with the second clock signal. Or, the phase is different from that of the second clock signal.

[0060] The wiring 159 has a function of transmitting a signal having a high level and a low level. For example, the wiring 159 transmits an output signal of the circuit 100 in the first operation and a During operation, the wiring 159 has a function of transmitting an output signal from the circuit 100 at the subsequent stage. When the output signal to be transmitted is transmitted from an external source, it is sometimes called a start pulse.

[0061] The wiring 160 has a function of transmitting a signal having a high level and a low level. For example, the wiring 160 transmits an output signal of the circuit 100 in the second operation. During operation, the output signal of the circuit 100 in the previous stage is transmitted. When the output signal to be transmitted is transmitted from an external source, it is sometimes called a start pulse.

[0062] As described above, the circuit 100 can be configured to switch the potentials of the wirings 155 and 157 connected to the circuit 100. The circuit 10 can be switched between two operations, a first operation and a second operation. The semiconductor device having 0 is output to the subsequent circuit 100 in the first scanning direction during the first operation. During the second operation, the output signal is transmitted to the downstream circuit 100 in the second scanning direction. This switching operation can be achieved by simply switching the potentials of the wirings 155 and 157. As a result, the scanning direction can be easily switched. The semiconductor device can perform inversion display.

[0063] (Embodiment 2) The operation of a semiconductor device according to one embodiment of the present invention will be described with reference to FIGS. 2. The operation described in FIG. 3 corresponds to the operation of the circuit 100 described in the first embodiment. In this embodiment, the transistors 101 to 109 are N-channel transistors. This is explained as follows.

[0064] In accordance with one aspect of the present invention, a semiconductor device includes: a first operation; a downstream circuit in a first scanning direction; In the second operation, the output signal is transmitted to the subsequent circuit 100 in the second scanning direction. FIG. 2 is a timing diagram showing a possible implementation of the first operation. FIG. 3 is an example of a timing chart capable of realizing the second operation.

[0065] 2 and 3, in order to explain the operation of the circuit 100, the wiring 155, the wiring 157, and the wiring 158, wiring 151, wiring 156, wiring 159, wiring 160, node ND1, node ND 2 shows the potentials of the node ND3 and the wiring 152.

[0066] <Regarding the first operation> First, the first operation will be described with reference to FIG. The first operation is performed by setting the potential of the wiring 157 to VH and the potential of the wiring 158 to VL. The operation will be described for each of the periods T1 to T6. By tracing the change in the potential of D3 and the change in the potential of the wiring 152 that transmits the output signal, Cut.

[0067] For the sake of simplicity, the potential of the signal transmitted by each wiring and node is set to a high level potential. The following description uses two types of potentials: VH and a low-level potential VL. By using two types of potentials, VH and VL, the number of potentials to be generated can be reduced. Therefore, the circuit scale for generating the potential can be reduced. In the case of a wiring configuration, even if the potential of the wiring is described as the same VH, it does not necessarily mean that they are equipotential, but rather that they are different. Similarly, even if the potential of the wiring is described as the same VL, it does not necessarily mean that they are equipotential. The same applies to the second operation described later. do.

[0068] The operation during period T1 will be described.

[0069] The potential of the node ND1 will be described. The potential of the wiring 159 becomes VH. The potential of the wiring 160 becomes VL, so that the transistor 109 As described later, the potential of the node ND3 becomes VL, so the transistor Therefore, the potential of the wiring 155, that is, VH, is applied to the transistor 10 8 to the node ND1, so that the potential of the node ND1 rises from VL. The potential of the node ND1 is changed from VH, which is the potential of the gate of the transistor 108, to When the threshold voltage of 108 (Vth108) is subtracted from the threshold voltage of 108 (VH-Vth108), Therefore, the node ND1 is in a floating state, and the node ND The potential of 1 is maintained at VH-Vth108.

[0070] The potential of the node ND2 will be described. The potential of the wiring 156 becomes VL. The potential of the wiring 158 becomes VH, so that the transistor 107 Therefore, the potential of the wiring 157, VL, is supplied to the transistor 107. Since the signal is transmitted to the node ND2, the potential of the node ND2 becomes VL.

[0071] The potential of the node ND3 will be described. Since the potential of the node ND2 becomes VL, The potential of the node ND1 becomes (VH-Vth108). Therefore, the transistor 105 is turned on. Since the potential is transmitted to the node ND3 via Vdd05, the potential of the node ND3 becomes VL.

[0072] The potential of the wiring 152 will be described. Since the potential of the node ND1 is VH-Vth108, Therefore, the transistor 101 is turned on. Therefore, the potential of VL of the wiring 151 is Since the potential of the wiring 152 is transmitted through the potential detector 101, the potential of the wiring 152 becomes VL. The output signal of 00 becomes VL.

[0073] The operation during period T2 will be described.

[0074] The potential of the node ND1 will be described. The potential of the wiring 159 becomes VL. The potential of the wiring 160 becomes VL, so that the transistor 109 As will be described later, the potential of the node ND3 becomes VL, so the transistor Therefore, the node ND1 is in a floating state, and the node ND1 The potential is maintained at (VH-Vth108).

[0075] The potential of the node ND2 will be described. The potential of the wiring 156 becomes VL. The potential of the wiring 158 becomes VL, so that the transistor 107 Therefore, the node ND2 is in a floating state, and the potential of the node ND2 is is maintained at VL.

[0076] The potential of the node ND3 will be described. Since the potential of the node ND2 becomes VL, The potential of the node ND1 becomes (VH-Vth108). Therefore, the transistor 105 is turned on. Since the voltage is transmitted to the node ND3 via the transistor 105, the potential of the node ND3 becomes VL.

[0077] The potential of the wiring 152 will be described. When the potential of the node ND1 becomes (VH-Vth108), Therefore, the transistor 101 is turned on. The potential of the node ND3 becomes VL, The transistor 102 is turned off. Since the potential is transmitted to the wiring 152 via the capacitor 101, the potential of the wiring 152 starts to rise from VL. At this time, the capacitor 110 holds the potential difference between the wiring 152 and the node ND1, and The node ND1 is in a floating state. The potential of the node ND1 rises from (VH-Vth108). The potential of one of the source and drain of the transistor 101 (VH, which is the potential of the wiring 151) and the The sum of the threshold voltage of transistor 101 (Vth101) and the threshold voltage of transistor 102 (VH+Vth101) is Then, the potential of the wiring 152 rises to VH. That is, the output signal of the circuit 100 becomes VH. do.

[0078] The operation during period T3 will be described.

[0079] The potential of the node ND1 will be described. The potential of the wiring 159 becomes VL. The potential of the wiring 160 becomes VH, so that the transistor 109 As will be described later, the potential of the node ND3 becomes VH, so the transistor Therefore, the potential VL of the wiring 157 is The potential VL of the wiring 153 is transmitted to the node ND1 via the Since the potential is transmitted to the node ND1 via Vdd03, the potential of the node ND1 becomes VL.

[0080] The potential of the node ND2 will be described. The potential of the wiring 156 becomes VH. The potential of the wiring 158 becomes VL, so that the transistor 107 Therefore, the potential of the wiring 155, that is, VH, is supplied through the transistor 106. Since the potential of the node ND2 is transmitted to the node ND2, the potential of the node ND2 rises from VL. The potential of D2 is changed from the potential of the gate of the transistor 106 (VH, which is the potential of the wiring 156) to The threshold voltage of the transistor 106 (Vth106) is subtracted from the value (VH-Vth106). Therefore, the node ND2 is in a floating state. The potential of the node ND2 is maintained at (VH-Vth106).

[0081] The potential of the node ND3 will be described. When the potential of the node ND2 becomes (VH-Vth106), Therefore, the transistor 104 is turned on. Therefore, the potential of the wiring 154 is The potential of the node ND3 rises because the potential of the node ND3 is transmitted to the node ND3 via the node The potential difference between the node ND3 and the node ND2 is The node ND1 is held in a floating state by the parasitic capacitance between the other node and the Therefore, as the potential at the node ND3 rises, the potential at the node ND2 rises. The potential of the node ND2 is the potential of one of the source and drain of the transistor 104 (the potential of the wiring 15 The sum (VH+ When Vth104) becomes higher than the potential of the node ND3, the potential of the node ND3 rises to VH.

[0082] The potential of the wiring 152 will be described. Since the potential of the node ND1 becomes VL, The potential of the node ND3 becomes VH, so the transistor 101 becomes non-conductive. 2 is turned on. Therefore, VL, which is the potential of the wiring 153, is supplied to the transistor 102. The potential of the wiring 152 becomes VL. The signal becomes VL.

[0083] The operation during period T4 will be described.

[0084] The potential of the node ND1 will be described. The potential of the wiring 159 becomes VL. The potential of the wiring 160 becomes VL, so that the transistor 109 As will be described later, the potential of the node ND3 becomes VH, so the transistor Therefore, the potential VL of the wiring 153 is 3 to the node ND1, so that the potential of the node ND1 becomes VL.

[0085] The potential of the node ND2 will be described. The potential of the wiring 156 becomes VL. The potential of the wiring 158 becomes VH, so that the transistor 107 Therefore, the potential of the wiring 157, VL, is supplied to the transistor 107. Since the signal is transmitted to the node ND2, the potential of the node ND2 becomes VL.

[0086] The potential of the node ND3 will be described. Since the potential of the node ND2 becomes VL, The potential of the node ND1 becomes VL, so the transistor 104 becomes non-conductive. 05 is turned off. Therefore, the node ND3 is turned on and the potential of the node ND3 is turned off. However, since the potential of the node ND2 drops, the potential of the node ND3 is often lower than VH.

[0087] The potential of the wiring 152 will be described. Since the potential of the node ND1 becomes VL, The potential of the node ND3 becomes VH, so the transistor 101 becomes non-conductive. 2 is turned on. Therefore, VL, which is the potential of the wiring 153, is supplied to the transistor 102. The potential of the wiring 152 becomes VL. The signal becomes VL.

[0088] The operation during period T5 will be described.

[0089] The potential of the node ND1 will be described. The potential of the wiring 159 becomes VL. The potential of the wiring 160 becomes VL, so that the transistor 109 As will be described later, the potential of the node ND3 becomes VH, so the transistor Therefore, the potential VL of the wiring 153 is 3 to the node ND1, so that the potential of the node ND1 becomes VL.

[0090] The potential of the node ND2 will be described. The potential of the wiring 156 becomes VL. The potential of the wiring 158 becomes VL, so that the transistor 107 Therefore, the node ND2 is in a floating state, and the potential of the node ND2 is is maintained at VL.

[0091] The potential of the node ND3 will be described. Since the potential of the node ND2 becomes VL, The potential of the node ND1 becomes VL, so the transistor 104 becomes non-conductive. 05 is turned off. Therefore, the node ND3 is turned on and the potential of the node ND3 is turned off. is maintained in VH.

[0092] The potential of the wiring 152 will be described. Since the potential of the node ND1 becomes VL, The potential of the node ND3 becomes VH, so the transistor 101 becomes non-conductive. 2 is turned on. Therefore, VL, which is the potential of the wiring 153, is supplied to the transistor 102. The potential of the wiring 152 becomes VL. The signal becomes VL.

[0093] The operation during the period T6 will be described.

[0094] The potential of the node ND1 will be described. The potential of the wiring 159 becomes VL. The potential of the wiring 160 becomes VL, so that the transistor 109 As will be described later, the potential of the node ND3 becomes VH, so the transistor Therefore, the potential VL of the wiring 153 is 3 to the node ND1, so that the potential of the node ND1 becomes VL.

[0095] The potential of the node ND2 will be described. The potential of the wiring 156 becomes VH. The potential of the wiring 158 becomes VL, so that the transistor 107 Therefore, the potential of the wiring 155, that is, VH, is supplied through the transistor 106. Since the potential of the node ND2 is transmitted to the node ND2, the potential of the node ND2 rises from VL. The potential of D2 is changed from the potential of the gate of the transistor 106 (VH, which is the potential of the wiring 156) to When the threshold voltage of the transistor 106 is subtracted from the threshold voltage (VH-Vth106), 106 is turned off. Therefore, the node ND2 is turned on and the voltage of the node ND2 is The position is maintained at VH-Vth106.

[0096] The potential of the node ND3 will be described. When the potential of the node ND2 becomes (VH-Vth106), Therefore, the transistor 104 is turned on. Therefore, the transistor 105 is turned off. The voltage is transmitted to the node ND3 via the transistor 104, so the potential of the node ND3 rises. At this time, the potential difference between the node ND3 and the node ND2 is or the other drain is held by a parasitic capacitance between the drain and the node ND2. Therefore, as the potential of the node ND3 rises, the potential of the node ND2 The potential of the node ND2 increases. potential (VH, which is the potential of the wiring 154) and the threshold voltage (Vth104) of the transistor 104. When the potential at node ND3 becomes higher than the sum (VH+Vth104), the potential at node ND3 rises to VH. .

[0097] The potential of the wiring 152 will be described. Since the potential of the node ND1 becomes VL, The potential of the node ND3 becomes VH, so the transistor 101 becomes non-conductive. Therefore, the potential of the wiring 153 is applied to the wiring 15 through the transistor 102. 2, the potential of the wiring 152 becomes VL. become.

[0098] The above is a description of the first operation. In a semiconductor device having a plurality of circuits 100, For example, the (n-1)th stage, the nth stage, the (n+ 1) In a semiconductor device in which the circuits 100 of the first stage (n is a natural number of 2 or more) are provided in order, Output signals are output in the scanning direction, that is, in the order of the (n-1)th stage, the nth stage, and the (n+1)th stage. It is possible.

[0099] Specifically, in the n-th stage circuit 100, the potential of the wiring 155 is set to VH and the potential of the wiring 157 is set to VL. The signal transmitted to the wiring 159 is the output signal of the circuit 100 in the previous stage (n-1 stage), and the signal transmitted to the wiring 1 The signal transmitted to the first scanning line 60 is used as the output signal of the circuit 100 in the next stage (n+1 stage). It is possible to output an output signal in a direction.

[0100] <About the second operation> Next, the second operation will be described with reference to FIG. This is done by setting the potential of the line 154 to VL and the potential of the line 157 to VH. The operation will be explained by dividing it into periods t1 to t6. Note that the operation in each period is By tracking the change in potential of ND3 and the change in potential of the wiring 152 that transmits the output signal, It can be clarified.

[0101] The operation during period t1 will be described.

[0102] The potential of the node ND1 will be described. The potential of the wiring 159 becomes VL. The potential of the wiring 160 becomes VH, so that the transistor 109 As will be described later, the potential of the node ND3 becomes VL, so the transistor Therefore, the potential of the wiring 157, that is, VH, is applied to the transistor 10 9 to the node ND1, so that the potential of the node ND1 rises from VL. The potential of the node ND1 is equal to the potential of the gate of the transistor 109 (the potential of the wiring 160, V H) minus the threshold voltage (Vth109) of the transistor 109 (VH-Vth10 9), the transistor 109 is turned off. Therefore, the node ND1 is in a floating state. The potential of the node ND1 is maintained at VH-Vth109.

[0103] The potential of the node ND2 will be described. The potential of the wiring 156 becomes VH. The potential of the wiring 158 becomes VL, so that the transistor 107 Therefore, the potential VL of the wiring 155 is supplied to the transistor 106 through the transistor 106. Since the signal is transmitted to the node ND2, the potential of the node ND2 becomes VL.

[0104] The potential of the node ND3 will be described. Since the potential of the node ND2 becomes VL, The potential of the node ND1 becomes (VH-Vth109). Therefore, the transistor 105 is turned on. Since the voltage is transmitted to the node ND3 via the transistor 105, the potential of the node ND3 becomes VL.

[0105] The potential of the wiring 152 will be described. When the potential of the node ND1 becomes (VH-Vth109), Therefore, the transistor 101 is turned on. The potential of the node ND3 becomes VL, The transistor 102 is turned off. The potential of the wiring 152 becomes VL because the potential is transmitted to the wiring 152 via the transistor 101. , the output signal of the circuit 100 becomes VL.

[0106] The operation during period t2 will be described.

[0107] The potential of the node ND1 will be described. The potential of the wiring 159 becomes VL. The potential of the wiring 160 becomes VL, so that the transistor 109 As will be described later, the potential of the node ND3 becomes VL, so the transistor Therefore, the node ND1 is in a floating state, and the node ND1 The potential is maintained at (VH-Vth109).

[0108] The potential of the node ND2 will be described. The potential of the wiring 156 becomes VL. The potential of the wiring 158 becomes VL, so that the transistor 107 Therefore, the node ND2 is in a floating state, and the potential of the node ND2 is is maintained at VL.

[0109] The potential of the node ND3 will be described. Since the potential of the node ND2 becomes VL, The potential of the node ND1 becomes (VH-Vth109). Therefore, the transistor 105 is turned on. Since the voltage is transmitted to the node ND3 via the transistor 105, the potential of the node ND3 becomes VL.

[0110] The potential of the wiring 152 will be described. When the potential of the node ND1 becomes (VH-Vth109), Therefore, the transistor 101 is turned on. The potential of the node ND3 becomes VL, The transistor 102 is turned off. Since the potential of the wiring 152 starts to rise from VL, the potential of the wiring 152 starts to rise from VL. At this time, the capacitor 110 holds the potential difference between the wiring 152 and the node ND1. In addition, the node ND1 is in a floating state. The potential of the node ND1 rises from (VH-Vth109). The potential of one of the source and drain of the transistor 101 (VH, which is the potential of the wiring 151) The sum of the threshold voltage (Vth101) and the threshold voltage (VH+Vth101) of the transistor 101 is higher than When the potential of the wiring 152 increases, the potential of the wiring 152 increases to VH. become.

[0111] The operation during period t3 will be described.

[0112] The potential of the node ND1 will be described. Since the wiring 159 is set to VH, The potential of the wiring 160 becomes VL, so that the transistor 109 becomes non-conductive. As described later, the potential of the node ND3 becomes VH, so that the transistor 10 3 is turned on. Therefore, the potential of VL of the wiring 155 is The potential of the wiring 153 is supplied to the transistor 103. Since the potential of the node ND1 is supplied to the node ND1 via the VSS, the potential of the node ND1 becomes VL.

[0113] The potential of the node ND2 will be described. The potential of the wiring 156 becomes VL. The potential of the wiring 158 becomes VH, so that the transistor 107 Therefore, the potential of the wiring 157, VH, is supplied to the node 106 through the transistor 107. Then, the potential of the node ND2 rises from VL. The potential of the transistor 2 is changed from the potential of the gate of the transistor 107 (VH, which is the potential of the wiring 158) to the potential of the transistor 109. When the threshold voltage of transistor 107 (Vth107) is subtracted (VH-Vth107), Therefore, the node ND2 is in a floating state, and the transistor 107 is turned off. The potential of node ND2 is maintained at (VH-Vth107).

[0114] The potential of the node ND3 will be described. The potential of the node ND2 becomes VH-Vth107. Therefore, the transistor 104 is turned on. Therefore, the transistor 105 is in a non-conducting state. The potential at the node ND3 rises because the potential is transmitted to the node ND3 via the transistor 104. When the potential difference between the node ND3 and the node ND2 is The drain is held by a parasitic capacitance between the drain and the other drain, and the node ND2 is in a floating state. Therefore, as the potential of the node ND3 rises, the potential of the node ND2 also rises. The potential of the node ND2 is equal to the potential of one of the source and drain of the transistor 104 (arrangement The sum (VH, which is the potential of the line 154) and the threshold voltage (Vth104) of the transistor 104 When the potential of the node ND3 becomes higher than VH+Vth104), the potential of the node ND3 rises to VH.

[0115] The potential of the wiring 152 will be described. Since the potential of the node ND1 becomes VL, The potential of the node ND3 becomes VH, so the transistor 101 becomes non-conductive. Therefore, the potential of the wiring 153 is applied to the wiring 15 through the transistor 102. 2, the potential of the wiring 152 becomes VL. become.

[0116] The operation during period t4 will be described.

[0117] The potential of the node ND1 will be described. The potential of the wiring 159 becomes VL. The potential of the wiring 160 becomes VL, so that the transistor 109 As will be described later, the potential of the node ND3 becomes VH, so the transistor Therefore, the potential VL of the wiring 153 is 3 to the node ND1, so that the potential of the node ND1 becomes VL.

[0118] The potential of the node ND2 will be described. The potential of the wiring 156 becomes VH. The potential of the wiring 158 becomes VL, so that the transistor 107 Therefore, the potential VL of the wiring 155 is supplied to the transistor 106 through the transistor 106. Since the signal is transmitted to the node ND2, the potential of the node ND2 becomes VL.

[0119] The potential of the node ND3 will be described. Since the potential of the node ND2 becomes VL, The potential of the node ND1 becomes VL, so the transistor 104 becomes non-conductive. 05 is turned off. Therefore, the node ND3 is turned on and the potential of the node ND3 is turned off. However, since the potential of the node ND2 drops, the potential of the node ND3 is often lower than VH.

[0120] The potential of the wiring 152 will be described. Since the potential of the node ND1 becomes VL, The potential of the node ND3 becomes VH, so the transistor 101 becomes non-conductive. 2 is turned on. Therefore, VL, which is the potential of the wiring 153, is supplied to the transistor 102. The potential of the wiring 152 becomes VL. The signal becomes VL.

[0121] The operation during period t5 will be described.

[0122] The potential of the node ND1 will be described. The potential of the wiring 159 becomes VL. The potential of the wiring 160 becomes VL, so that the transistor 109 As will be described later, the potential of the node ND3 becomes VH, so the transistor Therefore, the potential VL of the wiring 153 is 3 to the node ND1, so that the potential of the node ND1 becomes VL.

[0123] The potential of the node ND2 will be described. The potential of the wiring 156 becomes VL. The potential of the wiring 158 becomes VL, so that the transistor 107 Therefore, the node ND2 is in a floating state, and the potential of the node ND2 is is maintained at VL.

[0124] The potential of the node ND3 will be described. Since the potential of the node ND2 becomes VL, The potential of the node ND1 becomes VL, so the transistor 104 becomes non-conductive. 05 is turned off. Therefore, the node ND3 is turned on and the potential of the node ND3 is turned off. is maintained in VH.

[0125] The potential of the wiring 152 will be described. Since the potential of the node ND1 becomes VL, The potential of the node ND3 becomes VH, so the transistor 101 becomes non-conductive. Therefore, the potential of the wiring 153 is applied to the wiring 15 through the transistor 102. 2, the potential of the wiring 152 becomes VL. become.

[0126] The operation during period t6 will be described.

[0127] The potential of the node ND1 will be described. The potential of the wiring 159 becomes VL. The potential of the wiring 160 becomes VL, so that the transistor 109 As will be described later, the potential of the node ND3 becomes VH, so the transistor Therefore, the potential VL of the wiring 153 is 3 to the node ND1, so that the potential of the node ND1 becomes VL.

[0128] The potential of the node ND2 will be described. The potential of the wiring 156 becomes VL. The potential of the wiring 158 becomes VH, so that the transistor 107 Therefore, VH, which is the potential of the wiring 157, is supplied to the transistor 107. Since the potential of the node ND2 is transmitted to the node ND2, the potential of the node ND2 rises from VL. The potential of D2 is changed from the potential of the gate of the transistor 107 (VH, which is the potential of the wiring 158) to When the threshold voltage of the transistor 107 is subtracted from the threshold voltage (VH-Vth107), 107 is turned off. Therefore, the node ND2 is turned on and the voltage of the node ND2 is The position is maintained at VH-Vth107.

[0129] The potential of the node ND3 will be described. The potential of the node ND2 becomes VH-Vth107. Therefore, the transistor 104 is turned on. Therefore, the transistor 105 is in a non-conducting state. The potential at the node ND3 rises because the potential is transmitted to the node ND3 via the transistor 104. When the potential difference between the node ND3 and the node ND2 is The drain is held by a parasitic capacitance between the drain and the other drain, and the node ND2 is in a floating state. Therefore, as the potential of the node ND3 rises, the potential of the node ND2 also rises. The potential of the node ND2 is equal to the potential of one of the source and drain of the transistor 104 (arrangement The sum (VH, which is the potential of the line 154) and the threshold voltage (Vth104) of the transistor 104 When the potential of the node ND3 becomes higher than VH+Vth104), the potential of the node ND3 rises to VH.

[0130] The potential of the wiring 152 will be described. Since the potential of the node ND1 becomes VL, The potential of the node ND3 becomes VH, so the transistor 101 becomes non-conductive. 2 is turned on. Therefore, VL, which is the potential of the wiring 153, is supplied to the transistor 102. The potential of the wiring 152 becomes VL. The signal becomes VL.

[0131] The above is the description of the second operation. In a semiconductor device having a plurality of circuits 100, For example, the (n-1)th stage, the nth stage, the (n+ 1) In a semiconductor device in which the circuits 100 of the first stage (n is a natural number of 2 or more) are provided in order, The second scanning direction is opposite to the scanning direction, that is, the (n+1)th stage, the nth stage, and the (n-1)th stage. The output signals can be output in sequence.

[0132] Specifically, in the n-th stage circuit 100, the potential of the wiring 157 is set to VH and the potential of the wiring 155 is set to VL. The signal transmitted to the wiring 159 is the output signal of the circuit 100 in the previous stage (n-1 stage), and the signal transmitted to the wiring 1 The signal transmitted to the second scanning line 60 is used as the output signal of the circuit 100 in the subsequent stage (n+1 stage). It is possible to output an output signal in a direction.

[0133] <Summary> The operation of the circuit 100 described above is performed by switching the potentials of the wirings 155 and 157. The scanning direction of the semiconductor device having the scanning element 100 can be switched. The semiconductor device having a display function and a switching function can perform inversion display. Cut.

[0134] In the operation of the circuit 100, the node ND1 is in a floating state and the potential of the wiring 152 is increased. Therefore, even if the potential of the node ND1 is lower than VH, the wiring 152 Therefore, the potential of the output terminal 152 can be boosted to VH and output. This can reduce malfunctions of circuits that operate based on this.

[0135] Similarly, in the operation of the circuit 100, the node ND2 is in a floating state, and the potential of the node ND3 is increased. Therefore, even if the potential of the node ND2 is lower than VH, Therefore, the potential of the node ND3 can be boosted to VH and output. In response, the malfunction of the transistors 102 and 103 that switch between a conductive state and a non-conductive state is reduced. It is possible.

[0136] (Embodiment 3) In this embodiment, a modification of the first and second embodiments will be described.

[0137] In the first and second embodiments, transistors 101 to 109 are used as an example of the circuit and an example of the operation. and a capacitor 110 are illustrated, however, one embodiment of the present invention is not limited thereto. The circuit may also include other transistors and / or other capacitors. Furthermore, one embodiment of the present invention is a method for making a variety of A modified example of such a circuit configuration will be described below.

[0138] In this embodiment, if the explanation overlaps with the explanation in the first and second embodiments, the explanation will be omitted. do.

[0139] <Variation 1> The semiconductor device shown in FIG. 4 differs from that shown in FIG. 1 in that a circuit 100 includes a transistor 111. .

[0140] The gate of the transistor 111 is connected to the wiring 154. One of the drains is connected to the gate of the transistor 101 and the first electrode of the capacitor 110. The other of the source and the drain of the transistor 111 is connected to the The other of the source or drain, the gate of the transistor 105, and the source of the transistor 108 or the other of the drain and the source or drain of the transistor 109. .

[0141] In the semiconductor device shown in FIG. 4, the transistor 111 is in a non-conducting state during periods T2 and t2. Therefore, the other of the source or drain of the transistor 111 (the source of the transistor 108) The potential of the other side (source or drain) does not increase with the increase in the potential of the wiring 152. a transistor 103 connected to the other of the source and drain of the transistor 111; A large voltage is applied to transistors 105, 108, and 109. This prevents the transistors from being damaged, and suppresses the breakdown of the transistors and the change in their characteristics. It is possible to control this.

[0142] Alternatively, the semiconductor device shown in FIG. 4 may be as shown in FIG. 5. In FIG. 5, the transistor 11 The gate of the first transistor is connected to a wiring 154A which is different from the wiring 154. In FIG. The potential transmitted by the wiring 153 is set to be lower than the potential VH transmitted by the wiring 154. During periods T1 and t1, one of the source and drain of the transistor 111 is VH-Vt When the voltage is lower than h108 or VH-Vth109, the transistor 111 is turned off. Therefore, the timing at which the gate of the transistor 101 is made to be in a floating state can be set as follows. This allows the operation speed to be improved.

[0143] <Variation 2> The semiconductor device shown in FIG. 6 differs from that shown in FIG. 1 in that the circuit 100 includes a transistor 112. .

[0144] The gate of the transistor 112 is connected to the wiring 151. One of the source and drain of the transistor 112 is connected to the wiring 153. The other input is connected to node ND3.

[0145] Periods T1, T3, T4 and T6, and periods t1, t3, t4 and In a period t6, when the potential of the wiring 151 becomes VL, the transistor 112 is turned off. In the periods T2 and T5, and in the periods t2 and t5, the voltage of the wiring 151 is When the potential of the wiring 153 becomes VH, the transistor 112 is turned on. Since a certain VL is transmitted to the node ND3 through the transistor 112, the potential of the node ND3 becomes VL. Then, the transistors 102 and 103 become non-conductive. In this way, During periods T5 and t5, the transistors 102 and 103 can be made non-conductive. Therefore, deterioration of the characteristics of the transistors 102 and 103 can be suppressed.

[0146] <Modification 3> The semiconductor device shown in FIG. 7 differs from that shown in FIG. 1 in that the circuit 100 includes a transistor 113. .

[0147] The gate of the transistor 113 is connected to the wiring 151. One of the source and drain of the transistor 113 is connected to the wiring 153. The other input is connected to node ND2.

[0148] Periods T1, T3, T4 and T6, and periods t1, t3, t4 and In a period t6, when the potential of the wiring 151 becomes VL, the transistor 113 is turned off. In the periods T2 and T5, and in the periods t2 and t5, the voltage of the wiring 151 is When the potential of the wiring 153 becomes VH, the transistor 113 is turned on. Since a certain VL is transmitted to the node ND2 through the transistor 113, the potential of the node ND2 becomes VL. Then, the transistor 104 becomes non-conductive. Thus, during the period T5 In the period t5, the transistor 104 can be turned off. This makes it possible to suppress deterioration of the characteristics of the resistor 104.

[0149] <Variation 4> The semiconductor device shown in FIG. 8 differs from that in FIG.

[0150] A first electrode of the capacitor 114 is connected to the node ND2. The pole is connected to the node ND3.

[0151] During periods T3 and t3, the node ND2 is in a floating state and the node ND3 is in a In order to raise the potential of node ND3 while the potential difference with node ND2 is maintained, At this time, the potential of the gate and source or drain of the transistor 104 increases. If the parasitic capacitance between the node ND1 and the other node ND2 is small, the potential of the node ND2 is unlikely to rise. A capacitor 114 is provided between the gate and the other of the source and the drain of the transistor 104. By doing so, it is possible to easily increase the potential of the node ND2. 3 can be more reliably set to VH to turn on the transistor 102. As a result, malfunctions of the output signal of the circuit 100 can be reduced.

[0152] <Variation 5> In the semiconductor device illustrated in FIG. 9, the gate of the transistor 102 is connected to the wiring 161. 1. Similarly, in the semiconductor device shown in FIG. 10, the gate of the transistor 103 is connected to the wiring. 1 in that it is connected to 161.

[0153] The wiring 161 has a function of transmitting a signal having a high level and a low level. For example, the potential of the wiring 161 is the same as that of the wiring 152 during the first operation and the second operation. A signal for turning on the transistor 102 or 103 is transmitted during periods other than VH. For example, in the periods T4 to T6 and t4 to t6, A signal that becomes VH at the timing may be transmitted to the wiring 161. It is preferable that the first to third clock signals are different in phase from each other. The clock signal transmitted by 61 may be called the fourth clock signal. With this configuration, the potential of the wiring 152 can be set to VL more reliably. 00 output signal malfunction can be reduced.

[0154] Alternatively, in the semiconductor device shown in FIG. 9, the gate of the transistor 102 is connected to the wiring 156 or It may be connected to wiring 158.

[0155] <Variation 6> The semiconductor device shown in FIG. 11 includes transistors 105 to 109 and switches 105A to 10 1 in that the semiconductor device shown in FIG. 1 in that the switch 102A is a switch 102B. 1 in that transistor 103 is replaced with switch 103A.

[0156] The switches 102A, 103A, 105A to 109A are not limited to transistors, but may be electrically Since a switch or a mechanical switch can be used, the degree of freedom of design is increased. can be done.

[0157] <Variation 7> The semiconductor device shown in FIG. 14 differs from that shown in FIG. 1 in that the capacitive element 110 is omitted.

[0158] In the semiconductor device shown in FIG. 14, the gate and the other of the source and the drain of a transistor 101 are By designing the parasitic capacitance between the first and second gates to be large, the capacitance element 110 can be omitted. The omission of the capacitance element increases the degree of freedom in design. The area occupied by the sensor can be reduced.

[0159] <Variation 8> In the semiconductor device shown in FIG. 15, transistors 101 to 109 are shown as P-channel transistors. This differs from FIG.

[0160] The semiconductor device shown in Figure 15 uses semiconductor materials that can only be used to make P-channel transistors. and can be applied to the circuit 100.

[0161] <Variation 9> The semiconductor device shown in FIG. 16 is a combination of the above-mentioned modifications 1 to 3, and includes a transistor 111. 1 in that it includes a transistor 112 and a transistor 113.

[0162] The semiconductor device shown in FIG. 16 can be realized by combining the above-mentioned modified examples 1 to 3, which are shown as examples. Thus, the circuit 100 can have the advantages of each of the modifications described above.

[0163] <Modification 10> The semiconductor device shown in FIG. 17 includes transistors 101 to 109 each having a back gate. 1 in that it is shown as a transistor and the back gate is connected to a wiring 162. In addition, the semiconductor device shown in FIG. The transistor is shown as having a back gate, and the back gate is connected to the wiring 162. 1. In addition, the semiconductor device shown in FIG. 19 has transistors 101 to 109, The transistors 101, 104, 106, and The back gate of the transistor 108 is connected to the wiring 162, and the transistors 102, 103, 105, 1 in that the back gates of 107 and 109 are connected to a wiring 163. The semiconductor device shown in FIG. 20 includes transistors 101 to 109 as transistors having back gates. The back gates of the transistors 101 and 102 are connected to the gates. The back gates of the transistors 103 to 109 are connected to the wiring 162, which is different from FIG. different.

[0164] The wiring 162 has a function of transmitting a high-level or low-level potential. In other words, the wiring 162 controls the threshold voltage of the transistor during the first operation and the second operation. The wiring 163 has a function of transmitting a controllable potential. As a specific example, the wiring 163 has a function of transmitting a potential. During operation, a potential that can control the threshold voltage of the transistor is different from the potential of the wiring 162. For example, the threshold voltage of a transistor can be controlled by the following potential: It is preferable that the potential is equal to or lower than VH, or equal to or higher than VL.

[0165] The semiconductor device shown in FIGS. 17 to 19 has wiring set to VH and wiring set to VL. Therefore, the through current between the first and second gates can be reduced, and the power consumption can be reduced. In addition, in the semiconductor device shown in FIG. The potential of the transistors 101 and 102 is set to be equal to the gate potential, and the current supply capacity of the transistors 101 and 102 is increased. Therefore, the rise time and fall time of the signal transmitted to the wiring 152 can be shortened. It is possible.

[0166] <Summary> As described above, one embodiment of the present invention is described with reference to the examples of the circuits and the examples of the operations in Embodiments 1 and 2. In one embodiment of the present invention, a separate transistor and / or a separate capacitor element, separate wiring, By providing or omitting the above, various circuit configurations can be realized.

[0167] (Embodiment 4)

[0168] In this embodiment, the shift register using the circuit 100 described in the above embodiments 1 to 3 is An example of the star will now be described.

[0169] The shift register 200 shown in FIG. 21 corresponds to the circuit 100 described in the first to third embodiments. The corresponding circuits 201[i] to 201[i+2] (i is a natural number of 3 or more) are included. The circuits 201[i] to 201[i+2] include transistors 101 to 10 9, and a capacitive element 110.

[0170] In FIG. 21, the output signals of the circuits 201[i] to 201[i+2] are represented as OUT[i] to OUT[i+2] is illustrated. The wires are illustrated as wires 218[i] through 218[i+2]. 218[i+2] correspond to the wiring 152 described in the first to third embodiments. In addition, the output signal OU of the circuit 201[i-1] (not shown) which is the previous stage of the circuit 201[i] The wiring that transmits T[i-1] is illustrated as wiring 218[i-1]. Similarly, The output signal OUT[ The wire conveying signal i+3] is illustrated as wire 218[i+3].

[0171] In FIG. 21, wirings 211 to 217 are shown as examples of wirings connecting to the circuit 201[i]. is.

[0172] In the circuit 201[i], for example, the wiring 211 is the wiring 1 described in the above embodiments 1 to 3. 58. The wiring 211 has a function of transmitting a signal CK1, for example. K1 corresponds to any one of the first to third clock signals.

[0173] In the circuit 201[i], for example, the wiring 212 is the wiring 1 described in the first to third embodiments. 51. The wiring 212 has a function of transmitting a signal CK2, for example. K2 corresponds to any one of the first to third clock signals that is different from the signal CK1.

[0174] In the circuit 201[i], for example, the wiring 213 is the wiring 1 described in the above embodiments 1 to 3. 56. The wiring 213 has a function of transmitting a signal CK3, for example. K3 corresponds to one of the first to third clock signals different from the signals CK1 and CK2. Correct.

[0175] In the circuit 201[i], for example, the wiring 214 is the wiring 1 described in the first to third embodiments. 54. The wiring 214 has a function of being set to VDD, for example. VDD corresponds to VH.

[0176] For example, in the circuit 201[i], the wiring 215 is the wiring 1 described in any of the above embodiments 1 to 3. 53. The wiring 215 has a function of being set to VSS, for example. VSS corresponds to VL.

[0177] In the circuit 201[i], for example, the wiring 216 is the wiring 1 described in the first to third embodiments. The wiring 216 corresponds to, for example, a signal SEL1. SEL1 is at a high level, for example, VDD, during the first period, and at a low level during the second period. For example, a signal that is VSS.

[0178] In the circuit 201[i], for example, the wiring 217 is the wiring 1 described in the above embodiments 1 to 3. The wiring 217 corresponds to, for example, a signal SEL2. SEL2 is at a low level, for example, VSS, during the first period, and at a high level during the second period. For example, this is a signal that becomes VDD.

[0179] In the first operation of the shift register 200, for example, in the circuit 201[i], The output signal OUT[i-1] of 01[i-1] (not shown) is shifted. [i] to the wiring 218[i]. Similarly, for example, the circuit 201[i+1] Then, the output signal OUT[i+1 ] to the wiring 218[i+1]. The waveforms of the signals are shown in FIG. For the operation of each transistor, refer to the description of the second embodiment.

[0180] In addition, in the second operation of the shift register 200, for example, in the circuit 201[i+1] is the output signal OUT[i+2] of the circuit 201[i+2] shifted. i+1] to the wiring 218[i+1]. ], the output signal OUT[i+1] of the circuit 201[i+1] is shifted to the output signal OU T[i] to the wiring 218[i]. The waveforms of the signals are shown in FIG. For the operation of each transistor in the above, the description in the second embodiment may be referred to.

[0181] As shown in FIG. 22, in the first operation, the shift register 200 has a wiring 218[ 218[i+1]. Similarly, during the second operation, the line 218[i+1] to the line 218[ i]. In this way, The shift register 200 is a shift register that can output pulses in sequence in both directions. The shift register 200 has the following functions: The shift direction of the pulse is determined by the signal SE L1 or signal SEL2 can be changed to a high level or a low level. However, the functions of the shift register 200 are not limited to this.

[0182] FIG. 33 shows an example of a layout diagram of the circuit 201[i] shown in FIG. In the example shown in FIG. 1, a first wiring 401, a source electrode, and a drain electrode are provided in the same layer as the gate electrode. A second wiring 402, a semiconductor layer 403, and a first wiring 401 and a second wiring 402 are provided in the same layer. An example of the arrangement of openings 404 for connection to lines 402 is shown.

[0183] The semiconductor layer 403 and the first wiring 401 overlap each other, and the second wiring 4 is connected to both ends of the semiconductor layer. The area where the first wiring 401 and the second wiring 402 overlap is the area where the transistor is located. The region where the wiring 402 overlaps is the region occupied by the capacitance element. The arrangement of the transistors 101 to 109 and the capacitor element 110 is shown in FIG. Now, the layout of the wiring 211 to 217 and the wiring 218[i-1] to wiring 218[i+1] is as follows: It shows.

[0184] In the example of the layout shown in FIG. 33, the top-bottom relationship between the wiring and the semiconductor layers is as follows: In the example shown, the semiconductor layer 403, the first wiring 401, and the second wiring 402 are stacked in this order. Alternatively, the first wiring 401 may be placed on the lower layer, or the second wiring 402 may be placed on the lower layer. In addition, the semiconductor layer 403 is wider than the first wiring 401 and the second wiring 402. Alternatively, the semiconductor layer 403 may be provided so as to be connected to the first wiring 401 and the second wiring 402. It may be provided so as to have a smaller width.

[0185] (Embodiment 5) In this embodiment, a display device to which a semiconductor device according to one embodiment of the present invention can be applied will be described. Reveal.

[0186] The display device illustrated in FIG. 23A includes a circuit 300 and a pixel portion 130. 0 has N wirings GL (also indicated as GL[1] to GL[N]) (N is a natural number greater than or equal to 3). In addition, M (M is a natural number) wirings SL (also indicated as wirings SL[1] to SL[M]) are provided. Then, pixels 131 are provided corresponding to the N wirings GL and the M wirings SL. The circuit 300 includes a gate driver (a gate line driving circuit, a gate signal line driving circuit, a scanning line driving circuit, The N wirings GL are gate lines (gate signal lines, running The M lines SL have the function of transmitting video signals. That is, the M wirings SL are used as source lines (also called source signal lines or signal lines). The M lines SL are connected to a source driver (a source line driver circuit, a source The pixel electrodes 111 and 112 are connected to a circuit having a function as a signal line driver circuit or a signal line driver circuit.

[0187] As the circuit 300, the shift register 200 described in the fourth embodiment is used. In this case, the N wirings GL correspond to the wiring 218. 300 includes N circuits 301 (also shown as circuits 301[1] to 301[N]). The circuit 100 described in any one of the first to third embodiments can be used. In this case, the N wirings GL correspond to the wiring 152.

[0188] The selection or non-selection of the pixel 131 is controlled based on the potential of the wiring GL. The selection or non-selection of pixel 131 is controlled by circuit 300. When pixel 131 is selected, the video A video signal is written to the pixel 131 from the line SL. The pixel 131 displays a picture according to the video signal. When deselected, pixel 131 continues to display according to the held video signal.

[0189] Next, a specific example of the configuration of the pixel 131 will be described.

[0190] The pixel 131 illustrated in FIG. 23B includes a transistor 132, a liquid crystal element 133, and a capacitor. The transistor 132 has a first terminal connected to the line SL and a second terminal The first electrode (also called a pixel electrode) of the liquid crystal element 133 and the first electrode of the capacitor element 134 are The second electrode (conductive layer) of the liquid crystal element 133 is electrically connected to the gate electrode (conductive layer) of the liquid crystal element 133 and the gate electrode (conductive layer) of the liquid crystal element 133 is electrically connected to the wiring GL. The pixel electrode (also referred to as a mono electrode) is common to all or two or more of the pixels 131. The conductor having a region that becomes the second electrode of the liquid crystal element 133 of the first pixel 131 is The second electrode of the liquid crystal element 133 of the pixel 131 is provided. The second electrode of the capacitor 134 is connected to a wiring that functions as a capacitor line. is connected to the same wiring in all or two or more of the pixels 131. The second electrode of the element 134 may be connected to the second electrode of the liquid crystal element 133. The transistor 132 is turned on or off depending on the potential of the wiring GL. When the line SL is turned on, the video signal of the line SL is input to the pixel 131. The liquid crystal element 133 The liquid crystal material is aligned by the first electrode of the liquid crystal element 133 and the The capacitance element 134 is controlled by the potential difference between the first electrode and the second electrode. That is, the capacitor 134 has a function of storing the potential of the first electrode of the liquid crystal element 133. It has the function of maintaining the position at a value corresponding to the video signal.

[0191] The pixel 131 illustrated in FIG. 23C includes a transistor 135, a transistor 136, and an EL The transistor 135 has a first terminal connected to the wiring SL and a second terminal connected to the The terminal is connected to the gate of the transistor 136, and the gate is connected to the wiring GL. The resistor 136 is a wiring having a function of supplying a current to the EL element 137 at a first terminal. and the second terminal is connected to a first electrode (also called a pixel electrode) of the EL element 137. The second electrode (also called a common electrode) of the EL element 137 is connected to all or a part of the pixels 131. That is, the second electrode of the EL element 137 of the first pixel 131 is The conductor having a region that will become the second electrode of the EL element 137 of the second pixel 131 is The transistor 135 is turned on or off depending on the potential of the wiring GL. When the transistor 135 is turned on, the video signal on the wiring SL is input to the pixel 131. The transistor 136 has a function of supplying a current to the EL element 137. The current supplied from 136 to EL element 137 has a value according to the video signal. The LED 7 has a function of emitting light in response to a current supplied from a transistor 136 .

[0192] The configuration of the pixel 131 is not limited to that shown in FIG. 23(B) and FIG. 23(C). a transistor having a first terminal connected to a line GL and a second terminal connected to a line SL; A display element that displays a picture based on a video signal input via a transistor. Alternatively, the pixel 131 may have a gate connected to the wiring GL and a first terminal connected to the wiring SL. and a transistor connected to the and a pixel electrode to which the potential or current is supplied. a transistor having a gate connected to a wiring GL and a first terminal connected to a wiring SL; A current based on a video signal input through a transistor is supplied to a display element or pixel electrode. and a transistor for supplying the same.

[0193] (Embodiment 6) In this embodiment, a transistor applicable to the transistors 101 to 109 of the circuit 100 is An example of the configuration of the register will be described with reference to the drawings.

[0194] <Example of transistor configuration> FIG. 24A is a schematic top view of a transistor 600, which will be described below. FIG. 24B is a schematic cross-sectional view of the transistor 600 taken along the line AB in FIG. The transistor 600 illustrated in FIGS. 24(A) and 24(B) is a bottom-gate transistor. It is.

[0195] The transistor 600 includes a gate electrode 602 provided on a substrate 601 and a An insulating layer 603 is provided on the gate electrode 602, and the gate electrode 602 is provided on the insulating layer 603. The oxide semiconductor layer 604 provided so as to overlap with the oxide semiconductor layer 604 The pair of electrodes 605a and 605b are provided. The insulating layer 603 and the oxide semiconductor layer 604 are provided. An insulating layer 606 covers the pair of electrodes 605a and 605b, and an insulating layer 607 is formed on the insulating layer 606. is provided.

[0196] There is no particular restriction on the material of the substrate 601, but it should be at least strong enough to withstand the subsequent heat treatment. Use heat-resistant materials. For example, glass substrate, ceramic substrate, quartz substrate, safa A ceramic substrate, a YSZ (yttria stabilized zirconia) substrate, etc. may be used as the substrate 601. In addition, a single crystal semiconductor substrate or a polycrystalline semiconductor substrate made of silicon or silicon carbide is preferably used. Compound semiconductor substrates made of silicon germanium, SOI substrates, etc. can also be used. In addition, the above substrates on which semiconductor elements are provided are referred to as the substrate 601. It may be used.

[0197] In addition, a flexible substrate such as plastic is used as the substrate 601, and the substrate is directly formed on the flexible substrate. Alternatively, the transistor 600 may be formed between the substrate 601 and the transistor 600. A peeling layer may be provided on the upper layer of the transistor. After that, it can be separated from the substrate 601 and used for transfer to another substrate. Therefore, the transistor 600 can be transferred to a substrate having low heat resistance or a flexible substrate.

[0198] The gate electrode 602 may be made of any of aluminum, chromium, copper, tantalum, titanium, molybdenum, tungsten, etc. A metal selected from the group consisting of tin, tin, tin alloys, and tin alloys containing the above-mentioned metals. In addition, it can be formed by using an alloy of manganese and zirconium. The gate electrode 602 may be a single layer. For example, a silicon-containing aluminum film may be used. Single layer structure, two-layer structure with titanium layer laminated on aluminum layer, titanium layer on titanium nitride layer a two-layer structure in which a tungsten film is laminated on a titanium nitride film; A two-layer structure in which a tungsten film is laminated on a titanium film or a tungsten nitride film, and a titanium film and A three-layer structure in which an aluminum film is laminated on a titanium film, and a titanium film is further formed on the aluminum film. In addition, titanium, tantalum, tungsten, molybdenum, chromium, , neodymium, and scandium, or an alloy film made by combining one or more metals selected from the group consisting of Alternatively, a nitride film may be used.

[0199] The gate electrode 602 is made of indium tin oxide or indium oxide containing tungsten oxide. oxide, indium zinc oxide with tungsten oxide, indium oxide with titanium oxide Indium tin oxide, indium zinc oxide, silicon oxide with titanium oxide A light-transmitting conductive material such as indium tin oxide can also be used. A laminated structure of the above-mentioned light-transmitting conductive material and the above-mentioned metal may also be used.

[0200] In addition, an In-Ga-Zn-based oxynitride semiconductor film is formed between the gate electrode 602 and the insulating layer 603. , In-Sn-based oxynitride semiconductor film, In-Ga-based oxynitride semiconductor film, In-Zn-based oxynitride Semiconductor film, Sn-based oxynitride semiconductor film, In-based oxynitride semiconductor film, metal nitride film (InN, These materials have an energy of 5 eV or more, preferably 5.5 eV or more. This is the work function, and the threshold voltage of the transistor can be made positive, so-called normal For example, an In-Ga-Zn-based oxynitride semiconductor film can be used In the case of using the oxide semiconductor layer 604, the nitrogen concentration is at least 7 atomic %. The above-mentioned In-Ga-Zn-based oxynitride semiconductor film is used.

[0201] The insulating layer 603 functions as a gate insulating film. The edge layer 603 is preferably an insulating oxide film.

[0202] The insulating layer 603 is, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, or silicon nitride. Copper, aluminum oxide, hafnium oxide, gallium oxide or Ga-Zn-based metal oxide The above may be used, and the layer may be a laminate or a single layer.

[0203] The insulating layer 603 is made of hafnium silicate (HfSiO x ), nitrogen added Hafnium Silicate (HfSi x O y N z ), nitrogen-doped hafnium aluminate HfAl x O y N z ), high-k materials such as hafnium oxide and yttrium oxide By using this, the gate leakage of the transistor can be reduced.

[0204] The pair of electrodes 605a and 605b serve as source and drain electrodes of the transistor. It works like this.

[0205] The pair of electrodes 605a and 605b are made of a conductive material such as aluminum, titanium, chromium, or nickel. Nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum, or tungsten Metals such as zinc or alloys containing these as the main component are used in a single layer structure or a laminated structure. For example, a single layer structure of an aluminum film containing silicon, Two-layer structure with titanium film laminated, two-layer structure with titanium film laminated on tungsten film, copper-ma A two-layer structure in which a copper film is laminated on a magnesium-aluminum alloy film, a titanium film or a titanium nitride film A titanium film or titanium nitride film is laminated with an aluminum film or a copper film. a three-layer structure in which a titanium film or a titanium nitride film is formed on the first layer; Molybdenum nitride film and aluminum layer on the molybdenum film or molybdenum nitride film A molybdenum film or a molybdenum nitride film is then formed on the copper film. There are three-layer structures. Transparent conductive materials containing indium oxide, tin oxide, or zinc oxide are used. It may be used.

[0206] The insulating layer 606 is formed using an oxide insulating film containing more oxygen than the oxygen required for the stoichiometric composition. It is preferable that the oxide insulating film contains more oxygen than the oxygen required for the stoichiometric composition. When heated, some oxygen is released. The oxide insulating film, including the In the on-line spectroscopy analysis, the amount of oxygen released when converted to oxygen atoms was 1 .0×10 18 atoms / cm 3 More than 3.0×10 20 atoms / cm 3 The oxide insulating film is as above. Note that the surface temperature of the film during the TDS analysis was The temperature is preferably in the range of 100° C. or higher and 700° C. or lower, or 100° C. or higher and 500° C. or lower.

[0207] The insulating layer 606 can be made of silicon oxide, silicon oxynitride, or the like.

[0208] The insulating layer 606 is formed so as to cover the oxide semiconductor layer 60 when the insulating layer 607 is formed later. It also functions as a damage mitigation membrane for 4.

[0209] Alternatively, an oxide film that transmits oxygen may be provided between the insulating layer 606 and the oxide semiconductor layer 604. good.

[0210] As the oxide film that transmits oxygen, silicon oxide, silicon oxynitride, etc. can be used. In this specification, the silicon oxynitride film is a film containing less than or equal to nitrogen. A silicon nitride film is a film that contains more oxygen than silicon dioxide. This refers to a film with a high nitrogen content.

[0211] The insulating layer 607 can be made of an insulating film having a blocking effect against oxygen, hydrogen, water, and the like. By providing the insulating layer 607 over the insulating layer 606, oxygen from the oxide semiconductor layer 604 can be prevented. Therefore, the diffusion of hydrogen, water, and the like to the outside and the intrusion of hydrogen, water, and the like into the oxide semiconductor layer 604 from the outside can be prevented. Examples of insulating films that have a blocking effect against oxygen, hydrogen, water, etc. include silicon nitride, Silicon oxide, aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride Yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride Examples include

[0212] <Example of transistor manufacturing method> Next, an example of a method for manufacturing the transistor 600 illustrated in FIGS.

[0213] First, as shown in FIG. 25(A), a gate electrode 602 is formed on a substrate 601. An insulating layer 603 is formed on the electrode 602 .

[0214] Here, a glass substrate is used as the substrate 601 .

[0215] The method of forming the gate electrode 602 will be described below. First, the sputtering method, the CVD method, and the evaporation method are used. A conductive film is formed by deposition or the like, and a first photomask is used to perform photolithography on the conductive film. A resist mask is formed by a deposition process. Next, a part of the conductive film is The resist mask is then etched to form a gate electrode 602. After that, the resist mask is removed.

[0216] The gate electrode 602 may be formed by electrolytic plating, printing, inkjet printing, or the like instead of the above-mentioned method. It may be formed by a jet method or the like.

[0217] The insulating layer 603 is formed by a sputtering method, a PECVD method, a vapor deposition method, or the like.

[0218] As the insulating layer 603, a silicon oxide film, a silicon oxynitride film, or a silicon nitride oxide film is used. In the case of forming the silicon-containing film, a deposition gas containing silicon and an oxidizing gas are used as the source gas. Representative examples of deposition gases containing silicon include silane, disilane, trisilane, and Examples of oxidizing gases include oxygen, ozone, nitrous oxide, and dioxygen. Examples include nitrogen oxides.

[0219] In addition, when forming a silicon nitride film as the insulating layer 603, a two-stage formation method is used. First, a mixture of silane, nitrogen, and ammonia is used as a raw material gas. A first silicon nitride film with few defects is formed by the plasma CVD method using the same material. The fuel gas was changed to a mixture of silane and nitrogen, and the hydrogen concentration was low and hydrogen was not blown. A second silicon nitride film capable of being coated is formed. As the insulating layer 603, a silicon nitride film having few defects and a hydrogen blocking property is used. can be formed.

[0220] In addition, when a gallium oxide film is formed as the insulating layer 603, MOCVD (Metal O Formed using the organic chemical vapor deposition (OCVD) method It is possible.

[0221] Next, as shown in FIG. 25B, an oxide semiconductor layer 604 is formed over the insulating layer 603.

[0222] A method for forming the oxide semiconductor layer 604 is described below. First, an oxide semiconductor film is formed. Subsequently, a second photomask is used to form a photoresist film on the oxide semiconductor film through a photolithography process. A resist mask is formed. Next, part of the oxide semiconductor film is etched using the resist mask. Then, etching is performed to form the oxide semiconductor layer 604. After that, the resist mask is removed.

[0223] After this, a heat treatment may be performed. When the heat treatment is performed, it is performed in an atmosphere containing oxygen. The temperature of the heat treatment is preferably, for example, 150° C. or higher and 600° C. or lower. and preferably, the heating temperature is set to 200° C. or higher and 500° C. or lower.

[0224] Next, as shown in FIG. 25(C), a pair of electrodes 605a and 605b are formed.

[0225] The method for forming the pair of electrodes 605a and 605b will be described below. First, a sputtering method is used. A conductive film is formed by a PECVD method, a vapor deposition method, etc. Next, a third photomask is applied to the conductive film. A resist mask is formed by a photolithography process using the resist mask. The conductive film is partially etched using a etch mask to form a pair of electrodes 605a and 605b. Thereafter, the resist mask is removed.

[0226] Note that as shown in FIG. 25C, when the conductive film is etched, the upper part of the oxide semiconductor layer 604 is Therefore, the oxide semiconductor layer 604 may be partially etched and thinned. When the oxide semiconductor film is formed, the thickness of the oxide semiconductor film is preferably set to be large in advance.

[0227] Next, as shown in FIG. 25D, the oxide semiconductor layer 604 and the pair of electrodes 605a and 60 An insulating layer 606 is formed on 5b, and then an insulating layer 607 is formed on the insulating layer 606.

[0228] When a silicon oxide film or a silicon oxynitride film is formed as the insulating layer 606, the source gas As the gas, a deposition gas containing silicon and an oxidizing gas are preferably used. Representative examples of deposition gases containing silane include silane, disilane, trisilane, and fluorosilane. The oxidizing gases include oxygen, ozone, nitrous oxide, and nitrogen dioxide.

[0229] For example, a substrate placed in a vacuum-evacuated processing chamber of a plasma CVD device is heated to 180° C. or higher. The temperature is kept at 260° C. or less, more preferably at 200° C. or more and 240° C. or less, and the raw material gas is introduced into the processing chamber. By introducing the gas, the pressure in the processing chamber is adjusted to 100 Pa or more and 250 Pa or less, more preferably 1 00 Pa to 200 Pa, and 0.17 W / cm2 to the electrode installed in the treatment chamber 2 End 0.5W / cm 2 Less than or equal to 0.25 W / cm 2 More than 0.35W / cm 2 Below Silicon oxide film or silicon oxynitride film is formed by supplying high frequency power under the following conditions. do.

[0230] As a film formation condition, high frequency power with the above power density is supplied in a processing chamber with the above pressure. In the plasma, the decomposition efficiency of the source gas increases, oxygen radicals increase, and the source gas is oxidized. As a result, the oxygen content in the oxide insulating film becomes higher than the stoichiometric ratio. However, when the substrate temperature is above this level, the bond between silicon and oxygen is weak, and the A portion of the oxygen is released. As a result, the mixture contains more oxygen than the stoichiometric composition. In this case, an oxide insulating film from which part of oxygen is released by heating can be formed.

[0231] In addition, in the case where an oxide insulating film is provided between the oxide semiconductor layer 604 and the insulating layer 606, In the step of forming the layer 606 , the oxide insulating film serves as a protective film for the oxide semiconductor layer 604 . As a result, damage to the oxide semiconductor layer 604 is reduced, and high-frequency power density is achieved. A force may be used to form the insulating layer 606 .

[0232] For example, a substrate placed in an evacuated processing chamber of a PECVD apparatus is heated to 180° C. or higher for 40 The temperature is kept at 0° C. or lower, more preferably at 200° C. or higher and 370° C. or lower, and the raw material gas is introduced into the processing chamber. The pressure in the processing chamber is set to 20 Pa or more and 250 Pa or less, and more preferably 100 Pa or less. a or more and 250 Pa or less, and high-frequency power is supplied to the electrode installed in the treatment chamber. As a result, a silicon oxide film or a silicon oxynitride film can be formed as the oxide insulating film. In addition, by setting the pressure in the treatment chamber to 100 Pa or more and 250 Pa or less, the oxide insulating film When the oxide semiconductor layer 604 is formed, damage to the oxide semiconductor layer 604 can be reduced.

[0233] As the source gas for the oxide insulating film, a deposition gas containing silicon and an oxidizing gas are used. Representative examples of deposition gases containing silicon include silane, disilane, trisilane, and Examples of oxidizing gases include oxygen, ozone, nitrous oxide, and dioxygen. Examples include nitrogen oxides.

[0234] The insulating layer 607 can be formed by a sputtering method, a PECVD method, or the like.

[0235] When a silicon nitride film or a silicon nitride oxide film is formed as the insulating layer 607, the raw material gas The gas used may be a deposition gas containing silicon, an oxidizing gas, or a gas containing nitrogen. Representative examples of deposition gases containing silicon include silane, disilane, trisilane, and Examples of oxidizing gases include oxygen, ozone, nitrous oxide, and fluorinated silane. Nitrogen, etc. Nitrogen-containing gases include nitrogen and ammonia.

[0236] Through the above steps, the transistor 600 can be formed.

[0237] <Modifications of Transistor> An example of a configuration of a transistor that is partially different from the transistor 600 will be described below.

[0238] FIG. 26A is a schematic cross-sectional view of a transistor 610, which will be described below. The transistor 610 differs from the transistor 600 in the structure of the oxide semiconductor layer.

[0239] The oxide semiconductor layer 614 in the transistor 610 includes an oxide semiconductor layer 614a and an oxide The semiconductor layer 614b is laminated thereon.

[0240] Note that the boundary between the oxide semiconductor layer 614a and the oxide semiconductor layer 614b may be unclear. Therefore, in figures such as FIG. 26(A), these boundaries are shown by dashed lines.

[0241] The oxide semiconductor layer 614a is typically made of In-Ga oxide, In-Zn oxide, or In-M -Zn oxide (M is Al, Ti, Ga, Y, Zr, La, Ce, Nd, or Hf) When the oxide semiconductor layer 614a is an In-M-Zn oxide, Zn and O The atomic ratio of In and M excluding the above is preferably less than 50 atomic % In, M is 50 atomic % or more, more preferably In is less than 25 atomic %, and M is For example, the oxide semiconductor layer 614a has an energy A material having a gap of 2 eV or more, preferably 2.5 eV or more, more preferably 3 eV or more. is used.

[0242] The oxide semiconductor layer 614b contains In or Ga, and is typically In-Ga oxide, I n-Zn oxide, In-M-Zn oxide (M is Al, Ti, Ga, Y, Zr, La, Ce) , Nd, or Hf) and has a lower energy of the conduction band than the oxide semiconductor layer 614a. is close to the vacuum level, and typically, the energy level of the conduction band of the oxide semiconductor layer 614b is and the energy difference between the conduction band minimum of the oxide semiconductor layer 614a and the conduction band minimum of the oxide semiconductor layer 614b is 0.05 eV or more. 0.07 eV or more, 0.1 eV or more, or 0.15 eV or more and 2 eV or less, 1 eV It is preferably 0.5 eV or less, or 0.4 eV or less.

[0243] When the oxide semiconductor layer 614b is an In-M-Zn oxide, the The atomic ratio of In and M is preferably 25 atomic % or more of In and 75 atomic % or more of M. %, more preferably, In is 34 atomic % or more and M is 66 atomic % or less. Less than ic%.

[0244] For example, the oxide semiconductor layer 614a may be made of In:Ga:Zn=1:1:1, In:Ga:Z In-Ga-Z with an atomic ratio of n=1:1:1.2 or In:Ga:Zn=3:1:2 The oxide semiconductor layer 614b may be made of In:Ga:Zn In-Ga-Zn oxide with atomic ratios of 1:3:2, 1:6:4, or 1:9:6 was used. Note that the atoms of the oxide semiconductor layer 614a and the oxide semiconductor layer 614b can be The atomic ratios each include a margin of error of plus or minus 20% from the atomic ratios listed above.

[0245] The oxide semiconductor layer 614b provided on the upper layer contains Ga, which functions as a stabilizer. By using an oxide having a large amount, the oxide semiconductor layer 614a and the oxide semiconductor layer 61 The release of oxygen from 4b can be suppressed.

[0246] In addition, the semiconductor characteristics and electrical characteristics (field effect The appropriate composition may be used depending on the required transistor (e.g., mobility, threshold voltage, etc.). In order to obtain the semiconductor characteristics of a transistor, the oxide semiconductor layer 614a and the oxide semiconductor layer 614b are Carrier density, impurity concentration, defect density, atomic ratio of metal elements to oxygen, interatomic distance, density It is preferable to make the above appropriate.

[0247] Note that in the above description, the oxide semiconductor layer 614 has a structure in which two oxide semiconductor layers are stacked. Although this is illustrated as an example, a structure in which three or more oxide semiconductor layers are stacked may be used.

[0248] FIG. 26B is a schematic cross-sectional view of a transistor 620, which will be described below. The transistor 620 is different from the transistor 600 in the structure of the oxide semiconductor layer. It is different from 10.

[0249] The oxide semiconductor layer 624 in the transistor 620 includes an oxide semiconductor layer 624a, an oxide The semiconductor layer 624b and the oxide semiconductor layer 624c are laminated in this order.

[0250] The oxide semiconductor layer 624a and the oxide semiconductor layer 624b are stacked over the insulating layer 603. The oxide semiconductor layer 624c is formed on a top surface of the oxide semiconductor layer 624b and on a pair of The electrodes 605a and 605b are provided in contact with the upper and side surfaces thereof.

[0251] For example, the oxide semiconductor layer 624b may be formed by using the oxide semiconductor The oxide semiconductor layer 614a may have a similar structure to that of the oxide semiconductor layer 614a. The oxide semiconductor layers 61 24 a and 624 c are the oxide semiconductor layers 61 A similar configuration to 4b can be used.

[0252] For example, the oxide semiconductor layer 624a provided under the oxide semiconductor layer 624b and the oxide semiconductor layer The oxide semiconductor layer 624c provided in the second insulating layer 624 has a Ga content functioning as a stabilizer. By using a large amount of oxide, the oxide semiconductor layer 624a, the oxide semiconductor layer 624b, and In addition, release of oxygen from the oxide semiconductor layer 624c can be suppressed.

[0253] In addition, when a channel is mainly formed in the oxide semiconductor layer 624b, for example, The conductor layer 624b is made of an oxide containing a large amount of In. By providing a pair of electrodes 605a and 605b, the on-current of the transistor 620 is increased. It can be done.

[0254] <Other examples of transistor configurations> A top-gate transistor to which the oxide semiconductor film of one embodiment of the present invention can be applied will be described below. A configuration example of the data recorder will be described below.

[0255] In the following, components having the same configuration or function as those described above will be referred to as the same. Each component will be given the same reference symbol, and duplicated explanations will be omitted.

[0256] FIG. 27A is a schematic cross-sectional view of a top-gate transistor 650, which will be described below. vinegar.

[0257] The transistor 650 is an oxide semiconductor provided on a substrate 601 on which an insulating layer 651 is provided. a pair of electrodes 605a and 605b in contact with an upper surface of the oxide semiconductor layer 604; an insulating layer 603 provided over an oxide semiconductor layer 604 and a pair of electrodes 605 a and 605 b; A gate electrode 602 is provided over the insulating layer 603 so as to overlap with the oxide semiconductor layer 604. In addition, an insulating layer 652 is provided to cover the insulating layer 603 and the gate electrode 602. do.

[0258] The insulating layer 651 has a function of suppressing diffusion of impurities from the substrate 601 to the oxide semiconductor layer 604. For example, the insulating layer 607 may have the same structure as the insulating layer 607. 651 does not have to be provided if it is not necessary.

[0259] The insulating layer 652 has a blocking effect against oxygen, hydrogen, water, etc., similar to the insulating layer 607. Note that the insulating layer 607 is not required if it is not necessary. stomach.

[0260] An example of the structure of a transistor that is partially different from the transistor 650 will be described below.

[0261] FIG. 27B is a schematic cross-sectional view of a transistor 660, which is described below. The transistor 660 differs from the transistor 650 in the structure of the oxide semiconductor layer.

[0262] The oxide semiconductor layer 664 in the transistor 660 includes an oxide semiconductor layer 664a, an oxide The semiconductor layer 664b and the oxide semiconductor layer 664c are stacked in this order.

[0263] Among the oxide semiconductor layer 664a, the oxide semiconductor layer 664b, and the oxide semiconductor layer 664c, The oxide semiconductor film described above may be used for any one, any two, or all of the above. This can be done.

[0264] For example, the oxide semiconductor layer 664b may be formed by using the oxide semiconductor The oxide semiconductor layer 614a may have a similar structure to that of the oxide semiconductor layer 614a. The oxide semiconductor layers 61 shown in the above <Modifications of Transistor> are used as the oxide semiconductor layers 61 A similar configuration to 4b can be used.

[0265] In addition, the oxide semiconductor layer 664a provided under the oxide semiconductor layer 664b and the oxide semiconductor layer The oxide semiconductor layer 664c to be provided has a high content of Ga functioning as a stabilizer. By using a thin oxide, the oxide semiconductor layer 664a, the oxide semiconductor layer 664b, and the oxide This can suppress the release of oxygen from the organic semiconductor layer 664c.

[0266] An example of the structure of a transistor that is partially different from the transistor 650 will be described below.

[0267] FIG. 27C is a schematic cross-sectional view of a transistor 670, which is described below. The shape of the pair of electrodes 605a and 605b in contact with the oxide semiconductor layer 604 and the gate The transistor 602 differs from the transistor 650 in terms of the shape of the port electrode 602 and the like.

[0268] The transistor 670 is an oxide semiconductor provided on a substrate 601 on which an insulating layer 651 is provided. a gate electrode on the insulating layer 603; 602, an insulating layer 654 over the insulating layer 651 and the oxide semiconductor layer 604, The insulating layer 654 and the oxide semiconductor layer 6 A pair of electrodes 605a and 605b electrically connected to the insulating layer 656 and the pair of electrodes and an insulating layer 652 on the poles 605a, 605b.

[0269] The insulating layer 654 is formed of, for example, an insulating film containing hydrogen. An example of the insulating layer 654 is a silicon nitride film. The oxygen vacancies in the oxide semiconductor layer 604 are bonded to the oxygen vacancies, and the oxygen vacancies in the oxide semiconductor layer 604 become carriers. In the structure shown in FIG. 27C, the oxide semiconductor layer 604 and the insulating layer 654 are in contact with each other. The regions corresponding to the n-type region 604b and the n-type region 604c are shown. The region between n-type region 604b and n-type region 604c becomes channel region 604a.

[0270] By providing n-type regions 604b and 604c in the oxide semiconductor layer 604, a pair of electrodes 60 The contact resistance between the n-type regions 604b and 605a can be reduced. As for 4c, when the gate electrode 602 is formed and when the insulating layer 654 covering the gate electrode 602 is formed, The transistor 670 shown in FIG. This is a so-called self-aligned top-gate transistor. By adopting a p-gate type transistor structure, there is no overlap between the gate electrode 602 and the pair of electrodes 605a and 605b that function as the source electrode and the drain electrode, so that the parasitic capacitance generated between the electrodes can be reduced. Also, since there is no overlap between the gate electrode 602 and the pair of electrodes 605a and 605b that function as the source electrode and the drain electrode, the parasitic capacitance generated between the electrodes can be reduced. The parasitic capacitance generated between the electrodes can be reduced.

[0271] In addition, as the insulating layer 656 included in the transistor 670, for example, it can be formed of a silicon oxynitride film or the like. It can be formed of, for example, a silicon oxynitride film or the like.

[0272] (Embodiment 7) In this embodiment, the OS transistor described in the above embodiment will be described.

[0273] <Characteristics of OS Transistor> The OS transistor can reduce the off-current by reducing the impurity concentration in the oxide semiconductor and making the oxide semiconductor intrinsic or substantially intrinsic. Here, substantially intrinsic means that the carrier density in the oxide semiconductor is less than 1×10 / cm 17 3 less than 1×10 1 5 / cm 3 less than 1×10 13 / cm 3 less than 1×10 3 less than 1×10 In the oxide semiconductor, hydrogen, nitrogen, carbon, silicon, and metal elements other than the main component are impurities. For example, hydrogen and nitrogen contribute to the formation of donor levels and increase the carrier density. For example, hydrogen and nitrogen contribute to the formation of donor levels and increase the carrier density. As a result, the carrier density increases.

[0274] Since the transistor using an intrinsic or substantially intrinsic oxide semiconductor has a low carrier density, it rarely has electrical characteristics in which the threshold voltage becomes negative. In addition, since the transistor using the oxide semiconductor has few carrier traps in the oxide semiconductor, the electrical characteristics Since the transistor using an intrinsic or substantially intrinsic oxide semiconductor has a low carrier density, it rarely has electrical characteristics in which the threshold voltage becomes negative. Also, since the transistor using the oxide semiconductor has few carrier traps in the oxide semiconductor, the electrical characteristics of the transistor using the oxide semiconductor are less affected by the carrier traps in the oxide semiconductor. In addition, a transistor using the oxide semiconductor can be obtained that has small fluctuations and is highly reliable. The transistor can have a very low off-state current.

[0275] In addition, an OS transistor with a low off-state current has a channel width of 1 μ Off-state current per m is 1×10 -18 Below A, 1×10 -21 A or less, or 1×10 -24 A or less, or 1 x 10 at 85°C -15 Below A, 1×10 -18 A or below, or 1×10 -21 It can be set to A or lower.

[0276] <Off-state current> In this specification, unless otherwise specified, the off-state current is the current that flows when a transistor is in an off state (non-conducting state). The drain current when the device is in the on or off state. In the absence of a gate-source resistor, the voltage Vgs between the gate and source of an n-channel transistor is equal to the threshold Below the voltage Vth, for a p-channel transistor, the voltage between the gate and source This refers to the state in which Vgs is higher than the threshold voltage Vth. For example, in the case of an n-channel transistor, The off-state current is the drain current when the gate-source voltage Vgs is lower than the threshold voltage Vth. This is sometimes referred to as in-current.

[0277] The off-state current of a transistor may depend on Vgs. The current is I or less if there is a Vgs value at which the off-state current of the transistor is I or less. The off-state current of a transistor is the off-state current at a given Vgs. Off-state at Vgs within a given range or sufficiently reduced off-current is obtained It may refer to the off-state current at Vgs, etc.

[0278] As an example, when the threshold voltage Vth is 0.5 V and Vgs is 0.5 V, the drain current is 1×10 -9 A, and the drain current at Vgs of 0.1 V is 1×10 -13 A The drain current at Vgs of -0.5V is 1×10 -19 A and Vgs is - Drain current at 0.8V is 1×10 -22 A n-channel transistor The drain current of the transistor is is 1×10 when Vgs is in the range of -0.5V to -0.8V. -19 Is it below A? Therefore, the off-current of the transistor is 1×10 -19 It may be said that it is below A. The drain current of the transistor is 1×10 -22 Since there exists a Vgs below A, The off-current of the transistor is 1×10 -22 It may be said that it is below A.

[0279] In this specification, the off-state current of a transistor having a channel width W is expressed as It may be expressed as the current value that flows. It may also be expressed as the current that flows per a given channel width (for example, 1 μm). In the latter case, the unit of the off-state current is a unit with the dimensions of current / length. It is sometimes expressed in units (e.g., A / μm).

[0280] The off-state current of a transistor may depend on temperature. Unless otherwise specified, the off-state current is measured at room temperature, 60℃, 85℃, 95℃, or 125℃. Or, the reliability of the semiconductor device containing the transistor may be in doubt. or the temperature at which a semiconductor device or the like that includes the transistor is used (for example, For example, the off-state current at any one of temperatures from 5°C to 35°C. The off-state current of the transistor is I or less at room temperature, 60°C, 85°C, 95°C, 125°C, The temperature at which the reliability of a semiconductor device including the transistor is guaranteed, or the temperature at which the transistor The temperature at which the semiconductor device or the like containing the stator is used (for example, any one of 5°C to 35°C) This indicates that there exists a value of Vgs at which the off-state current of the transistor at This may happen.

[0281] The off-state current of a transistor may depend on the voltage Vds between the drain and source. In this specification, unless otherwise specified, the off-state current is measured when Vds is 0.1 V, 0.8 V, 1 V, 1.2V, 1.8V, 2.5V, 3V, 3.3V, 10V, 12V, 16V, or It may represent the off-state current at 20 V. Or, the semiconductor including the transistor Vds that guarantees the reliability of devices, etc., or semiconductor devices that include the transistor The off-state current of a transistor may be expressed as the off-state current at the Vds used in the The current is less than I when Vds is 0.1V, 0.8V, 1V, 1.2V, 1.8V, 2 .5V, 3V, 3.3V, 10V, 12V, 16V, 20V, transistors included Vds that guarantees the reliability of the semiconductor device in which the transistor is included, or Vds used in the device, etc., Vg at which the off-state current of the transistor is I or less It may refer to the existence of a value of s.

[0282] In the above description of the off-state current, the drain may be read as the source. may also refer to the current that flows through the source when the transistor is in the off state.

[0283] In this specification, the term "leakage current" may be used to mean the same thing as the off-state current.

[0284] In this specification, the off-state current is, for example, the current that flows through a source when a transistor is in an off state. It can also refer to the current that flows between the source and drain.

[0285] <Composition of oxide semiconductor> The oxide semiconductor used for the semiconductor layer of the OS transistor is at least indium It is preferable that the compound contains In (In) or zinc (Zn). It is particularly preferable that the compound contains In and Zn. In addition, it is preferable to have a stabilizer that strongly binds oxygen. The stabilizers are gallium (Ga), tin (Sn), and zirconium (Zr). , hafnium (Hf), or aluminum (Al).

[0286] Other stabilizers include the lanthanides lanthanum (La) and cerium ( Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), hol Ho, Erbium, Thulium, Ytterbium, Ru The element may contain one or more of tetraethynyl ions (Te).

[0287] Examples of oxide semiconductors used for the semiconductor layer of a transistor include indium oxide and Tin, zinc oxide, In-Zn oxide, Sn-Zn oxide, Al-Zn oxide, Zn -Mg oxide, Sn-Mg oxide, In-Mg oxide, In-Ga oxide, In -Ga-Zn oxide (also written as IGZO), In-Al-Zn oxide, In-S n-Zn oxide, Sn-Ga-Zn oxide, Al-Ga-Zn oxide, Sn-Al -Zn oxide, In-Hf-Zn oxide, In-Zr-Zn oxide, In-Ti- Zn-based oxide, In-Sc-Zn-based oxide, In-Y-Zn-based oxide, In-La-Zn In-Ce-Zn oxide, In-Pr-Zn oxide, In-Nd-Zn oxide Oxide, In-Sm-Zn oxide, In-Eu-Zn oxide, In-Gd-Zn oxide oxides, In-Tb-Zn oxides, In-Dy-Zn oxides, In-Ho-Zn oxides In-Er-Zn oxides, In-Tm-Zn oxides, In-Yb-Zn oxides , In-Lu-Zn ​​oxide, In-Sn-Ga-Zn oxide, In-Hf-Ga-Z n-based oxides, In-Al-Ga-Zn-based oxides, In-Sn-Al-Zn-based oxides, In -Sn-Hf-Zn oxide, In-Hf-Al-Zn oxide, etc.

[0288] For example, In:Ga:Zn=1:1:1, In:Ga:Zn=3:1:2, or In In-Ga-Zn oxides with an atomic ratio of Ga:Zn=2:1:3 and oxides with similar compositions In particular, the atomic ratio of In:Ga:Zn=4:2:3 or close thereto is recommended. It is recommended to use In-Ga-Zn oxide of In:Ga:Zn=4:2:3 or similar. In order to obtain an In-Ga-Zn oxide with an atomic ratio close to In:Ga:Zn=4: An oxide semiconductor film is formed using a 2:4.1 target.

[0289] <Impurities in oxide semiconductors> When hydrogen is contained in the oxide semiconductor film that constitutes the semiconductor layer, it bonds with the oxide semiconductor. As a result, some of the hydrogen atoms become donors, generating electrons that act as carriers. The threshold voltage of the transistor is shifted in the negative direction. After the formation of the oxide semiconductor film, dehydration treatment (dehydrogenation treatment) is performed to remove hydrogen or It is preferable to remove moisture and purify the material to minimize the amount of impurities contained therein.

[0290] Note that the dehydration treatment (dehydrogenation treatment) of the oxide semiconductor film causes the oxide semiconductor film to lose its oxygen. Therefore, the oxide semiconductor film is preferably subjected to a dehydration treatment (dehydrogenation treatment) In order to compensate for oxygen vacancies increased by the above-mentioned treatment, oxygen is added to the oxide semiconductor film. is preferred.

[0291] In this manner, hydrogen or moisture is removed from the oxide semiconductor film by the dehydration treatment (dehydrogenation treatment). By adding oxygen to compensate for the oxygen deficiency, the material becomes i-type (intrinsic) or i-type. In this case, the oxide semiconductor film can be substantially i-type (intrinsic).

[0292] <Structure of oxide semiconductor> The structure of an oxide semiconductor will be described.

[0293] In this specification, "parallel" means that two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it includes the case where the angle is between -5° and 5°. "Approximately parallel" refers to a state in which two straight lines are arranged at an angle of -30° or more and 30° or less. Also, "perpendicular" means that two straight lines are arranged at an angle of 80° to 100°. Therefore, it also includes the case where the angle is between 85° and 95°. This refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0294] In addition, in this specification, when the crystal is a trigonal or rhombohedral crystal, it is represented as a hexagonal crystal system. .

[0295] Oxide semiconductor films are classified into non-single-crystal oxide semiconductor films and single-crystal oxide semiconductor films. Alternatively, oxide semiconductors are divided into, for example, crystalline oxide semiconductors and amorphous oxide semiconductors. do.

[0296] As the non-single-crystal oxide semiconductor, CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor, polycrystalline oxide Semiconductors made of crystalline oxides include semiconductors made of microcrystalline oxides and amorphous oxides. The materials include single-crystal oxide semiconductors, CAAC-OS, polycrystalline oxide semiconductors, and microcrystalline oxides. Semiconductors, etc.

[0297] First, we will explain the CAAC-OS film.

[0298] The CAAC-OS film is one of oxide semiconductor films having a plurality of crystal parts aligned along the c-axis.

[0299] Transmission Electron Microscope (TEM) A bright-field image and a combined diffraction pattern of the CAAC-OS film were obtained by using a microscope. By observing the TEM image, multiple crystalline regions can be confirmed. On the other hand, the high-resolution TEM image also shows clear boundaries between crystals, i.e., grain boundaries. Therefore, the CAAC-OS film is It can be said that the decrease in electron mobility caused by grain boundaries is unlikely to occur.

[0300] When a high-resolution TEM image of the cross section of the CAAC-OS film was observed from a direction approximately parallel to the sample surface, It can be seen that the metal atoms are arranged in layers in the crystal part. Each layer of metal atoms is The CAAC-OS film is formed on the surface (also called the surface on which the film is formed) or on the upper surface. The CAAC-OS film has a shape similar to that of the crystalline silicon film, and is aligned parallel to the surface on which the CAAC-OS film is formed or the upper surface.

[0301] On the other hand, a high-resolution TEM image of the plane of the CAAC-OS film was observed from a direction approximately perpendicular to the sample surface. It was confirmed that the metal atoms in the crystals were arranged in triangular or hexagonal shapes. However, there is no regularity in the arrangement of metal atoms between different crystal parts.

[0302] X-ray diffraction (XRD) was performed on the CAAC-OS film. For example, a CAAC-OS film with InGaZnO4 crystals was In the out-of-plane analysis, a peak was observed at a diffraction angle (2θ) of approximately 31°. This peak is attributed to the (009) plane of the InGaZnO4 crystal. From this, it can be seen that the crystals of the CAAC-OS film have a c-axis orientation, and the c-axis is approximately aligned on the surface on which the film is formed or on the upper surface. You can see that it is oriented vertically.

[0303] In addition, the out-of-plane method of CAAC-OS film with InGaZnO4 crystals In the analysis by , in addition to the peak at 2θ near 31°, a peak also appeared at 2θ near 36°. The peak at 2θ of around 36° may be due to the c-axis orientation in some parts of the CAAC-OS film. The CAAC-OS film contains crystals that do not have a 2θ of around 31°. It is preferred that the spectrum exhibits a peak and does not exhibit a peak at 2θ of around 36°.

[0304] The CAAC-OS film is an oxide semiconductor film with a low concentration of impurities. The impurities include hydrogen, carbon, and The elements are other than the main components of the oxide semiconductor film, such as silicon and transition metal elements. The elements that bond to oxygen more strongly than the metal elements that form the oxide semiconductor film, such as arsenic, are oxidized. By removing oxygen from the oxide semiconductor film, the atomic arrangement of the oxide semiconductor film is disrupted, reducing its crystallinity. In addition, heavy metals such as iron and nickel, argon, and carbon dioxide have an atomic radius of Since the molecular radius is large, when the cation is contained in the oxide semiconductor film, the The impurities in the oxide semiconductor film may cause the atomic arrangement to be disturbed, which may result in a decrease in crystallinity. Objects can act as carrier traps or carrier generation sources.

[0305] The CAAC-OS film is an oxide semiconductor film having a low density of defect states. Oxygen vacancies in the semiconductor film can become carrier traps or trap hydrogen, It can be a carrier source.

[0306] A material with a low impurity concentration and a low defect level density (few oxygen vacancies) is called a high-purity intrinsic or The term "substantially high-purity intrinsic" refers to a highly-purified intrinsic oxide semiconductor film. Since there are fewer carrier generation sources, the carrier density can be reduced. The transistor using the oxide semiconductor film has electrical characteristics in which the threshold voltage is negative ( Also called marion.) It is rare for it to become high purity genuine or substantially high purity genuine. The oxide semiconductor film has few carrier traps. A transistor using such a material has small fluctuation in electrical characteristics and is highly reliable. Note that it takes a long time for charges trapped in the carrier traps in the oxide semiconductor film to be released. The charge is long and can behave like a fixed charge. In addition, a transistor using an oxide semiconductor film having a high density of defect states has unstable electrical characteristics. There are cases.

[0307] In addition, the electrical characteristics of transistors using CAAC-OS films were improved by irradiation with visible light or ultraviolet light. The fluctuation is small.

[0308] Next, a microcrystalline oxide semiconductor film will be described.

[0309] The microcrystalline oxide semiconductor film has a region where crystals can be confirmed in a high-resolution TEM image. The microcrystalline oxide semiconductor film has a crystal structure including a region where a crystal part is not clearly observed and a region where a crystal part is not clearly observed. The crystal part contained in the crystal has a size of 1 nm to 100 nm or 1 nm to 10 nm. In particular, the fineness is often between 1 nm and 10 nm, or between 1 nm and 3 nm. The oxide semiconductor film having nanocrystals (nc) is called nc -OS(nanocrystalline oxide semiconductor) In the nc-OS film, for example, the grain boundaries are clearly identified in high-resolution TEM images. It may not be possible to recognize

[0310] The nc-OS film is a microscopic region (e.g., a region of 1 nm to 10 nm, especially a region of 1 nm or more). The atomic arrangement has periodicity in the region of 3 nm or less. There is no regularity in the crystal orientation between the crystal parts. Therefore, no orientation is observed throughout the film. Therefore, the nc-OS film cannot be distinguished from an amorphous oxide semiconductor film depending on the analysis method. For example, X-ray diffraction (XR) is used to measure the nc-OS film using X-rays with a diameter larger than that of the crystals. When structural analysis was performed using the D instrument, the crystal plane In addition, the peaks indicating the probe size were not detected in the nc-OS film. Electron diffraction (also called selected area electron diffraction) using an electron beam with a diameter (for example, 50 nm or more) When the diffraction pattern is changed to 0.05μm, a halo-like diffraction pattern is observed. Nano-beam electrons are used, which use an electron beam with a probe diameter close to or smaller than the size of the crystal part. When diffraction is performed, spots are observed. When this is done, a circular (ring-shaped) area of ​​high brightness may be observed. Nanobeam electron diffraction of the nc-OS film revealed multiple spots within the ring-shaped region. It may be observed.

[0311] The nc-OS film is an oxide semiconductor film that has higher order than an amorphous oxide semiconductor film. Therefore, the nc-OS film has a lower density of defect states than the amorphous oxide semiconductor film. In the nc-OS film, there is no regularity in the crystal orientation between different crystal parts. The S film has a higher density of defect states than the CAAC-OS film.

[0312] Next, the amorphous oxide semiconductor film will be described.

[0313] The amorphous oxide semiconductor film is an oxide semiconductor film in which the atomic arrangement in the film is irregular and does not have a crystal part. An example is an oxide semiconductor film that has an amorphous state, such as quartz.

[0314] In the amorphous oxide semiconductor film, no crystalline parts can be confirmed in a high-resolution TEM image.

[0315] When the structure of the amorphous oxide semiconductor film is analyzed using an XRD device, out-of-p In the lane analysis, no peaks indicating crystal planes were detected. When electron diffraction is performed on a conductive film, a halo pattern is observed. When nanobeam electron diffraction is performed on a conductive film, no spots are observed, and a halo pattern is observed. Observed.

[0316] Note that the oxide semiconductor film has a structure that exhibits physical properties between the nc-OS film and the amorphous oxide semiconductor film. An oxide semiconductor film having such a structure may have a structure such as the following. Amorphous-like Oxide Semiconductor (a-like OS) The conductor membrane is called the endothelium.

[0317] In the a-like OS film, voids are observed in the high-resolution TEM image. In addition, crystals may be clearly visible in high-resolution TEM images. The a-like OS film has a region in which a crystal part is not observed and a region in which a crystal part is not observed. Crystallization occurs due to the small amount of electron irradiation, which is the level observed in TEM observations, and the growth of the crystals can be seen. On the other hand, if the nc-OS film is of good quality, the small amount of charge observed by TEM can be observed. Almost no crystallization due to electron irradiation was observed.

[0318] The size of the crystals in the a-like OS film and the nc-OS film was measured using a high-resolution T This can be done using EM images. For example, InGaZnO4 crystals have a layered structure, There are two Ga-Zn-O layers between the In-O layers. Unit cell of the InGaZnO4 crystal The layer has three In-O layers and six Ga-Zn-O layers, for a total of nine layers aligned in the c-axis direction. The spacing between adjacent layers is therefore the (009) plane. This is approximately the same as the lattice spacing (also called the d value), and crystal structure analysis has determined that this value is 0.29 nm Therefore, we focused on the lattice fringes in high-resolution TEM images and In the region where the distance is between 0.28 nm and 0.30 nm, the lattice fringes are InG aIt corresponds to the ab plane of the ZnO4 crystal.

[0319] In addition, the density of an oxide semiconductor film may differ depending on the structure. If the composition of the membrane is known, the density can be determined by comparing it with that of a single crystal of the same composition. The structure of the oxide semiconductor film can be estimated. The density of the OS-like film is 78.6% or more and less than 92.3%. The density of the nc-OS film and the CAAC-OS film was 92.3% or more. Note that an oxide semiconductor film having a density of less than 78% of the density of a single crystal is The film formation itself is difficult.

[0320] The above will be explained using a specific example. For example, In:Ga:Zn=1:1:1 [atomic In the oxide semiconductor film that satisfies the ratio of the number of ZnO atoms to the number of ZnO atoms, single crystal InGaZnO4 with a rhombohedral crystal structure is The density of is 6.357g / cm3 Therefore, for example, In:Ga:Zn=1:1:1 In the oxide semiconductor film that satisfies the atomic ratio, the density of the a-like OS film is 5.0 g / cm 3 More than 5.9g / cm 3 For example, In:Ga:Zn=1:1: In the oxide semiconductor film that satisfies the atomic ratio of 1, the density of the nc-OS film and the CAAC- The density of the OS film is 5.9 g / cm 3 More than 6.3g / cm 3 It will be less than.

[0321] In addition, there are cases where single crystals with the same composition do not exist. In such cases, the composition may differ in any ratio. By combining single crystals, it is possible to calculate the density equivalent to a single crystal of the desired composition. The density of a single crystal of a desired composition can be determined by the ratio of the single crystals of different compositions. However, the density should be calculated using as few types of single crystals as possible. It is preferable to perform the calculation in combination.

[0322] Note that the oxide semiconductor film may be, for example, an amorphous oxide semiconductor film, an a-like OS film, or a microcrystalline oxide semiconductor film. The semiconductor layer may be a stacked film including two or more of a crystalline oxide semiconductor film and a CAAC-OS film.

[0323] As described above, the OS transistor can achieve extremely excellent off-state current characteristics.

[0324] (Embodiment 8) In this embodiment, a display module to which the semiconductor device described in the above embodiment is applied is The semiconductor device is, for example, a gate driver circuit section or a source The display module can be applied to a part of the display driver circuit or the pixel section. This will be described below with reference to FIG. 28 and FIG. 29.

[0325] <Top view of display module> FIG. 28 is a top view showing an example of a display module. The display module 700 shown in FIG. The pixel portion 702 is provided on the first substrate 701, and the semiconductor device 702 is provided on the first substrate 701. A source driver circuit section 704 and a gate driver circuit section 706, a pixel section 702, a source driver circuit section 706, and a gate driver circuit section 706. A sealant is disposed to surround the gate driver circuit section 704 and the gate driver circuit section 706. 712 and a second substrate 705 provided so as to face the first substrate 701. The first substrate 701 and the second substrate 705 are sealed with a sealant 712. That is, the pixel section 702, the source driver circuit section 704, and the gate driver circuit section 706 is sealed by a first substrate 701, a sealant 712, and a second substrate 705. Although not shown in FIG. 28, a display is provided between the first substrate 701 and the second substrate 705. An element is provided.

[0326] The display module 700 is surrounded by a sealant 712 on the first substrate 701. The pixel section 702, the source driver circuit section 704, and the gate driver circuit section 705 are arranged in a region different from the region where the pixel is located. The driver circuit portion 706 and the FPC terminal portion 708 (FPC: Flexible Printed Circuit) electrically connected to each other. In addition, the FPC terminal portion 70 is provided with a flexible printed circuit. 8, an FPC 716 is connected to the pixel section 702, the source driver Various signals and the like are supplied to the circuit portion 704 and the gate driver circuit portion 706. 702, a source driver circuit section 704, a gate driver circuit section 706, and an FPC terminal Signal lines 710 are connected to the respective units 708. Signals and the like are transmitted through a signal line 710 to the pixel section 702, the source driver circuit section 704, the gate It is provided to a driver circuit section 706 and an FPC terminal section 708 .

[0327] In addition, the display module 700 may be provided with a plurality of gate driver circuits 706. The display module 700 includes a source driver circuit section 704 and a gate driver circuit section In the example shown, the pixel portion 702 and the pixel portion 706 are formed on the same first substrate 701. For example, only the gate driver circuit section 706 may be formed on the first substrate 701. Alternatively, only the source driver circuit section 704 may be formed on the first substrate 701. In this case, the substrate on which the source driver circuit or the gate driver circuit is formed (e.g. For example, a driving circuit board formed of a single crystal semiconductor film or a polycrystalline semiconductor film is placed on the first substrate 70. The method of connecting the separately formed drive circuit board is not particularly limited. The method is not specified, and may be COG (Chip On Glass) or wire bonding. A method such as a tagging method can be used.

[0328] The display module 700 includes a pixel portion 702, a source driver circuit portion 704, and a gate driver circuit portion 705. The gate driver circuit section 706 includes a plurality of transistors. The transistor described in the above embodiment can be used as the gate electrode.

[0329] The display module 700 can also include various elements, such as: Liquid crystal elements, EL (electroluminescence) elements (EL elements containing organic and inorganic materials, Organic EL elements, inorganic EL elements), LEDs (white LEDs, red LEDs, green LEDs, blue LEDs ED, etc.), transistors (transistors that emit light according to the current), electron emitters, electron Ink, electrophoretic element, grating light valve (GLV), plasma display Using panels (PDP) and MEMS (Micro-Electro-Mechanical Systems) Display element, Digital Micromirror Device (DMD), DMS (Digital Micromirror Device) Shutter), IMOD (Interference Modulation) element, Shutter MEMS display element using the optical interference method, MEMS display element using the optical interference method, electrowetting element display elements using carbon nanotubes, piezoelectric ceramic displays, etc. In addition to these, contrast can also be achieved by electrical or magnetic effects. The display medium may have a variable brightness, reflectance, transmittance, etc. An example of a display device is an EL display. One example is a field emission display (FED) or SED type flat panel display. Display (SED: Surface-conduction Electron-e Examples of display devices using liquid crystal elements include the LCD (Light Emitting Diode) and the LCD (Light Emitting Diode). , LCD (transmissive LCD, semi-transmissive LCD, reflective LCD) LCDs include LCDs, direct-view LCDs, and projection LCDs. An example of a display device using ink or electrophoretic elements is electronic paper. In order to realize a semi-transmissive liquid crystal display or a reflective liquid crystal display, the pixel electrodes A part or the whole of the pixel may function as a reflective electrode. A part or the whole of the electrodes may be made of aluminum, silver, or the like. In this case, it is also possible to provide a memory circuit such as an SRAM under the reflective electrode. This makes it possible to further reduce power consumption. A configuration in which liquid crystal elements are used as display elements will be described below.

[0330] The display method of the display module 700 may be a progressive method or an interlace method. In addition, the color elements controlled by pixels when displaying colors are , RGB (R stands for red, G stands for green, B stands for blue) are not limited to three colors. For example, R pixel and It may be made up of four pixels: a G pixel, a B pixel, and a W (white) pixel. Like the pixel array, one color element is made up of two colors of RGB, and different colors are Alternatively, yellow, cyan, magenta, etc. may be added to the RGB. You can add more than one color. Note that the size of the display area for each dot of the color element is different. However, the disclosed invention is not limited to color display devices, and may be used in monolithic display devices. It can also be applied to a display device with a black display.

[0331] In addition, the backlight (organic EL element, inorganic EL element, LED, fluorescent lamp, etc.) is white light (W In order to make a display device display full color, a colored layer (also called a color filter) is used. The colored layer may be, for example, red (R), green (G), blue (B), Yellow (Y) and other colors can be used in combination. The color reproducibility can be improved compared to when no color layer is used. By disposing a region having a colored layer and a region not having a colored layer, The white light from the colored layer may be directly used for display. This reduces the decrease in brightness caused by the colored layer during bright display, reducing power consumption by 20%. However, it may be possible to reduce the light emission by about 30% when using self-luminous elements such as organic EL elements and inorganic EL elements. When using a full-color display, R, G, B, Y, and white (W) are generated by It is also possible to emit light from an element having a certain color. In this embodiment, the power consumption can be further reduced. The following describes a configuration that does not include a backlight, i.e., a so-called reflective liquid crystal display module. Do the following.

[0332] <Cross-section of display module> FIG. 29 shows a cross-sectional view taken along the dashed line QR in FIG. 28. The details of the rule are explained below.

[0333] The display module 700 shown in FIG. 29 includes a wiring section 711, a pixel section 702, and a The wiring section 702 includes a driver circuit section 704 and an FPC terminal section 708. 11 includes a signal line 710. The pixel portion 702 includes a transistor 750 and a capacitor. The source driver circuit portion 704 also includes a transistor 752. .

[0334] The transistors 750 and 752 can be the transistors shown above. Cut.

[0335] The transistor used in this embodiment is a highly purified oxide semiconductor in which the formation of oxygen vacancies is suppressed. The transistor has a conductive film, and the current value in the off state (off-state current value) is reduced. Therefore, the retention time of electrical signals such as image signals can be extended, and the power can be turned off. In the ON state, the write interval can be set longer. This reduces the frequency of refresh operations. This has the effect of reducing power consumption.

[0336] In addition, the transistor used in this embodiment has a relatively high field-effect mobility. For example, a transistor capable of high speed driving is used in a display device. By using this, the switching transistor in the pixel section and the driver used in the driver circuit section can be The transistors can be formed on the same substrate. Since there is no need to use semiconductor devices formed from silicon wafers, etc., The number of points can be reduced. Also, in the pixel area, transistors that can be driven at high speed can be used. By using this, high quality images can be provided.

[0337] The capacitor 790 has a structure having a dielectric between a pair of electrodes. One electrode of the transistor 790 is a conductive film that functions as a gate electrode of the transistor 750. The other electrode of the capacitor 790 is formed using a conductive film formed in the same process. A conductive film is used to function as the source electrode and the drain electrode of the capacitor 750. The dielectric sandwiched between the electrodes is an insulating film that functions as a gate insulating film of the transistor 750. Use the velum.

[0338] 29, a transistor 750, a transistor 752, and a capacitor 790 Over the top of this, insulating films 764 and 768 and a planarizing insulating film 770 are provided.

[0339] The insulating film 764 is, for example, a silicon oxide film, a silicon oxynitride film, or the like, which is formed by using a PECVD apparatus. The insulating film 768 may be formed by, for example, a PECVD apparatus. A silicon nitride film or the like may be formed using the planarization insulating film 770. Imide resin, acrylic resin, polyimide amide resin, benzocyclobutene resin, polyamide Organic materials having heat resistance, such as olefin resin and epoxy resin, can be used. The planarization insulating film 770 may be formed by stacking a plurality of insulating films made of the above material. The planarization insulating film 770 does not necessarily have to be provided.

[0340] The signal line 710 serves as the source and drain electrodes of the transistors 750 and 752. The signal line 710 is formed in the same process as the conductive film that functions as the transistor 750. 752, a conductive film formed in a process different from the source electrode and drain electrode, e.g., a gate The conductive film may be formed in the same process as the conductive film that functions as the electrode. For example, when a material containing copper is used, signal delays caused by wiring resistance are reduced. , making it possible to display on a large screen.

[0341] The FPC terminal portion 708 includes a connection electrode 760, an anisotropic conductive film 780, and an FPC 716. The connection electrode 760 is connected to the source and drain electrodes of the transistors 750 and 752. The connection electrode 760 is formed in the same process as the conductive film that functions as the FPC. It is electrically connected to a terminal of C716 via an anisotropic conductive film 780.

[0342] The first substrate 701 and the second substrate 705 may be, for example, a glass substrate. In addition, the first substrate 701 and the second substrate 705 may be flexible substrates. The flexible substrate may be, for example, a plastic substrate. .

[0343] In addition, a structure 778 is provided between the first substrate 701 and the second substrate 705. The body 778 is a columnar spacer obtained by selectively etching an insulating film. The distance (cell gap) between the first substrate 701 and the second substrate 705 is controlled by a In addition, a spherical spacer may be used as the structure 778. In the embodiment, the structure 778 is provided on the first substrate 701 side. For example, a structure 778 may be provided on the second substrate 705 side. A structure in which the structures 778 are provided on both the first substrate 701 and the second substrate 705 may be used.

[0344] In addition, on the second substrate 705 side, a light-shielding film 738 functioning as a black matrix and a A colored film 736 which functions as a color filter, a light-shielding film 738 and an insulating film which is in contact with the colored film 736 are provided. A veneer 734 is provided.

[0345] The cross-sectional view of a display module 700 shown as an example in FIG. The liquid crystal element 775 includes a conductive film 772, a conductive film 774, and a liquid crystal layer 776. The liquid crystal material 76 has a dielectric constant anisotropy of 2 or more and 3.8 or less, as described above. The conductive film 774 is provided on the second substrate 705 side and functions as a counter electrode. The display module 700 shown in FIG. 29 is a display module in which a voltage is applied to a conductive film 772 and a conductive film 774. By changing the orientation state of the liquid crystal layer 776, the transmission or non-transmission of light is controlled, and an image is displayed. It can be displayed.

[0346] The conductive film 772 serves as a source electrode and a drain electrode of the transistor 750. The conductive film 772 is formed on the planarization insulating film 770. The conductive film 772 functions as a reflective electrode, that is, one of the electrodes of the display element. The display module 700 shown in FIG. The light is reflected by the colored film 736 and displayed on the screen. .

[0347] The conductive film 772 may be a conductive film that transmits visible light or a conductive film that reflects visible light. A conductive film having a light-transmitting property in visible light can be used. For example, a material containing one selected from indium (In), zinc (Zn), and tin (Sn) As a conductive film having a reflectivity in visible light, for example, aluminum, Alternatively, a material containing silver may be used. In this embodiment, the conductive film 772 may be a A conductive film that is reflective in visible light is used.

[0348] In addition, when a conductive film that is reflective to visible light is used as the conductive film 772, the conductive film For example, an aluminum film having a thickness of 100 nm may be formed as a lower layer, and A 30 nm thick silver alloy film (e.g., an alloy film containing silver, palladium, and copper) is formed on the layer. The above-mentioned structure provides the following excellent effects.

[0349] (1) The adhesiveness between the base film and the conductive film 772 can be improved. (2) By using a chemical solution, It is possible to etch the aluminum film and the silver alloy film at the same time. (3) Conductivity The cross-sectional shape of the membrane 772 can be made to have a good shape (for example, a tapered shape). (3) The reason is that the etching rate of the aluminum film by the chemical solution is slower than that of the silver alloy film. Or, when the lower aluminum film is exposed after etching the upper silver alloy film, the silver alloy The electrons are drawn from aluminum, which is a metal that is less noble than the membrane, in other words, has a high ionization tendency. Therefore, etching of the silver alloy film is suppressed and etching of the underlying aluminum film progresses. This is because the journey will be faster.

[0350] In the display module 700 shown in FIG. The unevenness is formed, for example, by forming the planarization insulating film 770 with an organic resin film. The organic resin film is formed of a material such as a resin, and the surface of the organic resin film is provided with irregularities. The conductive film 772, which functions as a reflective electrode, is formed along the above-mentioned unevenness. When light enters the conductive film 772, the light may be diffusely reflected on the surface of the conductive film 772. As shown in Figure 29, a reflective color LCD By using it as a display device, it is possible to display without using a backlight, so the power consumption is The force can be reduced.

[0351] The display module 700 shown in FIG. 29 is a reflective color liquid crystal display module. For example, the conductive film 772 may be a transparent film that transmits visible light. By using a conductive film, a transmissive color liquid crystal display module can be formed. In the case of a liquid crystal display module, the unevenness provided on the planarization insulating film 770 is not provided. Alternatively, a different configuration may be used.

[0352] Although not shown in FIG. 29, the conductive films 772 and 774 are provided on the side in contact with the liquid crystal layer 776. Although not shown in FIG. Optical members (optical substrates) such as a member, a phase difference member, and an anti-reflection member may be provided as appropriate. For example, circular polarization using a polarizing substrate and a retardation substrate may be used. In the case of a module or a transflective display module, a backlight, sidelight, etc. are used as a light source. A gate or the like may also be provided.

[0353] Liquid crystal elements include thermotropic liquid crystal, low molecular weight liquid crystal, polymer liquid crystal, and polymer dispersed liquid crystal. The liquid crystal material may be a ferroelectric liquid crystal, an antiferroelectric liquid crystal, or the like. Therefore, cholesteric phase, smectic phase, cubic phase, chiral nematic phase, etc. Shows dimensions etc.

[0354] In addition, when the in-plane switching system is adopted, liquid crystal that exhibits a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases. When the temperature of a cholesteric liquid crystal is increased, the cholesteric The blue phase appears just before the transition from the crystalline phase to the isotropic phase. In order to improve the temperature range, a liquid crystal composition containing a chiral agent of several weight percent or more is used. The liquid crystal composition containing the liquid crystal exhibiting the blue phase and the chiral agent is used in the liquid crystal layer. It has a short response time, is optically isotropic so no alignment treatment is required, and has little viewing angle dependency. In addition, since there is no need to provide an alignment film, rubbing treatment is also unnecessary. It is possible to prevent electrostatic damage caused by the electrostatic discharge, and to prevent defects in the liquid crystal display device during the manufacturing process. and damage can be reduced.

[0355] When liquid crystal elements are used as display elements, TN (Twisted Nematic) mode, IPS (In-Plane-Switching) mode, FFS (Fring e Field Switching) mode, ASM (Axially Symmet ric aligned Micro-cell) mode, OCB (Optical C ompensated birefringence mode, FLC (Ferroel etric Liquid Crystal) mode, AFLC (AntiFerro You can use modes such as electric Liquid Crystal.

[0356] In addition, normally black type liquid crystal display devices, such as those using a vertical alignment (VA) mode, The liquid crystal display device may be a transmission type liquid crystal display device. There are several types of vertical alignment modes, including: For example, MVA (Multi-Domain Vertical Alignment) mode, PVA (Patterned Vertical Alignment) mode , ASV mode, etc. can be used.

[0357] (Embodiment 9) In this embodiment, a touch sensor ( By providing a touch detection device, it functions as an input / output device (also called a touch panel). A configuration that can achieve the above will be described with reference to Figs. 30 and 31. Descriptions of parts that overlap with the embodiment may be omitted.

[0358] FIG. 30 is a projection diagram for explaining the configuration of the input / output device.

[0359] FIG. 30(A) is a projection view of the input / output device 800, and FIG. 30(B) is a projection view of the input / output device 800. 13 is a projection diagram illustrating the configuration of a detection unit 820U provided. FIG.

[0360] FIG. 31 is a cross-sectional view of the input / output device 800 shown in FIG. 30(A) taken along the line Z1-Z2.

[0361] The input / output device 800 described in this embodiment has a window 834 that transmits visible light, and A plurality of detection units 820U are arranged in a matrix. ) and a scanning line G1 electrically connected to a plurality of detection units 820U arranged in a row direction (FIG. A signal line electrically connecting the detection units 820U arranged in the detection unit 820U (indicated by arrow Ry in FIG. 1) line DL, and a first supporting the detection unit 820U, the scanning line G1, and the signal line DL. An input device 850 having a base material 836 and a matrix-shaped arrangement overlapping the window portion 834. A display module including a plurality of pixels 802 and a second substrate 810 supporting the pixels 802. 801 (see FIG. 30(A) to FIG. 30(C)).

[0362] The detection unit 820U is electrically connected to the detection element Ca that overlaps the window portion 834 and the detection element Ca. (See FIG. 30B).

[0363] The sensing element Ca has an insulating layer 823 and an insulating layer 823 (not shown in FIG. 30(B)). It includes a first electrode 821 and a second electrode 822 (see FIG. 30(B)).

[0364] The detection circuit 839 is supplied with a selection signal and generates a detection signal based on a change in the capacitance of the detection element Ca. Supply the number DATA.

[0365] The scanning line G1 can supply a selection signal, and the signal line DL supplies a detection signal DATA. The detection circuit 839 is disposed so as to overlap the gaps between the windows 834. .

[0366] The input / output device 800 described in this embodiment includes a detection unit 820U and a detection unit A colored layer is provided between the window portion 834 of the unit 820U and the pixel 802 that overlaps it.

[0367] The input / output device 800 described in this embodiment is a detector having a window 834 that transmits visible light. An input device 850 having a plurality of sensing units 820U and a pixel 802 overlapping a window portion 834 are overlapped. A display module 801 including a plurality of pixels 802 and a color layer between the window portion 834 and the pixel 802. It is composed of:

[0368] In this way, the input / output device receives a detection signal based on the change in capacitance and a detection unit that supplies the detection signal. and providing position information of the sensing unit, and image information associated with the position information of the sensing unit. As a result, a novel input / output device with excellent convenience and reliability can be provided. can be provided.

[0369] The input / output device 800 is also a flexible board that receives signals from the input device 850. A flexible printed circuit board (FPC) 1 or / and a flexible printed circuit board (FPC) 2 that supplies a signal including image information to the display module 801 It may also include a flexible substrate FPC2.

[0370] In addition, a protective substrate 837 and a protective layer 837p are provided to protect the input / output device 800 by preventing scratches. Or / and the input / output device 800 is provided with an anti-reflection layer 867p that reduces the intensity of reflected external light. It is also possible to do so.

[0371] The input / output device 800 also includes a scanning line for supplying a selection signal to the scanning line of the display module 801. The driving circuit 803g, the wiring 811 for supplying signals, and the flexible substrate FPC2 are electrically The input terminal 819 is connected to the

[0372] The individual elements constituting the input / output device 800 will be described below. are not clearly separable, and one component may also be part of another. For example, the input device 850 having a colored layer at a position overlapping the multiple window portions 834 is The device 850 is also a color filter.

[0373] The input / output device 800 includes an input device 850 and a display module 801 (see FIG. 30). See A).

[0374] The input device 850 supports a plurality of detection units 820U and A first substrate 836 is provided. For example, a plurality of detection units are arranged in a matrix of 40 rows and 15 columns. 820U is disposed on a first substrate 836.

[0375] The window 834 transmits visible light.

[0376] A colored layer that transmits light of a predetermined color is provided at a position overlapping the window portion 834. For example, A transparent colored layer CFB, a green light transparent colored layer CFG or a red light transparent colored layer It has a layer CFR (see FIG. 30(B)).

[0377] In addition to blue, green and / or red, a colored layer that transmits white light or a yellow Colored layers that transmit light of various colors may be provided.

[0378] The colored layer may contain a metal material, a pigment, a dye, or the like.

[0379] A light-shielding layer BM is provided so as to surround the window portion 834. The light-shielding layer BM prevents light from passing through the window portion 834. Hard to penetrate.

[0380] Carbon black, metal oxides, and composite oxides including solid solutions of multiple metal oxides are used as light-shielding materials. It can be used for the layer BM.

[0381] At positions overlapping the light-shielding layer BM, the scanning line G1, the signal line DL, the wiring VPI, the wiring RES, and A wiring VRES and a detection circuit 839 are provided.

[0382] In addition, a light-transmitting overcoat layer that covers the colored layer and the light-shielding layer BM may be provided. do.

[0383] The sensing element Ca has a first electrode 821, a second electrode 822, and a pair of electrodes An insulating layer 823 is provided between the electrodes 822 (see FIG. 31).

[0384] The first electrode 821 is formed, for example, in an island shape so as to be separated from other regions. The first electrode 821 and the second electrode 822 are connected to each other so that the first electrode 821 cannot be identified by a user of the output device 800. A configuration in which a layer that can be fabricated in the same process is disposed adjacent to the first electrode 821 is preferred. More preferably, the first electrode 821 and a layer disposed adjacent to the first electrode 821 It is preferable to minimize the number of windows 834 arranged in the gap. A configuration in which 834 is not placed is preferable.

[0385] For example, the first electrode 821 or the second electrode 822 of the sensing element Ca placed in the air is When something with a dielectric constant different from that of the air approaches, the capacitance of the sensing element Ca changes. When a finger or other object approaches the sensing element Ca, the capacitance of the sensing element Ca changes. This means that it can be used as a proximity detector.

[0386] The first electrode 821 and the second electrode 822 include a conductive material.

[0387] For example, inorganic conductive materials, organic conductive materials, metals, conductive ceramics, etc. It can be used for the electrode 821 and the second electrode 822.

[0388] Specifically, the first electrode 821 and the second electrode 822 are made of aluminum, chromium, copper, etc. , tantalum, titanium, molybdenum, tungsten, nickel, silver or manganese The metal elements, alloys containing the above-mentioned metal elements, or combinations of the above-mentioned metal elements An alloy thereof can be used.

[0389] Alternatively, the first electrode 821 and the second electrode 822 may be made of indium oxide or indium tin. Conductive acids such as oxide, indium zinc oxide, zinc oxide, and zinc oxide doped with gallium Compounds such as fluorine-containing fluorine compounds can be used.

[0390] Alternatively, the first electrode 821 and the second electrode 822 may be made of graphene or graphite. The graphene-containing film can be, for example, a graphene oxide film. The film can be formed by reducing the film containing the compound. The reduction method includes applying heat or reducing the compound. A method using a base agent, etc. can be mentioned.

[0391] Alternatively, a conductive polymer may be used for the first electrode 821 and the second electrode 822. Cut.

[0392] The detection circuit 839 includes, for example, transistors M1 to M3. 839 includes wiring for supplying a power supply potential and a signal. For example, the signal line DL, the wiring VPI, This includes wiring CS, scanning line G1, wiring RES, and wiring VRES.

[0393] The detection circuit 839 may be disposed in a region that does not overlap with the window portion 834 .

[0394] Conductive materials are wired (for example, signal lines DL, wiring VPI, wiring CS, scanning lines G1, For example, inorganic conductive materials, organic conductive materials, etc. Conductive materials, metals, conductive ceramics, etc. can be used for the wiring. The same material as that which can be used for the first electrode 821 and the second electrode 822 is used for the wiring. It may be applied as follows.

[0395] Also, aluminum, gold, platinum, silver, nickel, titanium, tungsten, chromium, molybdenum Metal materials such as tin, iron, cobalt, copper, or palladium, or alloy materials containing such metal materials. It can be used for the scanning line G1, the signal line DL, the wiring VPI, the wiring RES, and the wiring VRES. Cut.

[0396] The detection circuit 839 may be formed on the first base material 836. Alternatively, the detection circuit 839 may be formed on another base material. The assembled sensing circuit 839 may then be transferred to the first substrate 836 .

[0397] The first substrate 836 and the second substrate 810 may be a glass substrate or a flexible material (e.g. For example, a resin, a resin film, a plastic film, or the like can be used.

[0398] More specifically, the first substrate 836 and the second substrate 810 are made of non-alkali glass. Soda-lime glass, potash glass, crystal glass, etc. can be used. The first base material 836 may be polyester, polyolefin, polyamide, polyimide, or the like. Use a resin film or plate such as polycarbonate, acrylic resin, etc. can be done.

[0399] The protective substrate 837 and / or the protective layer 837p may be, for example, glass or polyester. , polyolefin, polyamide, polyimide, polycarbonate, acrylic resin, etc. A resin film, a resin plate or a laminate thereof can be used.

[0400] The protective layer 837p may be, for example, a hard coat layer or a ceramic coat layer. Specifically, a layer containing a UV curable resin or aluminum oxide can be formed on the second electrode 8. It may be formed at a position overlapping with 22.

[0401] The display module 801 includes a plurality of pixels 802 arranged in a matrix (see FIG. 30). (See (C)).

[0402] For example, pixel 802 includes subpixel 802B, subpixel 802G, and subpixel 802R, Each sub-pixel comprises a display element and a pixel circuit for driving the display element.

[0403] The subpixel 802B of the pixel 802 is disposed at a position overlapping the colored layer CFB, and the subpixel 80 The subpixel 2G is disposed at a position overlapping the colored layer CFG, and the subpixel 802R is disposed at a position overlapping the colored layer CFR. The device is placed in a position.

[0404] The colored layer CFR is located so as to overlap the liquid crystal element 880. Note that the liquid crystal element 880 is As a result, the light reflected by the reflective electrode 872 is A part of the reflected light is transmitted through the colored layer CFR and emitted in the direction of the arrow shown in the figure. The electrode 872 may be a conductive film similar to the conductive film 772 functioning as a reflective electrode in the above embodiment. The liquid crystal element 880 may have a dielectric constant anisotropy of 2 or more and 3.8 or less. The liquid crystal layer has a

[0405] In addition, a light-shielding layer BM is provided so as to surround the colored layer (for example, the colored layer CFR).

[0406] The scanning line driver circuit 803g includes a transistor 803t and a capacitor 803c (see FIG. 31). see).

[0407] The detection signal DATA supplied by the detection unit 820U is converted and then fed to the flexible substrate FPC1 Various circuits that can be used for the converter CONV (FIG. 3) 0(A) and Figure 31).

[0408] For example, transistor M4 can be used for converter CONV.

[0409] The display module 801 includes an anti-reflection layer 867p at a position overlapping the pixel. For example, a circular polarizing plate can be used as 867p.

[0410] As shown in FIG. 30A, the display module 801 includes wiring that can supply signals. A terminal 819 is provided on the wiring 811. A flexible circuit board FPC2 that can supply signals such as This is being continued.

[0411] In addition, a printed wiring board (PWB) is attached to the flexible board FPC2. is also good.

[0412] The display module 801 has wiring such as scanning lines, signal lines, and power lines. can be used for wiring.

[0413] The wiring of the display module 801 is made of, for example, aluminum, chromium, copper, tin, etc. Ta, titanium, molybdenum, tungsten, nickel, yttrium, zirconium, silver or manganese; an alloy containing the above-mentioned metal element; or In particular, alloys of aluminum, chromium, etc., which are combinations of metal elements, can be used. , copper, tantalum, titanium, molybdenum, and tungsten. In particular, the alloy of copper and manganese is suitable for microfabrication using a wet etching method. This is preferable.

[0414] The specific structure of the wiring of the display module 801 is titanium on an aluminum film. A two-layer structure in which a titanium film is laminated on a titanium nitride film, a two-layer structure in which a titanium film is laminated on a titanium nitride film, A two-layer structure in which a tungsten film is laminated on a tantalum nitride film or a tungsten nitride film is laminated on a tantalum nitride film. A two-layer structure in which a titanium film is laminated with an tungsten film, and an aluminum film is laminated on the titanium film. A three-layer structure can be used in which a titanium film is formed on the aluminum film. Titanium, tantalum, tungsten, molybdenum, chromium, neodymium, sca A laminated layer of an alloy film or a nitride film made of one or more selected from tin, nickel, tin, or tin. Alternatively, a light-transmitting material containing indium oxide, tin oxide, or zinc oxide can be used. Alternatively, a conductive material having such properties may be used.

[0415] (Embodiment 10) In this embodiment mode, electronic devices manufactured using the liquid crystal display device described in the above embodiment mode will be described. A specific example of this will be described with reference to FIG.

[0416] As an example of an electronic device to which the present invention can be applied, a television device (television or television (also called television receivers), computer monitors, digital cameras, digital video Cameras, digital photo frames, mobile phones, portable game consoles, personal digital assistants, music players These include video game devices, gaming machines (pachinko machines, slot machines, etc.), and game cabinets. A specific example of electronic equipment is shown in FIG.

[0417] FIG. 32(A) shows a portable information terminal 1400 having a display unit. The 00 has a display unit 1402 and an operation button 1403 built into a housing 1401. The liquid crystal display device of one embodiment of the present invention can be used for the display portion 1402.

[0418] FIG. 32B shows a mobile phone 1410. The mobile phone 1410 has a housing 141 1, a display unit 1412, operation buttons 1413, a speaker 1414, and a microphone 1415. The liquid crystal display device of one embodiment of the present invention can be used for the display portion 1412. Cut.

[0419] FIG. 32C shows a music playback device 1420. The music playback device 1420 has a housing 1 A display unit 1422, an operation button 1423, and an antenna 1424 are incorporated in 421. Moreover, the antenna 1424 can transmit and receive information by radio signals. The liquid crystal display device of one embodiment can be used for the display portion 1422.

[0420] The display unit 1402, the display unit 1412, and the display unit 1422 each have a touch input function. Display buttons (not shown) displayed on the display units 1402, 1412, and 1422 ) you can operate the screen and input information by touching it with your finger or other object.

[0421] The liquid crystal display device shown in the above embodiment includes a display portion 1402, a display portion 1412, and a display portion 14 22, the display unit 1402, the display unit 1412, and the display It can be a display unit 1422.

[0422] (Additional notes regarding the present specification, etc.) The above embodiment and each configuration in the embodiment will be described below with additional notes. <Additional Notes on One Aspect of the Invention Described in the Embodiments>

[0423] The configurations shown in each embodiment may be appropriately combined with the configurations shown in other embodiments to form one embodiment of the present invention. In addition, when multiple configuration examples are shown in one embodiment, The configuration examples can be appropriately combined with each other.

[0424] In addition, the contents (or even a part of the contents) described in one embodiment may be used in the embodiment. Another content (or a part of the content) described in the embodiment, and / or one or more other embodiments The application, combination, or replacement of the contents (or part of the contents) described in the form It is possible to do the following:

[0425] The contents described in the embodiments are explained in detail with reference to various figures in each embodiment. This refers to the content that is stated or stated using the text in the specification.

[0426] In addition, a figure (or a part thereof) described in one embodiment may be different from another part of the figure, Another figure (or a part thereof) described in the embodiment, and / or one or more By combining with the figure (or a part of it) described in another embodiment of the present invention , and many more diagrams can be constructed.

[0427] Although one aspect of the present invention has been described in each embodiment, the present invention is not limited thereto. For example, in one aspect of the present invention, in the first and second embodiments, a first operation and a second operation are We have explained the configuration in which the scanning direction is switched by switching between the two operations. However, one aspect of the present invention is not limited to this. Depending on the situation, for example, a configuration in which scanning is performed in one direction may be used. For example, in a fourth embodiment of the present invention, the circuit 100 may be However, the present invention is not limited to this embodiment. Depending on the circumstances, for example, the circuit 100 may be applied to various circuits as one aspect of the present invention.

[0428] <Notes regarding the description of the drawings>

[0429] In this specification, the words "above" and "below" that indicate the positional relationship between components are used. are used for convenience in describing the drawings. Therefore, the terms indicating the arrangement may be changed as appropriate depending on the direction in which the arrangement is depicted. The above description is not limited to the above, and may be rephrased appropriately depending on the situation.

[0430] In addition, the terms "above" and "below" refer to the positional relationship of a component directly above or below and directly connected to it. For example, if the expression is "electrode B on insulating layer A," It is not necessary that the electrode B is formed directly on the insulating layer A. This does not exclude the inclusion of other components in between.

[0431] In the present specification and the like, in the block diagrams, components are classified by function and are independent of each other. However, in actual circuits, the components are divided into blocks according to their functions. In some cases, it is difficult to separate the circuits, and multiple functions are involved in one circuit, or multiple circuits are involved. Therefore, the blocks in the block diagram may be different from those described in the specification. The present invention is not limited to the disclosed components.

[0432] In addition, in the drawings, the size, layer thickness, and area are shown arbitrarily for convenience of explanation. Therefore, the drawings are not necessarily limited to the scale. The drawings are merely schematic illustrations for the purpose of illustration, and are not limited to the shapes or values ​​shown in the drawings. For example, Signal, voltage, or current variations due to noise, or timing errors , voltage or current variations, etc.

[0433] In addition, in the drawings, in top views (also called plan views or layout views) and perspective views, In order to clarify the drawings, some components may be omitted.

[0434] <Notes on possible alternative descriptions>

[0435] In the present specification and the like, when describing the connection relationship of a transistor, is expressed as "one of the source and drain" (or the first electrode, or the first terminal), and The other side of the drain is referred to as the "other side of the source or drain" (or the second electrode, or the second terminal). This is because the source and drain of a transistor are This is because it changes depending on the conditions. Regarding the names of the source and drain of a transistor, can be appropriately rephrased as source (drain) terminal, source (drain) electrode, etc., depending on the situation. It is possible to do so.

[0436] In addition, the terms "electrode" and "wiring" used in this specification and the like do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring." In addition, the term "electrode" or "wiring" may be used to refer to the plural "electrodes" or "wirings". This also includes cases where the "line" is formed as a single unit.

[0437] In this specification and the like, the terms voltage and potential can be interchanged as appropriate. For example, the reference potential is the ground potential (earth potential). If we define the potential as the ground potential, the voltage can be expressed as the potential. Note that the potential is relative, and the arrangement may differ depending on the reference potential. The potential applied to the wires may be changed.

[0438] In this specification, the terms "film" and "layer" may be used depending on the circumstances. For example, the term "conductive layer" can be used interchangeably with "conductive layer" depending on the application. Alternatively, for example, the term "insulating film" may be used. In some cases, it may be possible to change the term "insulating layer" to the term "insulating layer."

[0439] <Notes on definitions of terms> The following provides definitions of terms that were mentioned in the above embodiment. <<About switches>> In this specification, a switch refers to a device that is in a conductive state (on state) or a non-conductive state (off state). A switch that is in a "switchable state" and has the function of controlling whether or not current flows. A switch is a device that has the function of selecting and switching the path through which a current flows.

[0440] As an example, an electrical switch or a mechanical switch can be used. The switch is not limited to a specific one as long as it can control the current.

[0441] An example of an electrical switch is a transistor (e.g., a bipolar transistor, M OS transistors, etc.), diodes (e.g., PN diodes, PIN diodes, Schottky diode, MIM (Metal Insulator Metal) diode , MIS (Metal Insulator Semiconductor) diode diode-connected transistors, or logic circuits that combine these. be.

[0442] When a transistor is used as a switch, the "conduction state" of the transistor is This refers to a state in which the source and drain of a transistor can be considered to be electrically shorted. The "non-conducting state" of a transistor is when the source and drain of the transistor are electrically isolated. In addition, when a transistor is operated simply as a switch, In this case, the polarity (conductivity type) of the transistor is not particularly limited.

[0443] An example of a mechanical switch is a digital micromirror device (DMD). There are switches that use MEMS (microelectromechanical systems) technology. The switch has an electrode that can be mechanically moved, and the movement of the electrode causes Thus, the device operates by controlling conduction and non-conduction.

[0444] <<About channel length>> In this specification and the like, the channel length is, for example, the length of a semiconductor (or the part of the semiconductor through which current flows when the transistor is on) and the gate The distance between the source and drain in the overlapping region, or the region where the channel is formed This refers to.

[0445] In addition, the channel length of a single transistor does not necessarily have the same value in all regions. That is, the channel length of a transistor may not be fixed to a single value. Therefore, in this specification, the channel length is defined as the length of any one of the regions in which the channel is formed. The value may be a maximum, minimum or average value.

[0446] <<About channel width>> In this specification, the channel width is, for example, the width of a semiconductor (or a transistor) when it is in an on-state. The area where the gate electrode overlaps with the gate electrode (the part of the semiconductor through which current flows when the This refers to the length of the portion where the source and drain face each other in the region where the source and drain are formed.

[0447] In addition, the channel width of a single transistor does not necessarily have the same value in all regions. That is, the channel width of a transistor may not be fixed to a single value. Therefore, in this specification, the channel width refers to any one of the widths in the region where the channel is formed. The value, maximum, minimum or average value.

[0448] Depending on the structure of the transistor, the channel in the region where the channel is actually formed may vary. The effective channel width (hereinafter referred to as the effective channel width) shown in the top view of the transistor The channel width (hereinafter referred to as the apparent channel width) may be different. For example, In a transistor having a three-dimensional structure, the effective channel width is The effect of the channel width becomes larger than the apparent channel width shown in For example, in a transistor with a fine, three-dimensional structure, The percentage of the channel region that is formed on the side of the semiconductor, compared to the percentage of the channel region that is formed In that case, the apparent channel width shown in the top view may be larger. In this case, the effective channel width where the channel is actually formed is larger than the width of the channel formed by the MOSFET.

[0449] By the way, in a transistor having a three-dimensional structure, the effective channel width is For example, it may be difficult to estimate the effective channel width from the design value. In order to obtain this, it is necessary to assume that the shape of the semiconductor is known. Unless k is precisely known, it is difficult to accurately measure the effective channel width.

[0450] Therefore, in this specification, in a top view of a transistor, a semiconductor and a gate electrode are overlapped. The apparent channel length is the length of the area where the source and drain face each other. The width of the channel is called the surrounded channel width (SCW). In this specification, when simply referred to as channel width, may refer to enclosed channel width or apparent channel width. In this document, when the term "channel width" is used, it may refer to the effective channel width. Channel length, channel width, effective channel width, apparent channel width, enclosure channel The channel width, etc., can be determined by acquiring cross-sectional TEM images and analyzing those images. A value can be determined.

[0451] In addition, the field effect mobility of the transistor and the current value per channel width are calculated. In some cases, the effective channel width is calculated using the enclosed channel width. The value may differ from that calculated using the channel width.

[0452] <<About pixels>> In this specification, a pixel refers to, for example, one element whose brightness can be controlled. Therefore, as an example, one pixel refers to one color element, and one color element Therefore, the brightness is expressed by the color components R (red), G (green), and B (blue). In the case of a color display device, the smallest unit of an image is a triplet of R, G, and B pixels. It is assumed that it is composed of elements.

[0453] The color elements are not limited to three colors, and may be more than three. For example, RGBW (W is white) , and RGB with the addition of yellow, cyan, and magenta.

[0454] <<About connection>> In this specification, "A and B are connected" means that A and B are directly connected. In addition to those that are electrically connected, A and B are also included. Being connected means that there is an object between A and B that has some electrical effect. A means a device that enables the transmission and reception of electrical signals between A and B.

[0455] For example, the source (or the first terminal, etc.) of the transistor is connected via Z1 (or The drain (or second terminal, etc.) of the transistor is electrically connected to Z 2 (or not), it may be electrically connected to Y, or the source of the transistor (or the first terminal, etc.) is directly connected to a part of Z1, and another part of Z1 is directly connected to X. The drain (or second terminal, etc.) of the transistor is directly connected to a part of Z2. and another part of Z2 is directly connected to Y, It is possible to do so.

[0456] For example, "X and Y and the source (or first terminal, etc.) and drain (or second terminal, etc.) of a transistor The terminals of the transistor (or the first terminal, etc.) are electrically connected to each other, and X, the source of the transistor (or the first terminal, etc.) 1 terminal, etc.), the drain (or second terminal, etc.) of the transistor, and Y. "The source (or the third) of the transistor is connected to the The drain (or second terminal, etc.) of the transistor is electrically connected to X. The transistor source (or first terminal, etc.) is electrically connected to Y, and the transistor source (or first terminal, etc.) is electrically connected to X. The drain (or second terminal, etc.) of the transistor, Y, is electrically connected in this order. " Alternatively, "X is the source (or first terminal, etc.) of a transistor. The transistor is electrically connected to Y via a drain (or a second terminal, etc.) and a transistor is electrically connected to X via a drain (or a second terminal, etc.). The source (or first terminal, etc.) of a resistor, the drain (or second terminal, etc.) of a transistor ), Y is provided in this connection order. By using a simple expression method and specifying the order of connections in the circuit configuration, Distinguish between the source (or first terminal, etc.) and the drain (or second terminal, etc.) of a transistor. The technical scope can be determined based on the above.

[0457] Or, as another way of expressing it, for example, "the source (or first terminal, etc.) of a transistor is electrically connected to X through at least a first connection path, and the first connection path is , the second connection path does not have a second connection path, and the second connection path is a transistor The source (or first terminal, etc.) of the transistor and the drain (or second terminal, etc.) of the transistor The first connection path is a path via Z1, and the second connection path is a path between the transistor The drain (or second terminal, etc.) of the capacitor is electrically connected to Y through at least a third connection path. The third connection path does not include the second connection path, and the third connection path The connection path is the path through Z2. The source (or the first terminal, etc.) of the resistor is connected to the resistor via Z1 by at least the first connection path. and X is electrically connected to the first connection path, and the first connection path does not have a second connection path; The second connection path includes a connection path through a transistor, and the second connection path includes a drain of the transistor. (or the second terminal, etc.) is connected to Y via Z2 by at least a third connection path. The third connection path does not have the second connection path. Alternatively, the source (or the first terminal, etc.) of the transistor may be at least The first electrical path is electrically connected to X through Z1, and the first electrical path is The primary path does not have a second electrical path, and the second electrical path is a From the source (or first terminal, etc.) to the drain (or second terminal, etc.) of the transistor The drain (or second terminal, etc.) of the transistor is connected to at least a third The third electrical path is electrically connected to Y through Z2. , the fourth electrical path is not included, and the fourth electrical path is a drain of the transistor (or second terminal, etc.) to the source (or first terminal, etc.) of the transistor. Using the same expression as these examples, the circuit configuration By defining the connection path in Distinguish between the first terminal (or the second terminal, etc.) and the drain (or the second terminal, etc.) to determine the technical scope. can be done.

[0458] Note that these expression methods are merely examples, and the present invention is not limited to these expression methods. , Y, Z1, and Z2 are objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layer, etc.). [Explanation of symbols]

[0459] CK1 signal CK2 signal CK3 signal OUT[i] Output signal OUT[i+1] Output signal OUT[i+2] Output signal G1 scan line M1 Transistor M3 Transistor M4 Transistor ND1 Node ND2 Node ND3 Node t1 Period t2 Period t3 Period t4 Period t5 Period t6 period T1 Period T2 Period T3 Period T4 Period T5 Period T6 period SL Wiring OUT wiring SEL1 signal SEL2 signal RES wiring VPI Wiring VRES wiring DL signal line CS wiring DATA detection signal FPC1 Flexible Circuit Board FPC2 Flexible Circuit Board 100 circuits 101 Transistor 102 Transistor 102A Switch 103 Transistor 103A Switch 104 Transistor 105 Transistor 105A Switch 106 Transistor 107 Transistor 108 Transistor 109 Transistor 110 Capacitive element 111 Transistor 112 Transistor 113 Transistor 114 Capacitive element 130 Pixel section 131 pixels 132 Transistor 133 Liquid crystal element 134 Capacitive element 135 Transistor 136 Transistor 137 EL element 151 Wiring 152 Wiring 153 Wiring 154 Wiring 154A Wiring 155 Wiring 156 Wiring 157 Wiring 158 Wiring 159 Wiring 160 Wiring 161 Wiring 162 Wiring 163 Wiring 200 Shift Registers 201 Circuit 211 Wiring 212 Wiring 213 Wiring 214 Wiring 215 Wiring 216 Wiring 217 Wiring 218 Wiring 300 circuits 301 Circuit 401 First Wiring 402 Second Wiring 403 Semiconductor Layer 404 Opening 600 Transistors 601 Substrate 602 Gate electrode 603 Insulating layer 604 Oxide semiconductor layer 604a Channel Region 604b n-type region 604c n-type region 605a electrode 605b electrode 606 Insulating layer 607 Insulating Layer 610 Transistor 614 Oxide semiconductor layer 614a Oxide semiconductor layer 614b Oxide semiconductor layer 620 Transistor 624 Oxide Semiconductor Layer 624a Oxide semiconductor layer 624b Oxide semiconductor layer 624c Oxide semiconductor layer 650 Transistors 651 Insulation Layer 652 Insulating layer 654 Insulating layer 656 Insulating Layer 660 Transistor 664 Oxide Semiconductor Layer 664a Oxide semiconductor layer 664b Oxide semiconductor layer 664c Oxide semiconductor layer 670 Transistors 700 Display Module 701 Substrate 702 Pixel section 704 Source driver circuit section 705 Substrate 706 Gate driver circuit section 708 FPC terminal section 710 Signal Line 711 Wiring section 712 Sealing material 716 FPC 734 Insulating film 736 Colored film 738 Light-shielding film 750 Transistors 752 Transistor 760 Connection electrode 764 Insulating film 766 Insulating Film 768 Insulating Film 770 Planarizing Insulating Film 772 Conductive Film 774 Conductive Film 775 Liquid crystal elements 776 Liquid crystal layer 778 Structure 780 Anisotropic Conductive Film 790 Capacitive element 800 I / O devices 801 Display module 802 pixels 802B subpixel 802G subpixel 802R subpixel 803c capacity 803g Scanning line driver circuit 803t Transistor 810 Base material 811 Wiring 817 Protective base material 819 Terminal 820U Detection Unit 821 Electrode 822 Electrode 823 Insulating layer 834 Window 836 Base material 837 Protective base material 837p protective layer 839 Detection circuit 850 Input Device 867p anti-reflection layer 872 Reflecting electrode 880 Liquid crystal element 1135 Transistor 1400 Mobile Information Terminal 1401 Case 1402 Display section 1403 Operation button 1410 Mobile Phones 1411 Case 1412 Display section 1413 Operation button 1414 Speaker 1415 Mike 1420 Music player 1421 Case 1422 Display section 1423 Operation button 1424 Antenna

Claims

1. The semiconductor device includes first to fifth transistors, one of a source electrode and a drain electrode of the first transistor is always electrically connected to a clock signal line; the other of the source electrode and the drain electrode of the first transistor is always electrically connected to a gate signal line; one of a source electrode and a drain electrode of the second transistor is always electrically connected to a first power supply line; the other of the source electrode and the drain electrode of the second transistor is always electrically connected to the gate signal line; one of a source electrode and a drain electrode of the third transistor is always electrically connected to a first signal line; the other of the source electrode and the drain electrode of the third transistor is always electrically connected to one of the source electrode and the drain electrode of the fifth transistor; a gate electrode of the third transistor is always electrically connected to a second signal line; one of a source electrode and a drain electrode of the fourth transistor is always electrically connected to a third signal line; the other of the source electrode and the drain electrode of the fourth transistor is always electrically connected to one of the source electrode and the drain electrode of the fifth transistor; a gate electrode of the fourth transistor is always electrically connected to a fourth signal line; the other of the source electrode and the drain electrode of the fifth transistor is always electrically connected to the gate electrode of the first transistor; a gate electrode of the fifth transistor is always electrically connected to a second power supply line; a signal from a fifth signal line is input to a gate electrode of the second transistor; W (channel width) / L (channel length) of the first transistor is larger than W / L of the second transistor, the W / L of the first transistor is greater than the W / L of the third transistor; the W / L of the first transistor is greater than the W / L of the fourth transistor; the W / L of the third transistor is 0.9 to 1.1 times the W / L of the fourth transistor; Semiconductor device.

2. The semiconductor device includes first to fifth transistors, one of a source electrode and a drain electrode of the first transistor is always electrically connected to a clock signal line; the other of the source electrode and the drain electrode of the first transistor is always electrically connected to a gate signal line; one of a source electrode and a drain electrode of the second transistor is always electrically connected to a first power supply line; the other of the source electrode and the drain electrode of the second transistor is always electrically connected to the gate signal line; one of a source electrode and a drain electrode of the third transistor is always electrically connected to a first signal line; the other of the source electrode and the drain electrode of the third transistor is always electrically connected to one of the source electrode and the drain electrode of the fifth transistor; a gate electrode of the third transistor is always electrically connected to a second signal line; one of a source electrode and a drain electrode of the fourth transistor is always electrically connected to a third signal line; the other of the source electrode and the drain electrode of the fourth transistor is always electrically connected to one of the source electrode and the drain electrode of the fifth transistor; a gate electrode of the fourth transistor is always electrically connected to a fourth signal line; the other of the source electrode and the drain electrode of the fifth transistor is always electrically connected to the gate electrode of the first transistor; a gate electrode of the fifth transistor is always electrically connected to a second power supply line; a signal from a fifth signal line is input to a gate electrode of the second transistor; W (channel width) / L (channel length) of the first transistor is larger than W / L of the second transistor, the W / L of the first transistor is greater than the W / L of the third transistor; the W / L of the first transistor is greater than the W / L of the fourth transistor; the W / L of the third transistor is 0.9 to 1.1 times the W / L of the fourth transistor, In a plan view, a channel length direction of the third transistor is aligned along the first direction, a channel length direction of the fourth transistor is aligned along the first direction in a plan view; a first conductive layer having a region functioning as one of a source electrode and a drain electrode of the third transistor is provided in the same layer as a second conductive layer having a region functioning as the first signal line, In a plan view, the second conductive layer has a region extending in the first direction. Semiconductor device.

3. The semiconductor device includes first to fifth transistors, one of a source electrode and a drain electrode of the first transistor is always electrically connected to a clock signal line; the other of the source electrode and the drain electrode of the first transistor is always electrically connected to a gate signal line; one of a source electrode and a drain electrode of the second transistor is always electrically connected to a first power supply line; the other of the source electrode and the drain electrode of the second transistor is always electrically connected to the gate signal line; one of a source electrode and a drain electrode of the third transistor is always electrically connected to a first signal line; the other of the source electrode and the drain electrode of the third transistor is always electrically connected to one of the source electrode and the drain electrode of the fifth transistor; a gate electrode of the third transistor is always electrically connected to a second signal line; one of a source electrode and a drain electrode of the fourth transistor is always electrically connected to a third signal line; the other of the source electrode and the drain electrode of the fourth transistor is always electrically connected to one of the source electrode and the drain electrode of the fifth transistor; a gate electrode of the fourth transistor is always electrically connected to a fourth signal line; the other of the source electrode and the drain electrode of the fifth transistor is always electrically connected to the gate electrode of the first transistor; a gate electrode of the fifth transistor is always electrically connected to a second power supply line; a signal from a fifth signal line is input to a gate electrode of the second transistor; W (channel width) / L (channel length) of the first transistor is larger than W / L of the second transistor, the W / L of the first transistor is greater than the W / L of the third transistor; the W / L of the first transistor is greater than the W / L of the fourth transistor; the W / L of the third transistor is 0.9 to 1.1 times the W / L of the fourth transistor, In a plan view, a channel length direction of the third transistor is aligned along the first direction, a channel length direction of the fourth transistor is aligned along the first direction in a plan view; a first conductive layer having a region functioning as one of a source electrode and a drain electrode of the third transistor is provided in the same layer as a second conductive layer having a region functioning as the first signal line, In a plan view, the second conductive layer has a region extending in the first direction, the first conductive layer is provided in the same layer as a third conductive layer having a region that functions as the first power supply line; the first conductive layer is provided in the same layer as a fourth conductive layer having a region that functions as the clock signal line; In a plan view, the third conductive layer has a region located between the second conductive layer and the fourth conductive layer. Semiconductor device.

4. The semiconductor device includes first to fifth transistors, one of a source electrode and a drain electrode of the first transistor is always electrically connected to a clock signal line; the other of the source electrode and the drain electrode of the first transistor is always electrically connected to a gate signal line; one of a source electrode and a drain electrode of the second transistor is always electrically connected to a first power supply line; the other of the source electrode and the drain electrode of the second transistor is always electrically connected to the gate signal line; one of a source electrode and a drain electrode of the third transistor is always electrically connected to a first signal line; the other of the source electrode and the drain electrode of the third transistor is always electrically connected to one of the source electrode and the drain electrode of the fifth transistor; a gate electrode of the third transistor is always electrically connected to a second signal line; one of a source electrode and a drain electrode of the fourth transistor is always electrically connected to a third signal line; the other of the source electrode and the drain electrode of the fourth transistor is always electrically connected to one of the source electrode and the drain electrode of the fifth transistor; a gate electrode of the fourth transistor is always electrically connected to a fourth signal line; the other of the source electrode and the drain electrode of the fifth transistor is always electrically connected to the gate electrode of the first transistor; a gate electrode of the fifth transistor is always electrically connected to a second power supply line; a signal from a fifth signal line is input to a gate electrode of the second transistor; W (channel width) / L (channel length) of the first transistor is larger than W / L of the second transistor, the W / L of the first transistor is greater than the W / L of the third transistor; the W / L of the first transistor is greater than the W / L of the fourth transistor; the W / L of the third transistor is 0.9 to 1.1 times the W / L of the fourth transistor, In a plan view, a channel length direction of the third transistor is aligned along the first direction, a channel length direction of the fourth transistor is aligned along the first direction in a plan view; a first conductive layer having a region functioning as one of a source electrode and a drain electrode of the third transistor is provided in the same layer as a second conductive layer having a region functioning as the first signal line, In a plan view, the second conductive layer has a region extending in the first direction, a third conductive layer having a region functioning as a gate electrode of the third transistor is provided in the same layer as the fourth conductive layer; the first conductive layer is always electrically connected to the second conductive layer via the fourth conductive layer; Semiconductor device.

5. The semiconductor device includes first to fifth transistors, one of a source electrode and a drain electrode of the first transistor is always electrically connected to a clock signal line; the other of the source electrode and the drain electrode of the first transistor is always electrically connected to a gate signal line; one of a source electrode and a drain electrode of the second transistor is always electrically connected to a first power supply line; the other of the source electrode and the drain electrode of the second transistor is always electrically connected to the gate signal line; one of a source electrode and a drain electrode of the third transistor is always electrically connected to a first signal line; the other of the source electrode and the drain electrode of the third transistor is always electrically connected to one of the source electrode and the drain electrode of the fifth transistor; a gate electrode of the third transistor is always electrically connected to a second signal line; one of a source electrode and a drain electrode of the fourth transistor is always electrically connected to a third signal line; the other of the source electrode and the drain electrode of the fourth transistor is always electrically connected to one of the source electrode and the drain electrode of the fifth transistor; a gate electrode of the fourth transistor is always electrically connected to a fourth signal line; the other of the source electrode and the drain electrode of the fifth transistor is always electrically connected to the gate electrode of the first transistor; a gate electrode of the fifth transistor is always electrically connected to a second power supply line; a signal from a fifth signal line is input to a gate electrode of the second transistor; W (channel width) / L (channel length) of the first transistor is larger than W / L of the second transistor, the W / L of the first transistor is greater than the W / L of the third transistor; the W / L of the first transistor is greater than the W / L of the fourth transistor; the W / L of the third transistor is 0.9 to 1.1 times the W / L of the fourth transistor, In a plan view, a channel length direction of the third transistor is aligned along the first direction, a channel length direction of the fourth transistor is aligned along the first direction in a plan view; a first conductive layer having a region functioning as one of a source electrode and a drain electrode of the third transistor is provided in the same layer as a second conductive layer having a region functioning as the first signal line, In a plan view, the second conductive layer has a region extending in the first direction, a third conductive layer having a region functioning as a gate electrode of the third transistor is provided in the same layer as the fourth conductive layer; the first conductive layer is always electrically connected to the second conductive layer via the fourth conductive layer; the first conductive layer is provided in the same layer as a fifth conductive layer having a region that functions as the third signal line, In a plan view, the fourth conductive layer has a region intersecting with the fifth conductive layer. Semiconductor device.

6. The semiconductor device includes first to fifth transistors, one of a source electrode and a drain electrode of the first transistor is always electrically connected to a clock signal line; the other of the source electrode and the drain electrode of the first transistor is always electrically connected to a gate signal line; one of a source electrode and a drain electrode of the second transistor is always electrically connected to a first power supply line; the other of the source electrode and the drain electrode of the second transistor is always electrically connected to the gate signal line; one of a source electrode and a drain electrode of the third transistor is always electrically connected to a first signal line; the other of the source electrode and the drain electrode of the third transistor is always electrically connected to one of the source electrode and the drain electrode of the fifth transistor; a gate electrode of the third transistor is always electrically connected to a second signal line; one of a source electrode and a drain electrode of the fourth transistor is always electrically connected to a third signal line; the other of the source electrode and the drain electrode of the fourth transistor is always electrically connected to one of the source electrode and the drain electrode of the fifth transistor; a gate electrode of the fourth transistor is always electrically connected to a fourth signal line; the other of the source electrode and the drain electrode of the fifth transistor is always electrically connected to the gate electrode of the first transistor; a gate electrode of the fifth transistor is always electrically connected to a second power supply line; a signal from a fifth signal line is input to a gate electrode of the second transistor; W (channel width) / L (channel length) of the first transistor is larger than W / L of the second transistor, the W / L of the first transistor is greater than the W / L of the third transistor; the W / L of the first transistor is greater than the W / L of the fourth transistor; the W / L of the third transistor is 0.9 to 1.1 times the W / L of the fourth transistor, In a plan view, a channel length direction of the third transistor is aligned along the first direction, a channel length direction of the fourth transistor is aligned along the first direction in a plan view; a first conductive layer having a region functioning as one of a source electrode and a drain electrode of the third transistor is provided in the same layer as a second conductive layer having a region functioning as the first signal line, In a plan view, the second conductive layer has a region extending in the first direction, the first conductive layer is provided in the same layer as a third conductive layer having a region that functions as the first power supply line; the first conductive layer is provided in the same layer as a fourth conductive layer having a region that functions as the clock signal line; the third conductive layer has a region located between the second conductive layer and the fourth conductive layer in a plan view, a fifth conductive layer having a region functioning as a gate electrode of the third transistor is provided in the same layer as the sixth conductive layer; the first conductive layer is always electrically connected to the second conductive layer via the sixth conductive layer; Semiconductor device.

7. The semiconductor device includes first to fifth transistors, one of a source electrode and a drain electrode of the first transistor is always electrically connected to a clock signal line; the other of the source electrode and the drain electrode of the first transistor is always electrically connected to a gate signal line; one of a source electrode and a drain electrode of the second transistor is always electrically connected to a first power supply line; the other of the source electrode and the drain electrode of the second transistor is always electrically connected to the gate signal line; one of a source electrode and a drain electrode of the third transistor is always electrically connected to a first signal line; the other of the source electrode and the drain electrode of the third transistor is always electrically connected to one of the source electrode and the drain electrode of the fifth transistor; a gate electrode of the third transistor is always electrically connected to a second signal line; one of a source electrode and a drain electrode of the fourth transistor is always electrically connected to a third signal line; the other of the source electrode and the drain electrode of the fourth transistor is always electrically connected to one of the source electrode and the drain electrode of the fifth transistor; a gate electrode of the fourth transistor is always electrically connected to a fourth signal line; the other of the source electrode and the drain electrode of the fifth transistor is always electrically connected to the gate electrode of the first transistor; a gate electrode of the fifth transistor is always electrically connected to a second power supply line; a signal from a fifth signal line is input to a gate electrode of the second transistor; W (channel width) / L (channel length) of the first transistor is larger than W / L of the second transistor, the W / L of the first transistor is greater than the W / L of the third transistor; the W / L of the first transistor is greater than the W / L of the fourth transistor; the W / L of the third transistor is 0.9 to 1.1 times the W / L of the fourth transistor, In a plan view, a channel length direction of the third transistor is aligned along the first direction, a channel length direction of the fourth transistor is aligned along the first direction in a plan view; a first conductive layer having a region functioning as one of a source electrode and a drain electrode of the third transistor is provided in the same layer as a second conductive layer having a region functioning as the first signal line, In a plan view, the second conductive layer has a region extending in the first direction, the first conductive layer is provided in the same layer as a third conductive layer having a region that functions as the first power supply line; the first conductive layer is provided in the same layer as a fourth conductive layer having a region that functions as the clock signal line; the third conductive layer has a region located between the second conductive layer and the fourth conductive layer in a plan view, a fifth conductive layer having a region functioning as a gate electrode of the third transistor is provided in the same layer as the sixth conductive layer; the first conductive layer is always electrically connected to the second conductive layer via the sixth conductive layer; the first conductive layer is provided in the same layer as a seventh conductive layer having a region that functions as the third signal line, In a plan view, the sixth conductive layer has a region intersecting with the seventh conductive layer. Semiconductor device.

8. The semiconductor device includes first to fifth transistors, one of a source electrode and a drain electrode of the first transistor is always electrically connected to a clock signal line; the other of the source electrode and the drain electrode of the first transistor is always electrically connected to a gate signal line; one of a source electrode and a drain electrode of the second transistor is always electrically connected to a first power supply line; the other of the source electrode and the drain electrode of the second transistor is always electrically connected to the gate signal line; one of a source electrode and a drain electrode of the third transistor is always electrically connected to a first signal line; the other of the source electrode and the drain electrode of the third transistor is always electrically connected to one of the source electrode and the drain electrode of the fifth transistor; a gate electrode of the third transistor is always electrically connected to a second signal line; one of a source electrode and a drain electrode of the fourth transistor is always electrically connected to a third signal line; the other of the source electrode and the drain electrode of the fourth transistor is always electrically connected to one of the source electrode and the drain electrode of the fifth transistor; a gate electrode of the fourth transistor is always electrically connected to a fourth signal line; the other of the source electrode and the drain electrode of the fifth transistor is always electrically connected to the gate electrode of the first transistor; a gate electrode of the fifth transistor is always electrically connected to a second power supply line; a signal from a fifth signal line is input to a gate electrode of the second transistor; W (channel width) / L (channel length) of the first transistor is larger than W / L of the second transistor, the W / L of the first transistor is greater than the W / L of the third transistor; the W / L of the first transistor is greater than the W / L of the fourth transistor; the W / L of the third transistor is 0.9 to 1.1 times the W / L of the fourth transistor, a first conductive layer having a region functioning as one of a source electrode and a drain electrode of the third transistor is provided in the same layer as a second conductive layer having a region functioning as the first signal line, the first conductive layer is provided in the same layer as a third conductive layer having a region that functions as the first power supply line; the first conductive layer is provided in the same layer as a fourth conductive layer having a region that functions as the clock signal line; In a plan view, the third conductive layer has a region located between the second conductive layer and the fourth conductive layer. Semiconductor device.

9. The semiconductor device includes first to fifth transistors, one of a source electrode and a drain electrode of the first transistor is always electrically connected to a clock signal line; the other of the source electrode and the drain electrode of the first transistor is always electrically connected to a gate signal line; one of a source electrode and a drain electrode of the second transistor is always electrically connected to a first power supply line; the other of the source electrode and the drain electrode of the second transistor is always electrically connected to the gate signal line; one of a source electrode and a drain electrode of the third transistor is always electrically connected to a first signal line; the other of the source electrode and the drain electrode of the third transistor is always electrically connected to one of the source electrode and the drain electrode of the fifth transistor; a gate electrode of the third transistor is always electrically connected to a second signal line; one of a source electrode and a drain electrode of the fourth transistor is always electrically connected to a third signal line; the other of the source electrode and the drain electrode of the fourth transistor is always electrically connected to one of the source electrode and the drain electrode of the fifth transistor; a gate electrode of the fourth transistor is always electrically connected to a fourth signal line; the other of the source electrode and the drain electrode of the fifth transistor is always electrically connected to the gate electrode of the first transistor; a gate electrode of the fifth transistor is always electrically connected to a second power supply line; a signal from a fifth signal line is input to a gate electrode of the second transistor; W (channel width) / L (channel length) of the first transistor is larger than W / L of the second transistor, the W / L of the first transistor is greater than the W / L of the third transistor; the W / L of the first transistor is greater than the W / L of the fourth transistor; the W / L of the third transistor is 0.9 to 1.1 times the W / L of the fourth transistor, a first conductive layer having a region functioning as one of a source electrode and a drain electrode of the third transistor is provided in the same layer as a second conductive layer having a region functioning as the first signal line, the first conductive layer is provided in the same layer as a third conductive layer having a region that functions as the first power supply line; the first conductive layer is provided in the same layer as a fourth conductive layer having a region that functions as the clock signal line; the third conductive layer has a region located between the second conductive layer and the fourth conductive layer in a plan view, a fifth conductive layer having a region functioning as a gate electrode of the third transistor is provided in the same layer as the sixth conductive layer; the first conductive layer is always electrically connected to the second conductive layer via the sixth conductive layer; Semiconductor device.

10. The semiconductor device includes first to fifth transistors, one of a source electrode and a drain electrode of the first transistor is always electrically connected to a clock signal line; the other of the source electrode and the drain electrode of the first transistor is always electrically connected to a gate signal line; one of a source electrode and a drain electrode of the second transistor is always electrically connected to a first power supply line; the other of the source electrode and the drain electrode of the second transistor is always electrically connected to the gate signal line; one of a source electrode and a drain electrode of the third transistor is always electrically connected to a first signal line; the other of the source electrode and the drain electrode of the third transistor is always electrically connected to one of the source electrode and the drain electrode of the fifth transistor; a gate electrode of the third transistor is always electrically connected to a second signal line; one of a source electrode and a drain electrode of the fourth transistor is always electrically connected to a third signal line; the other of the source electrode and the drain electrode of the fourth transistor is always electrically connected to one of the source electrode and the drain electrode of the fifth transistor; a gate electrode of the fourth transistor is always electrically connected to a fourth signal line; the other of the source electrode and the drain electrode of the fifth transistor is always electrically connected to the gate electrode of the first transistor; a gate electrode of the fifth transistor is always electrically connected to a second power supply line; a signal from a fifth signal line is input to a gate electrode of the second transistor; W (channel width) / L (channel length) of the first transistor is larger than W / L of the second transistor, the W / L of the first transistor is greater than the W / L of the third transistor; the W / L of the first transistor is greater than the W / L of the fourth transistor; the W / L of the third transistor is 0.9 to 1.1 times the W / L of the fourth transistor, a first conductive layer having a region functioning as one of a source electrode and a drain electrode of the third transistor is provided in the same layer as a second conductive layer having a region functioning as the first signal line, the first conductive layer is provided in the same layer as a third conductive layer having a region that functions as the first power supply line; the first conductive layer is provided in the same layer as a fourth conductive layer having a region that functions as the clock signal line; the third conductive layer has a region located between the second conductive layer and the fourth conductive layer in a plan view, a fifth conductive layer having a region functioning as a gate electrode of the third transistor is provided in the same layer as the sixth conductive layer; the first conductive layer is always electrically connected to the second conductive layer via the sixth conductive layer; the first conductive layer is provided in the same layer as a seventh conductive layer having a region that functions as the third signal line, In a plan view, the sixth conductive layer has a region intersecting with the seventh conductive layer. Semiconductor device.

11. The semiconductor device includes first to fifth transistors, one of a source electrode and a drain electrode of the first transistor is always electrically connected to a clock signal line; the other of the source electrode and the drain electrode of the first transistor is always electrically connected to a gate signal line; one of a source electrode and a drain electrode of the second transistor is always electrically connected to a first power supply line; the other of the source electrode and the drain electrode of the second transistor is always electrically connected to the gate signal line; one of a source electrode and a drain electrode of the third transistor is always electrically connected to a first signal line; the other of the source electrode and the drain electrode of the third transistor is always electrically connected to one of the source electrode and the drain electrode of the fifth transistor; a gate electrode of the third transistor is always electrically connected to a second signal line; one of a source electrode and a drain electrode of the fourth transistor is always electrically connected to a third signal line; the other of the source electrode and the drain electrode of the fourth transistor is always electrically connected to one of the source electrode and the drain electrode of the fifth transistor; a gate electrode of the fourth transistor is always electrically connected to a fourth signal line; the other of the source electrode and the drain electrode of the fifth transistor is always electrically connected to the gate electrode of the first transistor; a gate electrode of the fifth transistor is always electrically connected to a second power supply line; a signal from a fifth signal line is input to a gate electrode of the second transistor; W (channel width) / L (channel length) of the first transistor is larger than W / L of the second transistor, the W / L of the first transistor is greater than the W / L of the third transistor; the W / L of the first transistor is greater than the W / L of the fourth transistor; the W / L of the third transistor is 0.9 to 1.1 times the W / L of the fourth transistor, a first conductive layer having a region functioning as one of a source electrode and a drain electrode of the third transistor is provided in the same layer as a second conductive layer having a region functioning as the first signal line, a third conductive layer having a region functioning as a gate electrode of the third transistor is provided in the same layer as the fourth conductive layer; the first conductive layer is always electrically connected to the second conductive layer via the fourth conductive layer; Semiconductor device.

12. The semiconductor device includes first to fifth transistors, one of a source electrode and a drain electrode of the first transistor is always electrically connected to a clock signal line; the other of the source electrode and the drain electrode of the first transistor is always electrically connected to a gate signal line; one of a source electrode and a drain electrode of the second transistor is always electrically connected to a first power supply line; the other of the source electrode and the drain electrode of the second transistor is always electrically connected to the gate signal line; one of a source electrode and a drain electrode of the third transistor is always electrically connected to a first signal line; the other of the source electrode and the drain electrode of the third transistor is always electrically connected to one of the source electrode and the drain electrode of the fifth transistor; a gate electrode of the third transistor is always electrically connected to a second signal line; one of a source electrode and a drain electrode of the fourth transistor is always electrically connected to a third signal line; the other of the source electrode and the drain electrode of the fourth transistor is always electrically connected to one of the source electrode and the drain electrode of the fifth transistor; a gate electrode of the fourth transistor is always electrically connected to a fourth signal line; the other of the source electrode and the drain electrode of the fifth transistor is always electrically connected to the gate electrode of the first transistor; a gate electrode of the fifth transistor is always electrically connected to a second power supply line; a signal from a fifth signal line is input to a gate electrode of the second transistor; W (channel width) / L (channel length) of the first transistor is larger than W / L of the second transistor, the W / L of the first transistor is greater than the W / L of the third transistor; the W / L of the first transistor is greater than the W / L of the fourth transistor; the W / L of the third transistor is 0.9 to 1.1 times the W / L of the fourth transistor, a first conductive layer having a region functioning as one of a source electrode and a drain electrode of the third transistor is provided in the same layer as a second conductive layer having a region functioning as the first signal line, a third conductive layer having a region functioning as a gate electrode of the third transistor is provided in the same layer as the fourth conductive layer; the first conductive layer is always electrically connected to the second conductive layer via the fourth conductive layer; the first conductive layer is provided in the same layer as a fifth conductive layer having a region that functions as the third signal line, In a plan view, the fourth conductive layer has a region intersecting with the fifth conductive layer. Semiconductor device.

13. In any one of claims 1 to 12, The semiconductor device is capable of switching a scanning direction by switching a potential of the first signal line and a potential of the third signal line.

14. In claim 13, during a period in which the potential of the first signal line is at a high level and the potential of the third signal line is at a low level, the scanning direction is a first scanning direction; In a period in which the potential of the first signal line is at a low level and the potential of the third signal line is at a high level, the scanning direction is the second scanning direction.

15. A semiconductor device according to any one of claims 1 to 14, and a pixel, The pixel is connected to the gate signal line, The pixel includes a liquid crystal element, A display device in which the drive mode of the liquid crystal element is an FFS mode.

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