Semiconductor device and electronic apparatus

Abstract

To provide a semiconductor device that can maintain the accuracy of determining a failure of a sound reproduction device despite a change in temperature.SOLUTION: A semiconductor device comprises: a test signal generation circuit that modulates a test signal to generate a fifth modulated signal and a sixth modulated signal; a first amplifier circuit that outputs a third amplified signal and a fourth amplified signal obtained by amplifying the fifth modulated signal and the sixth modulated signal to a first output terminal and a second output terminal; a second amplifier circuit that outputs a seventh amplified signal and an eighth amplified signal obtained by amplifying the fifth modulated signal and the sixth modulated signal to a third output terminal and a fourth output terminal; a first peak frequency detection circuit that measures the electric potential difference between the first output terminal and the second output terminal and detects a first peak frequency; a second peak frequency detection circuit that measures the electric potential difference between the third output terminal and the fourth output terminal and detects a second peak frequency; and a determination circuit that determines whether the difference between the first peak frequency and the second peak frequency is included in a predetermined reference frequency difference range.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device and an electronic device. [Background technology]

[0002] Patent document 1 describes a speaker failure notification device in which a control unit measures the impedance that changes with structural changes in the speaker, determines whether the measured impedance is within a predetermined range, and if it determines that the impedance is not within that range, notifies the user that the speaker is malfunctioning. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2012-199854 A Summary of the Invention [Problem to be solved by the invention]

[0004] The speaker failure notification device described in Patent Document 1 determines whether the measured impedance is within a predetermined range, so if the speaker impedance changes due to a change in temperature, there is a risk that the speaker failure cannot be correctly determined. [Means for solving the problem]

[0005] One aspect of the semiconductor device according to the present invention is a first output terminal connected to a first terminal of the first sound reproduction device; a second output terminal connected to a second terminal of the first sound reproduction device; a third output terminal connected to the first terminal of the second sound reproduction device; a fourth output terminal connected to the second terminal of the second sound reproduction device; a first modulation circuit that modulates a signal based on a first sound source signal in a first operation mode to output a first modulated signal and a second modulated signal; a second modulation circuit that modulates a signal based on a second sound source signal in the first operation mode to output a third modulated signal and a fourth modulated signal; a test signal generating circuit that, in a second operation mode, generates a fifth modulated signal and a sixth modulated signal by modulating a test signal whose frequency is changed within a preset frequency band; a first amplifier circuit that, in the first operation mode, outputs a first amplified signal obtained by amplifying the first modulated signal to the first output terminal, and outputs a second amplified signal obtained by amplifying the second modulated signal to the second output terminal, and, in the second operation mode, outputs a third amplified signal obtained by amplifying the fifth modulated signal to the first output terminal, and outputs a fourth amplified signal obtained by amplifying the sixth modulated signal to the second output terminal; a second amplifier circuit that, in the first operation mode, outputs a fifth amplified signal obtained by amplifying the third modulated signal to the third output terminal, and outputs a sixth amplified signal obtained by amplifying the fourth modulated signal to the fourth output terminal, and, in the second operation mode, outputs a seventh amplified signal obtained by amplifying the fifth modulated signal to the third output terminal, and outputs an eighth amplified signal obtained by amplifying the sixth modulated signal to the fourth output terminal; a first peak frequency detection circuit that measures a potential difference between the first output terminal and the second output terminal in the second operation mode and detects a first peak frequency, which is a frequency of the test signal at which an impedance of the first sound reproduction device becomes a peak; a second peak frequency detection circuit that measures a potential difference between the third output terminal and the fourth output terminal in the second operation mode, and detects a second peak frequency, which is a frequency of the test signal at which an impedance of the second sound reproduction device becomes a peak; a determination circuit that determines whether a difference between the first peak frequency and the second peak frequency is within a predetermined reference frequency difference range; Equipped with.

[0006] One aspect of the electronic device according to the present invention is One aspect of the semiconductor device; the first sound reproduction device; the second sound reproduction device; Equipped with. [Brief description of the drawings]

[0007] [Figure 1] 1 is a diagram showing a configuration example of a semiconductor device according to an embodiment of the present invention; [Diagram 2] FIG. 2 shows an example of pulse width modulation for generating a modulated signal DOP. [Diagram 3] FIG. 2 is a diagram showing an example of pulse width modulation for generating a modulated signal DON. [Figure 4] 4 is a diagram showing an example of a difference between a modulated signal DOP and a modulated signal DON; [Diagram 5] 5 is a diagram showing an example of the relationship between the state of a speaker and impedance characteristics. [Figure 6] FIG. 2 is a diagram showing a configuration example of a class D amplifier, a peak frequency detection circuit, and their peripheral circuits. [Figure 7] FIG. 2 is a diagram showing a configuration example of a class D amplifier, a peak frequency detection circuit, and their peripheral circuits. [Figure 8] FIG. 13 is a diagram showing an example of the configuration of a differential low-pass filter. [Figure 9] FIG. 4 is a diagram showing an example of a relationship between a test signal and a peak frequency and a peak voltage. [Figure 10] FIG. 4 is a graph showing the temperature dependence of peak impedance and peak frequency. [Figure 11] 4 is a graph showing the temperature dependence of the waveform of the output voltage of a differential low-pass filter. [Figure 12] FIG. 11 is a flowchart showing an example of a processing procedure of an inspection circuit in an inspection mode. [Figure 13] FIG. 13 is a diagram showing another example of pulse width modulation for generating the modulated signal DON. [Figure 14] FIG. 13 is a diagram showing another example of the difference between the modulated signal DOP and the modulated signal DON. [Figure 15] FIG. 2 is a functional block diagram of the electronic device according to the embodiment. [Figure 16] FIG. 1 is a diagram showing an example of the configuration of a warning device, which is an example of an electronic device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] Preferred embodiments of the present invention will be described in detail below with reference to the drawings. Note that the embodiments described below do not unduly limit the contents of the present invention described in the claims. Furthermore, not all of the configurations described below are necessarily essential components of the present invention.

[0009] 1. Semiconductor Devices 1-1.Embodiment 1-1-1. Configuration of semiconductor device Fig. 1 is a diagram showing a configuration example of a semiconductor device according to the present embodiment. As shown in Fig. 1, the semiconductor device 1 according to the present embodiment includes a communication interface circuit 10, a memory 20, switches 81, 81a, 82, and 82a, a sound source reproducing circuit 100, and an inspection circuit 110. The semiconductor device 1 is connected to sound reproducing devices 3 and 3a. The semiconductor device 1 may be a one-chip semiconductor integrated circuit device, may be composed of semiconductor integrated circuit devices on multiple chips, or may be at least partially composed of electronic components other than semiconductor integrated circuit devices.

[0010] The semiconductor device 1 has three operation modes: a normal operation mode, a test mode, and a test mode. The normal operation mode is an operation mode in which the sound reproduction devices 3 and 3a reproduce sound. The test mode is an operation mode in which the state of the sound reproduction devices 3 and 3a is determined.

[0011] The memory 20 stores n pieces of sound source data 21-1 to 21-n, where n is an integer equal to or greater than 1. The memory 20 may be, for example, a flash memory. Each of the sound source data 21-1 to 21-n is, for example, pulse code modulated audio data. The sound source data 21-1 to 21-n may be data that is the basis of various sounds, such as sounds that imitate the voice of a person when speaking, mechanical warning sounds, sound effects, etc.

[0012] The communication interface circuit 10 is a circuit that performs data communication with the micro control unit 2. The communication interface circuit 10 may be, for example, an SPI interface circuit or an I2C interface circuit. SPI is an abbreviation for Serial Peripheral Interface, and I2C is an abbreviation for Inter-Integrated Circuit.

[0013] The communication interface circuit 10 receives various commands transmitted from the microcontrol unit 2 and generates various control signals according to the received commands. For example, when the communication interface circuit 10 receives a command to switch the operation mode of the semiconductor device 1 to a normal operation mode or an inspection mode, the communication interface circuit 10 generates a control signal for switching the connection of the switches 41, 41a, 42, 42a, 81, 81a, 82, 82a according to the operation mode. Also, for example, when the communication interface circuit 10 receives a sound source reproduction command for causing the sound reproduction device 3 to reproduce the sound source data 21-i, the communication interface circuit 10 reads the sound source data 21-i from the memory 20 and inputs it to the sound source reproduction circuit 100 as a sound source signal DI1, and instructs the sound reproduction circuit 100 to reproduce the sound source data 21-i by the sound reproduction device 3. The sound source data 21-i is any one of the sound source data 21-1 to 21-n stored in the memory 20. Also, for example, when the communication interface circuit 10 receives a sound source reproduction command for causing the sound reproduction device 3a to reproduce the sound source data 21-j, the communication interface circuit 10 reads out the sound source data 21-j from the memory 20 and inputs it to the sound source reproduction circuit 100 as a sound source signal DI2, and instructs the sound source reproduction circuit 100 to reproduce the sound source data 21-j by the sound reproduction device 3a. The sound source data 21-j is any one of the sound source data 21-1 to 21-n stored in the memory 20. Also, for example, when the communication interface circuit 10 receives a sound source stop command for the sound source data 21-i or sound source data 21-j being reproduced, the communication interface circuit 10 instructs the sound source reproduction circuit 100 to stop reproduction. Also, for example, when the communication interface circuit 10 receives various setting commands related to sound source reproduction, the communication interface circuit 10 performs various settings on the sound source reproduction circuit 100.

[0014] In this embodiment, the sound source signals DI1 and DI2 input to the sound source reproduction circuit 100 are pulse code modulated signals. When the sound source data 21-1 to 21-n are compressed audio data or adaptive differential pulse code modulated audio data, the sound source data 21-i and 21-j to be reproduced are converted by a decoder (not shown) into the sound source signals DI1 and DI2, which are pulse code modulated signals.

[0015] The sound source reproducing circuit 100 converts the sound source signal DI1 into amplified signals DOXP and DOXN, which are sound signals, and outputs them to the sound reproducing device 3. As a result, sounds corresponding to the amplified signals DOXP and DOXN are output from the sound reproducing device 3. The sound source reproducing circuit 100 also converts the sound source signal DI2 into amplified signals DOXPa and DOXNa, which are sound signals, and outputs them to the sound reproducing device 3a. As a result, sounds corresponding to the amplified signals DOXPa and DOXNa are output from the sound reproducing device 3a. For example, the sound reproducing devices 3 and 3a may be speakers or buzzers. The sounds output from the sound reproducing devices 3 and 3a may be, for example, sounds that imitate the voice of a person when speaking, or various sounds such as mechanical warning sounds and sound effects.

[0016] As shown in FIG. 1, in this embodiment, the sound source reproducing circuit 100 includes a modulation circuit 30, switches 41 and 42, and an amplifier circuit 50.

[0017] The modulation circuit 30 receives the sound source signal DI1, modulates a signal based on the sound source signal DI1, and outputs modulated signals DOP and DON. The signal based on the sound source signal DI1 may be the sound source signal DI1 itself, or may be a signal obtained by performing some processing on the sound source signal DI1. In this embodiment, the modulation circuit 30 includes a digital filter 31, a sigma-delta modulation circuit 32, and a pulse width modulation circuit 33.

[0018] The digital filter 31 is a low-pass filter that receives the sound source signal DI1 and outputs a signal DF that has been reduced in high-frequency noise contained in the sound source signal DI1. The sigma-delta modulation circuit 32 receives the signal DF from the digital filter 31, and oversamples the signal DF at a sampling ratio of n times and performs sigma-delta modulation to output a sigma-delta modulated signal DS in which noise is biased toward a high frequency band. n is an integer of 2 or more. Therefore, if the sampling frequency of the sound source signal DI1 is fs, the sampling frequency of the signal DF output from the digital filter 31 is fs, and the sampling frequency of the sigma-delta modulated signal DS is n×fs. The digital filter 31 functions as an anti-aliasing filter that reduces high-frequency noise that is folded back into the signal band by the oversampling of the sigma-delta modulation circuit 32.

[0019] The pulse width modulation circuit 33 pulse-width modulates the sigma-delta modulated signal DS to output the modulated signals DOP and DON. The modulated signals DOP and DON are each 1-bit digital signals. If the sampling frequency of the sigma-delta modulated signal DS is n×fs, then the sampling frequency of the modulated signals DOP and DON is n×m×fs. Here, if the number of bits of the sigma-delta modulated signal DS is M, then m=2 M It is.

[0020] In this manner, the modulation circuit 30 performs sigma-delta modulation on the signal obtained by digitally filtering the sound source signal DI1, and further performs pulse width modulation to output the modulated signals DOP and DON.

[0021] The pulse width modulation for generating the modulated signal DOP and the pulse width modulation for generating the modulated signal DON are different in type. FIG. 2 is a diagram showing an example of the pulse width modulation for generating the modulated signal DOP. FIG. 3 is a diagram showing an example of the pulse width modulation for generating the modulated signal DON. FIGS. 2 and 3 show an example in which the number of bits M of the sigma-delta modulated signal DS is 4. In FIGS. 2 and 3, the sigma-delta modulated signal DS is updated periodically with a period T, and the modulated signals DOP and DON are at a high level or a low level in each of the 16 sections T1 to T16 into which the period T is divided. That is, the length of the period T is 1 / (n×fs), and the length of each of the sections T1 to T16 is 1 / (n×m×fs).

[0022] As shown in FIG. 2, the higher the value of the sigma-delta modulated signal DS, the longer the time that the modulated signal DOP is at a high level. For example, when the sigma-delta modulated signal DS is "-7" in decimal, that is, "1001" in binary, the modulated signal DOP has one section T1 at a high level and 15 sections T2 to T16 at a low level. For example, when the sigma-delta modulated signal DS is "0" in decimal, that is, "0000" in binary, the modulated signal DOP has eight sections T1 to T8 at a high level and eight sections T9 to T16 at a low level. For example, when the sigma-delta modulated signal DS is "7" in decimal, that is, "0111" in binary, the modulated signal DOP has 15 sections T1 to T15 at a high level and one section T16 at a low level.

[0023] As shown in FIG. 3, the higher the value of the sigma-delta modulated signal DS, the shorter the time that the modulated signal DON is at high level. For example, when the sigma-delta modulated signal DS is "-7" in decimal, that is, "1001" in binary, the modulated signal DON has 15 sections T1 to T15 at high level and one section T16 at low level. Also, for example, when the sigma-delta modulated signal DS is "0" in decimal, that is, "0000" in binary, the modulated signal DON has 8 sections T1 to T8 at high level and 8 sections T9 to T16 at low level. Also, for example, when the sigma-delta modulated signal DS is "7" in decimal, that is, "0111" in binary, the modulated signal DON has 1 section T1 at high level and 1 section T2 at low level. The signal level is at a low level for 15 intervals T2 to T16.

[0024] Therefore, for example, when the sigma-delta modulated signal DS is the decimal numbers "-7", "0", and "7", the difference between the modulated signal DOP and the modulated signal DON is as shown in FIG.

[0025] 1, the switch 41 outputs either the modulated signal DOP or the modulated signal TP to the class-D amplifier 51P of the amplifier circuit 50 in response to a control signal output from the communication interface circuit 10. Specifically, the switch 41 outputs the modulated signal DOP to the class-D amplifier 51P when the operation mode of the semiconductor device 1 is the normal operation mode, and outputs the modulated signal TP to the class-D amplifier 51P when the operation mode of the semiconductor device 1 is the inspection mode.

[0026] Furthermore, the switch 42 outputs either the modulated signal DON or the modulated signal TN to the class D amplifier 51N of the amplifier circuit 50 in response to a control signal output from the communication interface circuit 10. Specifically, the switch 42 outputs the modulated signal DON to the class D amplifier 51N when the operation mode of the semiconductor device 1 is the normal operation mode, and outputs the modulated signal TN to the class D amplifier 51N when the operation mode of the semiconductor device 1 is the inspection mode.

[0027] In the normal operation mode, the amplifier circuit 50 receives the modulated signals DOP, DON, and outputs amplified signals DOXP, DOXN obtained by amplifying the modulated signals DOP, DON to the output terminals 91, 92 of the semiconductor device 1. In the inspection mode, the amplifier circuit 50 receives the modulated signals TP, TN, and outputs amplified signals DOXP, DOXN obtained by amplifying the modulated signals TP, TN to the output terminals 91, 92 of the semiconductor device 1.

[0028] In this embodiment, the amplifier circuit 50 includes two class D amplifiers 51P and 51N. In the normal operation mode, the class D amplifier 51P outputs the amplified signal DOXP obtained by amplifying the modulated signal DOP to the output terminal 91, and in the inspection mode, the class D amplifier 51P outputs the amplified signal DOXP obtained by amplifying the modulated signal TP to the output terminal 91. In the normal operation mode, the class D amplifier 51N outputs the amplified signal DOXN obtained by amplifying the modulated signal DON to the output terminal 92, and in the inspection mode, the class D amplifier 51N outputs the amplified signal DOXN obtained by amplifying the modulated signal TN to the output terminal 92. The output terminal 91 is connected to the terminal P1 of the sound reproducing device 3, and the output terminal 92 is connected to the terminal P2 of the sound reproducing device 3. The sound reproducing device 3 reproduces a sound having a volume corresponding to the voltage difference between the amplified signal DOXP and the amplified signal DOXN. In the normal operation mode, the sound reproducing device 3 preferably outputs a desired sound instructed by a sound source reproduction command, and in the inspection mode, preferably outputs a minute sound that is difficult for the human ear to hear. That is, the volume reproduced by the sound reproduction device 3 in the inspection mode is preferably smaller than the minimum volume reproduced by the sound reproduction device 3 in the normal operation mode. In other words, the voltage difference between the amplified signal DOXP and the amplified signal DOXN in the inspection mode is preferably smaller than the voltage difference between the amplified signal DOXP and the amplified signal DOXN when the minimum sound is output from the sound reproduction device 3 in the normal operation mode. This makes it difficult for the user to be aware that the semiconductor device 1 is operating in the inspection mode.

[0029] As shown in FIG. 1, the sound source reproducing circuit 100 further includes a modulation circuit 30a, switches 41a and 42a, and an amplifier circuit 50a.

[0030] The modulation circuit 30a receives the sound source signal DI2, modulates a signal based on the sound source signal DI2, and outputs modulated signals DOPa and DONa. The signal based on the sound source signal DI2 may be the sound source signal DI2 itself, or may be a signal obtained by performing some processing on the sound source signal DI2. In this embodiment, the modulation circuit 30a includes a digital filter 31a, a sigma-delta modulation circuit 32a, and a pulse width modulation circuit 33a.

[0031] The digital filter 31a receives the sound source signal DI2 and It is a low-pass filter that outputs a signal DFa with reduced high-frequency noise. The sigma-delta modulation circuit 32a receives the signal DFa from the digital filter 31a, and oversamples the signal DFa at a sampling ratio of n times and performs sigma-delta modulation to output a sigma-delta modulated signal DSa with noise biased toward a high frequency band. n is an integer of 2 or more. Therefore, if the sampling frequency of the sound source signal DI2 is fs, the sampling frequency of the signal DFa output from the digital filter 31a is fs, and the sampling frequency of the sigma-delta modulated signal DSa is n×fs. The digital filter 31a functions as an anti-aliasing filter that reduces high-frequency noise that is folded back into the signal band by the oversampling of the sigma-delta modulation circuit 32a.

[0032] The pulse width modulation circuit 33a pulse-width modulates the sigma-delta modulated signal DSa to output the modulated signals DOPa and DONa. The modulated signals DOPa and DONa are each 1-bit digital signals. If the sampling frequency of the sigma-delta modulated signal DSa is n×fs, then the sampling frequency of the modulated signals DOPa and DONa is n×m×fs. Here, if the number of bits of the sigma-delta modulated signal DSa is M, then m=2 M It is.

[0033] In this manner, the modulation circuit 30a performs sigma-delta modulation on the signal obtained by digitally filtering the sound source signal DI2, and further performs pulse width modulation to output the modulated signals DOPa and DONa.

[0034] The pulse width modulation method for generating the modulated signals DOPa and DONa is the same as the pulse width modulation method for generating the modulated signals DOP and DON shown in FIGS. 2 to 4, and therefore a description thereof will be omitted.

[0035] The switch 41a outputs either the modulated signal DOPa or the modulated signal TP to the class-D amplifier 51Pa of the amplifier circuit 50a in response to a control signal output from the communication interface circuit 10. Specifically, the switch 41a outputs the modulated signal DOPa to the class-D amplifier 51Pa when the operation mode of the semiconductor device 1 is the normal operation mode, and outputs the modulated signal TP to the class-D amplifier 51Pa when the operation mode of the semiconductor device 1 is the inspection mode.

[0036] Furthermore, the switch 42a outputs either the modulated signal DONa or the modulated signal TN to the class-D amplifier 51Na of the amplifier circuit 50a in response to a control signal output from the communication interface circuit 10. Specifically, the switch 42a outputs the modulated signal DONa to the class-D amplifier 51Na when the operation mode of the semiconductor device 1 is the normal operation mode, and outputs the modulated signal TN to the class-D amplifier 51Na when the operation mode of the semiconductor device 1 is the inspection mode.

[0037] In the normal operation mode, the amplifier circuit 50a receives modulated signals DOPa, DONa, and outputs amplified signals DOXPa, DOXNa obtained by amplifying the modulated signals DOPa, DONa to the output terminals 93, 94 of the semiconductor device 1. In the inspection mode, the amplifier circuit 50a receives modulated signals TP, TN, and outputs amplified signals DOXPa, DOXNa obtained by amplifying the modulated signals TP, TN to the output terminals 93, 94 of the semiconductor device 1.

[0038] In this embodiment, the amplifier circuit 50a includes two class-D amplifiers 51Pa and 51Na. In the normal operation mode, the class-D amplifier 51Pa outputs an amplified signal DOXPa obtained by amplifying the modulated signal DOPa to an output terminal 93, and in the inspection mode, outputs an amplified signal DOXPa obtained by amplifying the modulated signal TP to the output terminal 93. In the normal operation mode, the class-D amplifier 51Na outputs an amplified signal DOXNa obtained by amplifying the modulated signal DONa to an output terminal 94, and in the inspection mode, outputs an amplified signal DOXNa obtained by amplifying the modulated signal TN to an output terminal 94. The output terminal 93 is connected to a terminal P1a of the sound reproducing device 3a, and the output terminal 94 is connected to a terminal P2a of the sound reproducing device 3a. The sound reproducing device 3a reproduces a sound having a volume corresponding to the voltage difference between the amplified signal DOXPa and the amplified signal DOXNa. In the normal operation mode, the sound reproducing device 3a outputs a sound having a volume corresponding to the voltage difference between the amplified signal DOXPa and the amplified signal DOXNa. In the test mode, it is preferable that the desired sound instructed by the sound source playback command is output, and in the inspection mode, it is preferable that a minute sound that is difficult for the human ear to hear is output. That is, the volume reproduced by the sound reproduction device 3a in the test mode is smaller than the minimum volume reproduced by the sound reproduction device 3a in the normal operation mode. In other words, it is preferable that the voltage difference between the amplified signal DOXPa and the amplified signal DOXNa in the test mode is smaller than the voltage difference between the amplified signal DOXPa and the amplified signal DOXNa when the minimum sound is output from the sound reproduction device 3a in the normal operation mode. This makes it difficult for the user to be aware that the semiconductor device 1 is operating in the test mode.

[0039] The inspection circuit 110 is a circuit for inspecting the sound reproduction device 3 .

[0040] FIG. 5 is a diagram showing an example of the relationship between the state of a speaker, which is an example of the sound reproduction device 3, 3a, and the impedance characteristics. In FIG. 5, the horizontal axis is the frequency of the input signal of the speaker, and the vertical axis is the impedance value of the speaker. G1 is an example of the impedance characteristics when the speaker is normal. The peak frequency, which is the frequency of the input signal at which the impedance of the speaker peaks, varies depending on the type of speaker, but when the speaker is normal, it is at least included in the frequency band of 20 Hz or more, which is the lower limit of the human audible range, and 3 kHz or less, which is the frequency used for buzzer warning sounds. G2 is an example of the impedance characteristics when the magnet of the speaker is broken and removed. When the magnet of the speaker is removed, the speaker is left with only the coil, so the impedance value slowly increases as the frequency becomes higher, and the peak frequency disappears. G3 is an example of the impedance characteristics when the cone paper of the speaker is torn. When the cone paper, which is the vibration surface of the speaker, is torn, the bass sound is no longer produced and the peak frequency shifts to the higher frequency side.

[0041] In this way, the peak frequency changes depending on the state of the speaker. Therefore, in this embodiment, the inspection circuit 110 detects the peak frequency f1 of each of the sound reproduction devices 3 and 3a in the inspection mode. peak ,f2 peak Detect the peak frequency f1 peak ,f2 peak For example, if the sound reproduction devices 3 and 3a are the same type of speaker, and the sound reproduction devices 3 and 3a are normal, the peak frequency f1 peak ,f2 peak However, if one of the sound reproducing devices 3 and 3a fails, the peak frequency f1 peak ,f2 peak Since the difference between them becomes large and they do not match, the test circuit 110 can determine the state of the sound reproduction devices 3, 3a.

[0042] In this embodiment, the inspection circuit 110 includes a test signal generation circuit 60, a judgment circuit 61, a memory 62, and peak frequency detection circuits 70 and 70a. The test signal generation circuit 60, the judgment circuit 61, and the peak frequency detection circuits 70 and 70a operate in the inspection mode and stop operating in the normal operation mode.

[0043] The test signal generation circuit 60 generates the modulated signals TP and TN by modulating the test signal whose frequency has been changed in a preset frequency band. The frequency band in which the test signal generation circuit 60 changes the frequency of the test signal can be arbitrarily set by the micro control unit 2, and may be, for example, a frequency band of 10 Hz or more and 3 kHz or less. In this embodiment, the test signal generation circuit 60 pulse-width modulates the test signal to generate the modulated signals TP and TN. The method of pulse-width modulation by the test signal generation circuit 60 is the same as the method of pulse-width modulation by the pulse-width modulation circuits 33 and 33a.

[0044] The peak frequency detection circuit 70 measures the potential difference between the output terminal 91 and the output terminal 92, and detects a peak frequency f1, which is the frequency of the test signal at which the impedance of the sound reproduction device 3 becomes a peak. peak The peak frequency detection circuit 70 detects a peak voltage v 1 peak As described later, the peak frequency f1 is detected. peak and peak voltage v1 peak changes depending on the temperature of the sound reproducing device 3.

[0045] The peak frequency detection circuit 70a measures the potential difference between the output terminal 93 and the output terminal 94, and detects a peak frequency f2, which is the frequency of the test signal at which the impedance of the sound reproduction device 3a becomes a peak. peak The peak frequency detection circuit 70a detects a peak voltage v2 peak As described later, the peak frequency f2peak and peak voltage v2 peak varies depending on the temperature of the sound reproducing device 3a.

[0046] The determination circuit 61 detects the peak frequency f1 detected by the peak frequency detection circuit 70. peak and the peak frequency f2 detected by the peak frequency detection circuit 70a peak The determination circuit 61 determines whether the difference between the peak voltage v1 detected by the peak frequency detection circuit 70 is within a predetermined reference frequency difference range. The reference frequency difference range is a frequency range determined based on the difference between the peak frequencies of the sound reproduction devices 3 and 3a and the temperature characteristics of the peak frequency. peak and the peak voltage v2 detected by the peak frequency detection circuit 70a peak The determination circuit 61 further determines whether the difference between the peak frequency f1 and the reference voltage difference range is within a predetermined reference voltage difference range. The reference voltage difference range is a voltage range determined based on the difference in peak impedance between the sound reproduction devices 3 and 3a and the temperature characteristics of the peak impedance. Furthermore, in this embodiment, the determination circuit 61 peak and peak frequency f2 peak The result of judging whether the difference between the frequency and the peak voltage v1 is within the reference frequency difference range. peak and peak voltage v2 peak Based on the result of the determination as to whether the difference with respect to the reference voltage difference range or not, the state of the sound reproduction devices 3, 3a, such as the presence or absence of a malfunction of the sound reproduction devices 3, 3a, is determined. The process of the determination circuit 61 will be described in detail later.

[0047] The memory 62 includes a non-volatile memory (not shown), and constants α and β are stored in the non-volatile memory. The constant α is a constant for determining the aforementioned reference frequency difference range in consideration of the characteristic variation and temperature difference of the sound reproduction devices 3, 3a, and the constant β is a constant for determining the aforementioned reference voltage difference range in consideration of the characteristic variation and temperature difference of the sound reproduction devices 3, 3a. The memory 62 also includes a volatile memory (not shown) for storing various types of data that are temporarily created.

[0048] The switch 81 switches between electrically connecting and disconnecting the output terminal 91 of the semiconductor device 1 and the peak frequency detection circuit 70 in response to a control signal output from the communication interface circuit 10. Specifically, the switch 81 electrically disconnects the output terminal 91 and the peak frequency detection circuit 70 when the operation mode of the semiconductor device 1 is the normal operation mode, and electrically connects the output terminal 91 and the peak frequency detection circuit 70 when the operation mode of the semiconductor device 1 is the inspection mode.

[0049] Similarly, the switch 82 switches between electrically connecting or disconnecting the output terminal 92 of the semiconductor device 1 and the peak frequency detection circuit 70 in response to a control signal output from the communication interface circuit 10. Specifically, the switch 82 electrically disconnects the output terminal 92 and the peak frequency detection circuit 70 when the operation mode of the semiconductor device 1 is the normal operation mode, and electrically connects the output terminal 92 and the peak frequency detection circuit 70 when the operation mode of the semiconductor device 1 is the inspection mode.

[0050] In this manner, the peak frequency detection circuit 70 is electrically disconnected from the output terminals 91 and 92 by the switches 81 and 82 in the normal operation mode, and is electrically connected to the output terminals 91 and 92 in the inspection mode, and measures the potential difference between the output terminals 91 and 92 to detect the peak frequency f1. peak and peak voltage v1 peak Detect.

[0051] The switch 81a switches between electrically connecting and disconnecting the output terminal 93 of the semiconductor device 1 and the peak frequency detection circuit 70a in response to a control signal output from the communication interface circuit 10. Specifically, the switch 81a electrically disconnects the output terminal 93 and the peak frequency detection circuit 70a when the operation mode of the semiconductor device 1 is the normal operation mode, and electrically connects the output terminal 93 and the peak frequency detection circuit 70a when the operation mode of the semiconductor device 1 is the inspection mode.

[0052] Similarly, the switch 82a switches between electrically connecting and disconnecting the output terminal 94 of the semiconductor device 1 and the peak frequency detection circuit 70a in response to a control signal output from the communication interface circuit 10. Specifically, the switch 82a electrically disconnects the output terminal 94 and the peak frequency detection circuit 70a when the operation mode of the semiconductor device 1 is the normal operation mode, and electrically connects the output terminal 94 and the peak frequency detection circuit 70a when the operation mode of the semiconductor device 1 is the inspection mode.

[0053] In this way, the peak frequency detection circuit 70a is electrically disconnected from the output terminals 93 and 94 by the switches 81a and 82a in the normal operation mode, and is electrically connected to the output terminals 93 and 94 in the inspection mode, and measures the potential difference between the output terminals 93 and 94 to detect the peak frequency f2 peak and peak voltage v2 peak Detect.

[0054] When the communication interface circuit 10 receives a command to read out information on the determination result by the determination circuit 61 from the micro control unit 2, it acquires the information on the determination result from the determination circuit 61 and transmits it to the micro control unit 2. The micro control unit 2 recognizes the state of the sound reproduction devices 3, 3a based on the information on the determination result, and can perform various processes according to the state of the sound reproduction devices 3, 3a.

[0055] 1-1-2.Determining the status of the sound playback device 6 and 7 are diagrams showing configuration examples of the class-D amplifiers 51P and 51N, the peak frequency detection circuit 70, and the peripheral circuits thereof. Fig. 6 shows the configuration in the normal operation mode, and Fig. 7 shows the configuration in the inspection mode.

[0056] As shown in Fig. 6 and Fig. 7, the class D amplifier 51P has a plurality of inverter circuits 201-1 to 201-n, and the class D amplifier 51N has a plurality of inverter circuits 202-1 to 202-n. n is an integer of 2 or more, and may be, for example, about 10 to 100. Each of the inverter circuits 201-1 to 201-n is configured with a pair of a PMOS transistor and an NMOS transistor, and an output terminal which is a node where the drain of the PMOS transistor and the drain of the NMOS transistor are connected is connected to the output terminal 91. Similarly, each of the inverter circuits 202-1 to 202-n is configured with a pair of a PMOS transistor and an NMOS transistor, and an output terminal which is a node where the drain of the PMOS transistor and the drain of the NMOS transistor are connected is connected to the output terminal 92.

[0057] 6, in the normal operation mode, a modulation signal DOP is input to each input terminal of the inverter circuits 201-1 to 201-n of the class-D amplifier 51P via a switch 41, and a modulation signal DON is input to each input terminal of the inverter circuits 202-1 to 202-n of the class-D amplifier 51N via a switch 42. That is, in the normal operation mode, the inverter circuits 201-1 to 201-n of the class-D amplifier 51P are connected in parallel between the modulation circuit 30 and the output terminal 91 of the semiconductor device 1, and the inverter circuits 202-1 to 202-n of the class-D amplifier 51N are connected in parallel between the modulation circuit 30 and the output terminal 92 of the semiconductor device 1. As a result, the on-resistance R1 of the class-D amplifier 51P is onP is 1 / n of the on-resistance of the inverter circuit 201-1, and the on-resistance R 1 onN is 1 / n of the on-resistance of the inverter circuit 202-1.

[0058] The amplifier circuit 50 amplifies the modulated signal DOP to output an amplified signal DOXP to an output terminal 91, and amplifies the modulated signal DON to output an amplified signal DOXN to an output terminal 92. The output terminals 91 and 92 are connected to the terminals P1 and P2 of the sound reproducing device 3, respectively. An impedance R1 between the terminals P1 and P2 sp is, for example, 4Ω to 128Ω, and in the normal operation mode, the on-resistance R1 of the class D amplifier 51P onP and the on-resistance R1 of the class D amplifier 51N onN is the impedance R1 of the sound reproduction device 3 sp It is about 1 / 10 to 1 / 100 of that.

[0059] Furthermore, as shown in FIG. 6, in the normal operation mode, the switches 81 and 82 are non-conductive, and the peak frequency detection circuit 70 is electrically disconnected from the output terminals 91 and 92 of the semiconductor device 1.

[0060] On the other hand, as shown in FIG. 7, in the inspection mode, a modulated signal TP is input to each input terminal of some of the inverter circuits 201-1 to 201-n included in the class-D amplifier 51P via the switch 41, and each output terminal of the other inverter circuits 201-1 to 201-n becomes high impedance. For example, in the inspection mode, a modulated signal TP is input to the input terminal of the inverter circuit 201-1, and each output terminal of the inverter circuits 201-2 to 201-n becomes high impedance. Similarly, a modulated signal TN is input to each input terminal of some of the inverter circuits 202-1 to 202-n included in the class-D amplifier 51N via the switch 42, and each output terminal of the other inverter circuits 202-1 to 202-n becomes high impedance. For example, in the inspection mode, a modulated signal TN is input to the input terminal of the inverter circuit 202-1, and each output terminal of the inverter circuits 202-2 to 202-n becomes high impedance. This reduces, for example, the on-resistance R1 of the class D amplifier 51P. onP and the on-resistance R1 of the class D amplifier 51N onN is the impedance R1 sp It is about the same as:

[0061] Furthermore, as shown in FIG. 7, in the inspection mode, the switches 81 and 82 are conductive, and the peak frequency detection circuit 70 is electrically connected to the output terminals 91 and 92 of the semiconductor device 1.

[0062] The peak frequency detection circuit 70 includes a differential low-pass filter 71 , an A / D conversion circuit 72 , and a peak time measurement circuit 73 .

[0063] In the test mode, the differential low-pass filter 71 receives the voltages of the output terminals 91 and 92 via the switches 81 and 82. That is, the differential low-pass filter 71 receives the amplified signals DOXP and DOXN, reduces high-frequency noise components superimposed on the amplified signals DOXP and DOXN by pulse width modulation, and outputs a voltage V' corresponding to the potential difference between the amplified signals DOXP and DOXN. The cutoff frequency of the differential low-pass filter 71 is higher than the maximum frequency of the frequency band in which the test signal generation circuit 60 changes the frequency of the test signal. For example, when the test signal generation circuit 60 changes the frequency of the test signal in a frequency band of 10 Hz to 3 kHz, the cutoff frequency of the differential low-pass filter 71 is higher than 3 kHz. Since the cutoff frequency of the differential low-pass filter 71 is higher than the maximum frequency of the frequency band in which the frequency of the test signal is changed, the frequency components included in the frequency band are not attenuated by the differential low-pass filter 71.

[0064] Fig. 8 is a diagram showing an example of the configuration of the differential low-pass filter 71. As shown in Fig. 8, the differential low-pass filter 71 includes an operational amplifier 211, five resistors 212, 213, 214, 216, and 218, and three capacitors 215, 217, and 219.

[0065] In the inspection mode, an amplified signal DOXP output to the output terminal 91 of the semiconductor device 1 is input to one end of the resistor 212. Furthermore, an amplified signal DOXN output to the output terminal 92 of the semiconductor device 1 is input to one end of the resistor 213. The other end of the resistor 212, one end of the resistor 214, and one end of the capacitor 215 are connected to the non-inverting input terminal of the operational amplifier 211. The other end of the resistor 213, one end of the resistor 216, one end of the capacitor 217, one end of the resistor 218, and one end of the capacitor 219 are connected to the inverting input terminal of the operational amplifier 211.

[0066] The other end of the resistor 214 and the other end of the capacitor 215 are connected to the output terminal of the operational amplifier 211. The other end of the resistor 216 and the other end of the capacitor 217 are grounded, and the other end of the resistor 218 and the other end of the capacitor 219 are supplied with a power supply voltage.

[0067] The differential low-pass filter 71 configured in this manner reduces high-frequency noise components superimposed on the amplified signals DOXP, DOXN by pulse width modulation, and outputs a voltage V' corresponding to the potential difference between the amplified signals DOXP, DOXN, i.e., the potential difference between output terminals 91 and 92, from the output terminal of operational amplifier 211. When the power supply voltage is VDD and the ground voltage is 0V, if the potential difference between output terminals 91 and 92 in which the high-frequency noise components have been reduced is positive, voltage V' becomes higher than VDD×1 / 2, and when the potential difference between output terminals 91 and 92 in which the high-frequency noise components have been reduced is negative, voltage V' becomes lower than VDD×1 / 2.

[0068] The amplitude voltage V'(pp) of the voltage V' and the impedance R1 of the sound reproducing device 3 sp , On-resistance R1 of Class D amplifier 51P onP and the on-resistance R1 of the class D amplifier 51N onN There is a relationship between the impedance R1 and the impedance R2 as shown in formula (1). sp The larger the impedance R1, the larger the amplitude of the voltage V'. sp When the voltage V' reaches its peak, the amplitude of the voltage V' is maximum.

[0069]

number

[0070] Returning to the explanation of Fig. 7, the A / D conversion circuit 72 converts the output voltage V' of the differential low-pass filter 71 into an m-bit digital signal and outputs it as m-bit data DT, where m is an integer equal to or greater than 2. This integer m is set to an appropriate value according to requirements such as the detection accuracy of the peak frequency and the size of the peak frequency detection circuit 70.

[0071] The peak time measurement circuit 73 measures the peak time, which is the time when the potential difference between the output terminal 91 and the output terminal 92 is maximum, based on the data DT which is the output signal of the A / D conversion circuit 72. Specifically, the peak time measurement circuit 73 measures the time when the data DT is maximum as the peak time. Furthermore, the peak time measurement circuit 73 measures the output voltage V' of the differential low-pass filter 71 at the peak time as the peak voltage. Specifically, the peak time measurement circuit 73 measures the maximum value of the data DT as the peak voltage.

[0072] As mentioned above, the impedance R1 of the sound reproduction device 3 sp When the impedance R1 of the sound reproducing device 3 is maximized, sp When the impedance R1 sp is the peak impedance R1 peak When the frequency of the test signal changes sequentially at a predetermined timing, the impedance R1 of the sound reproducing device 3 is calculated from the peak time measured by the peak time measuring circuit 73. sp is the peak impedance R1 peak and A peak frequency, which is a frequency at which the test signal reaches a maximum, is uniquely determined. In this manner, in the inspection mode, the peak frequency detection circuit 70 detects the peak frequency by measuring the peak time, which is the time at which the potential difference between the output terminal 91 and the output terminal 92 is maximized. In addition, in the inspection mode, the peak frequency detection circuit 70 further detects a peak voltage, which is a voltage obtained by amplifying the potential difference between the output terminal 91 and the output terminal 92 when the frequency of the test signal is the peak frequency.

[0073] Figure 9 shows the test signal and peak frequency f1 in the test mode. peak and peak voltage v1 peak 9 is a diagram showing an example of the relationship between the peak frequency f1 of the test signal and the amplitude of the test signal. In the example of FIG. 9, the test signal generating circuit 60 continuously changes the frequency of the test signal in a frequency band of 10 Hz to 3 kHz while maintaining the amplitude of the test signal at a constant voltage V1. Then, when the sound reproducing device 3 is normal, the peak frequency f1 of the test signal peak The output voltage V' of the differential low-pass filter 71 is the peak voltage v1 peak On the other hand, when the sound reproducing device 3 breaks down, the peak frequency f1 peak and peak voltage v1 peak 9, when a disconnection fault occurs between the semiconductor device 1 and the sound reproducing device 3, the output voltage V' of the differential low-pass filter 71 is fixed to the power supply voltage. Therefore, the normal peak voltage v1 peak A predetermined voltage that is higher than the power supply voltage of the differential low-pass filter 71 and lower than the power supply voltage of the differential low-pass filter 71 is set as V err Then, the determination circuit 61 determines whether the output voltage V' of the differential low-pass filter 71 is equal to or smaller than the voltage V err If the data DT is higher than the voltage V err If the digital value is greater than the digital value corresponding to, it can be determined that a wire breakage has occurred.

[0074] As shown in Figure 10, the peak impedance R1 peak and peak frequency f1 peak changes with temperature. Impedance R1 spis larger as the temperature of the sound reproducing device 3 is higher, and is smaller as the temperature of the sound reproducing device 3 is lower. For example, if the temperature range in which the operation of the sound reproducing device 3 is guaranteed is −40° C. to 80° C., the peak impedance R1 at a high temperature such as 80° C. peak_High is the peak impedance R1 at normal temperature such as 25℃ peak_Nor Also, the peak impedance R1 at low temperatures such as -40°C is peak_Low is the peak impedance R1 at normal temperature such as 25℃ peak_Nor As shown in Figure 10, the peak frequency f1 peak The higher the temperature of the sound reproducing device 3, the lower the peak frequency f1. peak_High is the peak frequency f1 at normal temperature such as 25°C peak_Nor Also, the peak frequency f1 at low temperatures such as -40°C is peak_Low is the peak frequency f1 at normal temperature such as 25°C peak_Nor Higher than.

[0075] Peak impedance R1 peak and peak frequency f1 peak varies with temperature, so that the waveform of the output voltage V' of the differential low-pass filter 71 also varies with temperature, as shown in FIG.

[0076] The configurations of the class D amplifiers 51Pa, 51Na, the peak frequency detection circuit 70a, and the peripheral circuits are the same as those in Figs. 6 and 7, and therefore illustration and description thereof will be omitted. That is, like the peak frequency detection circuit 70, the peak frequency detection circuit 70a includes a differential low-pass filter 71, an A / D conversion circuit 72, and a peak time measurement circuit 73. Also, the configuration of the differential low-pass filter 71 included in the peak frequency detection circuit 70a is the same as that in Fig. 8, and therefore illustration and description thereof will be omitted. Also, in the test mode, the test signal and the peak frequency f2 peak and peak voltage v2 peak The relationship between the peak impedance R2 of the sound reproducing device 3a and the peak impedance R3 of the sound reproducing device 3a is the same as that in FIG. peak and peak frequency f2peak The temperature dependence of the waveform of the output voltage V' of the differential low-pass filter 71 included in the peak frequency detection circuit 70a is the same as that in Fig. 10, and therefore illustration and description thereof will be omitted. Also, the temperature dependence of the waveform of the output voltage V' of the differential low-pass filter 71 included in the peak frequency detection circuit 70a is the same as that in Fig. 11, and therefore illustration and description thereof will be omitted.

[0077] Here, when both the sound reproducing devices 3 and 3a are normal, the peak frequency f1 peak ,f2 peak changes with temperature in the same way. Therefore, when the temperatures of the sound reproduction devices 3 and 3a change in the same way, the peak frequency f1 peak and peak frequency f2 peak Therefore, the determination circuit 61 determines whether the peak frequency f1 detected by the peak frequency detection circuit 70 is a peak and the peak frequency f2 detected by the peak frequency detection circuit 70a peak It is determined whether the difference between the frequency and the reference frequency is within a predetermined reference frequency difference range.

[0078] Similarly, when both the sound reproducing devices 3 and 3a are normal, the peak impedance R1 peak ,R2 peak changes with temperature in the same way. Therefore, when the temperature of the sound reproduction devices 3 and 3a changes in the same way, the peak impedance R1 peak and peak impedance R2 peak Therefore, the determination circuit 61 determines whether the peak voltage v1 detected by the peak frequency detection circuit 70 is peak and the peak voltage v2 detected by the peak frequency detection circuit 70a peak It is determined whether the difference between the two is within a predetermined reference voltage difference range.

[0079] 1-1-3. Inspection mode processing procedure In this embodiment, when the communication interface circuit 10 receives a command to switch the operation mode of the semiconductor device 1 to the inspection mode from the micro control unit 2, the operation mode of the semiconductor device 1 is switched to the inspection mode. Also, when the supply of power supply voltage to the semiconductor device 1 starts, the operation mode of the semiconductor device 1 may be automatically switched to the inspection mode. Then, the inspection circuit 110 executes a predetermined process in the inspection mode.

[0080] FIG. 12 is a flow chart showing an example of a processing procedure of the inspection circuit 110 in the inspection mode.

[0081] First, in step S1, the determination circuit 61 sets the constants α and β. The constant α is a constant for determining the aforementioned reference frequency difference range in consideration of the characteristic variation and temperature difference of the sound reproduction devices 3 and 3a, and the constant β is a constant for determining the aforementioned reference voltage difference range in consideration of the characteristic variation and temperature difference of the sound reproduction devices 3 and 3a. As described above, the constants α and β are stored in the nonvolatile memory of the memory 62, and the determination circuit 61 reads out the constants α and β from the nonvolatile memory and sets them in a predetermined internal register.

[0082] Next, in step S2, the test signal generating circuit 60 starts outputting a test signal whose frequency has been swept, and in step S3, the determination circuit 61 determines whether the peak frequency f1 peak , peak voltage v1 peak In step S4, the determination circuit 61 obtains the peak frequency f2 peak , peak voltage v2 peak Get the.

[0083] Next, in step S5, the determination circuit 61 determines whether the peak voltage v1 peak ,v2 peak Both are voltage V err Determine whether the peak voltage v1 is higher than peak ,v2 peak Both are voltage V errIf it is higher, in step S6, the decision circuit 61 decides that both the sound reproducing devices 3, 3a are broken, and ends the process in the inspection mode.

[0084] On the other hand, the peak voltage v1 peak ,v2 peak Either of these is at voltage V err If it is equal to or less than the peak voltage v1, in step S7, the determination circuit 61 peak is the voltage V err Determine whether the peak voltage v1 is higher than peak is the voltage V err If it is higher, in step S8, the decision circuit 61 decides that the sound reproducing device 3 is broken, and ends the process in the inspection mode.

[0085] On the other hand, the peak voltage v1 peak is the voltage V err If the above is true, then in step S9, The constant circuit 61 detects the peak voltage v2 peak is the voltage V err Determine whether the peak voltage v2 is higher than peak is the voltage V err If it is higher, in step S10, the decision circuit 61 decides that the sound reproducing device 3a is broken, and ends the process in the inspection mode.

[0086] On the other hand, the peak voltage v2 peak is the voltage V err If it is equal to or less than the peak frequency f1 acquired in step S3, in step S11, the determination circuit 61 peak and the peak frequency f2 obtained in step S4 peak It is determined whether the difference between the peak frequency f1 and the peak frequency f2 is within a reference frequency difference range that is higher than -α and lower than +α. peak and peak frequency f2 peak If the difference with respect to the frequency is not included in the reference frequency difference range, in step S13, the determination circuit 61 determines that there is a possibility that one of the sound reproduction devices 3, 3a is malfunctioning, and ends the processing in the inspection mode.

[0087] On the other hand, the peak frequency f1peak and peak frequency f2 peak If the difference between the peak voltage v1 and the reference frequency difference range is included in step S12, the determination circuit 61 determines whether the peak voltage v1 peak and the peak voltage v2 obtained in step S4 peak It is determined whether the difference between the peak voltage v1 and the reference voltage difference range, which is higher than -β and lower than +β. peak and peak voltage v2 peak If the difference between the peak voltage v1 and the reference voltage difference range is not included, in step S13, the determination circuit 61 determines that there is a possibility that one of the sound reproduction devices 3, 3a is broken, and ends the process in the inspection mode. peak and peak voltage v2 peak If the difference is within the reference voltage difference range, in step S14, the determination circuit 61 determines that both the sound reproduction devices 3, 3a are normal, and ends the process in the inspection mode.

[0088] The sound reproducing device 3 is an example of a "first sound reproducing device", the terminal P1 of the sound reproducing device 3 is an example of a "first terminal of the first sound reproducing device", and the terminal P2 of the sound reproducing device 3 is an example of a "second terminal of the first sound reproducing device". The sound reproducing device 3a is an example of a "second sound reproducing device", the terminal P1a of the sound reproducing device 3a is an example of a "first terminal of the second sound reproducing device", and the terminal P2a of the sound reproducing device 3a is an example of a "second terminal of the second sound reproducing device". The output terminal 91 of the semiconductor device 1 is an example of a "first output terminal", and the output terminal 92 of the semiconductor device 1 is an example of a "second output terminal". The output terminal 93 of the semiconductor device 1 is an example of a "third output terminal", and the output terminal 94 of the semiconductor device 1 is an example of a "fourth output terminal". The sound source signal DI1 is an example of a "first sound source signal", and the sound source signal DI2 is an example of a "second sound source signal". Moreover, the modulation circuit 30 is an example of a "first modulation circuit", the modulation signal DOP is an example of a "first modulation signal", and the modulation signal DON is an example of a "second modulation signal". Moreover, the modulation circuit 30a is an example of a "second modulation circuit", the modulation signal DOPa is an example of a "third modulation signal", and the modulation signal DONa is an example of a "fourth modulation signal". Moreover, the modulation signal TP is an example of a "fifth modulation signal", and the modulation signal TN is an example of a "sixth modulation signal". Moreover, the amplifier circuit 50 is an example of a "first amplifier circuit", the amplified signal DOXP obtained by amplifying the modulation signal DOP is an example of a "first amplified signal", the amplified signal DOXN obtained by amplifying the modulation signal DON is an example of a "second amplified signal", the amplified signal DOXP obtained by amplifying the modulation signal TP is an example of a "third amplified signal", and the amplified signal DOXN obtained by amplifying the modulation signal TN is an example of a "fourth amplified signal". The amplifier circuit 50a is an example of a "second amplifier circuit", the amplified signal DOXPa obtained by amplifying the modulated signal DOPa is an example of a "fifth amplified signal", the amplified signal DOXNa obtained by amplifying the modulated signal DONa is an example of a "sixth amplified signal", the amplified signal DOXPa obtained by amplifying the modulated signal TP is an example of a "seventh amplified signal", and the amplified signal DOXNa obtained by amplifying the modulated signal TN is an example of an "eighth amplified signal". The peak frequency detection circuit 70 is an example of a "first peak frequency detection circuit", and the peak frequency f1 peak is an example of the "first peak frequency", and the peak voltage v1 peakis an example of a "first peak voltage." The peak frequency detection circuit 70a is an example of a "second peak frequency detection circuit." peak is an example of the "second peak frequency", and the peak voltage v2 peak "The second The differential low-pass filter 71, the A / D conversion circuit 72, and the peak time measurement circuit 73 included in the peak frequency detection circuit 70 are examples of a "first differential low-pass filter," a "first A / D conversion circuit," and a "first peak time measurement circuit," respectively. The differential low-pass filter 71, the A / D conversion circuit 72, and the peak time measurement circuit 73 included in the peak frequency detection circuit 70a are examples of a "second differential low-pass filter," a "second A / D conversion circuit," and a "second peak time measurement circuit," respectively. The normal operation mode is an example of a "first operation mode," and the inspection mode is an example of a "second operation mode."

[0089] Although the semiconductor device 1 of the present embodiment is configured to be capable of causing two sound reproducing devices 3 to output sound, it may be configured to be capable of causing three or more sound reproducing devices to output sound.

[0090] 1-1-4.Effects As described above, according to the semiconductor device 1 of the present embodiment, in the normal operation mode, the amplifier circuit 50 outputs the amplified signals DOXP and DOXN obtained by amplifying the modulated signals DOP and DON based on the sound source signal DI1 to the output terminals 91 and 92, respectively, so that the sound reproducing device 3 can reproduce sound. Also, in the normal operation mode, the amplifier circuit 50a outputs the amplified signals DOXPa and DOXNa obtained by amplifying the modulated signals DOPa and DONa based on the sound source signal DI2 to the output terminals 93 and 94, respectively, so that the sound reproducing device 3a can reproduce sound. On the other hand, in the test mode, the amplifier circuit 50 outputs the amplified signals DOXP and DOXN obtained by amplifying the modulated signals TP and TN based on the test signal to the output terminals 91 and 92, respectively, so that the peak frequency detection circuit 70 measures the potential difference between the output terminals 91 and 92, and detects the peak frequency f1 at which the impedance of the sound reproducing device 3 becomes peak. peakIn the test mode, the amplifier circuit 50a amplifies the modulated signals TP and TN based on the test signal, respectively, to output the amplified signals DOXPa and DOXNa to the output terminals 93 and 94, and the peak frequency detection circuit 70a measures the potential difference between the output terminals 93 and 94, and detects the peak frequency f2 at which the impedance of the sound reproduction device 3a becomes a peak. peak When the temperatures of the sound reproducing devices 3 and 3a change in the same way, the peak frequency f1 can be detected. peak ,f2 peak changes in the same way, so these differences are almost constant regardless of temperature. As a result, if both the sound reproducing devices 3 and 3a are normal, the peak frequency f1 peak ,f2 peak Even if the peak frequency f1 changes, the difference between these frequencies falls within the predetermined reference frequency difference range. peak and peak frequency f2 peak It is determined whether the difference between the frequency of the sound reproduction device 3 and the frequency of the sound reproduction device 3a is within a predetermined reference frequency difference range, and if the difference is not within the reference frequency difference range, it can be determined that there is a possibility that one of the sound reproduction devices 3 and 3a is malfunctioning. Therefore, according to the semiconductor device 1 of this embodiment, the accuracy of malfunction determination of the sound reproduction devices 3 and 3a can be maintained even if the temperature changes.

[0091] In the semiconductor device 1 of this embodiment, the amplifier circuit 50 generates the amplified signals DOXP and DOXN for causing the sound reproducing device 3 to reproduce sound in the normal operation mode, and generates the amplified signals DOXP and DOXN for causing the sound reproducing device 3 to reproduce sound in the test mode. peak Similarly, the amplifier circuit 50a is used for generating the amplified signals DOXPa and DOXNa for causing the sound reproducing device 3a to reproduce sounds in the normal operation mode, and for detecting the peak frequency f2 in the inspection mode. peak Therefore, according to the semiconductor device 1 of the present embodiment, the signals required to detect a failure of the sound reproduction devices 3, 3a can be generated with a small-scale circuit.

[0092] In addition, in the semiconductor device 1 of this embodiment, when the temperatures of the sound reproducing devices 3 and 3a change in the same manner, the peak voltage v1 peak ,v2 peak changes in the same way, so these differences are almost constant regardless of temperature. As a result, if both the sound reproducing devices 3 and 3a are normal, , the peak voltage v1 peak ,v2 peak Even if the peak voltage v1 changes, the difference between them is included in the predetermined reference voltage difference range. peak and peak voltage v2 peak It is determined whether the difference between the input voltage and the output voltage is within a predetermined reference voltage difference range, and if the difference is not within the reference voltage difference range, it can be determined that either of the sound reproduction devices 3, 3a may be malfunctioning. Therefore, according to the semiconductor device 1 of this embodiment, the risk of erroneously determining that both of the sound reproduction devices 3, 3a are normal is reduced when there is a possibility that either of the sound reproduction devices 3, 3a is malfunctioning.

[0093] In addition, according to the semiconductor device 1 of the present embodiment, the impedance R1 of the sound reproducing device 3 sp When the potential difference between the output terminal 91 and the output terminal 92 reaches a peak, the potential difference between the output terminal 91 and the output terminal 92 also reaches a peak. Therefore, the peak frequency detection circuit 70 measures the time when the potential difference between the output terminal 91 and the output terminal 92 reaches a maximum, thereby detecting the peak frequency f1. peak Similarly, the impedance R2 of the sound reproducing device 3a can be detected. sp When the potential difference between the output terminal 93 and the output terminal 94 reaches a peak, the peak frequency detection circuit 70a measures the time when the potential difference between the output terminal 93 and the output terminal 94 reaches a maximum, thereby detecting the peak frequency f2 peak can be detected.

[0094] Furthermore, according to the semiconductor device 1 of this embodiment, in each of the peak frequency detection circuits 70, 70a, the differential low-pass filter 71 reduces the high-frequency noise components superimposed on the amplified signals DOXP, DOXN by modulating the test signal, the A / D conversion circuit 72 converts the output voltage of the differential low-pass filter 71 into data DT, and the peak time measurement circuit 73 can easily perform high-precision measurements.

[0095] In addition, according to the semiconductor device 1 of the present embodiment, the impedance R1 of the sound reproducing device 3 sp does not depend on the magnitude of the voltage of the amplified signals DOXP and DOXN, and the impedance R2 of the sound reproducing device 3a sp does not depend on the magnitude of the voltage of the amplified signals DOXPa and DOXNa. Therefore, in the inspection mode, the sound reproduction devices 3 and 3a reproduce a very small sound that is difficult for the human ear to hear, and the peak frequency f1 peak ,f2 peak and peak voltage v1 peak ,v2 peak Therefore, according to the semiconductor device 1 of the present embodiment, it is possible to make the user less aware that the semiconductor device 1 is operating in the inspection mode.

[0096] 1-2.Modifications In the above embodiment, the peak frequency detection circuit 70 detects the peak frequency f1 peak and peak voltage v1 peak The peak frequency detection circuit 70a detects the peak frequency f2 peak and peak voltage v2 peak The peak frequency detection circuit 70 detects the peak frequency f1 peak and peak voltage v1 peak Detection of peak frequency f2 peak and peak voltage v2 peak The detection of the peak frequency f1 may be performed in a time-division manner. In this case, the peak frequency detection circuit 70a is not necessary. For example, in the test mode, the test signal generation circuit 60 first outputs a test signal whose frequency is swept, and the peak frequency detection circuit 70 detects the peak frequency f1. peak and peak voltage v1 peakNext, the test signal generating circuit 60 again outputs a test signal whose frequency is swept, and the peak frequency detecting circuit 70 detects the peak frequency f2 peak and peak voltage v2 peak may be detected.

[0097] In the above embodiment, the memory 20 in which the sound source data 21-1 to 21-n are stored is built into the semiconductor device 1, but instead of the memory 20, an external memory in which the sound source data 21-1 to 21-n are stored may be connected to the semiconductor device 1, and the semiconductor device 1 may read out the sound source data 21-i which is the sound source signal DI1 and the sound source data 21-j which is the sound source signal DI2 from the external memory. Alternatively, instead of the memory 20, the micro control unit 2 may have a built-in memory in which the sound source data 21-1 to 21-n are stored, and the micro control unit 2 may read out the sound source data 21-i, 21-j from the memory. Alternatively, the signals may be outputted from the semiconductor device 1 as the sound source signals DI1 and DI2.

[0098] In the above embodiment, the examples of the modulation method by the pulse width modulation circuit 33 are shown in Figs. 2 to 4, but other modulation methods may be used. For example, the pulse width modulation for generating the modulated signal DOP may be the same as that shown in Fig. 2, and the pulse width modulation for generating the modulated signal DON may be the method shown in Fig. 13. In the example of Fig. 13, the modulated signal DON is a signal obtained by inverting the logical level of the modulated signal DOP shown in Fig. 2, and the higher the value of the sigma-delta modulated signal DS, the shorter the high-level time becomes. For example, when the sigma-delta modulated signal DS is "-7" in decimal, that is, "1001" in binary, the modulated signal DON has one section T1 at a low level and 15 sections T2 to T16 at a high level. Also, for example, when the sigma-delta modulated signal DS is "0" in decimal, that is, "0000" in binary, the modulated signal DON has eight sections T1 to T8 at a low level and eight sections T9 to T16 at a high level. Also, for example, when the sigma-delta modulated signal DS is a decimal number "7", that is, a binary number "0111", the modulated signal DON has 15 sections T1 to T15 at a low level and one section T16 at a high level. Therefore, for example, when the sigma-delta modulated signal DS is a decimal number "-7", "0", and "7", the difference between the modulated signal DOP and the modulated signal DON is as shown in Fig. 14. The pulse width modulation for generating the modulated signal DONa may also be the method shown in Fig. 13.

[0099] 2.Electronic equipment FIG. 15 is a functional block diagram showing an example of the configuration of an electronic device of the present embodiment using the semiconductor device 1 of the present embodiment.

[0100] 15, electronic device 300 of this embodiment includes semiconductor device 1, m sound reproduction devices 3-1 to 3-m, processing unit 310, operation unit 320, storage unit 330, and display unit 340. Note that electronic device 300 of this embodiment may be configured such that some of the components in FIG. 15 are omitted or changed, or other components are added.

[0101] The processing unit 310 performs control processing of each unit of the electronic device 300 and various data processing. For example, the processing unit 310 transmits various commands to the semiconductor device 1 to control the operation of the semiconductor device 1. The processing unit 310 also performs various processes according to operation signals from the operation unit 320, and a process of transmitting a display signal for displaying various information on the display unit 340. For example, the processing unit 310 may be the micro control unit 2 described above.

[0102] The operation unit 320 is an input device including operation keys, button switches, and the like, and outputs to the processing unit 310 an operation signal in response to an operation by a user.

[0103] The storage unit 330 stores programs, data, and the like for performing various calculation processes and control processes by the processing unit 310. The storage unit 330 is realized by, for example, a hard disk, a flexible disk, an MO, an MT, various types of memory, a CD-ROM, a DVD-ROM, or the like.

[0104] The display unit 340 is a display device configured with an LCD or the like, and displays various information based on an input display signal. LCD is an abbreviation for Liquid Crystal Display. The display unit 340 may be provided with a touch panel that functions as the operation unit 320.

[0105] In the normal operation mode, the semiconductor device 1 generates a plurality of sound signals based on various commands transmitted from the processing unit 310 and outputs them to the sound reproduction devices 3-1 and 3-2. As a result, desired sounds are output from the sound reproduction devices 3-1 and 3-2. The sound reproduction device 3-1 corresponds to the above-mentioned sound reproduction device 3, and the sound reproduction device 3-2 corresponds to the above-mentioned sound reproduction device 3a. In the inspection mode, the semiconductor device 1 outputs amplified signals DOXP and DOXN based on the test signal to the sound reproduction device 3-1, and also outputs amplified signals DOXPa and DOXNa based on the test signal to the sound reproduction device 3-2. As a result, sounds are output from the sound reproduction devices 3-1 and 3-2, and it is preferable that a minute sound that is difficult for the human ear to hear is output. That is, it is preferable that the volume reproduced by the sound reproduction devices 3-1 and 3-2 in the inspection mode is smaller than the minimum volume reproduced by the sound reproduction devices 3-1 and 3-2 in the normal operation mode. This makes it difficult for the user to be aware that the semiconductor device 1 is operating in the inspection mode. Then, the semiconductor device 1 may inspect the sound reproduction devices 3-1 and 3-2 and transmit the inspection results to the processing unit 310, and the processing unit 310 may determine the presence or absence of a failure of the sound reproduction devices 3-1 and 3-2 and the failure mode. When the sound reproducing device 3-1 is broken, the processing unit 310 may, for example, cause one of the sound reproducing devices 3-3 to 3-m to reproduce a sound notifying that the sound reproducing device 3-1 is broken, or may switch the output destination of the sound signal from the sound reproducing device 3-1 to one of the sound reproducing devices 3-3 to 3-m. When the sound reproducing device 3-2 is broken, the processing unit 310 may, for example, cause one of the sound reproducing devices 3-3 to 3-m to reproduce a sound notifying that the sound reproducing device 3-2 is broken, or may switch the output destination of the sound signal from the sound reproducing device 3-2 to one of the sound reproducing devices 3-3 to 3-m.

[0106] The semiconductor device 1 can generate signals necessary for detecting failures in the sound reproduction devices 3-1 and 3-2, and therefore can realize the electronic device 300 with high reliability.

[0107] Various electronic devices are conceivable as such electronic device 300, and examples thereof include warning devices, various household electrical appliances such as rice cookers, IH cooking heaters, vacuum cleaners, and washing machines, electronic watches, personal computers such as mobile, laptop, and tablet types, mobile terminals such as smartphones and mobile phones, inkjet discharge devices such as digital cameras and inkjet printers, storage area network devices such as routers and switches, local area network devices, equipment for mobile terminal base stations, televisions, video cameras, video recorders, car navigation devices, real time clock devices, pagers, electronic notebooks, electronic dictionaries, calculators, electronic game devices, game controllers, word processors, workstations, videophones, security television monitors, electronic binoculars, POS terminals, medical devices such as electronic thermometers, blood pressure monitors, blood glucose meters, electrocardiogram measuring devices, ultrasound diagnostic devices, and electronic endoscopes, fish finders, various measuring devices, instruments for vehicles, aircraft, ships, and the like, flight simulators, head mounted displays, motion tracing, motion tracking, motion controllers, and pedestrian autonomous navigation devices.

[0108] Fig. 16 is a diagram showing a configuration example of a warning device 300A, which is an example of electronic device 300. In Fig. 16, the same components as those in Fig. 15 are given the same reference numerals. The warning device 300A shown in Fig. 16 is mounted on a vehicle 400. Sound reproduction devices 3-1 to 3-3 are each speakers, and sound reproduction devices 3-4 and 3-5 are each buzzers.

[0109] Based on signals from various sensors (not shown), the processing unit 310 transmits commands to reproduce various sounds to the semiconductor device 1. The various sounds include, for example, voices and warning sounds that imitate human voices to notify of abnormalities in the brakes, engine oil, power steering, brake override system, etc., driving with the door half-open, swaying, driving without releasing the parking brake, not fastening a seat belt, approaching a preceding vehicle, etc., and sound effects to notify of blinkers, hazards, reverse, etc.

[0110] The semiconductor device 1 generates a plurality of sound signals based on a portion of a plurality of sound source data corresponding to various sounds based on a command from the processing unit 310, and outputs the generated sound signals to the sound reproduction devices 3-1 and 3-2. The semiconductor device 1 also inspects the sound reproduction devices 3-1 and 3-2 and transmits the inspection results to the processing unit 310, and the processing unit 310 judges the presence or absence of a malfunction of the sound reproduction devices 3-1 and 3-2 and the malfunction mode. The processing unit 310 may, for example, cause one of the sound reproducing devices 3-3 to 3-5 to reproduce a sound notifying that the sound reproducing device 3-1 is malfunctioning, or may switch the output destination of the sound signal from the sound reproducing device 3-1 to one of the sound reproducing devices 3-3 to 3-5. Also, the processing unit 310 may, for example, cause one of the sound reproducing devices 3-3 to 3-5 to reproduce a sound notifying that the sound reproducing device 3-2 is malfunctioning, or may switch the output destination of the sound signal from the sound reproducing device 3-2 to one of the sound reproducing devices 3-3 to 3-5.

[0111] The semiconductor device 1 can generate signals required to detect failures in the sound reproducing devices 3-1 and 3-2, and therefore can realize a highly reliable warning device 300A.

[0112] The present invention is not limited to the present embodiment, and various modifications are possible within the scope of the present invention.

[0113] The above-described embodiment and modifications are merely examples, and the present invention is not limited to these. For example, the embodiments and modifications can be appropriately combined.

[0114] The present invention includes configurations that are substantially the same as the configurations described in the embodiments, for example, configurations with the same functions, methods, and results, or configurations with the same purpose and effects. The present invention also includes configurations in which non-essential parts of the configurations described in the embodiments are replaced. The present invention also includes configurations that achieve the same effects as the configurations described in the embodiments, or configurations that can achieve the same purpose. The present invention also includes configurations in which publicly known technology is added to the configurations described in the embodiments.

[0115] The following can be derived from the above-described embodiment and modified examples.

[0116] One aspect of the semiconductor device is a first output terminal connected to a first terminal of the first sound reproduction device; a second output terminal connected to a second terminal of the first sound reproduction device; a third output terminal connected to the first terminal of the second sound reproduction device; a fourth output terminal connected to the second terminal of the second sound reproduction device; a first modulation circuit that modulates a signal based on a first sound source signal in a first operation mode to output a first modulated signal and a second modulated signal; a second modulation circuit that modulates a signal based on a second sound source signal in the first operation mode to output a third modulated signal and a fourth modulated signal; a test signal generating circuit that, in a second operation mode, generates a fifth modulated signal and a sixth modulated signal by modulating a test signal whose frequency is changed within a preset frequency band; a first amplifier circuit that, in the first operation mode, outputs a first amplified signal obtained by amplifying the first modulated signal to the first output terminal, and outputs a second amplified signal obtained by amplifying the second modulated signal to the second output terminal, and, in the second operation mode, outputs a third amplified signal obtained by amplifying the fifth modulated signal to the first output terminal, and outputs a fourth amplified signal obtained by amplifying the sixth modulated signal to the second output terminal; a second amplifier circuit that, in the first operation mode, outputs a fifth amplified signal obtained by amplifying the third modulated signal to the third output terminal, and outputs a sixth amplified signal obtained by amplifying the fourth modulated signal to the fourth output terminal, and, in the second operation mode, outputs a seventh amplified signal obtained by amplifying the fifth modulated signal to the third output terminal, and outputs an eighth amplified signal obtained by amplifying the sixth modulated signal to the fourth output terminal; a first peak frequency detection circuit that measures a potential difference between the first output terminal and the second output terminal in the second operation mode and detects a first peak frequency, which is a frequency of the test signal at which an impedance of the first sound reproduction device becomes a peak; a second peak frequency detection circuit that measures a potential difference between the third output terminal and the fourth output terminal in the second operation mode, and detects a second peak frequency, which is a frequency of the test signal at which an impedance of the second sound reproduction device becomes a peak; a determination circuit that determines whether a difference between the first peak frequency and the second peak frequency is within a predetermined reference frequency difference range; Equipped with.

[0117] According to this semiconductor device, in the first operation mode, the first amplifier circuit outputs a first amplified signal obtained by amplifying a first modulated signal based on a first sound source signal to the first output terminal, and outputs a second amplified signal obtained by amplifying a second modulated signal based on the first sound source signal to the second output terminal, so that the first sound reproduction device can reproduce sound. In addition, in the first operation mode, the second amplifier circuit outputs a fifth amplified signal obtained by amplifying a third modulated signal based on a second sound source signal to the third output terminal, and outputs a sixth amplified signal obtained by amplifying a fourth modulated signal based on the second sound source signal to the fourth output terminal, so that the second sound reproduction device can reproduce sound. Meanwhile, in the second operation mode, the first amplifier circuit outputs a third amplified signal obtained by amplifying a fifth modulated signal based on a test signal to the first output terminal, and outputs a fourth amplified signal obtained by amplifying a sixth modulated signal based on a test signal to the second output terminal, so that the first peak frequency detection circuit measures the potential difference between the first output terminal and the second output terminal, and can detect a first peak frequency at which the impedance of the first sound reproduction device becomes a peak. In the second operation mode, the second amplifier circuit outputs a seventh amplified signal obtained by amplifying a fifth modulated signal based on the test signal to the third output terminal, and outputs an eighth amplified signal obtained by amplifying a sixth modulated signal based on the test signal to the fourth output terminal, so that the second peak frequency detection circuit measures the potential difference between the third output terminal and the fourth output terminal and detects the second peak frequency at which the impedance of the second sound reproduction device is at its peak. If the temperature of the first sound reproduction device and the temperature of the second sound reproduction device change in the same way, the first peak frequency and the second peak frequency also change in the same way, so that the difference between them is almost constant regardless of temperature. As a result, if both the first sound reproduction device and the second sound reproduction device are normal, even if the first peak frequency and the second peak frequency change due to a change in temperature, the difference between them will be within a predetermined reference frequency difference range. Therefore, the determination circuit determines whether the difference between the first peak frequency and the second peak frequency is within a predetermined reference frequency difference range, and, for example, if the difference is not within the reference frequency difference range, it can determine that the first sound reproduction device or the second sound reproduction device may be broken.Therefore, according to this semiconductor device, the accuracy of failure determination of the first sound reproduction device and the second sound reproduction device can be maintained even if the temperature changes.

[0118] In addition, in this semiconductor device, the first amplifier circuit is used to generate the first amplified signal and the second amplified signal for causing the first sound reproduction device to reproduce sound in the first operation mode, and to generate the third amplified signal and the fourth amplified signal required for detecting the first peak frequency in the second operation mode. Similarly, the second amplifier circuit is used to generate the fifth amplified signal and the sixth amplified signal for causing the second sound reproduction device to reproduce sound in the first operation mode, and to generate the seventh amplified signal and the eighth amplified signal required for detecting the second peak frequency in the second operation mode. Therefore, according to this semiconductor device, the signals required for detecting failures in the first sound reproduction device and the second sound reproduction device can be generated by a small-scale circuit.

[0119] In one embodiment of the semiconductor device, the first peak frequency detection circuit further detects, in the second operation mode, a first peak voltage that is a voltage obtained by amplifying a potential difference between the first output terminal and the second output terminal when a frequency of the test signal is the first peak frequency; the second peak frequency detection circuit further detects, in the second operation mode, a second peak voltage that is a voltage obtained by amplifying a potential difference between the third output terminal and the fourth output terminal when the frequency of the test signal is the second peak frequency; The determination circuit may further determine whether or not a difference between the first peak voltage and the second peak voltage is within a predetermined reference voltage difference range.

[0120] In this semiconductor device, when the temperature of the first sound reproducing device and the temperature of the second sound reproducing device change in the same way, the first peak voltage and the second peak voltage also change in the same way, so that the difference between them is almost constant regardless of temperature. As a result, if both the first sound reproducing device and the second sound reproducing device are normal, even if the first peak voltage and the second peak voltage change due to a change in temperature, the difference between them will be included in a predetermined reference voltage difference range. Therefore, the determination circuit determines whether the difference between the first peak voltage and the second peak voltage is included in a predetermined reference voltage difference range, and, for example, even if the difference between the first peak frequency and the second peak frequency is included in a predetermined reference frequency difference range, if the difference between the first peak voltage and the second peak voltage is not included in the predetermined reference voltage difference range, it can determine that the first sound reproducing device or the second sound reproducing device may be malfunctioning. Therefore, according to this semiconductor device, the risk of erroneously determining that both the first sound reproducing device and the second sound reproducing device are normal when there is a possibility that the first sound reproducing device or the second sound reproducing device is malfunctioning is reduced.

[0121] In one embodiment of the semiconductor device, the first peak frequency detection circuit detects the first peak frequency by measuring a time when a potential difference between the first output terminal and the second output terminal becomes maximum in the second operation mode; The second peak frequency detection circuit may detect the second peak frequency by measuring the time when a potential difference between the third output terminal and the fourth output terminal becomes maximum in the second operation mode.

[0122] According to this semiconductor device, since the potential difference between the first output terminal and the second output terminal also peaks when the impedance of the first sound reproduction device peaks, the first peak frequency detection circuit can detect the first peak frequency by measuring the time when the potential difference between the first output terminal and the second output terminal is maximum. Similarly, since the potential difference between the third output terminal and the fourth output terminal also peaks when the impedance of the second sound reproduction device peaks, the second peak frequency detection circuit can detect the second peak frequency by measuring the time when the potential difference between the third output terminal and the fourth output terminal is maximum.

[0123] In one embodiment of the semiconductor device, The first peak frequency detection circuit is a first differential low-pass filter to which the voltage at the first output terminal and the voltage at the second output terminal are input; a first A / D conversion circuit that converts an output voltage of the first differential low-pass filter into a digital signal; a first peak time measurement circuit that measures the time when a potential difference between the first output terminal and the second output terminal becomes maximum based on the digital signal output from a first A / D conversion circuit; Including, The second peak frequency detection circuit is a second differential low-pass filter to which the voltage at the third output terminal and the voltage at the fourth output terminal are input; a second A / D conversion circuit that converts an output voltage of the second differential low-pass filter into a digital signal; a second peak time measurement circuit that measures the time when a potential difference between the third output terminal and the fourth output terminal becomes maximum based on the digital signal output from the second A / D conversion circuit; may include:

[0124] According to this semiconductor device, the first differential low-pass filter reduces high-frequency noise components superimposed on the fifth amplified signal and the sixth amplified signal by modulating the test signal, the first A / D conversion circuit converts the output voltage of the first differential low-pass filter into a digital signal, and the first peak time measurement circuit can easily perform highly accurate measurements. Similarly, according to this semiconductor device, the second differential low-pass filter reduces high-frequency noise components superimposed on the fifth amplified signal and the sixth amplified signal by modulating the test signal, the second A / D conversion circuit converts the output voltage of the second differential low-pass filter into a digital signal, and the second peak time measurement circuit can easily perform highly accurate measurements.

[0125] In one embodiment of the semiconductor device, A cutoff frequency of the first differential low-pass filter and a cutoff frequency of the second differential low-pass filter may be higher than a maximum frequency of the frequency band.

[0126] According to this semiconductor device, the cutoff frequency of the first differential low-pass filter is higher than the maximum frequency of the frequency band in which the frequency of the test signal is changed, so that the frequency components included in the frequency band are not attenuated by the first differential low-pass filter, and the first peak time measurement circuit can perform highly accurate measurement. Similarly, according to this semiconductor device, the cutoff frequency of the second differential low-pass filter is higher than the maximum frequency of the frequency band in which the frequency of the test signal is changed, so that the frequency components included in the frequency band are not attenuated by the second differential low-pass filter, and the second peak time measurement circuit can perform highly accurate measurement.

[0127] One aspect of the electronic device is One aspect of the semiconductor device; the first sound reproduction device; the second sound reproduction device; Equipped with.

[0128] According to this electronic device, since it includes a semiconductor device capable of generating a signal required for detecting a failure of the first sound reproduction device and a failure of the second sound reproduction device, it is possible to improve reliability.

[0129] In one aspect of the electronic device, The volume of sound reproduced by each of the first sound reproduction device and the second sound reproduction device in the second operation mode may be lower than a minimum value of the volume of sound reproduced by each of the first sound reproduction device and the second sound reproduction device in the first operation mode.

[0130] According to this electronic device, the sounds output from the first sound reproduction device and the second sound reproduction device in the second operation mode are small sounds that are difficult for humans to hear, making it difficult for the user to be aware that the semiconductor device is operating in the second operation mode. [Explanation of symbols]

[0131] 1...semiconductor device, 2...microcontroller unit, 3,3a,3-1 to 3-m...sound reproduction device, 10...communication interface circuit, 20...memory, 21-1 to 21-n...sound source data, 30,30a...modulation circuit, 31,31a...digital filter, 32,32a...sigma-delta modulation circuit, 33,33a...pulse width modulation circuit, 41,41a...switch, 42,42a...switch, 50,50a...amplification Circuit, 51P, 51Pa, 51N, 51Na... Class D amplifier, 60... Test signal generation circuit, 61... Judgment circuit, 62... Memory, 70, 70a... Peak frequency detection circuit, 71... Differential low-pass filter, 72... A / D conversion circuit, 73... Peak time measurement circuit, 81, 81a... Switch, 82, 82a... Switch, 91... Output terminal, 92... Output terminal, 93... Output terminal, 94... Output terminal, 100... Sound source playback circuit, 110... inspection circuit, 201-1 to 201-n... inverter circuits, 202-1 to 202-n... inverter circuits, 211... operational amplifier, 212, 213, 214... resistor, 215... capacitor, 216... resistor, 217... capacitor, 218... resistor, 219... capacitor, 300... electronic device, 300A... warning device, 310... processing unit, 320... operation unit, 330... memory unit, 340... display unit, 400... vehicle

Claims

1. a first output terminal connected to a first terminal of the first sound reproduction device; a second output terminal connected to a second terminal of the first sound reproduction device; a third output terminal connected to the first terminal of the second sound reproduction device; a fourth output terminal connected to the second terminal of the second sound reproduction device; a first modulation circuit that modulates a signal based on a first sound source signal in a first operation mode to output a first modulated signal and a second modulated signal; a second modulation circuit that modulates a signal based on a second sound source signal in the first operation mode to output a third modulated signal and a fourth modulated signal; a test signal generating circuit that, in a second operation mode, generates a fifth modulated signal and a sixth modulated signal by modulating a test signal whose frequency is changed within a preset frequency band; a first amplifier circuit that, in the first operation mode, outputs a first amplified signal obtained by amplifying the first modulated signal to the first output terminal, and outputs a second amplified signal obtained by amplifying the second modulated signal to the second output terminal, and, in the second operation mode, outputs a third amplified signal obtained by amplifying the fifth modulated signal to the first output terminal, and outputs a fourth amplified signal obtained by amplifying the sixth modulated signal to the second output terminal; a second amplifier circuit that, in the first operation mode, outputs a fifth amplified signal obtained by amplifying the third modulated signal to the third output terminal, and outputs a sixth amplified signal obtained by amplifying the fourth modulated signal to the fourth output terminal, and, in the second operation mode, outputs a seventh amplified signal obtained by amplifying the fifth modulated signal to the third output terminal, and outputs an eighth amplified signal obtained by amplifying the sixth modulated signal to the fourth output terminal; a first peak frequency detection circuit that measures a potential difference between the first output terminal and the second output terminal in the second operation mode, and detects a first peak frequency, which is a frequency of the test signal at which an impedance of the first sound reproduction device becomes a peak; a second peak frequency detection circuit that measures a potential difference between the third output terminal and the fourth output terminal in the second operation mode, and detects a second peak frequency, which is a frequency of the test signal at which an impedance of the second sound reproduction device becomes a peak; a determination circuit that determines whether a difference between the first peak frequency and the second peak frequency is within a predetermined reference frequency difference range; A semiconductor device comprising:

2. In claim 1, the first peak frequency detection circuit further detects, in the second operation mode, a first peak voltage that is a voltage obtained by amplifying a potential difference between the first output terminal and the second output terminal when a frequency of the test signal is the first peak frequency; the second peak frequency detection circuit further detects, in the second operation mode, a second peak voltage that is a voltage obtained by amplifying a potential difference between the third output terminal and the fourth output terminal when the frequency of the test signal is the second peak frequency; The determination circuit further determines whether or not a difference between the first peak voltage and the second peak voltage is within a predetermined reference voltage difference range.

3. In claim 1, the first peak frequency detection circuit detects the first peak frequency by measuring a time when a potential difference between the first output terminal and the second output terminal becomes maximum in the second operation mode; The semiconductor device, wherein the second peak frequency detection circuit detects the second peak frequency by measuring a time when a potential difference between the third output terminal and the fourth output terminal becomes maximum in the second operation mode.

4. In claim 3, The first peak frequency detection circuit includes: a first differential low-pass filter to which the voltage at the first output terminal and the voltage at the second output terminal are input; a first A / D conversion circuit that converts an output voltage of the first differential low-pass filter into a digital signal; a first peak time measurement circuit that measures the time when a potential difference between the first output terminal and the second output terminal becomes maximum based on the digital signal output from the first A / D conversion circuit; Including, The second peak frequency detection circuit includes: a second differential low-pass filter to which the voltage at the third output terminal and the voltage at the fourth output terminal are input; a second A / D conversion circuit that converts an output voltage of the second differential low-pass filter into a digital signal; a second peak time measurement circuit that measures the time when a potential difference between the third output terminal and the fourth output terminal becomes maximum based on the digital signal output from the second A / D conversion circuit; 13. A semiconductor device comprising:

5. In claim 4, A semiconductor device, wherein a cutoff frequency of the first differential low-pass filter and a cutoff frequency of the second differential low-pass filter are higher than a maximum frequency of the frequency band.

6. A semiconductor device according to any one of claims 1 to 5, the first sound reproduction device; the second sound reproduction device; An electronic device comprising:

7. In claim 6, An electronic device, wherein the volume of sound reproduced by the first sound reproduction device and the second sound reproduction device in the second operating mode is smaller than the minimum volume of sound reproduced by the first sound reproduction device and the second sound reproduction device in the first operating mode.

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