Semiconductor device

Abstract

To provide a semiconductor device in which defects in an oxide semiconductor film are reduced; and to provide a semiconductor device improved in electric property or reliability, provided that an oxide semiconductor film is used in the semiconductor device.SOLUTION: A semiconductor device comprises: a transistor formed on a substrate and having a gate electrode, a gate insulative film covering the gate electrode, a multilayer film overlying the gate electrode through the gate insulative film, and a pair of electrodes put in contact with the multilayer film; and an oxide insulation film covering the transistor. The multilayer film has: an oxide semiconductor film; and an oxide film including In or Ga. The oxide insulation film includes oxygen more than oxygen that satisfies a stoichiometric composition. The transistor never causes the fluctuation in threshold voltage in a bias temperature stress test, otherwise suffers a fluctuation of 1.0 V or less toward a plus or minus direction.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device having a transistor and a manufacturing method thereof. [Background technology]

[0002] It is used in many flat panel displays, such as liquid crystal displays and light-emitting displays. The transistors used are made of amorphous silicon and single crystal silicon formed on a glass substrate. The silicon semiconductor is made of silicon semiconductor such as polycrystalline silicon or polysilicon. Transistors using silicon semiconductors are also used in integrated circuits (ICs).

[0003] In recent years, metal oxides that exhibit semiconducting properties have been used in transistors instead of silicon semiconductors. In this specification, the term "oxide" refers to a metal oxide that exhibits semiconductor properties. Let us call it a semiconductor.

[0004] For example, a transistor using zinc oxide or an In-Ga-Zn oxide as an oxide semiconductor may be used. A technique for manufacturing a transistor and using the transistor as a switching element for pixels of a display device. Techniques for this have been disclosed (see Patent Documents 1 and 2). [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2007-123861 A [Patent Document 2] JP 2007-96055 A Summary of the Invention [Problem to be solved by the invention]

[0006] In a transistor including an oxide semiconductor film, the amount of oxygen vacancies in the oxide semiconductor film The large number of defects can lead to poor electrical characteristics of transistors, as well as deterioration over time and stress testing. (For example, in the BT (Bias-Temperature) stress test) The cause of the increase in the variation of the electrical characteristics of the transistor, typically the threshold voltage (Vth), is become.

[0007] In view of the above, one embodiment of the present invention is a semiconductor device including an oxide semiconductor film. Another object of the present invention is to reduce defects in an oxide semiconductor film. Another object of the present invention is to improve electrical characteristics of a semiconductor device using the same. One embodiment of the present invention is to improve the reliability of a semiconductor device including an oxide semiconductor film. This is one of the challenges. [Means for solving the problem]

[0008] One aspect of the present invention is a gate electrode formed on a substrate, a gate insulating film covering the gate electrode, A multilayer film overlapping a gate electrode via a gate insulating film, and a pair of electrodes in contact with the multilayer film. and an oxide insulating film covering the transistor, The multilayer film includes an oxide semiconductor film and an oxide film containing In or Ga, and the oxide insulating film is an oxide insulating film that contains more oxygen than the oxygen that satisfies the stoichiometric composition, and is The threshold voltage of the transistor does not change or changes in the positive direction due to the bias temperature stress test. Or has the characteristic of fluctuating in a negative direction, and fluctuations in a negative or positive direction The amount of the potential difference is 1.0 V or less, preferably 0.5 V or less.

[0009] Note that the oxide semiconductor film preferably contains In or Ga.

[0010] In addition, the energy level of the lower end of the conduction band of an oxide film containing In or Ga is The energy level is closer to the vacuum level than the lower end of the conduction band of the conductor film. Energy level of the conduction band minimum of an oxide film containing Ga and the conduction band minimum of an oxide semiconductor film The difference between the energy level of the nucleus and the energy level of the nucleus is preferably 0.05 eV or more and 2 eV or less. The energy difference between the vacant level and the bottom of the conduction band is also called the electron affinity, so The electron affinity of the oxide film is smaller than that of the oxide semiconductor film, and the difference is 0.05e It is preferable that the electron density is 0.5 V or more and 2 eV or less.

[0011] In addition, the oxide semiconductor film and the oxide film containing In or Ga are In-M-Zn oxide (M is Al, Ti, Ga, Y, Zr, La, Ce, Nd, or Hf) The atomic ratio of M contained in the oxide film containing In or Ga is large compared to the conductor film. It is preferable that

[0012] In addition, the multilayer film has a constant light energy in the range of 1.5 eV to 2.3 eV. Current measurement method (CPM: Constant Photocurrent Method) The derived absorption coefficient is 1×10 -3 It is preferable that the thickness is less than 1 / cm.

[0013] In addition, the silicon concentration between the oxide semiconductor film and the oxide film containing In or Ga But 2×10 18 atoms / cm 3 It is preferable that it is less than 1000 .mu.m.

[0014] Further, one embodiment of the present invention is a method for forming a gate electrode and a gate insulating film on the gate insulating film, A multilayer film having an oxide semiconductor film and an oxide film containing In or Ga is formed, A pair of electrodes are formed in contact with each other, and an oxide insulating film is formed on the multilayer film and the pair of electrodes. The oxide insulating film is formed by insulating a substrate placed in a vacuum evacuated processing chamber. The temperature is kept at 180°C or higher and 260°C or lower, and the raw material gas is introduced into the treatment chamber to increase the pressure in the treatment chamber. The pressure is set to 100 Pa or more and 250 Pa or less, and the pressure applied to the electrode installed in the treatment chamber is set to 0.17 W / cm 2 More than 0.5W / cm 2 The formation is performed by supplying the following high frequency power. Effect of the Invention

[0015] According to one embodiment of the present invention, in a semiconductor device including an oxide semiconductor film, In addition, according to one embodiment of the present invention, the defect of the oxide semiconductor film can be reduced. In the semiconductor device, electrical characteristics can be improved. In this way, the reliability of a semiconductor device including an oxide semiconductor film can be improved. [Brief description of the drawings]

[0016] [Figure 1] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of a transistor, and a diagram illustrating Vg-Id characteristics. [Diagram 2] FIG. 1 illustrates a band structure of a transistor. [Diagram 3] 1A to 1C are cross-sectional views illustrating one mode of a method for manufacturing a transistor. [Figure 4] FIG. 1 is a cross-sectional view illustrating one embodiment of a transistor. [Diagram 5] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of a transistor. [Figure 6]FIG. 1 illustrates a band structure of a transistor. [Figure 7] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of a transistor. [Figure 8] 1A to 1C are cross-sectional views illustrating one mode of a method for manufacturing a transistor. [Figure 9] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of a transistor. [Figure 10] 1A to 1C are cross-sectional views illustrating one mode of a method for manufacturing a transistor. [Figure 11] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of a transistor. [Figure 12] FIG. 1 is a cross-sectional view illustrating one embodiment of a transistor. [Figure 13] FIG. 1 is a top view illustrating one embodiment of a semiconductor device. [Figure 14] 1 is a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 15] 1A to 1C are diagrams illustrating electronic devices using a semiconductor device which is one embodiment of the present invention. [Figure 16] 1A to 1C are diagrams illustrating electronic devices using a semiconductor device which is one embodiment of the present invention. [Figure 17] FIG. 1 is a diagram showing the Vg-Id characteristics of a transistor. [Figure 18] FIG. 13 is a diagram showing the amount of change in threshold voltage of a transistor after a light BT stress test. [Figure 19] FIG. 13 is a graph showing the spin density of the g value derived from oxygen vacancies in an oxide semiconductor film. [Figure 20] FIG. 13 is a diagram showing the results of CPM measurement of a multilayer film included in a transistor. [Figure 21] FIG. 13 is a diagram showing the results of ToF-SIMS of a multilayer film included in a transistor. [Figure 22] FIG. 13 shows the results of TDS measurement of an oxide insulating film included in a transistor. [Diagram 23] FIG. 13 is a graph showing the spin density of g values ​​originating from dangling bonds in an oxide insulating film. [Figure 24]FIG. 2 is a top view illustrating a configuration example of a pixel portion of a display device. [Diagram 25] 1 is a cross-sectional view showing a configuration example of a pixel portion of a display device. [Figure 26] 1A and 1B are diagrams showing an example of a connection structure of a common electrode of a display device and an example of a connection structure of wiring of the display device; [Figure 27] 1 is a cross-sectional view showing a configuration example of a pixel portion of a display device. [Figure 28] FIG. 1 is a top view illustrating one embodiment of a semiconductor device. [Figure 29] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of a semiconductor device. [Diagram 30] 1A and 1B are an exploded perspective view and a top view illustrating a configuration example of a touch sensor. [Diagram 31] 1A and 1B are a cross-sectional view and a circuit diagram illustrating a configuration example of a touch sensor. [Diagram 32] FIG. 1 is a cross-sectional view illustrating one embodiment of a transistor. [Diagram 33] FIG. 1 is a block diagram showing an example of the configuration of a liquid crystal display device. [Diagram 34] 4 is a timing chart illustrating an example of a method for driving a liquid crystal display device. [Diagram 35] FIG. 1 shows a valence band spectrum obtained by HAXPES measurement. [Diagram 36] FIG. 1 is a diagram for explaining a structure used in the calculation of a band structure. [Figure 37] FIG. 13 is a diagram for explaining calculation results of a band structure. [Figure 38] 1A and 1B are schematic diagrams of an oxide semiconductor film and diagrams illustrating a band structure in the oxide semiconductor film. [Figure 39] FIG. 13 is a diagram for explaining calculation results of a band structure. [Diagram 40] FIG. 13 is a diagram showing the change in energy barrier height with respect to the change in channel length. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0017] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the following description, and the embodiments and aspects of the present invention may be modified without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that various modifications may be made to the embodiments and details of the present invention. However, the present invention should not be construed as being limited to the description of the following embodiments and examples. In the following embodiments and examples, the same parts or parts having similar functions In the drawings, the same reference numerals or hatch patterns are used in common and their repetition is not permitted. The explanation of this will be omitted.

[0018] In each figure described in this specification, the size, thickness, or area of ​​each component is not clearly indicated. may be exaggerated for clarity and are not necessarily limited to scale .

[0019] In addition, the terms "first," "second," "third," etc., used in this specification are used interchangeably to avoid confusion of components. The number is added for convenience and is not intended to be a numerical limit. The terms can be replaced with "second" or "third" as appropriate for explanation.

[0020] The function of the "source" and "drain" is to change the direction of the current during circuit operation. For this reason, in this specification, the terms "sauce" and "dressing" are used interchangeably. The terms "in" and "in" may be used interchangeably.

[0021] Voltage is the potential difference between two points, and potential is the electrostatic field at a certain point. This refers to the electrostatic energy (electrical potential energy) possessed by a unit charge in a particle. Generally, the potential difference between a potential at a certain point and a reference potential (for example, ground potential) This is simply called potential or voltage, and potential and voltage are often used synonymously. Therefore, in this specification, unless otherwise specified, potential may be read as voltage. In this specification, voltage may be read as potential.

[0022] In this specification, when an etching process is performed after a photolithography process, The mask formed in the photolithography process is removed.

[0023] (Embodiment 1) In this embodiment, a semiconductor device according to one embodiment of the present invention and a manufacturing method thereof will be described with reference to drawings. Please refer to the following for explanation.

[0024] In a transistor including an oxide semiconductor film, An example of such defects is oxygen vacancies. The threshold voltage of a transistor using a thin film is easily shifted in the negative direction. This is because charges are generated due to oxygen vacancies in the oxide semiconductor film. When a transistor has normally-on characteristics, Various problems may occur, such as malfunctions becoming more likely or power consumption increasing when not in operation. In addition, the electrical characteristics of transistors, typically There is a problem in that the fluctuation amount of the threshold voltage increases.

[0025] One of the causes of oxygen vacancies is damage that occurs during the manufacturing process of a transistor. For example, when forming an insulating film on an oxide semiconductor film by plasma CVD, Depending on the conditions, the oxide semiconductor film might be damaged.

[0026] In addition to oxygen deficiencies, impurities such as silicon and carbon, which are constituent elements of the insulating film, can also cause damage to the transistor. Therefore, the impurities may be mixed into the oxide semiconductor film, which may cause poor electrical characteristics of the transistor. As a result, the resistance of the oxide semiconductor film is reduced, and the oxide semiconductor film is easily deteriorated due to deterioration over time or in a stress test. This leads to a problem that the amount of fluctuation in the electrical characteristics of the transistor, typically the threshold voltage, increases. There is.

[0027] In view of the above, in this embodiment, a semiconductor device including a transistor having an oxide semiconductor film is In the present invention, oxygen vacancies in an oxide semiconductor film having a channel region and defects in the oxide semiconductor film are The objective is to reduce the concentration of impurities.

[0028] 1A to 1C are a top view and a cross-sectional view of a transistor 50 included in a semiconductor device. FIG. 1A is a top view of a transistor 50, and FIG. 1B is a top view of the transistor 50 shown in FIG. FIG. 1(C) is a cross-sectional view taken along dashed line AB, and FIG. 1(A) is a cross-sectional view taken along dashed line CD. In FIG. 1(A), for clarity, the substrate 11, the gate insulating film 17, and the oxide The insulating film 24, the nitride insulating film 25, etc. are omitted.

[0029] The transistor 50 shown in FIG. 1B and FIG. 1C has a gate The gate electrode 15 is provided on the substrate 11. A gate insulating film 17 is formed on the substrate 11 and the gate electrode 15. The multilayer film 20 overlaps the gate electrode 15 via the gate insulating film 17, and the multilayer film 20 is connected to the gate electrode 15. The gate insulating film 17, the multilayer film 20, and the pair of electrodes 21 and 22 are connected to each other. A protective film composed of an oxide insulating film 24 and a nitride insulating film 25 is formed on the electrodes 21 and 22. 26 is formed.

[0030] In the transistor 50 described in this embodiment, the multilayer film 20 includes an oxide semiconductor film 18, The oxide semiconductor film 18 includes an oxide film 19 containing In or Ga. The multilayer film 20 is provided with an oxide insulating film 24, which functions as a panel region. That is, between the oxide semiconductor film 18 and the oxide insulating film 24, a layer containing In or Ga is formed. An oxide film 19 is provided.

[0031] The oxide semiconductor film 18 is typically made of In-Ga oxide, In-Zn oxide, In-Mn oxide, or In-Zn oxide. -Zn oxide (M is Al, Ti, Ga, Y, Zr, La, Ce, Nd, or Hf) .

[0032] When the oxide semiconductor film 18 is an In-M-Zn oxide, the atomic ratio of In to M is is preferably such that In is 25 atomic % or more and M is less than 75 atomic %; Preferably, In is 34 atomic % or more and M is less than 66 atomic %.

[0033] The oxide semiconductor film 18 has an energy gap of 2 eV or more, preferably 2.5 eV or more. More preferably, the energy gap is 3 eV or more. By using such a body, the off-state current of the transistor 50 can be reduced.

[0034] The thickness of the oxide semiconductor film 18 is 3 nm or more and 200 nm or less, preferably 3 nm or more and 10 0 nm or less, and more preferably 3 nm or more and 50 nm or less.

[0035] The oxide film 19 containing In or Ga is typically an In-Ga oxide or an In-Zn Oxide, In-M-Zn oxide (M is Al, Ti, Ga, Y, Zr, La, Ce, Nd or Hf), and the energy of the bottom of the conduction band is closer to the vacuum level than the oxide semiconductor film 18. The energy of the lower end of the conduction band of the oxide film 19 containing In or Ga is close to that of the lower end of the conduction band of the oxide film 19 containing In or Ga. , the difference between the energy of the lower end of the conduction band of the oxide semiconductor film 18 is 0.05 eV or more, 7 eV or more, 0.1 eV or more, or 0.15 eV or more and 2 eV or less, 1 eV or less, 0 That is, the oxide film 19 containing In or Ga has a refractive index of 0.5 eV or less, or 0.4 eV or less. The difference between the electron affinity of the oxide semiconductor film 18 and the electron affinity of the oxide semiconductor film 18 is 0.05 eV or more and 0.0 7 eV or more, 0.1 eV or more, or 0.15 eV or more and 2 eV or less, 1 eV or less, It is 0.5 eV or less, or 0.4 eV or less.

[0036] When the oxide film 19 containing In or Ga is an In-M-Zn oxide, The atomic ratio is preferably less than 50 atomic % for In and 50 atomic % or more for M. More preferably, In is less than 25 atomic % and M is 75 atomic % or more. do.

[0037] The oxide semiconductor film 18 and the oxide film 19 containing In or Ga are In-MZ n-oxide (M is Al, Ti, Ga, Y, Zr, La, Ce, Nd or Hf), oxidation In comparison with the oxide semiconductor film 18, M (Al, The atomic ratio of Ti, Ga, Y, Zr, La, Ce, Nd, or Hf is large, and typically The amount of the atoms contained in the oxide semiconductor film 18 is 1.5 times or more, and preferably 2 times or more. More preferably, the atomic ratio is at least three times higher.

[0038] The oxide semiconductor film 18 and the oxide film 19 containing In or Ga are In-MZ In the case of n-oxides (where M is Al, Ti, Ga, Y, Zr, La, Ce, Nd or Hf), Alternatively, the oxide film 19 containing Ga is In:M:Zn=x1:y1:z1 [atomic ratio], When the compound semiconductor film 18 has an atomic ratio of In:M:Zn=x2:y2:z2, y1 / x 1 is greater than y2 / x2, and preferably, y1 / x1 is 1.5 times or more greater than y2 / x2 More preferably, y1 / x1 is at least twice as large as y2 / x2. In most cases, y1 / x1 is three times larger than y2 / x2. When y2 is equal to or larger than x2, a transistor including the oxide semiconductor film can have a stable electric field. However, if y2 is three times or more larger than x2, the oxide semiconductor Since the field effect mobility of a transistor using a conductive film is reduced, y2 should be greater than or equal to x2. It is preferably less than three times 2.

[0039] For example, the oxide semiconductor film 18 may be made of a material having a composition of In:Ga:Zn=1:1:1 or 3:1:2. In-Ga-Zn oxide having a molecular ratio of In-Ga-Zn can be used. The oxide film 19 is made of In:Ga:Zn=1:3:2, 1:6:4, or 1:9:6 atomic ratio. In the oxide semiconductor film 18, an In-Ga-Zn oxide having a certain ratio can be used. The atomic ratio of the oxide film 19 containing In or Ga is the above atomic ratio with an error. This includes a fluctuation of plus or minus 20%.

[0040] In addition, the semiconductor characteristics and electrical characteristics (field effect) of the required transistors are not limited to these. It is sufficient to use a material with an appropriate composition according to the required properties (e.g., the resultant mobility, threshold voltage, etc.). In order to obtain semiconductor characteristics of a transistor, the carrier density and impurity of the oxide semiconductor film 18 are controlled. By appropriately adjusting the concentration, defect density, atomic ratio of metal elements to oxygen, interatomic distance, density, etc. is preferred.

[0041] The oxide film 19 containing In or Ga is formed when the oxide insulating film 24 is formed later. It also functions as a film for reducing damage to the oxide semiconductor film 18.

[0042] The thickness of the oxide film 19 containing In or Ga is preferably 3 nm or more and 100 nm or less. The thickness is between 3 nm and 50 nm.

[0043] When the oxide semiconductor film 18 contains silicon or carbon, which is one of the group 14 elements, As a result, oxygen vacancies increase in the oxide semiconductor film 18, and the oxide semiconductor film 18 becomes n-type. The concentration of silicon or carbon in the semiconductor film 18, or the concentration of the oxide film 19 containing In or Ga The concentration of silicon or carbon near the interface with the oxide semiconductor film 18 is set to 2×10 18 atom / c m 3 Less than or equal to 2×10 17 atoms / cm 3 The following applies.

[0044] The crystal structures of the oxide semiconductor film 18 and the oxide film 19 containing In or Ga are These structures are amorphous, single crystal, polycrystalline, microcrystalline, and amorphous regions with crystal grains dispersed in them. The mixed structure or the CAAC-OS (C Axis Aligned Crystal Structure) described later In addition, microcrystals may be used. A crystal structure is one in which the plane orientation of each crystal grain is random. It is also known as a microcrystalline structure or a mixed structure. The grain size of the crystal grains contained is 0.1 nm to 10 nm, preferably 1 nm to 10 nm. The thickness of the oxide semiconductor film 18 is preferably 2 nm or more and 4 nm or less. By using CAAC-OS as the crystal structure, the amount of change in electrical properties due to irradiation with visible light or ultraviolet light is reduced. It is possible to further reduce

[0045] In the transistor 50 according to the present embodiment, the oxide film 20 is in contact with the multilayer film 20. A material insulating film 24 is formed.

[0046] An oxide insulating film 24 is formed in contact with the multilayer film 20. The oxide insulating film 24 is The oxide insulating film contains more oxygen than the stoichiometric composition. When the oxide insulating film contains more oxygen than the oxygen required for the composition, some of the oxygen is released by heating. The oxide insulating film containing more oxygen than the stoichiometric composition was analyzed by TDS method. The amount of oxygen released is 1.0×10 18 atoms / cm 3 Above, I prefer 3.0×10 20 atoms / cm 3 The oxide insulating film is as described above.

[0047] The oxide insulating film 24 has a thickness of 30 nm to 500 nm, preferably 50 nm. A silicon oxide film, a silicon oxynitride film, or the like having a thickness of 400 nm or more and 400 nm or less can be used.

[0048] In addition, it is preferable that the oxide insulating film 24 has a small amount of defects. Therefore, the spin of the signal at g=2.001 originating from the silicon dangling bond Density is 1.5×10 18 spins / cm 3 Less than or even 1×10 18 spins / cm 3 It is preferable that:

[0049] Here, regarding the band structure in the dashed line EF in the vicinity of the multilayer film 20 in FIG. 1(B), The flow of carriers in the transistor 50 will be described with reference to FIG. This will be explained with reference to FIG. 2(B) and FIG. 2(C).

[0050] In the band structure shown in FIG. 2A, for example, the oxide semiconductor film 18 is The gap between the In-Ga-Zn oxide film and the GaAs film is 3.15 eV. The atomic ratio of the target is In:Ga:Zn=1:1:1, and the target contains In or Ga. The oxide film 19 is an In-Ga-Zn oxide (composition) having an energy gap of 3.5 eV. The atomic ratio of the sputtering target used for the film was In:Ga:Zn=1:3:2. The energy gap can be measured using a spectroscopic ellipsometer. .

[0051] Vacuum level and valence band of the oxide semiconductor film 18 and the oxide film 19 containing In or Ga The upper energy difference (also called the ionization potential) is 7.9 eV, and The energy difference between the vacuum level and the top of the valence band is 8.0 eV. Analysis(UPS:Ultraviolet Photoelectron Spectro Measurements can be performed using a fluoroscopy device (PHI VersaProbe).

[0052] The vacuum level and the conduction band of the oxide semiconductor film 18 and the oxide film 19 containing In or Ga The energy difference between the two edges (also called the electron affinity) is 4.7 eV and 4.5 eV, respectively. be.

[0053] The lower end of the conduction band of the oxide semiconductor film 18 is denoted as Ec_18, and the lower end of the conduction band of the oxide semiconductor film 18 containing In or Ga is denoted as Ec_18. The lower end of the conduction band of the oxide film 19 is Ec_19. The lower end of the conduction band of the oxide insulating film 24 is Ec_24.

[0054] As shown in FIG. 2A, in the multilayer film 20, an oxide semiconductor film 18 and In or G The bottom of the conduction band in the vicinity of the interface with the oxide film 19 containing a changes continuously. , a barrier near the interface between the oxide semiconductor film 18 and the oxide film 19 containing In or Ga. The oxide semiconductor film 18 and the oxide containing In or Ga change gradually. This shape is formed by the mutual transfer of oxygen between the films 19. In the oxide semiconductor film 18, the energy of the bottom of the conduction band is the lowest, and the region This becomes the channel region.

[0055] Here, the flow of electrons, which are carriers, in a transistor is shown in Figure 2(B 2(B) and 2(C). In FIG. 2(B) and FIG. 2(C), The amount of electrons flowing through the semiconductor film 18 is represented by the size of the dashed arrow.

[0056] In the vicinity of the interface between the oxide film 19 containing In or Ga and the oxide insulating film 24, The impurities and defects form trap levels 27. For this reason, for example, As shown in FIG. 1, when the channel region of the transistor is a single layer of the oxide semiconductor film 18, In the semiconductor film 18, electrons, which are carriers, mainly flow on the gate insulating film 17 side. As a result, the current flowing in the oxide semiconductor film 18 Some of the children are captured by trap level 27.

[0057] On the other hand, the transistor 50 in this embodiment is an oxide semiconductor as shown in FIG. An oxide film 19 containing In or Ga is provided between the insulating film 18 and the oxide insulating film 24. Therefore, there is a gap between the oxide semiconductor film 18 and the trap level 27. Electrons flowing through the compound semiconductor film 18 are not easily captured by the trap level 27. When a molecule is captured, the electron becomes a fixed negative charge. However, the oxide semiconductor film 18 and the trap level Since there is a gap between the trap level 27 and the electron trap level 27, the trap level 27 can be reduced. This makes it possible to reduce the variation in threshold voltage.

[0058] In addition, in the vicinity of the interface between the oxide semiconductor film 18 and the oxide film 19 containing In or Ga, When the energy difference ΔE1 between the lower ends of the conduction bands is small, the carriers flowing through the oxide semiconductor film 18 The electrons exceed the lower end of the conduction band of the oxide film 19 containing In or Ga and enter the trap level 27. Therefore, the lower end Ec_18 of the conduction band of the oxide semiconductor film 18 is The energy difference ΔE1 between the lower end Ec_19 of the conduction band of the oxide film 19 containing Ga or It is preferable to set the value to 1 eV or more, and more preferably 0.15 eV or more.

[0059] In addition, the back channel of the multilayer film 20 (opposing the gate electrode 15 in the multilayer film 20) On the other hand, the oxide insulating layer has more oxygen than meets the stoichiometric composition. A film 24 (see FIG. 1B) is provided. This allows oxygen to flow in a stoichiometric ratio. The oxygen contained in the oxide insulating film 24 containing more oxygen than the oxide contained in the multilayer film 20 is The oxygen vacancies in the oxide semiconductor film 18 can be reduced. It is possible.

[0060] From the above, the oxide semiconductor film 18 and the oxide film 19 containing In or Ga are A multilayer film 20 having a stoichiometric composition and more oxygen than the oxygen that satisfies the stoichiometric composition on the multilayer film 20. By including the oxide insulating film 24, oxygen vacancies in the multilayer film 20 can be reduced. It is also possible to form a semiconductor layer between the oxide semiconductor film 18 and the oxide insulating film 24 by using a material containing In or Ga. By providing the oxide film 19 containing In or Ga, the oxide semiconductor film 18 or the oxide film containing In or Ga is The concentration of silicon or carbon in the vicinity of the interface between the oxide semiconductor film 19 and the oxide semiconductor film 18 is reduced. It is possible.

[0061] As a result, the absorption coefficient of the multilayer film 20 derived by the constant photocurrent measurement method is 1× 10 -3 / cm, preferably less than 1×10 -4 / cm. The absorption coefficient is And the energy (converted by wavelength) corresponding to the localized level due to the inclusion of impurities is positively correlated Therefore, the localized level density in the multilayer film 20 is extremely low.

[0062] In addition, the absorption coefficient curve obtained by CPM measurement shows that the arbor due to the tail of the band is By removing the absorption coefficient called the "tail", the absorption coefficient due to the localized level is expressed by the following formula: The Urbach tail can be calculated from the This refers to a region in the absorption coefficient curve that has a certain slope, and this slope is called the Urbach Energy It's called ghee.

[0063]

number

[0064] Here, α(E) represents the absorption coefficient at each energy, and α u is Arbachthe represents the absorption coefficient by a

[0065] A transistor 50 having such a structure is formed in a multilayer film 20 including an oxide semiconductor film 18. Since there are very few defects in the semiconductor device, the electrical characteristics of the transistor can be improved. In addition, the threshold was set by the BT stress test and the optical BT stress test, which are examples of the stress test. The voltage does not fluctuate, or the fluctuation in the positive or negative direction is 1.0V or less. , preferably 0.5V or less, and is highly reliable.

[0066] Here, the amount of variation in the threshold voltage in the BT stress test and the light BT stress test is small. The electrical characteristics of the transistor will be described with reference to FIG.

[0067] BT stress test is a type of accelerated test that measures the transistor damage caused by long-term use. The characteristic changes (i.e., aging changes) of the BT stress can be evaluated in a short time. The amount of change in the threshold voltage of a transistor before and after testing is an important factor in determining reliability. The smaller the change in threshold voltage before and after the BT stress test, the higher the reliability. It can be said that this is a highly functional transistor.

[0068] Next, a specific BT stress test method will be described. First, Next, the temperature of the substrate on which the transistor is formed (substrate temperature) is kept constant. a pair of electrodes functioning as a source and a drain of a transistor are kept at the same potential; A potential different from that of the pair of electrodes that function as the source and drain is applied to the gate electrode for a certain period of time. The substrate temperature may be set appropriately depending on the purpose of the test. Next, the substrate temperature is adjusted to the initial characteristic temperature. The electrical characteristics of the transistor are measured at the same temperature as when the initial The difference between the threshold voltage in the initial characteristics and the threshold voltage after the BT stress test is called the threshold voltage. It can be obtained as the amount of voltage fluctuation.

[0069] In addition, the case where the potential applied to the gate electrode is higher than the potentials of the source and drain is called a positive potential. This is called a BT stress test, in which the potential applied to the gate electrode is higher than the potential of the source and drain. When the value is low, it is called a negative BT stress test. Also, BT stress test while irradiating light This is called a light BT stress test. When the potential of the source and drain is higher than that of the drain, it is called a light plus BT stress test. When the potential applied to the gate electrode is lower than the potentials of the source and drain, This is called a negative BT stress test.

[0070] The test strength of the BT stress test is determined by the substrate temperature, the electric field strength applied to the gate insulating film, and The electric field strength applied to the gate insulating film can be determined by the duration of the electric field application. It is determined by dividing the potential difference between the gate and the source and drain by the thickness of the gate insulating film. For example, If you want to apply an electric field strength of 3MV / cm to a gate insulating film with a thickness of 100nm, The potential difference between the gate and the source and drain may be set to 30V.

[0071] FIG. 1(D) shows the electrical characteristics of a transistor, with the horizontal axis representing gate voltage (Vg) and the vertical axis representing The axis is the drain current (Id). The initial characteristics of the transistor are shown by the dashed line 41, and the The electrical characteristics after the load test are indicated by a solid line 43. The transistor described in this embodiment is indicated by a dashed line 41. The amount of change in the threshold voltage in the solid line 43 is 0V, or in the positive or negative direction. The amount of change in the positive or negative direction is 1.0 V or less, preferably 0.5 V or less. The transistor shown in FIG. 1 has a small variation in threshold voltage after the BT stress test. As a result, It can be seen that the transistor 50 described in this embodiment has high reliability.

[0072] Note that the transistor including the oxide semiconductor film is an n-channel transistor; In this specification, when the gate voltage is 0V, it is considered that no drain current flows. A transistor capable of performing the above is defined as a transistor having normally-off characteristics. A transistor in which drain current can be considered to flow when the gate voltage is 0V is defined as a transistor having normally-on characteristics.

[0073] In this specification, the threshold voltage (Vth) is defined as the gate voltage (Vg [V]). axis, the square root of the drain current (Id 1 / 2 [A]) on the vertical axis. In the first place, the maximum slope is Id 1 / 2When the tangent of is extrapolated, the intersection of the tangent with the Vg axis is It is defined as the gate voltage at the point.

[0074] Other configuration details of transistor 50 are described below.

[0075] There is no particular restriction on the material of the substrate 11, but it should be at least strong enough to withstand the subsequent heat treatment. It is necessary to have heat resistance. For example, glass substrate, ceramic substrate, quartz substrate, surface treatment substrate, etc. A fiber substrate or the like may be used as the substrate 11. Also, a single material such as silicon or silicon carbide may be used. Crystalline semiconductor substrates, polycrystalline semiconductor substrates, compound semiconductor substrates such as silicon germanium, SO It is also possible to use a semiconductor substrate such as an I-substrate, and a semiconductor element is provided on the substrate. , may be used as the substrate 11.

[0076] In addition, a flexible substrate is used as the substrate 11, and the transistor 50 is directly formed on the flexible substrate. Alternatively, a peeling layer may be provided between the substrate 11 and the transistor 50. After a semiconductor device is partially or entirely completed on the layer, the layer is separated from the substrate 11 and another In this case, the transistor 50 is placed on a substrate having poor heat resistance. It can also be transferred to flexible substrates.

[0077] The gate electrode 15 may be made of aluminum, chromium, copper, tantalum, titanium, molybdenum, or titanium. or an alloy containing the above-mentioned metal elements, or The alloy may be made of a combination of manganese, zirconium, or other elements. The gate electrode 1 may be made of one or more metal elements selected from the group consisting of fluorine, arsenic, ... 5 may be a single-layer structure or a laminated structure of two or more layers. For example, aluminum containing silicon A single-layer structure of a titanium film, a two-layer structure of a titanium film on an aluminum film, and a titanium nitride film on a two-layer structure in which a titanium film is laminated on a titanium nitride film; Two-layer structure in which a tungsten film is laminated on a tantalum nitride film or a tungsten nitride film, titanium A titanium film is then formed on the aluminum film, which is then stacked on the titanium film. There are also aluminum, titanium, tantalum, tungsten, and molybdenum. An alloy film combining one or more elements selected from the group consisting of chromium, neodymium, and scandium Alternatively, a nitride film may be used.

[0078] The gate electrode 15 is made of indium tin oxide or indium oxide containing tungsten oxide. oxide, indium zinc oxide with tungsten oxide, indium oxide with titanium oxide Indium tin oxide, indium zinc oxide, silicon oxide with titanium oxide A light-transmitting conductive material such as indium tin oxide can also be used. A laminate structure of the above-mentioned light-transmitting conductive material and the above-mentioned metal element may also be used.

[0079] In addition, an In-Ga-Zn-based oxynitride semiconductor is formed between the gate electrode 15 and the gate insulating film 17. Semiconductor film, In-Sn-based oxynitride semiconductor film, In-Ga-based oxynitride semiconductor film, In-Zn-based oxynitride semiconductor film Nitride semiconductor film, Sn-based oxynitride semiconductor film, In-based oxynitride semiconductor film, metal nitride film (In These films may have a resistivity of 5 eV or more, preferably 5.5 eV or more. Since the electron affinity of the oxide semiconductor is larger than that of the oxide semiconductor, The threshold voltage of the transistor using the above-mentioned can be shifted to the positive side. It is possible to realize a switching element with off characteristics. For example, In-Ga-Zn-based oxynitride semiconductor In the case of using a film, the nitrogen concentration is at least higher than that of the oxide semiconductor film 18, specifically, 7 atomic %. The above-mentioned In-Ga-Zn-based oxynitride semiconductor film is used.

[0080] The gate insulating film 17 is made of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, or nitride. Silicon oxide, aluminum oxide, hafnium oxide, gallium oxide or Ga-Zn-based metal oxide Silicon oxide, silicon nitride, etc. may be used, and the layer may be a single layer or a multilayer. As shown in FIG. 1, the gate insulating film 17 has a laminated structure of a gate insulating film 17a and a gate insulating film 17b. The gate insulating film 17b in contact with the multilayer film 20 is made of an oxide insulating material from which oxygen is released by heating. By using a film from which oxygen is released by heating as the gate insulating film 17b, the oxidation It is possible to reduce the interface state density at the interface between the compound semiconductor film 18 and the gate insulating film 17. As a result, a transistor with little deterioration in electrical characteristics can be obtained. By providing an insulating film having a blocking effect against oxygen, hydrogen, water, etc. as 17a, The diffusion of oxygen from the oxide semiconductor film 18 to the outside and the diffusion of hydrogen from the outside to the oxide semiconductor film 18. It is possible to prevent the intrusion of water, etc. It is an insulating film that has a blocking effect on oxygen, hydrogen, water, etc. Examples include aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, Yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, etc. do.

[0081] The gate insulating film 17 is made of hafnium silicate (HfSiO x ), nitrogen is added Hafnium Silicate (HfSi x Oy N z ), nitrogen-doped hafnium aluminium minate (HfAl x O y N z ), hafnium oxide, yttrium oxide and other high- The use of k-materials can reduce the gate leakage of transistors.

[0082] The thickness of the gate insulating film 17 is 5 nm or more and 400 nm or less, and more preferably 10 nm or more. It is preferably 300 nm or less, and more preferably 50 nm or more and 250 nm or less.

[0083] The pair of electrodes 21 and 22 are made of a conductive material such as aluminum, titanium, chromium, or nickel. , copper, yttrium, zirconium, molybdenum, silver, tantalum, or tungsten A single metal or an alloy containing this as the main component is used as a single layer structure or a laminate structure. For example, a single-layer structure of an aluminum film containing silicon, or a titanium film laminated on an aluminum film, Two-layer structure: a titanium film laminated on a tungsten film; copper-magnesium-aluminum A two-layer structure in which a copper film is laminated on a titanium alloy film, a titanium film or titanium nitride film, and the titanium film Alternatively, an aluminum film or a copper film is laminated on the titanium nitride film, and a titanium film is further laminated on the aluminum film or a copper film. or a three-layer structure in which a titanium nitride film is formed, a molybdenum film or a molybdenum nitride film, and the molybdenum film An aluminum film or a copper film is laminated on the molybdenum film or the molybdenum nitride film, and then the aluminum film or the copper film is laminated on the molybdenum film or the molybdenum nitride film. There are three-layer structures, such as a molybdenum film or a molybdenum nitride film formed on the indium oxide film. Transparent conductive materials including aluminum, tin oxide, or zinc oxide may also be used.

[0084] In addition, a nitride insulating film having a blocking effect against oxygen, hydrogen, water, etc. is formed on the oxide insulating film 24. By providing the insulating film 25, the diffusion of oxygen from the multilayer film 20 to the outside and the diffusion of oxygen from the outside to the multilayer film 20 can be prevented. The nitride insulating film can prevent hydrogen, water, etc. from penetrating into the substrate. Silicon oxide, aluminum nitride, aluminum oxide nitride, etc. Instead of a nitride insulating film that has a blocking effect against water, etc., An oxide insulating film having a blocking effect against oxygen, hydrogen, water, etc. may be provided. Examples of the oxide insulating film include aluminum oxide, aluminum oxynitride, and gallium oxide. , gallium oxide, yttrium oxide, yttrium oxide nitride, hafnium oxide, Hafnium nitride and the like.

[0085] Next, a manufacturing method of the transistor 50 shown in FIGS.

[0086] As shown in FIG. 3A, a gate electrode 15 is formed on a substrate 11. A gate insulating film 17 is formed.

[0087] Here, a glass substrate is used as the substrate 11.

[0088] The method of forming the gate electrode 15 will be described below. First, the sputtering method, the CVD method, and the evaporation method are used. A conductive film is formed by deposition or the like, and a mask is formed on the conductive film by a photolithography process. Next, a part of the conductive film is etched using the mask to form the gate electrode 15. After this, the mask is removed.

[0089] The gate electrode 15 may be formed by electrolytic plating, printing, ink jet printing, or the like instead of the above-mentioned method. It may be formed by a jet method or the like.

[0090] Here, a tungsten film having a thickness of 100 nm is formed by sputtering. A mask is formed by a photolithography process, and a tungsten film is formed using the mask. The gate electrode 15 is formed by dry etching.

[0091] The gate insulating film 17 is formed by a sputtering method, a CVD method, a vapor deposition method or the like.

[0092] The gate insulating film 17 is a silicon oxide film, a silicon oxynitride film, or a silicon nitride oxide film. When forming a film, a deposition gas containing silicon and an oxidizing gas are used as the source gas. Representative examples of deposition gases containing silicon include silane, disilane, and trisilane. Examples of oxidizing gases include oxygen, ozone, nitrous oxide, Nitrogen dioxide, etc.

[0093] In addition, when forming a silicon nitride film as the gate insulating film 17, a two-stage formation method is used. First, a mixture gas of silane, nitrogen, and ammonia is used as a raw material gas. The first silicon nitride film with few defects is formed by the plasma CVD method used as the first silicon nitride film. The raw material gas is switched to a mixture of silane and nitrogen, and the hydrogen concentration is low. A second silicon nitride film capable of blocking the above-mentioned is formed. As a result, the gate insulating film 17 is made of a nitride film having few defects and a hydrogen blocking property. A silicon film can be formed.

[0094] In addition, when a gallium oxide film is formed as the gate insulating film 17, MOCVD (Metal Organic Chemical Vapor Deposition (OCVD) method It can be formed by:

[0095] Next, as shown in FIG. 3B, an oxide semiconductor film 18 and an In-based Alternatively, an oxide film 19 containing Ga is formed.

[0096] Regarding a method for forming the oxide semiconductor film 18 and the oxide film 19 containing In or Ga, The following description will be given. On the gate insulating film 17, an oxide semiconductor film that will become the oxide semiconductor film 18 and and an oxide film containing In or Ga which becomes an oxide film 19 containing In or Ga. Next, a photolithography process is performed on the oxide film containing In or Ga. After forming a mask, the oxide semiconductor film and the acid containing In or Ga are By etching each part of the oxide film, the gate insulating film is formed as shown in FIG. The oxide semiconductor film 1 is isolated from the gate electrode 15 so as to overlap with a part of the gate electrode 15. A multilayer film 20 having a first oxide film 8 and an oxide film 19 containing In or Ga is formed. The mask is removed.

[0097] The oxide semiconductor film that becomes the oxide semiconductor film 18 and the oxide film 19 containing In or Ga The oxide film containing In or Ga can be formed by sputtering, coating, pulse laser, etc. The film can be formed by using a deposition method, a laser ablation method, or the like.

[0098] The oxide semiconductor film and the oxide film containing In or Ga are formed by a sputtering method. In this case, the power supply for generating plasma can be an RF power supply, an AC power supply, or a DC power supply. Apparatuses etc. can be used as appropriate.

[0099] The sputtering gas is a rare gas (typically argon), oxygen gas, or a mixture of a rare gas and oxygen. A mixed gas is used as appropriate. In the case of a mixed gas of rare gas and oxygen, the ratio of oxygen to rare gas is It is preferable to increase the gas ratio.

[0100] The target is a target for forming an oxide semiconductor film and an oxide film containing In or Ga. It may be appropriately selected according to the composition.

[0101] When the oxide semiconductor film and the oxide film containing In or Ga are formed, for example, When the sputtering method is used, the substrate temperature is set to 150° C. or higher and 500° C. or lower, preferably 15 The temperature is set to 0°C or higher and 450°C or lower, and more preferably 200°C or higher and 350°C or lower. By forming an oxide semiconductor film and an oxide film containing In or Ga from the An AC-OS film can be formed.

[0102] The oxide semiconductor film and the oxide film containing In or Ga are not simply stacked. Continuous junctions (here, specifically, structures in which the energy at the bottom of the conduction band changes continuously between each film) In other words, trap centers and recombination centers are formed at the interfaces of each film. Impurities that form defect levels such as centers or barriers that impede the flow of carriers If the stacked oxide semiconductor film and In or When impurities are mixed in the oxide film containing Ga, the continuity of the energy band is lost. At the interface, the carriers are trapped or recombine and disappear.

[0103] To form continuous junctions, a multi-chamber deposition system equipped with a load lock chamber is required. Each film is laminated in succession using a sputtering device without exposing it to the air. Each chamber in the sputtering apparatus is required for the oxide semiconductor film. In order to remove impurities such as water as much as possible, an adsorption type vacuum pump such as a cryopump is used. High vacuum pump (1×10 -4 Pa~5×10 -7 It is preferable to use a temperature of up to about 1 Pa. Alternatively, a turbo molecular pump and cold trap can be combined to evacuate the chamber from the exhaust system. It is preferable to prevent gas from flowing back into the tank.

[0104] In order to obtain a highly pure intrinsic oxide semiconductor film, the inside of the chamber must be highly evacuated. In addition, the sputtering gas must be highly purified. Gongas has a dew point of -40°C or less, preferably -80°C or less, more preferably -100°C or less. By using a gas that is highly purified to the following level, moisture and the like are taken into the oxide semiconductor film. can be prevented as much as possible.

[0105] Here, a 35-nm-thick In-Ga oxide semiconductor film is formed by sputtering. -Zn oxide film (The atomic ratio of the sputtering target used for film formation was In:Ga:Zn =1:1:1), and then an oxide containing In or Ga is formed by sputtering. The film was a 20 nm thick In-Ga-Zn oxide film (the sputtering target used for the film formation). The atomic ratio of the dots is In:Ga:Zn=1:3:2). Next, In or Ga A mask is formed over the oxide film containing In or Ga, By selectively etching a part of each of the films, the oxide semiconductor film 18 and In or The multilayer film 20 includes an oxide film 19 containing Ga.

[0106] After this, a heat treatment may be carried out.

[0107] Next, as shown in FIG. 3(C), a pair of electrodes 21 and 22 are formed.

[0108] The method for forming the pair of electrodes 21 and 22 will be described below. First, the sputtering method and the CVD method are used. Next, a conductive film is formed on the conductive film by a photolithography process. Next, the conductive film is etched using the mask to form a pair of electrodes 21 and 2 2 is formed. After this, the mask is removed.

[0109] Here, a tungsten film having a thickness of 50 nm, an aluminum film having a thickness of 400 nm, and a A titanium film having a thickness of 100 nm is then laminated on the titanium film by sputtering. A mask is formed by a photolithography process, and a tungsten film and an aluminum film are formed by using the mask. The aluminum film and the titanium film are dry etched to form a pair of electrodes 21 and 22 .

[0110] Next, as shown in FIG. 3(D), an oxide insulating layer is formed on the multilayer film 20 and the pair of electrodes 21 and 22. A film 24 is formed.

[0111] After the pair of electrodes 21 and 22 are formed, they are continuously insulated with oxide without being exposed to the air. After the pair of electrodes 21 and 22 are formed, the electrodes are not exposed to the atmosphere. The oxide insulating film 24 is formed by adjusting one or more of the flow rate, pressure, high frequency power, and substrate temperature of the source gas. By successively forming the oxide film 19 containing In or Ga and the oxide insulating film 24, At the interface, the concentration of impurities derived from atmospheric components can be reduced, and the oxide insulation The oxygen contained in the film 24 can be transferred to the oxide semiconductor film 18, and the oxide semiconductor Therefore, the amount of oxygen vacancies in the membrane 18 can be reduced.

[0112] The oxide insulating film 24 is placed in a vacuum-evacuated processing chamber of a plasma CVD apparatus. The substrate is kept at a temperature of 180° C. or higher and 260° C. or lower, more preferably 200° C. or higher and 240° C. or lower. The raw material gas is introduced into the processing chamber to set the pressure in the processing chamber at 100 Pa or more and 250 Pa or less. More preferably, the pressure is set to 100 Pa or more and 200 Pa or less. .17W / cm 2 More than 0.5W / cm 2 Less than or equal to 0.25 W / cm 2 End 0.35W / cm 2 Silicon oxide or oxynitride is formed by supplying the following high frequency power. A silicon oxide film is formed.

[0113] As the source gas of the oxide insulating film 24, a deposition gas containing silicon and an oxidizing gas are used. Representative examples of silicon-containing deposition gases include silane, disilane, and trisilane. Examples of oxidizing gases include oxygen, ozone, nitrous oxide, Nitrogen dioxide, etc.

[0114] The oxide insulating film 24 is formed under the following film forming conditions: high frequency power density in a processing chamber at the above pressure Supplying electric power increases the efficiency of decomposing the source gas in the plasma, and oxygen radicals increase. However, since the oxidation of the source gas proceeds, the oxygen content in the oxide insulating film 24 becomes lower than the stoichiometric ratio. However, when the substrate temperature is set to the above temperature, the bonding strength between silicon and oxygen is increased. Since the oxygen is weak, some of the oxygen is released by heating. As a result, the oxygen content of the stoichiometric composition is The oxide insulating film contains more oxygen than the insulating film, and part of the oxygen is released by heating. In addition, the oxide film 19 containing In or Ga can serve as a protective film for the oxide semiconductor film 18. As a result, damage to the oxide semiconductor film 18 can be reduced while achieving high power density. The oxide insulating film 24 can be formed using frequency power.

[0115] In addition, in the deposition conditions of the oxide insulating film 24, the deposition gas containing silicon is By increasing the flow rate of the reactive gas, it is possible to reduce the number of defects in the oxide insulating film 24. Typically, ESR measurements reveal that the g value is 2.0 due to the dangling bonds of silicon. The spin density of the signal appearing in 01 is 6×10 17 spins / cm 3 Less than 3x, preferably 10 17 spins / cm 3 Less than or equal to 1.5×10 17 spins / cm 3 below As a result, an oxide insulating film with a small number of defects can be formed. Reliability can be improved.

[0116] Here, the oxide insulating film 24 is formed by using silane at a flow rate of 160 sccm and SiO2 at a flow rate of 4000 s. The source gas was nitrous oxide (N2O) at 1.0 ccm, the pressure in the processing chamber was 200 Pa, and the substrate temperature was 220° C. A 27.12MHz high-frequency power source was used to apply 1500W of high-frequency power to the parallel plate electrodes. A silicon oxynitride film with a thickness of 400 nm is formed by the supplied plasma CVD method. The plasma CVD device has an electrode area of ​​6000 cm 2 Parallel plate plasma CVD The power supplied to the device is converted to power per unit area (power density) of 0.25W. / cm 2 It is.

[0117] Next, a heat treatment is performed. The temperature of the heat treatment is typically 150° C. or higher but not higher than the substrate distortion point. Preferably, the temperature is 200° C. or higher and 450° C. or lower, and more preferably, the temperature is 300° C. or higher and 450° C. or lower. do.

[0118] The heat treatment can be performed using an electric furnace, an RTA device, or the like. Therefore, heat treatment can be performed at a temperature above the distortion point of the substrate for a short period of time. The processing time can be reduced.

[0119] Heat treatment is carried out in a vacuum of nitrogen, oxygen, or ultra-dry air (water content of 20 ppm or less, preferably 1 ppm). pm or less, preferably 10 ppb or less of air), or rare gases (argon, helium, etc.) The above-mentioned nitrogen, oxygen, ultra-dry air, or rare gas may be mixed with hydrogen, water, etc. It is preferable that it is not included.

[0120] By the heat treatment, part of oxygen contained in the oxide insulating film 24 is transferred to the oxide semiconductor film 18. By this, the amount of oxygen vacancies in the oxide semiconductor film 18 can be reduced. When the compound insulating film 24 contains water, hydrogen, etc., the compound insulating film 24 has a function of blocking water, hydrogen, etc. When the nitride insulating film 25 is subsequently formed and heat treatment is performed, the water contained in the oxide insulating film 24, Hydrogen and the like move to the oxide semiconductor film 18, causing defects in the oxide semiconductor film 18. However, the heating causes water, hydrogen, and the like contained in the oxide insulating film 24 to be desorbed. This reduces the variation in the electrical characteristics of the transistor 50 and reduces the threshold voltage The oxide insulating film 24 is then heated with In or By forming the oxide film 19 containing Ga, oxygen is transferred to the oxide semiconductor film 18, and the oxide Since it is possible to reduce oxygen vacancies in the oxide semiconductor film 18, the heat treatment is This does not have to be done.

[0121] Here, heat treatment is performed in a nitrogen and oxygen atmosphere at 350° C. for 1 hour.

[0122] In addition, when the pair of electrodes 21 and 22 are formed, the multilayer film 20 is formed by etching the conductive film. The oxide is damaged, and oxygen vacancies occur on the back channel side of the multilayer film 20. The insulating film 24 is an oxide insulating film containing more oxygen than the oxygen that satisfies the stoichiometric composition. By this, it is possible to repair the oxygen vacancies that have occurred on the back channel side due to the heat treatment. This can reduce defects in the multilayer film 20, improving the transistor performance. This can improve the reliability of the controller 50.

[0123] Next, the nitride insulating film 25 is formed by sputtering, CVD or the like.

[0124] When the nitride insulating film 25 is formed by the plasma CVD method, The substrate placed in the evacuated processing chamber is heated to 300° C. or higher and 400° C. or lower, more preferably A temperature of 320° C. or higher and 370° C. or lower is preferable because it allows the formation of a dense nitride insulating film. .

[0125] When a silicon nitride film is formed as the nitride insulating film 25 by the plasma CVD method, the silicon It is preferable to use a deposition gas containing carbon, nitrogen, and ammonia as the source gas. By using a small amount of ammonia as the source gas compared to nitrogen, ammonia is generated in the plasma. Ni dissociates and generates active species. The active species are contained in the deposition gas containing silicon. The bond between silicon and hydrogen and the triple bond between nitrogen are broken. As a result, silicon and nitrogen The bonding of silicon and hydrogen is promoted, resulting in fewer defects and a dense silicon nitride. On the other hand, the amount of ammonia relative to nitrogen in the source gas is If the amount is too large, the decomposition of the deposition gas containing silicon and nitrogen does not proceed, and silicon and hydrogen Bonds remain, resulting in a silicon nitride film with increased defects and a rough surface. For these reasons, the flow rate ratio of nitrogen to ammonia in the raw gas is set to 5 to 50. It is preferably 10 or more and 50 or less.

[0126] Here, silane at a flow rate of 50 sccm and 5000 The source gases were nitrogen at a flow rate of 100 sccm and ammonia at a flow rate of 100 sccm. The pressure in the processing chamber was The pressure was set at 100 Pa, the substrate temperature was set at 350°C, and a 27.12 MHz high frequency power source was used for 1000 A 50 nm thick nitride film was formed by plasma CVD using a 1000 MHz high frequency power supply to parallel plate electrodes. A silicon film is formed. The plasma CVD device has an electrode area of ​​6000 cm. 2 It is flat This is a horizontal and flat type plasma CVD device, and the supplied power is expressed as power per unit area (power density ) is converted to 1.7 × 10 -1 W / cm 2 It is.

[0127] Through the above steps, a protective film 26 consisting of the oxide insulating film 24 and the nitride insulating film 25 is formed. It can be formed.

[0128] Next, a heat treatment may be performed. The temperature of the heat treatment is typically 150° C. or higher. Less than the strain point, preferably 200°C or more and 450°C or less, more preferably 300°C or more and 450°C or less. ℃ or less.

[0129] Through the above steps, the transistor 50 can be manufactured.

[0130] An oxygen semiconductor film having a stoichiometric composition overlapping with the oxide semiconductor film functioning as a channel region By forming an oxide insulating film that contains more oxygen than the As a result, the amount of oxygen vacancies in the oxide semiconductor film can be reduced. can be reduced.

[0131] Then, an oxide film containing In or Ga is formed on the oxide semiconductor film, When forming an oxide insulating film containing more oxygen than the oxygen that satisfies the stoichiometric composition, In addition, the semiconductor film containing In or Ga can be further prevented from being damaged. By forming an oxide film, an insulating film, for example, an oxide insulating film, is formed on the oxide semiconductor film. Contamination of constituent elements of the film into the oxide semiconductor film can be suppressed.

[0132] From the above, it is possible to provide a semiconductor device including an oxide semiconductor film, in which the amount of defects is reduced. In addition, the electrical characteristics of a semiconductor device including an oxide semiconductor film can be improved. The above semiconductor device can be obtained.

[0133] <Variation 1> In the transistor 50 of this embodiment, the substrate 11 and the gate electrode A base insulating film may be provided between the electrodes 15. The base insulating film may be made of silicon oxide, oxide, or the like. Silicon nitride, silicon nitride, silicon oxynitride, gallium oxide, hafnium oxide, oxide Examples of the insulating film include yttrium oxide, aluminum oxide, and aluminum oxynitride. The materials used are silicon nitride, gallium oxide, hafnium oxide, yttrium oxide, and oxide. By using aluminum or the like, impurities, typically alkali metals, water, water The diffusion of elements and the like into the multilayer film 20 can be suppressed.

[0134] The base insulating film can be formed by a sputtering method, a CVD method, or the like.

[0135] <Variation 2> In the oxide semiconductor film 18 provided in the transistor 50 described in this embodiment, By using an oxide semiconductor film with a low concentration of dopants and a low density of defect states, it is possible to obtain even better electrical properties. In this embodiment, the impurity concentration is low, and A low density of defect levels (low oxygen vacancies) is called high purity intrinsic or substantially high purity intrinsic. A highly-purified intrinsic or substantially highly-purified intrinsic oxide semiconductor has a small carrier generation source. Therefore, the carrier density can be reduced in some cases. A transistor using a GaN-based channel region has electrical characteristics in which the threshold voltage is negative ( Also called marion.) It is rare for it to become high purity genuine or substantially high purity genuine. Since the oxide semiconductor, which is a conductive material, has a low density of defect states, the density of trap states is also low. Therefore, a transistor using the oxide semiconductor for a channel region has small fluctuation in electrical characteristics. In addition, the electrons trapped in the trap states of the oxide semiconductor can be removed by the The charge may take a long time to dissipate and may behave as if it were a fixed charge. Therefore, a transistor using an oxide semiconductor with a high density of trap states for the channel region is Impurities include hydrogen, nitrogen, alkali metals, Or alkaline earth metals, etc.

[0136] The hydrogen contained in the oxide semiconductor reacts with the oxygen that is bonded to the metal atom to form water, and the acid Oxygen vacancies are formed in the lattice from which oxygen has been removed (or in the area from which oxygen has been removed). When an element enters, electrons that act as carriers can be generated. Also, some of the hydrogen can become metal. By bonding with oxygen, which bonds with atoms, electrons that act as carriers may be generated. Therefore, a transistor using an oxide semiconductor containing hydrogen has normally-on characteristics. Cheap.

[0137] Therefore, it is preferable that the amount of hydrogen in the oxide semiconductor film 18 be reduced as much as possible. Specifically, the oxide semiconductor film 18 is subjected to secondary ion mass spectrometry (SIMS). The hydrogen concentration obtained by 5-ary Ion Mass Spectrometry was ×10 18 atoms / cm 3 Less than or equal to 1×10 18 atoms / cm 3 The following is more preferable: is 5 x 10 17 atoms / cm 3 Less than 1×10, more preferably 16 atoms / cm 3 The following do.

[0138] As a method for reducing the hydrogen concentration in the oxide semiconductor film 18, After forming a multilayer film 20 having a conductor film 18 and an oxide film 19 containing In or Ga, By performing the heat treatment, the hydrogen concentration in the oxide semiconductor film 18 can be reduced. The treatment temperature is typically 150° C. or higher and lower than the substrate distortion point, preferably 200° C. or higher and 45° C. or lower. The temperature is set to 0° C. or lower, and more preferably 300° C. to 450° C.

[0139] The oxide semiconductor film 18 is also formed of an alkali metal or The concentration of alkaline earth metals is 1×10 18 atoms / cm 3 Less than or equal to 2×10 16 original Child / cm 3 The alkali metal and alkaline earth metal bond to the oxide semiconductor. This can generate carriers, increasing the off-state current of the transistor. Therefore, the concentration of the alkali metal or alkaline earth metal in the oxide semiconductor film 18 is reduced. It is preferable.

[0140] By providing a nitride insulating film on a part of the gate insulating film 17, the alkali metal oxide semiconductor film 18 The concentration of alkali metals or alkaline earth metals can be reduced.

[0141] In addition, when the oxide semiconductor film 18 contains nitrogen, electrons that serve as carriers are generated. The rear density increases and it becomes easier to make it n-type. The transistor having the oxide semiconductor film tends to be normally on. It is preferable that the nitrogen is reduced as much as possible. For example, the nitrogen concentration is 5×10 1 8 atoms / cm 3 It is preferable to do the following:

[0142] In this way, impurities (hydrogen, nitrogen, alkali metals, alkaline earth metals, etc.) can be removed. By using the oxide semiconductor film 18, which is highly purified by reducing the amount of oxygen as much as possible, a transistor can be manufactured. This makes it possible to suppress the occurrence of marionation characteristics, and significantly reduce the off-state current of the transistor. Therefore, a semiconductor device having good electrical characteristics can be manufactured. A semiconductor device having such a structure can be manufactured.

[0143] The reason why the off-state current of a transistor using a highly purified oxide semiconductor film is low is that This can be proved by various experiments. For example, when the channel width is 1×10 6 Channel length L in μm Even if the element has a thickness of 10 μm, the voltage between the source and drain electrodes (drain voltage) is 1 In the range from V to 10 V, the off-state current is below the measurement limit of the semiconductor parameter analyzer. , i.e. 1 × 10 -13 In this case, the off-current can be reduced to less than 1 A. The value divided by the transistor channel width is found to be less than 100zA / μm. In addition, the capacitance element and the transistor are connected to each other, and the capacitance element is connected to the transistor. The off-state current was measured using a circuit that controls the charge of the transistor. The present invention relates to a transistor in which a part of a highly purified oxide semiconductor film is used for a channel region, and The off-state current of the transistor was measured from the change in the charge amount per unit time of the capacitance element. As a result, when the voltage between the source and drain electrodes of the transistor is 3V, several tens of yA / It was found that an even lower off-state current of 100 μm could be obtained. A transistor using a nitride semiconductor film has an extremely small off-state current.

[0144] <Variation 3> The pair of electrodes 21 and 22 in the transistor 50 shown in this embodiment are elemental or non-elementary metals such as tantalum, titanium, aluminum, copper, molybdenum, chromium, or tantalum It is preferable to use a conductive material that easily bonds with oxygen, such as an alloy. The oxygen contained in the electrode 21 and the conductive material contained in the pair of electrodes 22 are bonded to each other, and the multilayer film 20 In addition, a pair of electrodes 21 and 22 are formed on the multilayer film 20. In some cases, some of the constituent elements of the conductive material may be mixed in. As a result, in the multilayer film 20, A low resistance region is formed in the vicinity of the region in contact with the pair of electrodes 21 and 22. 4A is an enlarged cross-sectional view of the multilayer film 20 of the transistor 50 of FIG. Or, most of the low resistance regions 28a and 29a are formed in the oxide film 19 containing Ga. Alternatively, as shown in FIG. 4B, the oxide semiconductor film 18 and In or In the oxide film 19 containing Ga, low resistance regions 28b and 29b may be formed. Alternatively, as shown in FIG. 4C, an oxide semiconductor film 18 and an oxide containing In or Ga are In the oxide film 19, low resistance regions 28c and 29c are formed so as to contact the gate insulating film 17. The low resistance regions 28a to 28c and 29a to 29c have high electrical conductivity. Therefore, it is possible to reduce the contact resistance between the multilayer film 20 and the pair of electrodes 21 and 22. It is possible to increase the on-current of the transistor.

[0145] <Modification 4> In the method for manufacturing the transistor 50 described in this embodiment, After the etching, a cleaning process may be performed to remove etching residues. This makes it possible to suppress the occurrence of leakage current flowing between the pair of electrodes 21 and 22. The cleaning process is carried out using TMAH (Tetramethylammonium Hydroxide). de) alkaline solutions such as dilute hydrofluoric acid, oxalic acid, phosphoric acid, and other acidic solutions. This can be done.

[0146] <Variation 5> In the method for manufacturing the transistor 50 described in this embodiment, After the formation of the multilayer film 20, the multilayer film 20 is exposed to plasma generated in an oxygen atmosphere to form the oxide semiconductor film 18 and Oxygen may be supplied to the oxide film 19 containing In or Ga. The oxygen atmosphere may be The atmosphere may be oxygen, ozone, nitrous oxide, nitrogen dioxide, etc. In this case, the multilayer film 20 is exposed to plasma generated without applying a bias to the substrate 11 side. As a result, it is possible to supply oxygen without damaging the multilayer film 20. This makes it possible to reduce the amount of oxygen vacancies in the multilayer film 20. The impurities remaining on the surface of the multilayer film 20 due to the etching treatment, such as halogens such as fluorine and chlorine, are removed. etc. can be removed.

[0147] The structures and methods described in this embodiment may be used in conjunction with structures and methods described in other embodiments and examples. and the like.

[0148] (Embodiment 2) In this embodiment, the number of defects in the oxide semiconductor film is further reduced compared to that in the first embodiment. A semiconductor device having a transistor capable of implementing the above-mentioned method will be described with reference to the drawings. The transistor described in the present embodiment has a gate insulating film and an oxide film, which are different from those in the first embodiment. The difference is that an oxide film containing In or Ga is provided between the semiconductor films.

[0149] FIG. 5A shows a top view and a cross-sectional view of a transistor 60 included in the semiconductor device. 5(B) is a cross-sectional view of the transistor 60 taken along dashed line AB in FIG. 5(A). 5(C) is a cross-sectional view taken along dashed line CD in FIG. 5(A). In (A), for clarity, the substrate 11, the gate insulating film 17, the oxide insulating film 23, and the oxide insulating film 24 are shown. The insulating film 24, the nitride insulating film 25, etc. are omitted.

[0150] The transistor 60 shown in FIG. 5 has a gate electrode 15 provided on a substrate 11. Further, a gate insulating film 17 is formed on the substrate 11 and the gate electrode 15. a multilayer film 34 overlapping the gate electrode 15 via the gate electrode 15; and a pair of electrodes 21 in contact with the multilayer film 34. On the gate insulating film 17, the multilayer film 34, and the pair of electrodes 21 and 22, In addition, a protective film 26 made of an oxide insulating film 24 and a nitride insulating film 25 is formed.

[0151] In the transistor 60 according to this embodiment, the multilayer film 34 contains In or Ga. The oxide film 31 includes an oxide semiconductor film 32, and an oxide film 33 including In or Ga. A part of the oxide semiconductor film 32 functions as a channel region.

[0152] Also, the gate insulating film 17 and the oxide film 31 containing In or Ga are in contact with each other. An oxide film 31 containing In or Ga is provided between the insulating film 17 and the oxide semiconductor film 32. It is being done.

[0153] In addition, the oxide insulating film 24 and the oxide film 33 containing In or Ga are in contact with each other. Between the compound semiconductor film 32 and the oxide insulating film 24, an oxide film 33 containing In or Ga is provided. It is being done.

[0154] The oxide film 31 containing In or Ga and the oxide film 33 containing In or Ga are The same material and forming method as the oxide film 19 containing In or Ga shown in the first embodiment are used appropriately. It can be used.

[0155] The oxide semiconductor film 32 is formed using a material similar to that of the oxide semiconductor film 18 described in Embodiment 1. Any suitable method can be used.

[0156] When the oxide film 31 containing In or Ga is an In-M-Zn oxide, In The atomic ratio of In and M is preferably less than 50 atomic % and M is preferably less than 50 atomic %. % or more, more preferably In is less than 25 atomic % and M is 75 atomic % or more. The oxide semiconductor film 32 and the oxide film 33 containing In or Ga are In-M-Zn In the case of an oxide, the atomic ratio of In and M is preferably the same as that shown in the first embodiment.

[0157] Here, the oxide film 31 containing In or Ga is formed by sputtering to a thickness of 100 nm. The In-Ga-Zn oxide film with a thickness of 30 nm (atomic size of the sputtering target used for the film formation) The ratio of In:Ga:Zn is 1:6:4. A 10 nm thick In-Ga-Zn oxide film (atomic size of the sputtering target used for film formation) The numerical ratio is In:Ga:Zn=1:1:1). In addition, oxides containing In or Ga The substrate 33 is a 10 nm thick In-Ga-Zn oxide film (the sputtering method used for the deposition The atomic ratio of the target is In:Ga:Zn=1:3:2).

[0158] Here, the band structure in the dashed and dotted line GH in the vicinity of the multilayer film 34 of the transistor 60 in FIG. The structure of the transistor 60 will be described with reference to FIG. This will be explained with reference to FIG. 6(B).

[0159] In the band structure shown in FIG. 6A, for example, an oxide film 31 containing In or Ga The energy gap of the In-Ga-Zn oxide film is 3.8 eV. The atomic ratio of the sputtering target is In:Ga:Zn=1:6:4. Oxide The semiconductor film 32 is made of In-Ga-Zn oxide (compound) having an energy gap of 3.2 eV. The atomic ratio of the sputtering target used for the film was In:Ga:Zn=1:1:1. The oxide film 33 containing In or Ga has an energy gap of 3.5 eV. The atomic ratio of the sputtering target used for the deposition of In-Ga-Zn oxide was In: Ga:Zn=1:3:2) is used.

[0160] The oxide film 31 containing In or Ga, the oxide semiconductor film 32, and the In or Ga The energy difference between the vacuum level and the top of the valence band of the oxide film 33 containing ) are 7.8 eV, 7.9 eV, and 8.0 eV, respectively.

[0161] The oxide film 31 containing In or Ga, the oxide semiconductor film 32, and the In or Ga The energy difference between the vacuum level and the bottom of the conduction band of the oxide film 33 containing the silicon dioxide is expressed as follows (also called electron affinity): These are 4.0 eV, 4.7 eV, and 4.5 eV, respectively.

[0162] The lower end of the conduction band of the oxide film 31 containing In or Ga is Ec_31, The lower end of the conduction band of the semiconductor film 32 is Ec_32, and the lower end of the conduction band of the oxide film 33 containing In or Ga is Ec_32. The lower end of the conduction band is Ec_33. The lower end of the conduction band of the gate insulating film 17 is Ec_17. The bottom of the conduction band of the oxide insulating film 24 is Ec_24.

[0163] As shown in FIG. 6A, in the multilayer film 34, an oxide film 31 containing In or Ga is The lower end of the conduction band near the interface between the oxide semiconductor film 32 and the oxide semiconductor film 32 The lower end of the conduction band in the vicinity of the interface with the oxide film 33 containing n or gallium changes continuously. That is, in the vicinity of the interface between the oxide film 31 containing In or Ga and the oxide semiconductor film 32 and in the vicinity of the interface between the oxide semiconductor film 32 and the oxide film 33 containing In or Ga. There is no barrier and the slope changes smoothly. A structure with such a conduction band bottom is called a U-shaped It can also be called a U-shaped well structure. Oxide film containing In or Ga Between the oxide semiconductor film 32 and the oxide semiconductor film 32, and between the oxide semiconductor film 32 and the oxide containing In or Ga. This shape is formed by the mutual transfer of oxygen between the oxide film 33 and the multilayer film. In FIG. 34, the energy of the bottom edge Ec_32 of the conduction band in the oxide semiconductor film 32 is the lowest. The region becomes a channel region.

[0164] Here, the flow of electrons, which are carriers, in the transistor 60 will be described with reference to FIG. Note that in FIG. 6B, the electron The flow is represented by the size of the dashed arrow.

[0165] In the vicinity of the interface between the gate insulating film 17 and the oxide film 31 containing In or Ga, impurities The trap level 36 is formed by the defects and the oxide containing In or Ga. Similarly, a trap level 37 is formed in the vicinity of the interface between the film 33 and the oxide insulating film 24. In the transistor 60 of this embodiment, as shown in FIG. An oxide film 31 containing In or Ga is provided between the insulating film 17 and the oxide semiconductor film 32. There is a gap between the oxide semiconductor film 32 and the trap states 36. An oxide film 33 containing In or Ga is provided between the semiconductor film 32 and the oxide insulating film 24. There is a gap between the oxide semiconductor film 32 and the trap states 37 .

[0166] As a result, electrons flowing through the oxide semiconductor film 32 are captured by the trap states 36 and 37. This makes it possible to increase the on-state current of the transistor and to improve the field effect mobility. In addition, when an electron is captured by the trap levels 36 and 37, the electron This results in a negative fixed charge. As a result, the threshold voltage of the transistor fluctuates. However, between the oxide semiconductor film 32 and the trap states 36 and 37, The distance reduces the electron capture at the trap levels 36 and 37. As a result, the variation in threshold voltage can be reduced.

[0167] In addition, in the vicinity of the interface between the oxide film 31 containing In or Ga and the oxide semiconductor film 32, and the energy difference ΔE2 between the bottom ends of the conduction bands of the oxide semiconductor film 32 and the The energy difference ΔE3 at the bottom of the conduction band near the interface with the oxide film 33 is small. In other words, the carriers flowing through the oxide semiconductor film 32 are transported to the oxide film 31 containing In or Ga. and the lower end of the conduction band of the oxide film 33 containing In or Ga. The electrons exceed the trap levels 36 and 37 and are captured by the trap levels 36 and 37. The energy difference ΔE2 between the bottom ends of the conduction bands of the oxide film 31 and the oxide semiconductor film 32, and the oxide The energy difference Δ between the bottom of the conduction band of the semiconductor film 32 and the oxide film 33 containing In or Ga It is preferable that E3 is set to 0.1 eV or more, and more preferably 0.15 eV or more.

[0168] In addition, in the vicinity of the interface between the oxide film 31 containing In or Ga and the oxide semiconductor film 32, The energy difference ΔE2 between the oxide semiconductor film 32 and the oxide containing In or Ga is By reducing the energy difference ΔE3 in the vicinity of the interface with the oxide semiconductor film 3 2 and the pair of electrodes 21 and 22 can be reduced, and the trap level 36 can be reduced. This reduces the number of trapped electrons, which increases the on-state current of the transistor and The field effect mobility can be further increased.

[0169] In this case, the energy difference ΔE3 is smaller than the energy difference ΔE2, but According to the electrical characteristics of the transistor, the energy difference ΔE2 and the energy difference ΔE3 are the same, or In or Ga is included so that the energy difference ΔE3 is larger than the energy difference ΔE2. The oxide film 31 includes an oxide semiconductor film 32, and an oxide film 33 including In or Ga. The elements and compositions can be selected appropriately.

[0170] In addition, the back channel of the multilayer film 34 (the portion of the multilayer film 34 facing the gate electrode 15) On the other hand, the oxide insulating layer has more oxygen than meets the stoichiometric composition. For this reason, the oxygen content is higher than the oxygen content that satisfies the stoichiometric composition. The oxygen contained in the oxide insulating film 24 containing a large amount of oxygen is By moving the oxygen to the oxide semiconductor film 32, oxygen vacancies in the oxide semiconductor film 32 can be reduced. do.

[0171] In addition, the multilayer film 34 is damaged by the etching for forming the pair of electrodes 21 and 22. As a result, oxygen vacancies occur on the back channel side of the multilayer film 34, but oxygen that satisfies the stoichiometric composition is The oxygen vacancies are repaired by oxygen contained in the oxide insulating film 24, which contains more oxygen than silicon. This improves the reliability of the transistor 60. .

[0172] From the above, the oxide film 31 containing In or Ga, the oxide semiconductor film 32, and the I a multilayer film 34 having an oxide film 33 containing n or ga, and a stoichiometric amount of The oxide insulating film 24 contains more oxygen than the theoretical composition. It is possible to reduce oxygen vacancies in the oxide film 34. Between the semiconductor film 32, an oxide film 31 containing In or Ga is provided. Between the semiconductor film 32 and the oxide insulating film 24, an oxide film 33 containing In or Ga is provided. Therefore, the oxide semiconductor film 32 is formed near the interface between the oxide film 31 containing In or Ga. the concentration of silicon or carbon in the oxide semiconductor film 32; or in the vicinity of the interface between the oxide film 33 containing In or Ga and the oxide semiconductor film 32. As a result, the concentration of silicon and carbon in the multilayer film 34 can be reduced. The absorption coefficient derived from the constant photocurrent measurement method is 1×10 -3 / cm, preferably less than 1×1 0 -4 / cm, resulting in an extremely low localized level density.

[0173] The transistor 60 having such a structure is formed by a multilayer film 34 including an oxide semiconductor film 32. Since there are very few defects in the Typically, it is possible to increase the on-current and improve the field effect mobility. The threshold voltage varies depending on the BT stress test and the optical BT stress test, which are examples of tests. No change, or the change in the positive or negative direction is 1.0 V or less, preferably 0 It is less than .5V and is highly reliable.

[0174] <Variation 1> Instead of the multilayer film 34 shown in FIG. 5(A) to FIG. 5(C) in this embodiment, 5(E), an oxide film 31 containing In or Ga, an oxide semiconductor film 32, an oxide film containing In or Ga, 33, and an oxide film containing In or Ga, 35 In addition, FIG. 5(D) shows the multilayer film 34a shown in FIG. 5(B). FIG. 5(E) is an enlarged view of the vicinity of the multilayer film 34 shown in FIG. 5(C). It corresponds to the large map.

[0175] The oxide film 35 containing In or Ga is a film of the oxide film 31 containing In or Ga. The oxide film 33 containing In or Ga is provided on each of the side surfaces of the semiconductor film 32 and the oxide film 33 containing In or Ga. That is, the oxide semiconductor film 32 is surrounded by an oxide film containing In or Ga.

[0176] The oxide film 35 containing In or Ga is a film obtained by mixing the oxide films 31 and 33 containing In or Ga. That is, compared with the oxide semiconductor film 32, the oxide semiconductor film 33 is formed of a metal oxide similar to that of the oxide semiconductor film 31. Since the band gap of the oxide film 35 containing Ga is large, the multilayer film 34a and the gate insulating film 1 7, or the trap level near the interface between the multilayer film 34a and the oxide insulating film 23. It is possible to reduce the trapping of electrons in the trap level. Improved reliability.

[0177] The oxide film 35 containing In or Ga is the same as the oxide film 31 containing In or Ga. Then, a dry etching process is performed to form an oxide semiconductor film 32 and an oxide film 33 containing In or Ga. The reaction products generated in the etching process are an oxide film 31 containing In or Ga, The oxide film 33 containing In or Ga is attached to the side of the semiconductor film 32 and the oxide film 33 containing In or Ga. The dry etching conditions are, for example, boron trichloride gas as an etching gas. and chlorine gas, and inductively coupled plasma (ICP) This can be achieved by applying LED Plasma power and substrate bias power.

[0178] In the transistor 60, the gate insulating film 17 and the oxide insulating film 24 are formed of a stoichiometric amount of An oxide that contains more oxygen than satisfies the theoretical composition and loses some of the oxygen when heated. When an insulating film is used, the cross-sectional structure in the channel width direction (see FIG. 5(E)) is The oxide semiconductor film 32 is covered with the Ga-containing oxide films 31, 33, and 35. It contains more oxygen than the stoichiometric composition, and some of the oxygen is released by heating. The structure is covered with an oxide insulating film.

[0179] The cross-sectional structure reduces leakage current flowing through the side surface of the oxide semiconductor film 32. This makes it possible to suppress an increase in the off-current and to suppress the threshold voltage in a stress test. The amount of fluctuation in the gate voltage can be reduced, and the reliability can be improved. Oxygen can be efficiently transferred from the oxide insulating film 17 and the oxide semiconductor film 24 to the oxide semiconductor film 32. As a result, the amount of oxygen vacancies in the oxide semiconductor film 32 can be reduced.

[0180] <Variation 2> In the transistor 60 shown in this embodiment, the multilayer film 34 and the pair of electrodes 21 and 22 The laminated structure can be appropriately modified. For example, a modified example of the transistor shown in FIG. It can be 65.

[0181] A top view of the transistor 65 is shown in FIG. A cross-sectional view between the dashed line C and D is shown in FIG. 7(B), and a cross-sectional view between the dashed line C and D is shown in FIG. In FIG. 7A, for clarity, the substrate 11, the gate insulating film 17, and the semiconductor device including In or Ga are not shown. The oxide film 31, the oxide semiconductor film 32, the protective film 26, etc. are omitted.

[0182] The transistor 65 is different from the transistor 60 in that a part of the pair of electrodes 21 and 22 is an oxide. 1 in that it is surrounded by an oxide semiconductor film 32 and an oxide film 33 containing In or Ga. Specifically, the transistor 65 has an oxide semiconductor formed on an oxide film 31 containing In or Ga. A pair of electrodes 21 and 22 are provided on the oxide semiconductor film 32. The oxide semiconductor film 32 and the pair of electrodes 21 and 22 are in contact with each other, and an oxide containing In or Ga is provided. In the transistor 65, the thickness of the other components is The layer structure is the same as that of the transistor 60 .

[0183] The transistor 65 has a pair of electrodes 21 and 22 in contact with the oxide semiconductor film 32. Therefore, the contact resistance between the multilayer film 34 and the pair of electrodes 21 and 22 is lower than that of the transistor 60. The on-state current of the transistor is improved more than that of the transistor 60.

[0184] In addition, the transistor 65 has a pair of electrodes 21 and 22 in contact with the oxide semiconductor film 32. Therefore, it is possible to prevent the contact resistance between the multilayer film 34 and the pair of electrodes 21 and 22 from increasing, and to prevent the contact resistance from increasing. In this way, the oxide film 33 containing Ga can be made thicker. The plasma damage during the formation of the protective film 26 or the contamination of the constituent elements of the protective film 26 may cause a defect. The top level is near the interface between the oxide semiconductor film 32 and the oxide film 33 containing In or Ga. In other words, the transistor 65 has an improved on-state current and a reduced threshold voltage. This makes it possible to achieve both a reduction in pressure fluctuations and a reduction in pressure fluctuations.

[0185] A method for manufacturing the transistor 65 will be described with reference to FIG. 8. First, in the same manner as in FIG. A gate electrode and a gate insulating film 17 are formed on the substrate 11 (see FIG. 8(A)).

[0186] Next, the In or Ga-containing oxide film 4 which becomes the In or Ga-containing oxide film 31 is 4 and an oxide semiconductor film 45 which will become the oxide semiconductor film 32 are successively formed. The electrodes 21 and 22 are formed (see FIG. 8(B)). The oxide film 44 is made of the same material as the oxide film 19 containing In or Ga shown in the first embodiment. The oxide semiconductor film 45 can be formed by any suitable method. The same material and forming method as those for the nitride semiconductor film 18 can be used appropriately. The electrodes 21 and 22 can be formed in the same manner as in FIG. , 22 are formed on the oxide semiconductor film 45 .

[0187] Next, the oxide semiconductor film 45 that will become the oxide semiconductor film 32 and the pair of electrodes 21 and 22 are covered with In this way, the oxide film 33 containing In or Ga is formed. The oxide film containing In or Ga is formed by the method of forming the oxide film containing In or Ga shown in the first embodiment. The same material and formation method as those for the Ga-containing oxide film 19 can be used appropriately.

[0188] Thereafter, the oxide film containing In or Ga is formed as the oxide film 31 containing In or Ga. 44, an oxide semiconductor film 45 which becomes the oxide semiconductor film 32, and an oxide containing In or Ga The oxide film containing In or Ga that will become the insulating film 33 is partially etched to form In The oxide film 31 containing In or Ga, the oxide semiconductor film 32 and the oxide A multilayer film 34 having a metal film 33 is formed (see FIG. 8(C)). The oxide film containing In or Ga is formed as the oxide film 33 containing In or Ga. This can be achieved by forming a mask by a photolithography process and then using the mask.

[0189] Next, a protective film is formed so as to cover the gate insulating film 17, the multilayer film 34, and the pair of electrodes 21 and 22. The protective film 26 is formed. The protective film 26 can be formed in the same manner as in the first embodiment. In addition, in the manufacturing method of the transistor 65, the method of Embodiment 1 may be appropriately performed. Heat treatment can be carried out with reference to the above.

[0190] In addition, the oxide semiconductor film 32 is formed by etching to form the pair of electrodes 21 and 22. This may cause defects such as oxygen vacancies in the oxide semiconductor film, which increases the carrier density. In the above, an oxide film containing In or Ga is formed to become the oxide film 33 containing In or Ga. Before the oxide semiconductor film is heated, the oxide semiconductor film is exposed to plasma generated in an oxygen atmosphere. It is preferable to supply oxygen to the membrane of the transistor 65. Then, the oxide semiconductor film 32 and the oxide film 33 containing In or Ga are trapped near the interface between the oxide semiconductor film 32 and the oxide film 33 containing In or Ga. The formation of a level can be suppressed, and the fluctuation of the threshold voltage can be reduced. In the transistor 65, the multilayer film 34 flows near the side surface of the oxide semiconductor film 32. The leakage current can be reduced, and an increase in the off current can be suppressed.

[0191] In addition, the multilayer film 34 is damaged by the etching for forming the pair of electrodes 21 and 22. As a result, oxygen vacancies occur on the back channel side of the multilayer film 34, but oxygen that satisfies the stoichiometric composition is The oxygen vacancies are repaired by oxygen contained in the oxide insulating film 24, which contains more oxygen than silicon. This improves the reliability of the transistor 65. .

[0192] <Variation 3> In the transistor 60 shown in this embodiment, the multilayer film 34 and the pair of electrodes 21 and 22 The laminated structure can be appropriately modified. For example, a modified example of the transistor shown in FIG. It can be made to be 66.

[0193] A top view of the transistor 66 is shown in FIG. A cross-sectional view between the dashed line CD and the dashed line D is shown in FIG. In FIG. 9A, the substrate 11, the gate insulating film 17, the protective film 26, etc. are omitted for clarity. is.

[0194] The transistor 66 is different from the transistor 60 in that the oxide film containing In or Ga is 33 is formed on the gate insulating film 17, the pair of electrodes 21 and 22, and the oxide semiconductor film 32. Specifically, the transistor 66 is made of an oxide film containing In or Ga. An oxide semiconductor film 32 is provided on the oxide film 31 containing In or Ga. A pair of electrodes 21 and 22 are provided so as to cover the oxide semiconductor film 32. The oxide film 31 containing Ga, the oxide semiconductor film 32 and the pair of electrodes 21 and 22 are covered with a As shown in FIG. 1, an oxide film 33 containing In or Ga is provided. In the second embodiment, the stacked structure of the other components is the same as that of the transistor 60.

[0195] The transistor 66 is different from the transistor 60 in that the oxide semiconductor layer of the pair of electrodes 21 and 22 is Since the area in contact with the conductive film 32 is large, the contact between the multilayer film 34 and the pair of electrodes 21 and 22 This transistor has a low contact resistance and an improved on-state current compared to the transistor 60.

[0196] In addition, the transistor 66 has a pair of electrodes 21 and 22 and an oxide semiconductor film 32 in a large area. Since the multilayer film 34 is in contact with the pair of electrodes 21 and 22, the contact resistance between the multilayer film 34 and the pair of electrodes 21 and 22 is not increased. In addition, the oxide film 33 containing In or Ga can be made thicker. In order to prevent plasma damage during the formation of the protective film 26 or contamination with the constituent elements of the protective film 26, The trap levels generated in the oxide semiconductor film 32 and the oxide film 33 containing In or Ga are In other words, the transistor 66 has a tendency to have an on-current. This makes it possible to achieve both the above and a reduction in the variation in the threshold voltage.

[0197] A method for manufacturing the transistor 66 will be described with reference to FIG. A gate electrode and a gate insulating film 17 are formed on the substrate 11 (see FIG. 10(A)). .

[0198] Next, an oxide film containing In or Ga which becomes the oxide film 31 containing In or Ga, and an oxide semiconductor film that is to be the oxide semiconductor film 32 is successively formed. A mask is provided by a photolithography process, and the mask is used for etching to form I An oxide film 31 containing In or Ga and an oxide semiconductor film 32 are then formed. A pair of electrodes are disposed so as to cover the ends of the oxide film 31 containing Ga and the oxide semiconductor film 32. The electrodes 21 and 22 are formed (see FIG. 10(B)). The oxide film is made of the same material as the oxide film 19 containing In or Ga described in the first embodiment. The oxide semiconductor film can be formed by any suitable method. The same material and forming method as those for the semiconductor film 18 can be used appropriately. 1 and 22 can be formed in the same manner as in FIG. 3(C).

[0199] Next, In or A Ga-containing oxide film 33 is formed, and a multilayer film 34 is formed (see FIG. 10(C)). The oxide film containing In or Ga is the oxide film containing In or Ga shown in embodiment 1. The same material and forming method as those for the film 19 can be appropriately used. The oxide film 33 containing In or Ga is a mass formed by a photolithography process or the like. The film may be processed by etching using a tungsten carbide or may be left in its as-deposited state.

[0200] Next, the protective film 26 is formed on the gate insulating film 17 and the oxide film 33 containing In or Ga. The protective film 26 can be formed in the same manner as in the first embodiment (see FIG. 10(D)). In addition, in the manufacturing method of the transistor 66, the heating Processing can be performed.

[0201] In addition, the etching for forming the oxide film 31 containing In or Ga and the oxide semiconductor film 32 is performed. As a result, defects such as oxygen vacancies occur on the side surfaces of the oxide semiconductor film 32, and the carrier density decreases. In addition, the etching for forming the pair of electrodes 21 and 22 may increase the amount of oxygen. In some cases, defects such as oxygen vacancies may occur on the surface of the oxide semiconductor film 32, resulting in an increase in carrier density. Therefore, the oxide film 31 containing In or Ga and the oxide semiconductor film 32 are formed. After forming the pair of electrodes 21 and 22, the oxide semiconductor film 3 is 2 is exposed to plasma generated in an oxygen atmosphere to supply oxygen to the oxide semiconductor film 32. is preferred.

[0202] In addition, the multilayer film 34 is damaged by the etching for forming the pair of electrodes 21 and 22. As a result, oxygen vacancies occur on the back channel side of the multilayer film 34, but oxygen that satisfies the stoichiometric composition is The oxygen vacancies are repaired by oxygen contained in the oxide insulating film 24, which contains more oxygen than silicon. This improves the reliability of the transistor 66. .

[0203] In this manner, in the transistor 66, the side surfaces of the oxide semiconductor film 32 and A trap level is formed near the interface between the oxide semiconductor film 32 and the oxide film 33 containing In or Ga. Therefore, the formation of a gate insulating film can be suppressed, and the fluctuation of the threshold voltage can be reduced.

[0204] In addition, the transistor 66 has an oxide film 33 containing In or Ga. The oxide film 31 and the oxide semiconductor film 32 are formed so as to cover the side surfaces (side surfaces in the channel length direction). Therefore, the side surface of the oxide semiconductor film 32 is The leakage current can be reduced, and an increase in the off-current can be suppressed.

[0205] In addition, when forming the oxide film 31 containing In or Ga and the oxide semiconductor film 32 (FIG. 9(B). After the oxide semiconductor film 32 is formed, an oxide semiconductor film containing In or Ga is In the etching process for forming the oxide film 31, the oxide film 31 containing In or Ga and The reaction products adhere to the side surface of the oxide semiconductor film 32, forming an oxide film containing In or Ga (FIG. In some cases, an oxide film containing In or Ga (corresponding to an oxide film 35 containing In or Ga shown in FIG. 5(D)) may be formed. In this case, the oxide film 33 containing In or Ga is an oxide semiconductor film 32 containing In and Ga. The oxide film containing n or ga is formed so as to further cover the insulating layer.

[0206] <Modification 4> In the transistor 60 shown in this embodiment, the multilayer film 34 and the pair of electrodes 21 and 22 The laminated structure can be appropriately changed. For example, a modified example shown in FIG. Transistor 67 may be used.

[0207] A top view of the transistor 67 is shown in FIG. A cross-sectional view between -B is shown in FIG. 11(B), and a cross-sectional view between dashed lines CD is shown in FIG. 11(C). In FIG. 11A, for clarity, the substrate 11, the gate insulating film 17, the protective film 26, etc. are not shown. etc. are omitted.

[0208] The transistor 67 is the same as the transistor 66 shown in FIG. An oxide film 33 containing In is provided so as to cover the pair of electrodes 21 and 22. Alternatively, the end of the oxide film 33 containing Ga is located on the pair of electrodes 21 and 22. In the transistor 67, the stacked structure of the other components is the same as that of the transistor 66. It's the same.

[0209] As shown in FIG. 11C, the transistor 67 is formed by forming an oxide film 3 containing In or Ga. 3, on the side surface intersecting the channel width direction, an oxide film 31 containing In or Ga and The oxide semiconductor film 32 is provided so as to cover the side surfaces of the oxide semiconductor film 32. The leakage current flowing along the side surface of the film 32 can be reduced, and an increase in the off-current can be suppressed. can be done.

[0210] (Embodiment 3) In this embodiment, a transistor having a structure different from those in the first and second embodiments will be described. 12. A transistor 70 described in this embodiment includes an oxide semiconductor film The semiconductor device is characterized in that it has a plurality of gate electrodes opposed to each other via a gate electrode.

[0211] A transistor 70 shown in FIG. 12 has a gate electrode 15 provided on a substrate 11 . In addition, a gate insulating film 17 is formed on the substrate 11 and the gate electrode 15. A multilayer film 20 overlapping the gate electrode 15 via a gate electrode 7 and a pair of electrodes 21 in contact with the multilayer film 20 The multilayer film 20 includes an oxide semiconductor film 18 and an In or Ga semiconductor film 22. The oxide film 19 includes a gate insulating film 17, a multilayer film 20, and a pair of electrodes 21. A protective film 26 made of an oxide insulating film 24 and a nitride insulating film 25 is formed on the insulating film 22. Also, a gate electrode 61 overlaps with the multilayer film 20 via a protective film 26.

[0212] The gate electrode 61 can be formed in the same manner as the gate electrode 15 shown in the first embodiment. .

[0213] The transistor 70 shown in this embodiment has a gate electrode 15 opposed to the multilayer film 20. and a gate electrode 61. Different potentials are applied to the gate electrode 15 and the gate electrode 61. This allows the threshold voltage of the transistor 70 to be controlled.

[0214] In addition, by having the multilayer film 20 including the oxide semiconductor film 18 with a reduced amount of oxygen vacancies, In addition, the amount of change in the threshold voltage can be reduced. This results in a highly reliable transistor.

[0215] The oxide semiconductor film disclosed in the above embodiment can be formed by a sputtering method. However, it may be formed by other methods, for example, thermal CVD. VD(Metal Organic Chemical Vapor Depositi) Alternatively, the on-coating method or the ALD (Atomic Layer Deposition) method may be used. stomach.

[0216] Thermal CVD is a film formation method that does not use plasma, so defects can occur due to plasma damage. This has the advantage that no additional steps are required.

[0217] In the thermal CVD method, the pressure in the chamber is set to atmospheric pressure or reduced pressure, and the source gas and the oxidizing agent are simultaneously The reaction is carried out in the chamber near or on the substrate, where it is deposited on the substrate to form a film. You may go.

[0218] In addition, in the ALD method, the pressure inside the chamber is set at atmospheric pressure or reduced pressure, and the source gas for the reaction is The gases may be introduced into the chamber in sequence, and the film may be formed by repeating the gas introduction sequence. For example, by switching each switching valve (also called high-speed valve), two or more types of The above source gases are supplied to the chamber in order, and the first An inert gas (such as argon or nitrogen) is introduced simultaneously with or after the raw material gas. The second source gas is introduced. When an inert gas is introduced at the same time, the inert gas is It acts as a carrier gas, and even if an inert gas is introduced at the same time as the second source gas is introduced, Also, instead of introducing an inert gas, the first source gas is discharged by vacuum evacuation. After that, a second source gas may be introduced. The first source gas is adsorbed on the surface of the substrate to form a first unit. The atomic layer is deposited, and reacts with the second source gas introduced later, and the second monoatomic layer is formed on the first The order of gas introduction is controlled to obtain a thin film of the desired thickness. By repeating the process several times until the desired thickness is reached, a thin film with excellent step coverage can be formed. The thickness of the film can be adjusted by changing the number of times the gas introduction sequence is repeated, so a precise film thickness can be achieved. This allows for adjustment and is suitable for fabricating miniaturized FETs.

[0219] The thermal CVD method such as MOCVD method or ALD method is disclosed in the embodiments described above. For example, an oxide semiconductor film such as InGaZnO can be formed by MOCVD. X When forming a (X>0) film, trimethylindium, trimethylgallium, and di Ethyl zinc is used. The chemical formula for trimethylindium is (CH3)3In. The chemical formula for trimethylgallium is (CH3)3Ga. The chemical formula is (CH3)2Zn. In addition, the combination is not limited to these, and trime Triethylgallium (chemical formula (C2H5)3Ga) can also be used instead of ethylgallium. Dimethylzinc (chemical formula (C2H5)2Zn) can also be used instead of diethylzinc. can.

[0220] For example, an oxide semiconductor film, such as InGaZnO, can be formed by a film formation apparatus using ALD. X ( When forming a film (x>0), In(CH3)3 gas and O3 gas are introduced in sequence. Then, Ga(CH3)3 gas and O3 gas are introduced simultaneously to form an InO2 layer. An O layer is formed, and then Zn(CH3)2 and O3 gas are introduced simultaneously to form a ZnO layer. The order of these layers is not limited to this example. Mixed compounds such as aO2 layer, InZnO2 layer, GaInO layer, ZnInO layer, GaZnO layer, etc. Alternatively, a layer may be formed by bubbling an inert gas such as Ar instead of O3 gas. However, it is preferable to use O gas that does not contain H. Alternatively, In(C2H5)3 gas may be used instead of In(CH3)3 gas. Ga(C2H5)3 gas may be used instead of (CH3)3 gas. 3) Instead of the Zn(CH3)2 gas, In(C2H5)3 gas may be used. A gas may also be used.

[0221] In addition, the configuration and method described in this embodiment may be applied to configurations and methods described in other embodiments and examples. and the like.

[0222] (Embodiment 4) In this embodiment, a transistor included in the semiconductor device described in the above embodiment is In this section, one embodiment applicable to an oxide semiconductor film will be described.

[0223] The oxide semiconductor film may be an amorphous oxide semiconductor, a single crystal oxide semiconductor, or a polycrystalline oxide semiconductor. The oxide semiconductor film can be a crystalline oxide semiconductor (CA The AC-OS may be used.

[0224] The CAAC-OS film is one of the oxide semiconductor films that has multiple crystal parts. The crystal part is small enough to fit inside a cube with one side less than 100 nm. The crystal parts contained in the OS film are in the form of cubes with one side less than 10 nm, 5 nm, or 3 nm. The CAAC-OS film has a smaller defect density than a microcrystalline oxide semiconductor film. The CAAC-OS film has a low density of recessed states. .

[0225] The CAAC-OS film was observed under a transmission electron microscope (TEM). When observed using a quartz crystal microscope, clear boundaries between the crystals were observed. It is not possible to confirm the grain boundary. It can be said that the AAC-OS film is less susceptible to the decrease in electron mobility caused by grain boundaries.

[0226] The CAAC-OS film was observed by TEM from a direction roughly parallel to the sample surface (cross-sectional TEM observation). When the metal atoms are observed, it can be confirmed that they are arranged in layers in the crystal part. Each of the layers has a surface on which the CAAC-OS film is to be formed (also called a surface on which the film is to be formed) or a top surface having irregularities. The shape of the CAAC-OS film reflects this, and the CAAC-OS films are aligned parallel to the surface on which the film is formed or the upper surface.

[0227] On the other hand, the CAAC-OS film was observed by TEM from a direction roughly perpendicular to the sample surface (plane T EM observation revealed that metal atoms were arranged in triangular or hexagonal shapes in the crystals. However, no regularity was observed in the arrangement of metal atoms between different crystal parts. stomach.

[0228] Cross-sectional and planar TEM observations revealed that the crystals in the CAAC-OS film had an orientation. It can be seen that...

[0229] X-ray diffraction (XRD) of CAAC-OS film When the structure was analyzed using the device, for example, CAAC-OS with InGaZnO4 crystals was In the out-of-plane analysis of the film, the diffraction angle (2θ) peaked at around 31°. This peak is attributed to the (009) plane of the InGaZnO4 crystal. Therefore, the crystals of the CAAC-OS film have a c-axis orientation, and the c-axis is generally aligned on the surface on which the film is formed or on the upper surface. It can be seen that it is oriented in a substantially vertical direction.

[0230] On the other hand, in-p X-rays are incident on the CAAC-OS film from a direction approximately perpendicular to the c-axis. In the lane method, a peak may appear at 2θ around 56°. is attributed to the (110) plane of the InGaZnO4 crystal. In the case of a nitride semiconductor film, 2θ is fixed at around 56°, and the normal vector of the sample surface is the axis (φ axis). When the sample is rotated and analyzed (φ scan), a crystal plane equivalent to the (110) plane is detected. In contrast, in the case of the CAAC-OS film, six peaks are observed, which are assigned to Even when φ is fixed at around 56° and scanned, no clear peak appears.

[0231] From the above, it is considered that the orientation of the a-axis and b-axis is uniform between different crystal regions in the CAAC-OS film. Although it is irregular, it has a c-axis orientation, and the c-axis is parallel to the normal vector of the surface to be formed or the upper surface. Therefore, the layered arrangement confirmed by the cross-sectional TEM observation mentioned above is consistent with the above. Each layer of aligned metal atoms is a plane parallel to the ab plane of the crystal.

[0232] The crystalline portion is formed when the CAAC-OS film is formed or when a crystallization process such as a heat treatment is performed. As described above, the c-axis of the crystal is aligned along the surface on which the CAAC-OS film is formed or along the surface on which the CAAC-OS film is formed. The orientation is parallel to the normal vector of the top surface. When the crystal orientation is changed by etching, the c-axis of the crystal is aligned with the surface on which the CAAC-OS film is formed or the may not be parallel to the normal vector of the top surface.

[0233] In addition, the crystallinity in the CAAC-OS film does not have to be uniform. When the crystalline part of the film is formed by crystal growth from the vicinity of the top surface of the CAAC-OS film, The area near the surface may have a higher crystallinity than the area near the surface on which it is formed. When impurities are added to the AC-OS film, the crystallinity of the region to which the impurities are added changes, resulting in a partial In some cases, regions of differing crystallinity may be formed.

[0234] In addition, the out-of-plane crystal structure of the CAAC-OS film with InGaZnO4 crystals In the analysis by the method, in addition to the peak at 2θ near 31°, a peak also appeared at 2θ near 36°. The peak at 2θ of around 36° may be due to the c-axis orientation in some parts of the CAAC-OS film. The CAAC-OS film contains crystals that do not have the 2θ value of about 31°. It is preferable that the spectrum shows a peak at 2θ of about 36° and does not show a peak at 2θ of about 36°.

[0235] There are three methods for forming the CAAC-OS film.

[0236] In the first method, the film formation temperature is set to 150° C. or higher and 500° C. or lower, preferably 150° C. or higher and 450° C. or lower. C. or less, more preferably 200.degree. C. to 350.degree. C., inclusive, to form an oxide semiconductor film. In this way, the c-axis of the crystal part included in the oxide semiconductor film is aligned along a normal vector of the surface on which the film is formed or along a normal vector of the surface. This is a method for forming crystal parts that are aligned in a direction parallel to the normal vector.

[0237] The second method is to form an oxide semiconductor film to a small thickness, and then heat the film at a temperature of 200° C. to 700° C. By performing heat treatment, the c-axis of a crystal part included in the oxide semiconductor film is aligned with the normal vector of the formation surface. This is a method for forming crystals aligned in a direction parallel to the normal vector of the crystal or surface.

[0238] The third method is to form a thin oxide semiconductor film as a first layer, and then heat the film at 200° C. or higher for 700 The oxide semiconductor film is then formed by performing a heat treatment at or below 1000°C. The c-axis of the crystal part contained in the film is parallel to the normal vector of the surface on which it is formed or the normal vector of the surface. This is a method for forming crystal parts that are aligned in a certain direction.

[0239] A transistor that uses CAAC-OS for an oxide semiconductor film can be irradiated with visible light or ultraviolet light. Therefore, the change in electrical characteristics due to the application of CAAC-OS to the oxide semiconductor film is small. The transistor has good reliability.

[0240] In addition, CAAC-OS uses a polycrystalline oxide semiconductor sputtering target. It is preferable to form the film by a sputtering method. When ions collide with the sputtering target, the crystalline regions in the sputtering target are transformed from the ab plane to The sputtered particles are then cleaved from the ab plane to obtain plate-like or pellet-like sputtered particles with a surface parallel to the ab plane. In this case, the plate-like or pellet-like sputtered particles may peel off. By reaching the surface while maintaining the crystalline state, the CAAC-OS film can be formed. Cut.

[0241] In addition, in order to form a CAAC-OS film, the following conditions are preferably applied.

[0242] By reducing the amount of impurities mixed in during film formation, it is possible to prevent the crystal state from being destroyed by impurities. For example, the concentration of impurities (hydrogen, water, carbon dioxide, nitrogen, etc.) present in the film formation chamber can be In addition, the impurity concentration in the deposition gas may be reduced. A deposition gas having a temperature of -80°C or lower, preferably -100°C or lower, is used.

[0243] In addition, by increasing the heating temperature (for example, the substrate heating temperature) of the surface to be film-formed during film formation, After the sputtering particles reach the target surface, they migrate. The temperature is set to 100° C. or higher and 740° C. or lower, preferably 150° C. or higher and 500° C. or lower. By increasing the temperature of the surface during film formation, plate-like or pellet-like sputtering particles When the particles reach the surface on which the film is to be formed, migration occurs on the surface, resulting in sputtering. The flat surface of the particle adheres to the surface on which it is formed.

[0244] In addition, by increasing the oxygen ratio in the deposition gas and optimizing the power, plasma damage during deposition is reduced. The oxygen ratio in the deposition gas is preferably 30% by volume or more, and more preferably 100% by volume or more. Expressed as volume percent.

[0245] As an example of a sputtering target, an In-Ga-Zn compound target is The details are shown below.

[0246] InO X powder, GaO Y Powder, and ZnO Z The powders are mixed in a specified number of moles and pressurized. Then, it is heated at a temperature between 1000℃ and 1500℃ to produce polycrystalline In-G The target is a-Zn-based metal oxide. Note that the pressure treatment is not performed without cooling (or cooling down). The reaction may be performed while heating or while cooling. X, Y and Z are any positive numbers. Here, the predetermined molar ratio is, for example, InO X powder, GaO Y Powder and ZnO Z powder The last is 2:2:1, 8:4:3, 3:1:1, 1:1:1, 4:2:3, 3:1:2, 1 The ratio is 1:3:2, 1:6:4, or 1:9:6. The type of powder and the mixture ratio are The ol ratio may be appropriately changed depending on the sputtering target to be produced.

[0247] Note that the structure described in this embodiment mode may be appropriately combined with structures described in other embodiments. It can be used.

[0248] (Embodiment 5) A semiconductor device having a display function (display) using the transistor shown as an example in the above embodiment In addition, a part of a driver circuit including a transistor can be manufactured. Or, the entire display can be formed on the same substrate as the pixel section to form a system-on-panel. In this embodiment, a display device using the transistor, one example of which is shown in the above embodiment, An example of this will be described with reference to Figs. 13 and 14. 13(B) is a cross-sectional view showing the cross-sectional configuration of a portion indicated by a dashed line MN in FIG. 13(B).

[0249] In FIG. 13A, a pixel portion 902 provided on a first substrate 901 is surrounded by a A sealant 905 is provided and the semiconductor device is sealed with a second substrate 906. ) is different from the region surrounded by the sealant 905 on the first substrate 901. A signal line driver formed of a single crystal semiconductor or a polycrystalline semiconductor on a separately prepared substrate is provided in the region where the signal line driver is formed. A signal line driver circuit 903 and a scanning line driver circuit 904 are mounted on the display panel. 3. Various signals and potentials given to the scanning line driver circuit 904 or the pixel portion 902 are transmitted through the FPC (Flexible printed circuit)918 is supplied.

[0250] In FIG. 13B and FIG. 13C, a pixel portion 90 provided on a first substrate 901 A sealant 905 is provided so as to surround the insulating film 902 and the scanning line driver circuit 904. A second substrate 906 is provided on the pixel portion 902 and the scanning line driver circuit 904. The pixel portion 902 and the scanning line driver circuit 904 are formed by a first substrate 901 and a sealing material 905. The display element is sealed with the second substrate 906. In FIG. 9C, the region surrounded by the sealant 905 on the first substrate 901 is Signals formed in different regions using single crystal semiconductors or polycrystalline semiconductors on a separately prepared substrate A signal line driver circuit 903 is mounted. In FIG. 13B and FIG. 13C, Various signals and power supplies to the driver circuit 903, the scanning line driver circuit 904, or the pixel portion 902 The position is provided by FPC918.

[0251] In addition, in FIG. 13B and FIG. 13C, a signal line driver circuit 903 is separately formed. 9, the scanning line 902 is mounted on the first substrate 901, but the present invention is not limited to this configuration. The driver circuit may be formed separately and mounted, or may be mounted as a part of the signal line driver circuit or the scanning line driver circuit. Only a part of it may be formed separately and mounted.

[0252] The method of connecting the separately formed drive circuit is not particularly limited, and may be any method such as COG ( hip on glass method, wire bonding method, or TAB (Tap The Automated Bonding method can be used. 9) is an example in which a signal line driver circuit 903 and a scanning line driver circuit 904 are mounted by the COG method. FIG. 13B shows an example in which a signal line driver circuit 903 is mounted by the COG method. 3(C) is an example in which a signal line driver circuit 903 is mounted by the TAB method.

[0253] The display device includes a panel in which a display element is sealed, and a controller for the panel. This includes modules in which ICs, etc., including lasers, are mounted.

[0254] In this specification, the display device refers to an image display device or a light source (including a lighting device). ) Also refers to a module with a connector, such as FPC or TCP. A module with a printed wiring board at the end of the TCP, or a display element with a COG method This also includes all modules on which ICs (integrated circuits) are directly mounted.

[0255] In addition, the pixel portion and the scan line driver circuit provided on the first substrate have a plurality of transistors. To this end, the transistor described in the above embodiment can be applied.

[0256] Examples of display elements provided in the display device include liquid crystal elements (also called liquid crystal display elements), light-emitting elements, and the like. A light-emitting element (also called a light-emitting display element) can be used. A light-emitting element emits light by applying a current or a voltage. This category includes elements whose brightness is controlled by a specific factor, such as inorganic EL (Electroluminescent) devices. Luminescence elements, organic electroluminescence elements, etc. Also, electronic ink, etc. A display medium in which the contrast is changed by electrical action can also be used. FIG. 14A shows an example of a liquid crystal display device using a liquid crystal element as a display element, and FIG. 1 shows an example of a light-emitting display device using a light-emitting element as a display element.

[0257] As shown in FIG. 14(A) and FIG. 14(B), the display device has a connection terminal electrode 915 and a terminal The connection terminal electrode 915 and the terminal electrode 916 are connected to the FPC 918. The electrode 914 is electrically connected to a terminal via an anisotropic conductive material 919 .

[0258] The connection terminal electrode 915 is formed from the same conductive film as the first electrode 930, and the terminal electrode 916 is formed of the same conductive film as the pair of electrodes of the transistors 910 and 911.

[0259] A pixel portion 902 and a scanning line driver circuit 904 provided on a first substrate 901 are In FIG. 14(A) and FIG. 14(B), the pixel portion 902 includes a plurality of transistors. 9 and a transistor 911 included in the scanning line driver circuit 904. In FIG. 14A, the transistor 910 and the transistor 911 are provided with an insulator. In FIG. 14B, a flattening film 921 is further provided on the insulating film 924. Note that the transistors 910 and 911 are made of oxide semiconductor. The multilayer film 926 having an oxide semiconductor film is the same as the multilayer film 20 having an oxide semiconductor film described in Embodiment 1. Alternatively, the multilayer film 34 including the oxide semiconductor film described in Embodiment 2 can be used as appropriate. The insulating film 924 can be formed using the protective film 26 described in Embodiment 1 as appropriate. Reference numeral 3 denotes an insulating film that functions as a base film.

[0260] In this embodiment, the transistors 910 and 911 are the same as those in the above embodiment. The transistors shown in FIG. 9 can be appropriately applied. The transistor described in any one of Embodiments 1 to 3 is used as the transistor 911. In this way, a display device with high image quality can be manufactured.

[0261] In FIG. 14B, the transistor 91 for the driver circuit is disposed on the planarizing film 921. 9 shows an example in which a conductive film 917 is provided at a position overlapping a channel region of a multilayer film 926 of FIG. In this embodiment mode, the conductive film 917 is formed using the same conductive film as the first electrode 930. By providing the conductive film 917 at a position overlapping the channel region of the multilayer film 926, the BT switch The amount of change in the threshold voltage of the transistor 911 before and after the stress test is further reduced. The potential of the conductive film 917 can be the same as that of the gate electrode of the transistor 911. The conductive film may function as a second gate electrode. The potential of the conductive film 917 is set to GND, 0 V, a floating state, or the lowest potential of the driver circuit. The same potential as the low potential (Vss, for example, the potential of the source electrode when the potential of the source electrode is used as the reference) The potential may be the same as or equal to the potential of the first electrode.

[0262] The conductive film 917 also has a function of blocking an external electric field. (The circuit part including the transistor) The shielding function of the conductive film 917 prevents the device from being affected by external electric fields such as static electricity. This can prevent the electrical characteristics of the transistor from being changed. The above-described embodiment mode can be applied to any of the transistors.

[0263] The transistor 910 provided in the pixel portion 902 is electrically connected to a display element. The display element is not particularly limited as long as it can display an image. It can be used.

[0264] In FIG. 14A, a liquid crystal element 913 which is a display element has a first electrode 930, a second electrode The liquid crystal layer 908 is sandwiched between two alignment films 931 and 938. The second electrode 931 is provided with an insulating film 932 and an insulating film 933 that function as a first insulating film. The first electrode 930 and the second electrode 931 are disposed on the second substrate 906 side, and the first electrode 930 and the second electrode 931 are disposed on the second substrate 906 side. The structure is such that they overlap through one another.

[0265] The spacer 935 is a columnar spacer obtained by selectively etching an insulating film. and in order to control the distance (cell gap) between the first electrode 930 and the second electrode 931, A spherical spacer may also be used.

[0266] When liquid crystal elements are used as display elements, thermotropic liquid crystal, low molecular weight liquid crystal, high molecular weight liquid crystal, etc. Liquid crystal, polymer dispersed liquid crystal, ferroelectric liquid crystal, antiferroelectric liquid crystal, etc. can be used. These liquid crystal materials can exhibit cholesteric, smectic, cubic, and chromatic phases depending on the conditions. It shows an isotropic phase, an isotropic phase, etc.

[0267] Alternatively, a liquid crystal that exhibits a blue phase without using an alignment film may be used. When the temperature of the cholesteric liquid crystal is increased, the cholesteric phase transitions to the isotropic phase. The blue phase appears only in a narrow temperature range, so it is necessary to improve the temperature range. In order to improve the liquid crystal layer, a liquid crystal composition containing a chiral agent is used. The liquid crystal composition containing the chiral agent has a short response time of 1 msec or less and is optically isotropic. Therefore, alignment treatment is not required and viewing angle dependency is small. Also, no alignment film is required. This eliminates the need for rubbing, preventing electrostatic damage caused by rubbing. This can prevent the liquid crystal display device from being damaged or broken during the manufacturing process. This makes it possible to improve the productivity of liquid crystal display devices.

[0268] The first substrate 901 and the second substrate 906 are fixed by a sealant 925. The molding material 925 can be an organic resin such as a thermosetting resin or a photosetting resin.

[0269] In addition, the transistor including the oxide semiconductor film used in the above embodiment has a switching It has excellent characteristics. In addition, it has a relatively high field effect mobility, which allows for high-speed operation. Therefore, by using the above transistor in a pixel portion of a semiconductor device having a display function, In addition, a driver circuit portion and a pixel portion can be formed on the same substrate. Since it is possible to manufacture the semiconductor device separately, the number of parts can be reduced. .

[0270] The size of the storage capacitor provided in the liquid crystal display device is determined by the capacitance of the transistor arranged in the pixel portion. It is set so that the charge can be held for a certain period of time, taking into account the break current, etc. By using a transistor having a nitride semiconductor film, the liquid crystal capacitance of each pixel is It is sufficient to provide a storage volume having a size of 1 / 3 or less, preferably 1 / 5 or less, of the capacity of the Therefore, the aperture ratio of the pixel can be increased.

[0271] In addition, in display devices, black matrices (light-shielding films), polarizing members, phase difference members, reflectors, Optical members (optical substrates) such as anti-reflection members are provided as appropriate. For example, a polarizing substrate and a retardation Circular polarization by the substrate may be used. Also, backlight, sidelight, etc. may be used as the light source. It may be used.

[0272] In addition, the display method in the pixel section uses the progressive method, interlace method, etc. In addition, the color elements controlled by pixels when displaying colors are RGB (RGB=RGB). The color is not limited to the three colors RGBW (W stands for white, G stands for red, B stands for green, and B stands for blue). ), or RGB plus one or more additional colors such as yellow, cyan, or magenta. The size of the display area may be different for each dot of the color element. The present invention is not limited to a color display device, but may be applied to a monochrome display device. It can also be applied.

[0273] In FIG. 14B, a light-emitting element 963 which is a display element is provided in a pixel portion 902. The light-emitting element 963 is electrically connected to the transistor 910. The laminated structure includes a first electrode 930, a light-emitting layer 961, and a second electrode 931. However, the laminated structure is not limited to the structure shown in FIG. The configuration of the light emitting element 963 is appropriately determined according to the direction of the light to be extracted from the light emitting element 963. It can be changed as needed.

[0274] The partition wall 960 is formed using an organic insulating material or an inorganic insulating material, particularly a photosensitive resin. An opening is formed on the first electrode 930 using a material, and the sidewall of the opening has a continuous curvature. It is preferable to form the inclined surface so that the inclined surface is formed with a groove.

[0275] The light-emitting layer 961 may be composed of a single layer or a plurality of layers may be laminated. Either way is fine.

[0276] In order to prevent oxygen, hydrogen, moisture, carbon dioxide, and the like from entering the light-emitting element 963, the second electrode 9 A protective layer may be formed on the insulating film 31 and the partition wall 960. The protective layer may be a silicon nitride film, a nitride film, or the like. Silicon oxide film, aluminum oxide film, aluminum nitride film, aluminum oxynitride film An aluminum nitride oxide film, a DLC film, or the like can be formed on the first substrate 90. A filler 964 is placed in the space sealed by the first and second substrates 906 and the sealant 936. In this way, the container is airtight and has minimal degassing, so that it is not exposed to the outside air. Protective films (lamination films, UV-curable resin films, etc.) or cover materials that do not Caging (encapsulation) is preferred.

[0277] The sealant 936 is made of organic resin such as thermosetting resin or photocurable resin, or a free resin containing low melting point glass. Frit glass can be used. Frit glass is highly resistant to impurities such as water and oxygen. In addition, when frit glass is used as the sealant 936, In this case, as shown in FIG. 14B, a frit glass is provided on the insulating film 924 to improve adhesion. This is preferable because it can increase

[0278] The filler 964 can be an inert gas such as nitrogen or argon, or an ultraviolet curing resin or Thermosetting resins can be used, such as PVC (polyvinyl chloride), acrylic resin, and poly Imide, epoxy resin, silicone resin, PVB (Polyvinyl Butyral) or EVA (Elastomer) For example, nitrogen may be used as a filler. stomach.

[0279] If necessary, a polarizing plate or a circular polarizing plate (including an elliptical polarizing plate) may be provided on the light-emitting surface of the light-emitting element. Optical films such as retardation plates (λ / 4 plates, λ / 2 plates), color filters, etc. may be installed as appropriate. In addition, the polarizing plate or the circular polarizing plate may be provided with an anti-reflection film. It is possible to apply an anti-glare treatment that can diffuse reflected light and reduce glare.

[0280] A first electrode and a second electrode (a pixel electrode, a common electrode, and a counter electrode) for applying a voltage to a display element In the case of a holographic laser, the direction of the light to be extracted, the location of the electrodes, and the pattern of the electrodes are all determined by the following factors: The translucency or reflectivity can be selected according to the layer structure.

[0281] The first electrode 930 and the second electrode 931 are made of indium oxide containing tungsten oxide. Indium zinc oxide with tungsten oxide, indium oxide with titanium oxide, acid Indium tin oxide containing titanium dioxide, indium tin oxide (hereinafter referred to as ITO), Conductive materials with translucency such as indium zinc oxide and indium tin oxide doped with silicon oxide Conductive materials can be used.

[0282] The first electrode 930 and the second electrode 931 are made of tungsten (W) and molybdenum (Mo ), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), Tantalum (Ta), Chromium (Cr), Cobalt (Co), Nickel (Ni), Titanium (T i), platinum (Pt), aluminum (Al), copper (Cu), silver (Ag), or other metals, The metal nitride may be formed by using one or more of the above metals.

[0283] The first electrode 930 and the second electrode 931 are made of a conductive polymer. The conductive polymer may be formed using a conductive composition containing a conductive polymer such as A so-called π-electron conjugated conductive polymer can be used. For example, polyaniline or derivatives thereof, polypyrrole or its derivatives, polythiophene or its derivatives, or aniline Copolymers or derivatives thereof made of two or more of phosphorus, pyrrole and thiophene, etc. Can be given.

[0284] In addition, since transistors are easily damaged by static electricity, etc., a protection circuit for protecting the drive circuit is It is preferable to provide a protection circuit using a non-linear element.

[0285] As described above, by using the transistor described in the above embodiment, Therefore, a highly reliable semiconductor device can be provided.

[0286] The structures and methods described in this embodiment may be used in conjunction with structures and methods described in other embodiments and examples. and the like.

[0287] (Embodiment 6) In this embodiment, a display device (touch panel) provided with a touch sensor (contact detection device) (also referred to as "commercial transaction").

[0288] FIG. 24 is a top view showing a configuration example of a pixel portion of a display device 900. FIG. 24 is a cross-sectional view taken along a dashed line OP. Note that in FIG. 24, some of the components are shown in FIG. In the present embodiment, the reference numerals used in the fifth embodiment will be used as appropriate. do.

[0289] The pixel portion includes at least a transistor 910 and a scan line including a gate electrode 972. A signal line including one electrode 974 of a pair of electrodes 974 and 975 and a pixel electrode A first electrode 930 that functions as a common electrode, a second electrode 931 that functions as a common electrode, and a spacer 935 (See FIG. 24.)

[0290] The transistor 910 includes a gate electrode 972, a gate insulating film 976, and a multilayer film 926. The gate electrode 972 includes a pair of electrodes 974 and 975 and an insulating film 924. The gate insulating film 923 is provided on an insulating film 923 that functions as a base film on a substrate 901. 76 is provided on the gate electrode 972, and the multilayer film 926 overlaps the gate electrode 972. The pair of electrodes 974 and 975 are formed on the multilayer film 9 26, the insulating film 924 is formed by a multilayer film 926 and a pair of electrodes 974, 975. (See FIG. 25.)

[0291] An organic resin film 945 is provided on the insulating film 924. A second electrode 931 is provided on the organic resin film 945. An insulating film 937 is provided. The insulating film 924, the insulating film 937, and the organic resin film 945 are provided with electrodes. An opening reaching the insulating film 937 is provided, and the first electrode 93 is formed on the opening and the insulating film 937. 0 is provided (see FIG. 25). That is, the first electrode 930 is a pair of electrodes 974 , 975.

[0292] In addition, an insulating film 932 functioning as an alignment film is formed on the insulating film 937 and the first electrode 930. The surface of the second substrate 906 facing the first substrate 901 is provided with a layer functioning as an alignment film. An insulating film 933 is provided between the insulating film 932 and the insulating film 933. In addition to the above components, optical members may be provided as appropriate. For example, a polarizing plate can be provided on the outer side of the first substrate 901 and the second substrate 906 .

[0293] The display device 900 also includes a capacitance sensor as a touch sensor. An electrode 941 is provided on the outer side of the first substrate 906. The polarizing plate in this case is provided between the electrode 941 and the second substrate 906 .

[0294] The second electrode 931 on the first substrate 901 side serves as a common electrode for the pixel and a capacitive element for the touch sensor. The electrode 941 functions as one electrode of the capacitor of the touch sensor. In addition, the pixel section of the display device 900 employs a pixel structure in the FFS mode. Since no conductive film is formed on the second substrate 906 side, the stripe of the second substrate 906 The electrode 941 functions as an antistatic conductor.

[0295] The transistor 910 is made of the same material and has the same structure as the transistor 50 described in the first embodiment. That is, the gate electrode 972, the gate insulating film 976, the multilayer film 9 26, the pair of electrodes 974 and 975 and the insulating film 924 are each the same as those described in the first embodiment. The gate electrode 15 of the transistor 50, the gate insulating film 17, the multilayer film 20, and the pair of electrodes 21 , 22 and the protective film 26 can be formed using the same materials and methods.

[0296] In addition, a signal line driver circuit and For example, one or both of the signal line driver circuit and the scanning line driver circuit can be manufactured. Transistors and diodes included in one or both of the scan line driving circuits, FPC, etc. It is possible to manufacture a lead wiring provided in a terminal portion connected to the

[0297] The organic resin film 945 can be applied to the planarizing film 921 or the partition wall 960 described in the fifth embodiment. The insulating film 937 can be formed by using a material and a manufacturing method that can be used for the transistor 9. Materials and methods applicable to the insulating film included in 10 (such as the gate insulating film 976 or the insulating film 924) The semiconductor device can be formed using the same and fabrication methods.

[0298] In addition, the electrode 975, which is one of the pair of electrodes 974 and 975, and the first electrode 9 30 is in contact with the insulating film 924, the insulating film 937, and the organic resin film 945 through an opening. The opening is formed by forming a resist mask by a photolithography process or the like. The insulating film 9 can be formed by etching using a resist mask. 24 and a part of the organic resin film 945, and a step of etching a part of the insulating film 937. The film is formed by a process of coating the film.

[0299] FIG. 26A shows a wiring 977 electrically connected to a pair of electrodes 974 and 975, and a second 9 is a cross-sectional view of an example of a connection structure in which the wiring 977 and the second electrode 931 are connected. The electrode 931 is in contact with the insulating film 924 and the organic resin film 945 through an opening provided therein. In this way, a potential is supplied to the wiring 977, and thus a potential is supplied to the second electrode 931. The wiring 977 can be formed by utilizing the manufacturing process of the pair of electrodes 974 and 975. It can be achieved.

[0300] FIG. 26B shows an example of a wiring connection structure in a terminal portion to be connected to an FPC or the like. The electrode 979 is formed at an opening provided in the insulating film 924 and the organic resin film 945. The wiring 977 is in contact with the gate insulating film 976, the insulating film 924, and the organic resin film 945. The opening is in contact with the wiring 978. By supplying a potential to the wiring 977, a potential can be supplied to the wiring 978. It can be formed by utilizing the manufacturing process of 972.

[0301] As shown in FIG. 26B, the wiring 977 and the wiring 978 are connected by an electrode 979. By doing so, the wiring 977 and the wiring 978 can be connected more easily than when a connection portion is formed in which the wiring 977 and the wiring 978 are directly connected to each other. This is because the wiring 977 and the wiring 978 are in direct contact with each other. In order to obtain such a connection structure, a gate insulating film is formed before forming a pair of electrodes 974 and 975. A photomask is required to form a contact hole in 976. This is because the photomask is not required for the connection structure.

[0302] 25, a transistor 910 shown in FIG. 27 is formed by using a multi-tone mask. By forming the transistor 912, the number of photomasks can be reduced. A multi-tone mask is a mask that can perform exposure with multiple levels of light intensity. Representative examples include The exposure is performed with three levels of light intensity: exposed area, half-exposed area, and unexposed area. By using this method, multiple thicknesses (typically two types) can be achieved by a single exposure and development process. Therefore, by using a multi-tone mask, The number of photomasks can be reduced. In the formation process of 928 and 929, a multi-tone mask is used, so that only one photomask is required. By using a multi-tone mask, the number of electrodes 928 and 929 can be reduced. The end of the multilayer film 927 is located outside the end of the multilayer film 927 .

[0303] FIG. 28 is a plan view showing a configuration example of the second electrode 931 and the electrode 941 of the display device 900. As shown in FIG. 28, the second electrode 931 and the electrode 941 are formed in a stripe shape. The second electrode 931 and the electrode 941 are arranged so as to be perpendicular to each other in a plane. The second electrode 931 is connected to the FPC 901 by a lead wire 951. 54, and each electrode 941 is attached to the substrate 906 by a lead wire 952. It is connected to the FPC955.

[0304] FIG. 29(A) is a cross-sectional view taken along the dashed line QR in FIG. 28, and FIG. 29(B) is a cross-sectional view taken along the dashed line QR in FIG. 29(A) is a plan view of a region 953 of the second electrode 931. , which is provided in common to a plurality of pixels, and the first electrode 930 is provided for each pixel, The second electrode 931 and the electrode 941 are connected to the transistor 910. The capacitance element of the touch sensor is formed in the region. The capacitance element includes a second electrode 931 and The dielectric layer is made up of an electrode 941 and a second electrode 931 and a dielectric layer provided between the electrode 941. The second electrode 931 is an electrode for supplying a potential to the electrostatic capacitance element. , which are electrodes for extracting the current flowing through the capacitance element.

[0305] The operation of the display device 900 is a display operation for inputting a video signal to the pixels and a sensor operation for detecting a contact. During a display operation, the potential of the second electrode 931 is fixed to a low level. During the sensing period, a pulse signal is sequentially applied to each of the second electrodes 931. At this time, if a finger is in contact with the display device 900, the touch of the finger The capacitance formed by the The current flowing through the electrodes 941 changes, and the potential of the electrodes 941 changes. By detecting the change in the potential, the touch position of the finger is detected.

[0306] As described above, in a display device having a liquid crystal element, the capacitance of the display device 900 is configured The antistatic conductive film originally provided in the FFS mode liquid crystal display device was used as an electrode to form the Since the display body and the pixel common electrode can be used, it is possible to produce a lightweight, thin, and high-quality touch panel. It is possible to provide a chip panel.

[0307] In this case, the second electrode 931 is disposed below the first electrode 930 (on the first substrate 901 side). However, the second electrode 931 may be provided above the first electrode 930. It is also possible.

[0308] Note that the structure of the display device may be other than that of the display device 900 shown in this embodiment. For example, a capacitance may be formed to connect the touch panel substrate to a liquid crystal display device or a light-emitting display device. The touch panel is an external type that is attached to the first substrate 901 or the second substrate 906. Also, an antistatic device attached to the outside of the first substrate 901 or the second substrate 906 can be used. A surface capacitive touch sensor is created using a conductive film for In the following, an external touch panel will be described with reference to Figs. 30 and 31. A configuration example of a touch sensor applied to the device will be described.

[0309] FIG. 30A is an exploded perspective view showing a configuration example of a touch sensor, and FIG. FIG. 30(C) is a plan view showing a configuration example of an electrode 981 of a touch sensor. 13 is a plan view showing a configuration example of an electrode 982. FIG.

[0310] As shown in FIG. 30(A) to FIG. 30(C), the touch sensor 980 is provided on a substrate 986. , a plurality of electrodes 981 arranged in the X-axis direction, and a plurality of electrodes 982 arranged in the Y-axis direction intersecting the X-axis direction. A plurality of electrodes 982 are formed.

[0311] Each of the electrodes 981 and 982 has a structure in which a plurality of quadrilateral-shaped conductive films are connected. The plurality of electrodes 981 and the plurality of electrodes 982 are arranged such that the positions of the quadrilateral portions of the conductive film are The electrodes 981 and 982 are arranged so as not to overlap each other. An insulating film is provided between 981 and electrode 982 so that they do not come into contact with each other.

[0312] FIG. 31A is a cross-sectional view illustrating an example of a connection structure between the electrodes 981 and 982. FIG. 31(B) shows a cross-sectional view of the intersection of electrodes 981 and 982. 31(B) is an equivalent circuit diagram of the intersection of the electrode 981 and the electrode 982. Additionally, a capacitance 983 is formed at the intersection of the electrode 981 and the electrode 982 .

[0313] As shown in FIG. 31A, in a sensor unit 989, an electrode 981 is a first conductive film 981a, a conductive film 981b, and a second conductive film 981c on the insulating film 985. The conductive film 981a and the conductive film 981b are connected to each other by a conductive film 981c. The electrode 982 is formed of the first conductive film. An insulating film 991 is formed to cover the insulating film 984 and the insulating film 985. As the insulating film 991, for example, a silicon oxide film, a silicon oxynitride film, or the like may be formed. Note that a base insulating film may be formed between the substrate 986 and the electrodes 981 and 984. As the base insulating film, for example, a silicon oxide film, a silicon oxynitride film, etc. can be formed. Cut.

[0314] The electrode 981 and the electrode 982 are formed using a conductive material that transmits visible light. For example, the conductive material having a light-transmitting property is indium tin oxide containing silicon oxide, These include indium tin oxide, zinc oxide, indium zinc oxide, and zinc oxide doped with gallium. .

[0315] The conductive film 981a is connected to an electrode 984 at a terminal portion 990. , which constitute a terminal for connection with an FPC. Similarly to the electrode 981, the electrode 982 is also connected to the other electrodes 984. The electrode 984 may be formed, for example, from a tungsten film.

[0316] In order to electrically connect the electrode 984 to the FPC, an insulating film 985 and an insulating film 986 are formed on the electrode 984. An opening is formed in the insulating film 991. A substrate 987 is attached on the insulating film 991 by adhesive or bonding. The substrate 986 is attached with an adhesive film or the like. The touch panel is constructed by attaching the touch panel to the first substrate 901 or the second substrate 906 of the display device. It is done.

[0317] The structures and methods described in this embodiment may be used in conjunction with structures and methods described in other embodiments and examples. and the like.

[0318] (Embodiment 7) In this embodiment mode, a driving method for reducing power consumption of a display device will be described. The driving method of this embodiment can be used to realize a display device in which an oxide semiconductor transistor is used in a pixel. Further reduction in power consumption can be achieved. An example of reducing power consumption in a liquid crystal display device will now be described.

[0319] FIG. 33 is a block diagram showing an example of the configuration of a liquid crystal display device according to the present embodiment. As shown, the liquid crystal display device 500 has a liquid crystal panel 501 as a display module, and further , a control circuit 510 and a counter circuit.

[0320] The liquid crystal display device 500 receives an image signal (Video) which is digital data, and a liquid crystal panel. A synchronization signal (SYNC) is input to control rewriting of the screen of the panel 501. The signals include, for example, a horizontal synchronization signal (Hsync), a vertical synchronization signal (Vsync), and There are reference clock signals (CLK), etc.

[0321] The liquid crystal panel 501 includes a display unit 530, a scanning line driving circuit 540, and a data line driving circuit 550. The display unit 530 has a plurality of pixels 531. The pixels 531 in the same row are shared. The pixels 531 in the same column are connected to a common scanning line 541 to a scanning line driving circuit 540. The data line 551 is connected to a data line driving circuit 550 .

[0322] The liquid crystal panel 501 is supplied with a common voltage (hereinafter referred to as Vcom) and a power supply voltage. The high power supply voltage (VDD) and the low power supply voltage (VSS) are supplied by the common voltage (Vcom ) is supplied to each pixel 531 of the display unit 530.

[0323] The data line driving circuit 550 processes the input image signal, generates a data signal, and The scanning line driving circuit 540 outputs a data signal to the data line 551. A scanning signal for selecting a pixel 531 to be scanned is output to a scanning line 541.

[0324] The pixel 531 is a switch whose electrical connection with the data line 551 is controlled by a scanning signal. When the switching element is turned on, a signal is sent from the data line 551 to the pixel 531. The data signal is written.

[0325] The electrode to which Vcom is applied corresponds to the common electrode.

[0326] The control circuit 510 is a circuit for controlling the entire liquid crystal display device 500. It is equipped with a circuit that generates a control signal for the circuit that constitutes 0.

[0327] The control circuit 510 controls the scanning line driver 540 and the data line driver 540 in response to a synchronization signal (SYNC). The scanning line driving circuit 540 has a control signal generating circuit that generates a control signal for the scanning line driving circuit 550. The control signals include a start pulse (GSP) and a clock signal (GCLK). As control signals for the data line driving circuit 550, a start pulse (SSP), a clock signal (SC For example, the control circuit 510 may generate clock signals (GCLK, SCLK) and This generates multiple clock signals with the same period but shifted phases.

[0328] The control circuit 510 also receives an image signal (Vide The output of the data line driver circuit 550 is controlled by the data line driver circuit 550.

[0329] The data line driving circuit 550 is a digital / analog conversion circuit (hereinafter, a DA conversion circuit 55 The DA conversion circuit 552 converts the image signal into an analog signal, and outputs a data signal. Generate a number.

[0330] When the image signal input to the liquid crystal display device 500 is an analog signal, the control circuit The signal is converted into a digital signal by a line 510 and output to a liquid crystal panel 501 .

[0331] The image signal is composed of image data for each frame. The control circuit 510 processes the image signal. Based on the information obtained by this processing, the output of the image signal to the data line driving circuit 550 is controlled. Therefore, the control circuit 510 detects the movement from the image data for each frame. When the motion detection unit 511 determines that there is no motion, Then, the control circuit 510 stops outputting the image signal to the data line driving circuit 550 and the motion is disabled. If it is determined that the image signal is not output, the output of the image signal is resumed.

[0332] There are no particular restrictions on the image processing for motion detection performed by the motion detection unit 511. For example, a motion detection method may be to extract differential data from image data between two consecutive frames. The difference data obtained can be used to determine whether there is movement or not. There are also methods for detecting motion vectors.

[0333] The liquid crystal display device 500 is also provided with an image signal correction circuit that corrects the input image signal. For example, a voltage higher than the voltage corresponding to the gray level of the image signal can be applied to the pixel 531. The image signal is corrected so that the image can be written in the correct manner. In this way, the image signal is corrected and processed to drive the control circuit 510. The method of changing the frame frequency of the image signal is called overdrive. When performing double-speed driving to drive the liquid crystal display device 500 at an integer multiple, the control circuit 510 Create image data that interpolates between two frames, or display black between two frames It is only necessary to generate image data for this purpose.

[0334] Below, using the timing chart shown in FIG. 34, we will explain how to deal with moving images such as video images, The operation of the liquid crystal display device 500 for displaying a stationary image such as a still image will now be described. FIG. 34 shows a vertical synchronization signal (Vsync) and a data line 550 from the data line driving circuit 550. The signal waveform of the data signal (Vdata) outputted to 51 is shown.

[0335] FIG. 34 is a timing chart of the liquid crystal display device 500 during a 3m frame period. So, there is motion in the image data for the first k frame period and the last j frame period. In other frame periods, there is no motion in the image data. Note that k and j are each 1 An integer greater than or equal to m-2 inclusive.

[0336] During the first k frame period, the motion detector 511 detects motion in the image data of each frame. Based on the result of the determination by the motion detector 511, the control circuit 510 The data signal (Vdata) is output to the data line 551 .

[0337] Then, the motion detection unit 511 performs image processing for motion detection, and the k+1th frame If it is determined that there is no motion in the image data, the control circuit 510 determines whether the motion detector 511 detects the motion. Based on the result, in the k+1-th frame period, the image signal (Vid eo) is stopped. Furthermore, in order to stop rewriting of the display unit 530, Therefore, a control signal (start pulse signal) to the scanning line driving circuit 540 and the data line driving circuit 550 is The control circuit 510 stops the supply of the signal (the signal, the clock signal, etc.). 1, the data line driving circuit 550 is turned on until a determination result that there is motion in the image data is obtained. output of the image signal, output of control signals to the scanning line driving circuit 540 and the data line driving circuit 550 The force is stopped and rewriting of the display unit 530 stops.

[0338] In this specification, "not supplying" a signal to the liquid crystal panel means that the signal is not supplied. Applying a voltage to the wiring that is different from the voltage required to operate the circuit, or This refers to putting a line into an electrically floating state.

[0339] When rewriting of the display unit 530 is stopped, the electric field in the same direction continues to be applied to the liquid crystal element. This may cause the liquid crystal in the liquid crystal element to deteriorate. Regardless of the result of the motion detection unit 511, the control circuit 510 outputs a scan signal at a predetermined timing. A signal is supplied to the line driving circuit 540 and the data line driving circuit 550, and a data A signal is written to the data line 551 to invert the direction of the electric field applied to the liquid crystal element. .

[0340] The polarity of the data signal input to the data line 551 is determined based on Vcom. The polarity is positive when the data signal voltage is higher than Vcom, and negative when it is lower. is the polarity.

[0341] Specifically, as shown in FIG. 34, in the (m+1)th frame period, the control circuit 510 , and outputs control signals to the scanning line driving circuit 540 and the data line driving circuit 550. The data line driving circuit 550 outputs an image signal Video to the data line driving circuit 550. During this period, the polarity of the data signal (Vdata) output to the data line 551 is inverted. The data signal (Vdata) is output to the data line 551. In the (m+1)th frame period and the (2m+1)th frame period in which the polarity is not detected, The inverted data signal (Vdata) is written to the data line 551. During the period when there is no change, the display unit 530 is rewritten intermittently, so that the power consumption due to the rewriting is This makes it possible to reduce costs and prevent deterioration of the liquid crystal element.

[0342] Then, the motion detection unit 511 detects whether there is any motion in the image data of the (2m+1)th frame and thereafter. When it is determined that the scanning line driving circuit 540 and the data line driving circuit 550 are to be driven, the control circuit 510 and rewrites the display unit 530.

[0343] As described above, according to the driving method of FIG. 34, the effectiveness of the motion of the image data (Video) is improved. Regardless of whether or not the data signal (Vdata) is inverted in polarity every m frame periods. On the other hand, the rewriting of the display unit 530 is performed for a period during which an image including a movement is displayed for each frame. The display unit 530 is rewritten, and the period during which a still image is displayed is every m frames. As a result, the power consumption associated with rewriting the display can be reduced. This makes it possible to suppress the increase in power consumption caused by an increase in the driving frequency and the number of pixels. Cut.

[0344] As described above, the liquid crystal display device 500 has a mode for displaying moving images and a mode for displaying still images. By changing the driving method of the LCD device in each mode, deterioration of the LCD can be suppressed and the display quality can be improved. It is therefore possible to provide a power-saving liquid crystal display device while maintaining a high level of image quality.

[0345] In addition, when displaying a still image, if the pixels are rewritten every frame, the human eye cannot read the rewritten pixels. In some cases, the image may appear as flickering, which can cause eye fatigue. Since the pixels of a display device are rewritten less frequently during the display period of a still image, this is effective in reducing eye fatigue. It is.

[0346] Therefore, it is possible to use a liquid crystal panel in which a backplane is formed using oxide semiconductor transistors. This provides a small- to medium-sized LCD display device with high resolution and low power consumption that is highly suitable for portable electronic devices. It is possible to do so.

[0347] In order to prevent deterioration of the liquid crystal, the interval between polarity inversions of the data signal (here, m frame periods) is The time between the start and end of the pulse should be 2 seconds or less, and preferably 1 second or less.

[0348] In addition, the motion detection of the image data was performed by the motion detection unit 511 of the control circuit 510. The motion detection unit 511 does not need to output the motion data. Alternatively, the signal may be input to the control circuit 510 from outside.

[0349] The condition for determining that there is no motion in the image data is the image data between two consecutive frames. The number of frames required for the determination does not depend on the data, but on the usage pattern of the liquid crystal display device 500. For example, if there is no motion in the image data of consecutive m frames, In this case, rewriting of the display unit 530 may be stopped.

[0350] The structures and methods described in this embodiment may be used in conjunction with structures and methods described in other embodiments and examples. and the like.

[0351] (Embodiment 8) The semiconductor device according to one embodiment of the present invention can be applied to various electronic devices (including game machines). The electronic equipment includes a television set (television or television receiver) (also called a monitor), computer monitors, digital cameras, digital video cameras , digital photo frames, mobile phones, portable game machines, personal digital assistants, audio playback devices , gaming machines (pachinko machines, slot machines, etc.), and game cabinets. An example of the device is shown in Figure 15.

[0352] FIG. 15A shows a table 9000 having a display section. A display unit 9003 is built into the housing 9001, and an image is displayed on the display unit 9003. It is possible to support the housing 9001 with four legs 9002. The housing 9001 also includes a power cord 9005 for supplying power.

[0353] The semiconductor device described in any of the above embodiments can be used for the display portion 9003. Therefore, the display quality of the display portion 9003 can be improved.

[0354] The display unit 9003 has a touch input function. By touching the display button 9004 displayed on the screen with a finger or the like, the screen can be operated or information can be input. It can also communicate with and control other home appliances, improving picture quality. It may also be a control device that controls other home appliances by surface manipulation. For example, If a semiconductor device having a sensor function is used, the display portion 9003 can have a touch input function. It is possible.

[0355] In addition, the screen of the display unit 9003 can be fixed to the floor by a hinge provided in the housing 9001. It can also be placed vertically and used as a television set. A large-screen television set will take up a lot of free space, but it can be placed on a table. If the display unit is built into the device, the space in the room can be used more effectively.

[0356] FIG. 15B shows a television device 9100. A display unit 9103 is incorporated in a housing 9101, and an image is displayed on the display unit 9103. In this example, the housing 9101 is supported by a stand 9105. The configuration shown is as follows.

[0357] The television device 9100 can be operated using an operation switch provided on the housing 9101 or a separate remote control. This can be done by using a remote control operation device 9110. The channel and volume can be controlled by the 9109, and the display 9103 shows The remote control device 9110 can control the video. A display unit 9107 for displaying information output from the device 9110 may be provided.

[0358] A television device 9100 shown in FIG. 15(B) includes a receiver, a modem, and the like. The television device 9100 can receive general television broadcasts using a receiver. Furthermore, by connecting to a wired or wireless communication network via a modem, One-way (from sender to receiver) or two-way (between sender and receiver, or between receivers) It is also possible to carry out information communication.

[0359] The semiconductor device described in any of the above embodiments can be used for the display portions 9103 and 9107. This makes it possible to improve the display quality of the television device.

[0360] FIG. 15C shows a computer 9200, which includes a main body 9201, a housing 9202, a display unit 9 203, keyboard 9204, external connection port 9205, pointing device 920 6, etc.

[0361] The semiconductor device described in any of the above embodiments can be used for the display portion 9203. Therefore, the display quality of the computer 9200 can be improved.

[0362] The display unit 9203 has a touch input function. 03 Touch the display buttons with your finger to operate the screen or input information. It can also communicate with other home appliances or control them, making it easier to operate the screen. It may also be used as a control device that controls other home appliances through its operation.

[0363] FIG. 16(A) and FIG. 16(B) show a tablet terminal that can be folded in two. 9631a, the tablet terminal is in an open state. 9631b, a display mode changeover switch 9034, a power switch 9035, a power saving mode It has a mode changeover switch 9036, a fastener 9033, and an operation switch 9038.

[0364] The semiconductor device described in any of the above embodiments includes a display portion 9631a and a display portion 9631b. Therefore, it is possible to improve the display quality of tablet devices. Cut.

[0365] A part of the display unit 9631a can be used as a touch panel area 9632a. By touching the operation keys 9638 displayed on the display unit 96, data can be input. In 31a, as an example, half of the area has a display function only, and the other half The display unit 96 has a touch panel function, but is not limited to this. The entire area of ​​the display unit 931a may have a touch panel function. The entire surface of 631a is made to display keyboard buttons to serve as a touch panel, and the display section 9631b is made to display It can be used as a display screen.

[0366] In addition, in the display unit 9631b, as in the display unit 9631a, The part of the touch panel can be the area 9632b of the touch panel. Touch the area where the mode display switch button 9639 is displayed with your finger or a stylus. A keyboard button can be displayed on the display portion 9631b.

[0367] In addition, the touch panel area 9632a and the touch panel area 9632b are simultaneously You can also use touch input.

[0368] A display mode changeover switch 9034 is used to change the display orientation, such as vertical or horizontal. You can choose between black and white and color display. The 9036 is a tablet-type device that detects external light during use using a built-in light sensor. The tablet device has a light sensor, which can adjust the display brightness to suit the amount of light. In addition to the sensor, other detection devices such as gyro, acceleration sensor, etc. that detect the inclination are also included. It may be built-in.

[0369] FIG. 16A shows an example in which the display area of ​​the display portion 9631b is the same as that of the display portion 9631a. However, there is no particular limitation, and one size may be different from the other size. The quality of the display may also be different. For example, one display panel may provide a higher resolution display than the other. It may also be used as a rule.

[0370] FIG. 16B shows the tablet terminal in a closed state. The tablet terminal includes a housing 9630 and a solar cell 9 16B, the charge / discharge control circuit 96 As an example of the 34, a configuration having a battery 9635 and a DC-DC converter 9636 is described below. This is shown.

[0371] In addition, since the tablet device can be folded in half, the case 9630 can be folded when not in use. Therefore, the display portions 9631a and 9631b can be protected. This makes it possible to provide a tablet device that is highly durable and reliable even when used for a long period of time.

[0372] In addition, the tablet terminals shown in Figs. 16(A) and 16(B) can be used in various Functions that display information (still images, videos, text images, etc.), calendars, dates, or times A function to display information on the display unit, and a function to input or edit information displayed on the display unit. It has input functions, functions to control processing by various software (programs), etc. It is possible.

[0373] The solar cell 9633 attached to the surface of the tablet device supplies power to the touch panel. The solar cell 9633 can supply the solar cell 9633 with the following components: The battery 9635 can be efficiently charged by providing the battery 9635 on one or both sides of the housing 9630. This is preferable because it can be configured to perform the above-mentioned operations. The use of lithium-ion batteries has the advantage of enabling miniaturization.

[0374] The configuration and operation of the charge / discharge control circuit 9634 shown in FIG. A block diagram is shown in FIG. 16(C) and will be explained. FIG. 16(C) shows a solar cell 9633, a battery 9 635, DC-DC converter 9636, converter 9637, switches SW1 to SW3 , a display unit 9631, a battery 9635, a DC-DC converter 963 6. The converter 9637 and the switches SW1 to SW3 are configured to perform the charge / discharge control shown in FIG. 16(B). This corresponds to the circuit 9634 .

[0375] First, an example of operation when power is generated by the solar cell 9633 due to external light will be described. The power generated by the solar cell is converted to a voltage to charge the Battery 9635. The CDC converter 9636 increases or decreases the voltage. When power is being used from the solar cell 9633, switch SW1 is turned on and the converter The voltage is increased or decreased to the voltage required for the display unit 9631 by the display unit 9637. When not displaying on the 9631, turn switch SW1 off and switch SW2 on. The battery 9635 may be charged by using the above configuration.

[0376] The solar cell 9633 is shown as an example of a power generating means, but is not limited thereto. , and other power generation methods such as piezoelectric elements and thermoelectric conversion elements (Peltier elements) For example, the battery 9635 may be charged. A non-contact power transmission module that transmits and receives power and charges, or a combination of other charging methods This may also be configured.

[0377] Note that the structure described in this embodiment mode may be appropriately combined with structures described in other embodiments. It can be used. EXAMPLES

[0378] In this example, the Vg-Id characteristics of the transistor and the measurement results of the optical BT stress test We will explain about this.

[0379] First, a manufacturing process of a transistor included in Sample 1 will be described. The following description will be given with reference to FIG.

[0380] First, as shown in FIG. 3(A), a glass substrate is used as the substrate 11, and a gate electrode is formed on the substrate 11. A contact electrode 15 was formed.

[0381] A tungsten film with a thickness of 100 nm was formed by sputtering, and then photolithography was performed. A mask is formed on the tungsten film by the process, and a part of the tungsten film is removed by using the mask. The portion was etched to form a gate electrode 15.

[0382] Next, the gate insulating film 17 was formed on the gate electrode 15 .

[0383] As the gate insulating film, a first silicon nitride film having a thickness of 50 nm and a second silicon nitride film having a thickness of 300 nm are used. A silicon nitride film, a third silicon nitride film having a thickness of 50 nm, and a silicon oxynitride film having a thickness of 50 nm were then formed. The silicon film was laminated.

[0384] The first silicon nitride film was formed using a mixture of silane at a flow rate of 200 sccm and nitrogen at a flow rate of 2000 sccm. and ammonia at a flow rate of 100 sccm was used as the source gas in the processing chamber of the plasma CVD device. The pressure in the processing chamber was controlled to 100 Pa, and a high frequency power source of 27.12 MHz was used. It was formed by supplying 2000W of power.

[0385] Next, under the conditions of the source gas for the first silicon nitride film, the flow rate of ammonia was set to 2000 The flow rate was changed to sccm to form a second silicon nitride film.

[0386] Next, silane at a flow rate of 200 sccm and nitrogen at a flow rate of 5000 sccm were used as source gases. The gas was supplied to the processing chamber of the plasma CVD device, and the pressure in the processing chamber was controlled to 100 Pa. A third silicon nitride film was formed by supplying 2000 W of power using a 2 MHz high frequency power source. Successful.

[0387] Next, silane at a flow rate of 20 sccm and dinitrogen monoxide at a flow rate of 3000 sccm were used as the source gas. The pressure in the processing chamber is controlled to 40 Pa, and 27. A silicon oxynitride film is formed by supplying 100 W of power using a 12 MHz high frequency power supply. did.

[0388] The first to third silicon nitride films and the silicon oxynitride film are formed In this process, the substrate temperature was set to 350°C.

[0389] Next, a multilayer film 20 was formed so as to overlap the gate electrode 15 with the gate insulating film 17 interposed therebetween.

[0390] Here, a first In film having a thickness of 35 nm is formed on the gate insulating film 17 as the oxide semiconductor film 18. After forming a -Ga-Zn oxide film by a sputtering method, an In-based Alternatively, a second In-Ga-Zn oxide film having a thickness of 20 nm may be used as the Ga-containing oxide film 19. Next, a photolithography process is performed on the oxide film 19 containing In or Ga. A mask is formed on the oxide semiconductor film 18 and the oxide containing In or Ga using the mask. Then, a part of the oxide semiconductor film 19 was etched. The oxide film 19 containing In or Ga was subjected to a heat treatment to form a multilayer film 20 .

[0391] The first In-Ga-Zn oxide film was formed by sputtering a target of In:Ga:Zn= The target was 1:1:1 (atomic ratio), and the flow rate of argon was 50 sccm and 50 s ccm of oxygen is supplied as sputtering gas into the processing chamber of the sputtering device, The pressure inside the tube was controlled to 0.6 Pa, and 5 kW of DC power was supplied. The substrate temperature was set to 170° C. when the n-Ga-Zn oxide film was formed.

[0392] The second In-Ga-Zn oxide film was prepared by sputtering a target of In:Ga:Zn= The target was 1:3:2 (atomic ratio) and the sputtering gas was 90sccm. Ar and oxygen at a flow rate of 10 sccm were supplied into the processing chamber of the sputtering device. The pressure was controlled to 0.3 Pa, and a direct current of 5 kW was supplied to form the second In- The substrate temperature was set to 25° C. when the Ga—Zn oxide film was formed.

[0393] Heat treatment was performed in a nitrogen atmosphere at 450°C for 1 hour, and then in a nitrogen and oxygen atmosphere. The mixture was then subjected to a heat treatment at 450° C. for 1 hour in an atmospheric environment.

[0394] The structure obtained through the steps up to this point can be seen in FIG.

[0395] Next, a part of the gate insulating film 17 is etched to expose the gate electrode (not shown). 3(C), a pair of electrodes 21 and 22 in contact with the multilayer film 20 was formed.

[0396] Here, a conductive film was formed on the gate insulating film 17 and the multilayer film 20. An aluminum film having a thickness of 400 nm is formed on a tungsten film having a thickness of 50 nm. A titanium film with a thickness of 100 nm was then formed on the aluminum film. A mask is formed on the conductive film, and a part of the conductive film is etched using the mask. The electrodes 21 and 22 were formed.

[0397] Next, the substrate is moved to a reduced pressure processing chamber, heated to 220°C, and then filled with nitrous oxide. The substrate was then moved to a processing chamber in which a 27.12 M H A high-frequency power supply of 150 W was used to supply high-frequency power to the device, and the generated nitrous oxide was generated by the decomposition of nitrous oxide. The multilayer film 20 was exposed to the generated oxygen plasma.

[0398] Next, a protective film 26 was formed on the multilayer film 20 and the pair of electrodes 21 and 22 (see FIG. 3(D)). Here, an oxide insulating film 24 and a nitride insulating film 25 are formed as the protective film 26. .

[0399] First, after the above plasma treatment, the oxide insulating film 24 is continuously formed without exposure to the atmosphere. As the oxide insulating film 24, a silicon oxynitride film was formed to a thickness of 400 nm.

[0400] The oxide insulating film 24 is formed by using silane at a flow rate of 160 sccm and monoxide at a flow rate of 4000 sccm. Dinitrogen was used as the source gas, the pressure in the processing chamber was 200 Pa, the substrate temperature was 220°C, and The film was formed by the plasma CVD method in which a high-frequency power of 1000 MW was supplied to parallel plate electrodes. As a result, the mixture contains more oxygen than the stoichiometric composition, and some of the oxygen is removed by heating. A silicon oxynitride film can be formed to separate the insulating film.

[0401] Next, heat treatment was performed to remove water, nitrogen, hydrogen, and the like from the oxide insulating film 24. The sample was subjected to a heat treatment at 350° C. for 1 hour in a nitrogen and oxygen atmosphere.

[0402] Next, the substrate is moved to a reduced pressure processing chamber and heated at 350° C., and then the oxide insulating film 24 is The nitride insulating film 25 was formed on the silicon substrate 21. A silicon nitride film was formed.

[0403] The nitride insulating film 25 is formed by mixing silane at a flow rate of 50 sccm, nitrogen at a flow rate of 5000 sccm, and Ammonia was used as the source gas at a flow rate of 100 sccm, the pressure in the processing chamber was set to 100 Pa, and the substrate temperature was set to 1000 . The plasma CVD method was performed with a temperature of 350°C and a high-frequency power of 1000 W supplied to parallel plate electrodes. More formed.

[0404] Next, although not shown, a part of the oxide insulating film 24 and the nitride insulating film 25 are etched. An opening was formed to expose a part of the pair of electrodes 21 and 22 .

[0405] Next, a planarizing film was formed on the nitride insulating film 25 (not shown). After being applied onto the nitride insulating film 25, exposure and development are performed to expose parts of the pair of electrodes. A planarizing film having an opening was formed. The planarizing film was made of an acrylic resin having a thickness of 1.5 μm. After that, a heat treatment was carried out. The heat treatment was carried out at a temperature of 250°C and nitrogen was added. It lasted for an hour in a relaxed atmosphere.

[0406] Next, a conductive film was formed to connect to a part of the pair of electrodes (not shown). A 100 nm thick ITO film containing silicon oxide was formed by the ion beam deposition method. Heat treatment was carried out in a nitrogen atmosphere at 250° C. for 1 hour.

[0407] Through the above steps, Sample 1 having a transistor was manufactured.

[0408] In addition, in the transistor of Sample 1, an oxide film 19 containing In or Ga is formed. A sample having a transistor without a pair of electrodes 21 and 22 was fabricated as Sample 2. After the formation, the oxide semiconductor film 18 was washed with a phosphoric acid solution obtained by diluting 85% phosphoric acid by 100 times. The surface was subjected to a cleaning treatment.

[0409] Next, the Vg-Id characteristics were measured as the initial characteristics of the transistors included in Sample 1 and Sample 2. Here, the substrate temperature was set at 25°C, and the potential difference between the source and drain (hereafter referred to as drain) was The potential difference between the source and gate electrodes (hereafter referred to as the gate voltage) is set to 1 V or 10 V. The current flowing between the source and drain when the power supply voltage is changed from -20V to +15V is The change in the current (hereinafter referred to as drain current), i.e., the Vg-Id characteristic, is measured. Ta.

[0410] FIG. 17(A) and FIG. 17(B) show the Vg-Id of the transistors included in each sample. 17, the horizontal axis represents the gate voltage Vg, and the vertical axis represents the drain current Id. The solid lines show the Vg-Id characteristics when the drain voltage Vd is 1 V and 10 V, respectively. The dashed line shows the field effect mobility versus gate voltage when the drain voltage Vd is set to 10 V. The field effect mobility is the result in the saturation region of each sample.

[0411] Each transistor has a channel length (L) of 6 μm and a channel width (W) of 50 μm. In addition, for each sample, 20 transistors with the same structure were fabricated on the substrate.

[0412] As shown in FIG. 17B, in the Vg-Id characteristics of the transistor included in Sample 2, The gate voltage at which the on-current starts to flow when the on-state voltage Vd is 1V (also called the rising gate voltage) (Vg). The rising gate voltage of the on-current at 10V is different from that at 10V. The Vg-Id characteristics of the transistors in 2 also vary widely. ) the Vg-Id characteristics of the transistor included in sample 1 are as follows: drain voltage Vd is 1V, The gate voltage (Vg) rise time of the on-state current at 10 V is almost the same. The variation in Vg-Id characteristics between the transistors in the device is small. The conductor film 18 and the oxide insulating film 24 are not in direct contact with each other. An oxide film 19 containing In or Ga is provided between the conductor film 18 and the oxide insulating film 24. It can be seen that the initial characteristics of the transistor are improved by this.

[0413] Next, the BT stress test and the light BT stress test were carried out on the samples 1 and 2. In the BT stress test, the substrate temperature was set to 80°C, and the electric field strength applied to the gate insulating film was set to 0 BT: Apply a certain voltage to the gate electrode with a voltage of 0.66MV / cm and a time of 2000 seconds. The BT stress test was performed in an air atmosphere with a dew point temperature of 12°C. Ta.

[0414] In addition, using the same conditions as the BT stress test, a 3000lx white LED light was used. A light BT stress test was performed by applying a certain voltage to the gate electrode while irradiating the transistor. The light BT stress test was carried out in a dry air atmosphere with a dew point of -30°C.

[0415] Here, we will explain the measurement method of the BT stress test. The initial Vg-Id characteristics of the transistor were measured.

[0416] Next, the substrate temperature was raised to 80° C., and then the source and drain potentials of the transistor were was set to 0 V. Next, the electric field strength applied to the gate insulating film was set to 0.66 MV / cm. A voltage was applied to the gate electrode as shown in FIG.

[0417] In addition, in the negative BT stress test (Dark -GBT), a voltage of -30V is applied to the gate electrode. In the plus BT stress test (Dark +GBT), a voltage of 100 V was applied to the gate electrode. A voltage of 30V was applied. In addition, in the light negative BT stress test (Photo -GBT), A voltage of -30 V was applied to the gate electrode while irradiating the device with 3000 lx of white LED light. In the Plus BT stress test (Photo +GBT), 3000lx white LED light was used. While irradiating the light, 30 V was applied to the gate electrode.

[0418] Next, while applying voltage to the gate electrode, source, and drain, the substrate temperature was increased to 25°C. After the substrate temperature reached 25°C, voltage was applied to the gate electrode, source, and drain. was terminated.

[0419] In addition, the initial characteristics of the threshold voltage and BT strike of the transistors included in Samples 1 and 2 were The difference in threshold voltage after the load test (i.e., the amount of change in threshold voltage (ΔVth)) is shown in Fig. 18. In Fig. 18, the positive BT stress test (Dark +GBT) and the negative BT Stress test (Dark -GBT), Light plus BT stress test (Photo +GB T), light negative BT stress test (Photo -GBT) The amount of fluctuation ΔVth is shown.

[0420] In this specification, the threshold voltage (Vth) is the gate voltage (Vg [V]). axis, the square root of the drain current (Id 1 / 2 [A]) on the vertical axis. In the first place, the maximum slope is Id 1 / 2 When the tangent of is extrapolated, the intersection of the tangent with the Vg axis is It is defined as the gate voltage at the point.

[0421] In addition, as shown in FIG. 18, the absolute value of the variation in the threshold voltage of the transistor included in Sample 1 is , compared to the absolute value of the threshold voltage fluctuation (ΔVth) of the transistor included in Sample 2. In particular, the dark +GBT stress test The amount of change in threshold voltage (ΔVth) due to the oxide semiconductor is significantly reduced. An oxide film 19 containing In or Ga is provided between the insulating film 18 and the oxide insulating film 24. This improves the reliability of the transistor.

[0422] From the above, an oxide semiconductor film containing In or Ga is formed between the oxide semiconductor film 18 and the oxide insulating film 24. By providing the oxide film 19, the electrical characteristics of the transistor can be improved. In addition, the initial characteristics can be improved and the reliability can also be improved. The oxide film 19 containing Ga is formed by forming an oxide insulating film 24 on the oxide semiconductor film 18 which is a channel region. It can be said that the inclusion of elements contained in the steel (such as nitrogen) is suppressed. The oxide film 19 containing In or Ga is formed by a plasma CVD method with a high power density. When the insulating film 24 is formed, the oxide semiconductor film 18, which is the channel region, is damaged by plasma. It can be said that it suppresses receiving. EXAMPLES

[0423] In this example, the oxide semiconductor films of the transistors included in Sample 1 and Sample 2 of Example 1 The amount of oxygen vacancies contained in Sample 18 will be described. A sample having the same structure as the stacked structure of the transistor in Sample 2 was fabricated, and the oxide semiconductor film 18 In order to evaluate the amount of oxygen vacancies contained in the material, ESR (electron spin resonance) analysis was carried out.

[0424] First, the samples measured will be described. Sample 3 is a sample in which an oxide semiconductor film 18 is formed on quartz by 35 An oxide film 19 containing In or Ga is formed on the oxide semiconductor film 18 to a thickness of 20 nm. An oxide insulating film 24 was formed to a thickness of 400 nm on the oxide film 19 containing In or Ga. .

[0425] The oxide semiconductor film 18 and the oxide film 19 containing In or Ga of Sample 3, and the oxide The insulating film 24 was formed under the same conditions as those for the sample 1 of the first embodiment.

[0426] In the sample 4, the oxide semiconductor film 18 is formed to a thickness of 35 nm, and an oxide insulating film is formed on the oxide semiconductor film 18. The film 24 was formed to a thickness of 400 nm.

[0427] The oxide semiconductor film 18 and the oxide insulating film 24 of Sample 4 were grown under the same conditions as those of Sample 2 of Example 1. was formed.

[0428] Next, ESR analysis was performed on Sample 3 and Sample 4. The ESR measurement was performed at a specified temperature. From the magnetic field value (H0) at which microwave absorption occurs, the g value is calculated using the formula g=hν / βH0. Here, ν is the microwave frequency, and h is the Planck constant. and β is the Bohr magneton, both of which are constants. The power (9.06 GHz) was 20 mW, and the magnetic field direction was parallel to the film surface of sample 3 and sample 4. The measurement temperature was room temperature.

[0429] The ESR analysis results are shown in Figure 19. In Figure 19, the horizontal axis indicates the sample name, and the vertical axis indicates the oxide The oxygen vacancy density in the semiconductor film 18 and the oxide film 19 containing In or Ga is The spin density at g=1.93 is shown.

[0430] Comparing sample 3 and sample 4, it is clear from FIG. 19 that sample 3 has a smaller spin density. That is, an oxide film containing In or Ga is provided between the oxide semiconductor film 18 and the oxide insulating film 24. By providing 19, oxygen deficiency caused by plasma damage during the formation of the oxide insulating film 24 is prevented. It can be said that the generation of losses in the oxide semiconductor film 18 can be suppressed.

[0431] In addition, although not shown, in the sample 3, the oxide film 19 containing In or Ga was By providing the distance of 100 nm, the spin density was below the detection limit. The density detection limit is 1.0e+17spins / cm 3 Therefore, the oxygen vacancy can be reduced. From the viewpoint of achieving this, the oxide insulating film 19 containing In or Ga is provided at a thickness of 50 nm. This makes it possible to significantly reduce plasma damage that occurs when forming the insulating film 24.

[0432] From the above, by providing the oxide film 19 containing In or Ga, a plate with high power density can be obtained. Even when the oxide insulating film 24 is formed by the CVD method, a transistor having good electrical characteristics and A semiconductor device having the transistor can be manufactured. EXAMPLES

[0433] In this example, a localized level of a multilayer film included in a transistor according to one embodiment of the present invention will be described. Here, the results of evaluating the multilayer film by CPM measurement will be described.

[0434] First, the sample measured by CPM will be described.

[0435] A first oxide film containing In or Ga having a thickness of 30 nm is formed on a glass substrate. A 100-nm-thick oxide semiconductor film is formed on the oxide film containing In or Ga. By forming a second oxide film containing In or Ga with a thickness of 30 nm on the semiconductor film, A multi-layer film was formed.

[0436] In this embodiment, the first oxide film containing In or Ga and the second oxide film containing In or Ga The second oxide film is made of In-Ga-Zn oxide (In:Ga:Zn=1:3:2 [atomic ratio] The oxide film was formed by sputtering using a target with a [number ratio] of 100 to 1500. The deposition gas was argon gas at 30 sccm and oxygen gas at 15 sccm. The pressure was 0.4 Pa, the substrate temperature was 200°C, and a DC power of 0.5 kW was applied. Ta.

[0437] The oxide semiconductor film is made of In-Ga-Zn oxide (In:Ga:Zn=1:1:1[

[0036] An oxide semiconductor film formed by a sputtering method using a target having a [atomic ratio] of 1.0 to 1.0 atomic percent The deposition gases used were argon gas at 30 sccm and oxygen gas at 15 sccm. The pressure was set to 0.4 Pa, the substrate temperature was set to 200° C., and a DC power of 0.5 kW was applied. It was formed with.

[0438] The sample prepared in the above manner is designated as Sample 5.

[0439] Next, the CPM measurement was performed on sample 5. Specifically, The terminals were then adjusted so that the photocurrent value was constant when a voltage was applied between the first and second electrodes. The amount of light irradiated onto the sample surface between the two points is adjusted, and the absorption coefficient is calculated from the amount of light irradiated within the desired wavelength range. Derived.

[0440] Figure 20 shows the absorption coefficient measured by a spectrophotometer (bold dotted line) and the absorption coefficient derived by CPM measurement. The absorption coefficient (thick solid line) and the energy gap of each layer in the multilayer film are The fitting results are shown in the range. The Urbach energy, which is the slope of the Urbach tail (thin dotted line) in the coefficient curve The CP The absorption coefficient of the Urbach tail (thin dotted line) is subtracted from the absorption coefficient obtained by the M measurement. The integral value of the absorption coefficient in the energy range was derived (see FIG. 20(B)). As a result, the absorption coefficient of this sample is 2.02×10 -4 cm -1 It was found to be.

[0441] From the above, it can be considered that the localized levels in the multilayer film of Sample 5 are levels caused by impurities or defects. Therefore, it was found that the multilayer film has an extremely low level density caused by impurities and defects. It can be seen that the transistor using the multilayer film has stable electrical characteristics. EXAMPLES

[0442] In this example, the silicon concentration of a multilayer film included in a transistor according to one embodiment of the present invention was Here, we will explain the results of evaluating the multilayer film by SIMS measurement. .

[0443] First, the sample measured by SIMS will be described.

[0444] An oxide film 81 containing In or Ga having a thickness of 10 nm is formed on a silicon wafer Si. A 10 nm-thick oxide semiconductor film 82 is formed on an oxide film 81 containing In or Ga. An oxide film 83 containing In or Ga is formed to a thickness of 10 nm on the oxide semiconductor film 82. A multilayer film was formed by this.

[0445] In this embodiment, the oxide film 81 containing In or Ga is an In-Ga-Zn oxide. A sputtering process was performed using a target with an atomic ratio of In:Ga:Zn=1:3:2. The oxide film was formed by the deposition method using argon gas at 30 sccm. The oxygen gas was 15 sccm, the pressure was 0.4 Pa, the substrate temperature was 200° C., and DC It was formed by applying 0.5 kW of power.

[0446] The oxide semiconductor film 82 is made of In-Ga-Zn oxide (In:Ga:Zn=1:1: 1 [atomic ratio]) using a target, the oxide semiconductor film formed by the sputtering method The deposition gas was argon gas at 30 sccm and oxygen gas at 15 sccm. The pressure was set to 0.4 Pa, the substrate temperature was set to 300°C, and a DC power of 0.5 kW was applied. It was formed by

[0447] The oxide film 83 containing In or Ga is an In-Ga-Zn oxide (In:Ga The target was formed by sputtering using a ZnO (Zn=1:3:2 [atomic ratio]) The deposition gas was argon gas at 30 sccm and oxygen gas at 30 sccm. The gas was heated to 15 sccm, the pressure was 0.4 Pa, the substrate temperature was 200° C., and the DC power was 0.5 It was formed by applying kW.

[0448] After forming the multilayer film, the sample was divided into two groups: one that was not heat-treated and one that was heat-treated at 450°C for 2 hours. The sample that was not heat-treated was designated as sample 6, and the sample that was heat-treated was designated as sample 7. The fee was set at 7.

[0449] Samples 6 and 7 were analyzed by time-of-flight secondary ion mass spectrometry (ToF-SIMS). e-of-flight secondary ion mass spectrome The Si concentration in the depth direction [atoms / cm 3 ] was measured. The Si concentration calculated from the secondary ion intensity of SiO3 in the depth direction of the multilayer film in sample 6 [atoms / cm 3 21(B) shows the Si Si concentration calculated from secondary ion intensity of O3 [atoms / cm 3 ] is indicated.

[0450] As shown in FIG. 21(A) and FIG. 21(B), a silicon wafer and an oxide containing In or Ga are The Si concentration is In addition, the Si concentration of the oxide semiconductor film 82 was found to be high by ToF-SIMS. The lower limit is 1×10 18 atoms / cm 3 This is because the An oxide film 81 containing In or Ga and an oxide film 83 containing In or Ga are provided. As a result, silicon originating from the silicon wafer or surface contamination is absorbed into the oxide semiconductor film 82. This can be considered to be because the effect on

[0451] In addition, the results shown in FIG. 21(A) and FIG. 21(B) show that the silicon expansion was caused by the heat treatment. It is clear that dispersion is unlikely to occur, and mixing during film formation is the main cause.

[0452] From the above, by using the multilayer film as shown in this embodiment, a transistor having stable electrical characteristics can be obtained. A transistor can be fabricated.

[0453] (Reference example 1) Here, the oxide insulating film 24 of the transistor described in the above embodiment is a stoichiometric A nitrided oxide film contains more oxygen than meets the composition requirement, and some of the oxygen is released when heated. The silicon film will now be described.

[0454] It contains more oxygen than the stoichiometric composition, and some of the oxygen is released when heated. To evaluate this, TDS measurements were performed to measure the amount of oxygen outgassing.

[0455] First, the sample structure measured is explained. Reference sample 1 is a silicon wafer with A silicon oxynitride film having a thickness of 400 nm was formed under the following conditions: flow rate 160 Silane at a flow rate of 4000 sccm and dinitrogen monoxide at a flow rate of 4000 sccm were used as the source gases. The pressure was set to 200 Pa, the substrate temperature was set to 220°C, and 1500 W of high frequency power was applied to the parallel plate electrodes. The film was formed by plasma CVD using a 1000-kV supply.

[0456] Reference sample 2 is a silicon oxynitride film with a thickness of 400 nm formed on a silicon wafer under the following conditions: This is a reference sample on which a film was formed. The conditions were the same as those for Reference Sample 1, except that silane was used at a flow rate of 200 The other conditions were the same as those of Reference Sample 1.

[0457] The results of the TDS measurements of Reference Sample 1 and Reference Sample 2 are shown in Figures 22(A) and 22(B). In Figures 22(A) and 22(B), the oxygen quality of both Reference Sample 1 and Reference Sample 2 is A peak at M / z=32, which corresponds to the amount of the ion, was observed. It can be said that a part of the oxygen contained in the silicon oxynitride film is released by heating. do.

[0458] The amount of oxygen released by heating is calculated as the amount of oxygen molecules (per unit area). ) can be used to evaluate the sample. 14 molecules / cm 2 Reference sample 2 is 1.9 x 10 14 molecules / cm 2 The amount of oxygen released from Reference Sample 1 was The value converted to elementary atoms (per unit volume) is 1.6 × 10 19 atoms / cm 3 And the reference test The amount of oxygen released from sample 2 converted to oxygen atoms (per unit volume) is 9.5 × 10 18 atoms / cm 3 It was.

[0459] From the above, the silicon oxynitride films formed under the conditions of Reference Sample 1 and Reference Sample 2 were considered to be oxide nitride films. After the oxide semiconductor film is provided in a region overlapping with the conductive film, heat treatment is performed to reduce oxygen vacancies in the oxide semiconductor film. This makes it possible to repair the defects, and thus to manufacture a transistor with excellent electrical characteristics.

[0460] (Reference example 2) The defect density of the oxide insulating film used in the reference sample 1 and the reference sample 2 in the reference example 1 will be described. Here, the defect amount of the oxide insulating film is analyzed by ESR (electron spin resonance) method. The following results will be used to explain.

[0461] First, the structure of the evaluated sample will be described.

[0462] Reference samples 3 and 4 are oxide semiconductors with a thickness of 100 nm formed on a quartz substrate. and a 400-nm-thick oxide insulating film formed over the oxide semiconductor film.

[0463] The oxide semiconductor films of Reference Sample 3 and Reference Sample 4 were prepared by sputtering In:G The target was a:Zn=1:1:1 (atomic ratio), and the flow rate was 50 sccm of argon and Oxygen is supplied to the processing chamber of the sputtering equipment as sputtering gas at a flow rate of 50 sccm. The pressure in the treatment chamber was controlled to 0.6 Pa, and a direct current of 5 kW was supplied to the treatment chamber. The substrate temperature was set to 170° C. when the oxide semiconductor film was formed.

[0464] Next, the specimen was heat-treated at 450°C for 1 hour in a nitrogen atmosphere, and then cooled in a nitrogen and oxygen atmosphere. Then, heat treatment was carried out at 450° C. for 1 hour.

[0465] Next, an oxide insulating film was formed over the oxide semiconductor film. A sample formed under the same conditions as those for the silicon oxynitride film is designated as Reference Sample 3.

[0466] The oxide insulating film formed on the oxide semiconductor film was the same as the silicon oxynitride film of Reference Sample 2. A sample formed using similar conditions is designated as Reference Sample 4.

[0467] Next, ESR analysis was performed on Reference Sample 3 and Reference Sample 4 under the following conditions. The ESR analysis was performed under the following conditions. The measurement temperature was -170°C, and the high-frequency power (Ma The microwave power was set to 1 mW, and the magnetic field direction was parallel to the film surface of the prepared sample.

[0468] The signal speed at g (g value) = 2.001 due to the silicon dangling bond The density is shown in FIG.

[0469] It can be seen that the spin density is reduced in Reference Sample 4 compared to Reference Sample 3. That is, The deposition conditions for the oxide insulating film were: silane flow rate of 200 sccm, dinitrogen monoxide flow rate of By setting the flow rate at 4000sccm, a silicon oxynitride film with few defects, typically ESR The spin density of the signal at g = 2.001 is 6 × 10 17 spins / c m 3 Less than 3 x 10 17 spins / cm 3 Less than or equal to 1.5×10 1 7 spins / cm 3 The following silicon oxynitride film can be formed.

[0470] From the above, it is found that forming an oxide insulating film under the above conditions increases the flow rate of silane. This makes it possible to reduce the defect density in the formed oxide insulating film.

[0471] (Reference example 3) Here, we will discuss the quantification of defect states generated in the energy gap of an oxide semiconductor film. In this reference example, we will explain the HAXPES ( Hard X-ray Photoelectron Spectroscopy The measurement results will be explained below.

[0472] The samples used for HAXPES measurements are described below.

[0473] A silicon oxynitride film with a thickness of 100 nm is formed on a silicon wafer. A 100-nm-thick oxide semiconductor film is formed on the silicon film, and a 5-nm-thick oxide semiconductor film is formed on the oxide semiconductor film. A sample (sample 8) was prepared on which a silicon oxide film having a thickness of 100 nm was formed.

[0474] In sample 8, the silicon oxynitride film was formed using silane with a flow rate of 1 sccm and The source gas was nitrous oxide of 40 cm, the pressure in the processing chamber was 40 Pa, and the substrate temperature was 400°C. The plasma CVD method was used, in which 150 W of high-frequency power (60 MHz) was supplied to parallel plate electrodes. It was formed.

[0475] In Sample 8, the oxide semiconductor film was made of In-Ga-Zn oxide (In:Ga:Zn=1 The deposition gas was argon gas at 30 The pressure was set to 0.4 Pa, and the substrate temperature was set to 300° C. The film was formed by sputtering with a DC power of 0.5 kW applied.

[0476] In the sample 8, the silicon oxide film was formed by using a target containing silicon and a deposition gas of The oxygen gas was 50 sccm, the pressure was 0.4 Pa, the substrate temperature was 100°C, and The silicon oxide film was formed by sputtering with a power of 1.5 kW. contains more oxygen than is required for the stoichiometric composition, and some of the oxygen is released by heating. The silicon oxide film is

[0477] In addition, a sample (sample 9) in which an oxide semiconductor film having a thickness of 100 nm was formed on a silicon wafer was used. A silicon oxynitride film with a thickness of 100 nm was formed on a silicon wafer. A sample (sample 10) in which an oxide semiconductor film having a thickness of 100 nm was formed on the silicon oxynitride film ) was prepared.

[0478] In Samples 9 and 10, the oxide semiconductor film and the silicon oxynitride film were the same as those in Sample 8. In addition, in Samples 8 to 10, oxide semiconductor films were formed by the same method. After the formation, a heat treatment was performed at 450°C in a nitrogen and oxygen atmosphere. In the case of the SiO2 film, a silicon oxide film is formed and then heat treatment is performed at 300° C. in an oxygen atmosphere. Ta.

[0479] Next, HAXPES measurements were performed on Samples 8 to 10. This is a photoelectron spectroscopy method that uses hard X-rays (approximately 6 to 8 keV) as the excitation X-rays.

[0480] Figure 35 shows the valence band spectra obtained by HAXPES measurement for each sample. In FIG. 35, the horizontal axis represents binding energy. The vertical axis indicates the spectral intensity. The position of 0 eV on the horizontal axis indicates the acid The position on the horizontal axis where the value is around 3 eV corresponds to the conduction band of the oxide semiconductor film. This can be considered as the valence band of the film. In other words, the position from 0 eV to about 3 eV on the horizontal axis can be regarded as the energy gap of the oxide semiconductor film.

[0481] The intensity of the valence band spectrum is also increased by the For example, the presence of defect levels increases the intensity of the valence band spectrum. It becomes.

[0482] In addition, based on the principle of HAXPES measurement, the signal detected by HAXPES measurement is, This is considered to reflect defects near the surface of the sample. From the result of 0, the defect level generated in the energy gap of the oxide semiconductor film is It can be considered that this corresponds to defects present near the surface of the semiconductor film.

[0483] In the range of 0 eV to 3 eV on the horizontal axis of FIG. 35, the spectrum of sample 8 is larger than that of sample 9 and sample It was confirmed that the intensity of the spectrum was lower than that of the spectrum of 10. Therefore, like sample 8, the A silicon oxide film from which oxygen is partly released is provided in contact with the oxide semiconductor film, and heat treatment is performed. By this, the vicinity of the surface of the oxide semiconductor film (the interface between the oxide semiconductor film and the silicon oxide film) It was confirmed that the defects existing in the oxide semiconductor layer (near the oxide semiconductor layer) can be repaired. This can be considered to correspond to oxygen vacancies in the conductor film. A silicon oxide film from which a part of the oxide semiconductor film is released is provided in contact with the oxide semiconductor film, and heat treatment is performed. Therefore, it can be said that oxygen vacancies in the vicinity of the surface of the oxide semiconductor film can be repaired.

[0484] Here, a silicon oxide film is formed over an oxide semiconductor film by a sputtering method. However, the silicon oxide film contains more oxygen than the stoichiometric composition, and If the silicon oxide film is one in which part of the oxygen is released by heat, the oxygen formed by the plasma CVD method can be used. It is believed that defects existing near the surface of an oxide semiconductor film can be repaired even in a silicon oxide film. Therefore, the silicon oxide film formed by the method described in the present specification, such as the first embodiment, can be used. It can be considered that, if such a film is present, defects existing in the vicinity of the surface of the oxide semiconductor film can be repaired.

[0485] (Reference example 4) Here, an energy barrier between the source and drain of a transistor using an oxide semiconductor is Explain about the walls.

[0486] As the oxide semiconductor film to be a channel region, an intrinsic or substantially intrinsic oxide semiconductor film is used. In the case where the oxide semiconductor film is used, the energy of the oxide semiconductor film is The barrier is about half the energy gap between the pair of electrodes, the source and drain electrodes, and the oxide. However, in reality, the oxide semiconductor film is The transistor used has a Vg-Id characteristic in which the gate voltage increases from around 0 V to the drain voltage This suggests that there is a problem with this way of thinking, as currents begin to flow.

[0487] Therefore, as shown in FIG. 36(A), the gate insulating film GI and the oxide film on the gate insulating film GI are A semiconductor film OS and a source electrode S and a drain electrode D provided on the semiconductor film OS. A transistor having a structure having the above-mentioned structure was assumed, and the channel length (L) of the transistor was changed. The band structure in the dashed line H1-H2 in the case of the above case was derived by calculation. In the example shown in FIG. 1, the region of the oxide semiconductor film OS in contact with the source electrode S and the drain electrode D is made n-type. That is, the oxide semiconductor film OS has a low resistance region n and In this calculation, the oxide semiconductor The calculation was performed assuming that the film OS had a thickness of 35 nm and the gate insulating film GI had a thickness of 400 nm.

[0488] The band bending width can be estimated by solving the Poisson equation, and is given by , Debye screening length λ D It was found that the length is characterized by the Debye screening. Long λ D can be expressed as follows, where k B is the Boltzmann constant.

[0489]

number

[0490] In the above formula, the intrinsic carrier density n i 6.6×10 -9 cm - 3 The dielectric constant ε of the oxide semiconductor film OS is 15, and the temperature is 300 K. Shielding length λ D is 5.7 x 10 10 It was found that the value was very large, about 1 μm. The channel length is the Debye screening length λ D is twice as large as 1.14 × 10 11 Larger than μm In this case, the energy barrier between the low resistance region n and the intrinsic or substantially intrinsic region i is the oxide semiconductor. It can be seen that the energy gap is half that of the conductive film OS.

[0491] FIG. 37 shows the results for channel lengths of 0.03 μm, 0.3 μm, 1 μm, 10 μm, 100 μm, and 1×10 12 The calculation results of the band structure at 1 μm are shown. The potential of the in-electrode is fixed to GND (0 V). In FIG. 37, n is the low resistance region. The dashed line indicates the oxide region, i indicates the intrinsic or substantially intrinsic region between the low resistance regions, and the dashed line indicates the oxide region. The Fermi energy of the nitride semiconductor film is shown in Fig. 1, and the dashed line shows the mid gap of the oxide semiconductor film. vinegar.

[0492] From Figure 37, the channel length is sufficiently large, 1×10 12 In the case of μm, the low resistance region and the intrinsic or The difference in electron energy between the substantially intrinsic region and the energy gap of the oxide semiconductor film is However, as the channel length is reduced, the low resistance region gradually The difference in electron energy between the intrinsic or substantially intrinsic region becomes smaller, and the channel length becomes It was found that there is almost no energy barrier below 1 μm. The energy is fixed by a pair of electrodes, a source electrode and a drain electrode.

[0493] As mentioned above, when the channel length is small, the low resistance region and the intrinsic or substantially intrinsic It can be seen that the energy barrier between the regions is sufficiently small.

[0494] Here, when the channel length is small, the low resistance region and the intrinsic or substantially intrinsic region are separated. We consider why the energy barrier is sufficiently small.

[0495] A schematic diagram of an oxide semiconductor film and a band structure in the oxide semiconductor film are shown in FIG. FIG. 38A shows an intrinsic or substantially intrinsic region 601 and a low resistance region 602. The conduction band minimum E The channel length of the oxide semiconductor film 600 is denoted by L_0. In L_0>2λ D It is.

[0496] FIG. 38B shows an oxide semiconductor film having a shorter channel length than that shown in FIG. FIG. 38(B) shows a structure of an intrinsic or substantially intrinsic region 611 and a low resistance region 622. The bottom of the conduction band at the center of the channel length of the oxide semiconductor film 610 having the gates 612 and 613 Ec_1 is shown. The channel length of the oxide semiconductor film 610 is L_1. ) with channel length L_1 <L_0であり、L_1<2λ D It is. .

[0497] FIG. 38C shows that the channel is larger than that of the oxide semiconductor film shown in FIG. FIG. 38C shows an oxide semiconductor film having a short length and its band structure. An oxide semiconductor film 620 having a qualitatively intrinsic region 621 and low resistance regions 622 and 623. The conduction band minimum Ec_2 at the center of the channel length of the oxide semiconductor film 620 is also shown. The channel length is L_2. Channel length L_2 <L_1であり、L_2<<2λ D is .

[0498] In FIG. 38(A), the energy difference between the Fermi level Ef and the bottom of the conduction band Ec_0 is In Fig. 38(B), the Fermi level Ef and the bottom of the conduction band are The energy difference of Ec_1 is shown as the energy barrier ΔH_1. The energy difference between the Lummi level Ef and the bottom edge of the conduction band Ec_2 is denoted as the energy barrier ΔH_2.

[0499] In the oxide semiconductor film, a region in contact with a pair of electrodes becomes a low resistance region. The closer the junction between the intrinsic or substantially intrinsic region and the low resistance region, the lower the energy of the conduction band. As shown in FIG. 38(A), when the channel length L_0 is sufficiently large, In this case, the energy barrier ΔH_0 corresponds to Eg(band gap) / 2.

[0500] On the other hand, as shown in FIG. 38(B) and FIG. 38(C), when the channel length is reduced, the conduction The curved parts of the lower ends of the bands Ec_1 and Ec_2 overlap, so the energy barrier ΔH_1 In this way, the channel length becomes smaller. This results in a lowering of the conduction band edge in the intrinsic or substantially intrinsic region. In this specification, the CBL effect (Conduction Band Lowering E fect).

[0501] Next, in the structure shown in FIG. 36(A), a gate electrode GE is provided under the gate insulating film GI. Assuming a bottom-gate transistor, the channel length (L) of the transistor is The band structure at the dashed line H1-H2 when the change was made was derived by calculation. The structure of the transistor used in the calculation is shown in FIG. The calculation was performed assuming that the conductor film OS had a thickness of 35 nm and the gate insulating film GI had a thickness of 400 nm.

[0502] FIG. 39 shows the results of the transistor with the above structure, with the channel length set to 1 μm, 10 μm, and 50 μm. m, 100 μm, 1 × 10 5 μm and 1×10 12 The calculation results of the band structure at μm However, the potentials of the source electrode, drain electrode, and gate electrode are fixed to GND (0 V). Note that in FIG. 39, n indicates a low-resistance region, and i indicates a region , an intrinsic or substantially intrinsic region sandwiched between low resistance regions, and the dashed dotted line indicates an oxide semiconductor The Fermi energy of the film is shown, and the dashed line indicates the mid gap of the oxide semiconductor film.

[0503] The band structure shown in FIG. 39 is similar to the calculation performed for the structure shown in FIG. This is the result obtained by calculation. However, if a gate electrode is provided as in the structure of FIG. 36(B), In the case of a channel length (L) of more than 1 μm, the low resistance region and the intrinsic or real The energy barrier to the qualitatively intrinsic region is approximately constant and does not depend on the channel length (L). It can be seen that it becomes a value.

[0504] FIG. 40 shows the relationship between the channel length (L length) and the energy of each of the structures shown in FIG. 36(A) and FIG. 36(B). This indicates the height of the energy barrier.

[0505] As shown in FIG. 40, in the structure of FIG. 36(A) in which a gate electrode is not provided, the channel length is large. As the channel length increases, the energy barrier height increases monotonically, reaching 1×10 12 μm In some cases, the energy gap is half that of the oxide semiconductor film (1.6 eV). On the other hand, in the structure of FIG. 36(B) in which a gate electrode is provided, the channel length is longer than 1 μm. It can be seen that the energy barrier height does not depend on the channel length even when the channel length is not large.

[0506] From the above, the transistor using an intrinsic or substantially intrinsic oxide semiconductor film has a CBL As a result, the energy barrier becomes smaller than half the energy gap of the oxide semiconductor film. Therefore, the drain current starts to flow when the gate voltage is close to 0V in the Vg-Id characteristic. In addition, the transistors with a channel length larger than a certain value (1 μm) The energy barrier of the FET is a constant value independent of the channel length. In general, a transistor using an intrinsic oxide semiconductor film has a gate voltage It can be considered that drain current begins to flow around 0V.

[0507] The multilayer film included in the transistor according to one embodiment of the present invention is an intrinsic or substantially intrinsic oxide. Since the multilayered film has a semiconductor film, the transistor has a gate-type Vg-Id characteristic. It can be considered that the drain current starts to flow when the base voltage is around 0V.

Claims

[Claim 1] A gate electrode; a gate insulating film on the gate electrode; a multilayer film on the gate insulating film; a source electrode and a drain electrode on the multilayer film; an oxide insulating film on the source electrode and the drain electrode; the multilayer film includes an oxide semiconductor film and an oxide film, the oxide semiconductor film contains indium, zinc, and gallium; the oxide film contains indium, zinc, and gallium; the energy level of the lower end of the conduction band of the oxide film is closer to a vacuum level than the energy level of the lower end of the conduction band of the oxide semiconductor film.

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