Manufacturing method for semiconductor device

Abstract

To provide a manufacturing method for a semiconductor device that can improve the characteristics.SOLUTION: A manufacturing method for a semiconductor device according to an embodiment includes forming a first metal layer including a first metal element on a first surface of a structure including a substrate including SiC and including the first surface. The manufacturing method includes injecting a first element including at least one selected from the group consisting of He, Ne, Ar, Kr, Xe, Rn, and Si into the first surface through the first metal layer. The manufacturing method includes irradiating the first surface with a laser through the first metal layer after the injection.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] An embodiment of the present invention relates to a method for manufacturing a semiconductor device. [Background technology]

[0002] It is desirable to improve the characteristics of semiconductor devices. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2023-40706 A Summary of the Invention [Problem to be solved by the invention]

[0004] The embodiments provide a method for manufacturing a semiconductor device capable of improving characteristics. [Means for solving the problem]

[0005] According to an embodiment, a method for manufacturing a semiconductor device includes forming a first metal layer including a first metal element on a first surface of a structure including a substrate including SiC and including a first surface. The manufacturing method includes injecting a first element including at least one selected from the group consisting of He, Ne, Ar, Kr, Xe, Rn, Si, N, P, As, B, Al, and Ga into the first surface through the first metal layer. The manufacturing method includes, after the injection, irradiating the first surface with a laser through the first metal layer. [Brief description of the drawings]

[0006] [Figure 1] FIG. 1 is a flowchart illustrating the method for manufacturing a semiconductor device according to the first embodiment. [Diagram 2] 2A to 2C are schematic cross-sectional views illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Diagram 3]3A to 3C are schematic cross-sectional views illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 4] 4A to 4C are schematic cross-sectional views illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Diagram 5] 5A to 5C are schematic cross-sectional views illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 6] 6A to 6C are schematic cross-sectional views illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 7] 7A to 7C are schematic cross-sectional views illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 8] 8A to 8C are schematic cross-sectional views illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 9] FIG. 9 is a flowchart illustrating the method for manufacturing the semiconductor device according to the second embodiment. [Figure 10] 10A to 10C are schematic cross-sectional views illustrating the method for manufacturing the semiconductor device according to the second embodiment. [Figure 11] 11A to 11C are schematic cross-sectional views illustrating the method for manufacturing the semiconductor device according to the second embodiment. [Figure 12] 12A to 12C are schematic cross-sectional views illustrating the method for manufacturing the semiconductor device according to the second embodiment. [Figure 13] 13A to 13C are schematic cross-sectional views illustrating the method for manufacturing the semiconductor device according to the second embodiment. [Figure 14] 14A to 14C are schematic cross-sectional views illustrating the method for manufacturing the semiconductor device according to the second embodiment. [Figure 15] FIG. 15 is a schematic cross-sectional view illustrating the semiconductor device according to the third embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Hereinafter, embodiments of the present invention will be described with reference to the drawings. The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between parts, etc. are not necessarily the same as those in reality. Even when the same part is shown, the dimensions and ratios of each part may be different depending on the drawing. In this specification and each drawing, elements similar to those described above with reference to the previous drawings are given the same reference numerals and detailed descriptions thereof will be omitted as appropriate.

[0008] (First embodiment) FIG. 1 is a flowchart illustrating the method for manufacturing a semiconductor device according to the first embodiment. 2 to 8 are schematic cross-sectional views illustrating the method for manufacturing the semiconductor device according to the first embodiment. 1 and 2, for example, a structure 18 is prepared (step S105). As shown in FIG. 2, the structure 18 includes a substrate 15. The substrate 15 may be, for example, a semiconductor substrate. The substrate 15 includes SiC. The substrate 15 includes a first surface 15a. The substrate 15 may be, for example, at least a portion of a SiC wafer.

[0009] 1 and 2, a first metal layer 61 is formed on the first surface 15a of the structure 18 (step S110). The first metal layer 61 includes a first metal element.

[0010] 1 and 3, a first element 81 is implanted into the first surface 15a through the first metal layer 61 (step S120). The first element 81 includes, for example, at least one selected from the group consisting of He, Ne, Ar, Kr, Xe, Rn, Si, N, P, As, B, Al, and Ga. The first element 81 may include, for example, at least one selected from the group consisting of He, Ne, Ar, Kr, Xe, Rn, and Si. The implantation is, for example, ion implantation. For example, ions of the first element 81 are implanted.

[0011] 1 and 5, after the implantation, a laser 80L is irradiated onto the first face 15a through the first metal layer 61 (step S130). For example, laser annealing is performed. As a result, a silicide layer 61S is formed from at least a portion of the first metal layer 61, as shown in FIG.

[0012] In the embodiment, after the first metal layer 61 is formed, the first element 81 is injected through the first metal layer 61. This allows a stable low-resistance ohmic contact to be obtained. This is believed to be because the injection of the first element 81 causes a part of the first metal element contained in the first metal layer 61 to be introduced into the substrate 15. For example, it is believed that a knock-on phenomenon occurs.

[0013] For example, the first metal element is relatively uniformly and stably introduced near the first surface 15a of the substrate 15. As a result, a mixed layer (a mixed region 15M described later) having a high reaction rate of the silicide reaction is uniformly formed. The highly reactive mixed layer is efficiently silicided by subsequent annealing by laser irradiation. As a result, a uniform silicide layer 61S is stably formed. As a result, low electrical resistance is obtained. High flatness is obtained. For example, high flatness and low electrical resistance are obtained. According to the embodiment, a manufacturing method for a semiconductor device capable of improving characteristics is provided. For example, a highly flat silicide layer 61S is obtained. The surface morphology can be improved.

[0014] In the embodiment, after the first element 81 is injected through the first metal layer 61, laser annealing is performed. This allows a stable silicide layer 61S to be obtained even by low-power laser irradiation. For example, a laser 80L with a low energy density can be applied. This allows the efficiency of the laser irradiation process to be improved. For example, a high throughput can be obtained. For example, energy consumption can be reduced.

[0015] 2, the substrate 15 may include a second surface 15b. In addition to the substrate 15, the structure 18 may include a semiconductor layer 10. The structure 18 may include a conductive layer 50 and an insulating member 40.

[0016] For example, the semiconductor layer 10 is provided between the substrate 15 and the insulating member 40. The conductive layer 50 is provided between the semiconductor layer 10 and the insulating member 40. The conductive layer 50 may be, for example, an electrode layer. The insulating member 40 is, for example, a passivation layer. The second surface 15b is between the semiconductor layer 10 and the first surface 15a. The first surface 15a corresponds to, for example, a surface on which an ohmic electrode is provided. For example, the semiconductor layer 10 includes SiC.

[0017] For example, at least a portion of the semiconductor layer 10 may be epitaxially grown on a base (SiC wafer) that will become the substrate 15. A conductive layer 50 and an insulating member 40 may be formed on the semiconductor layer 10. After this, the base may be thinned. For example, a process such as grinding may be performed. Thus, preparation of the structure 18 (step S105) may include thinning the thickness of the base that will become the substrate 15.

[0018] 2 and 3, during the implantation of the first element 81, the structure 18 may be fixed to a support member 60. This increases the mechanical strength and allows for stable processing.

[0019] 3 and 4, the mixed region 15M is formed by the injection of the first element 81. The mixed region 15M includes, for example, Si, C, and a first metal element. For example, the injection of the first element 81 may include moving a portion of the first metal element to a region including the first surface 15a of the substrate 15. For example, the injection of the first element 81 forms the mixed region 15M in the region including the first surface 15a of the substrate 15. The formation of the mixed region 15M is due to the knock-on phenomenon, as described above.

[0020] The first metal element includes at least one selected from the group consisting of, for example, Ti, Co, Ni, Mo, Ta, W, and Pt. A mixed region 15M including such a first metal element, Si, and carbon is formed. For example, the first metal element is uniformly introduced in the vicinity of the first surface 15a. The mixed region 15M may further include a first element 81. Ti, Co, Ni, Mo, Ta, W, and Pt can react with Si to form a silicide.

[0021] As shown in FIG. 5, the first metal layer 61 and the mixed region 15M are irradiated with a laser 80L. As a result, a silicide layer 61S is formed as shown in FIG. 6. In this manner, the irradiation includes forming the silicide layer 61S from the first metal layer 61. After the silicide layer 61S is formed, the mixed region 15M may remain. At least a portion of the mixed region 15M may be amorphous. At least a portion of the mixed region 15M may include crystals (including polycrystals).

[0022] In the embodiment, the thickness of the first metal layer 61 is preferably 10 nm or more and 100 nm or less. If the thickness of the first metal layer 61 is excessively thin, for example, it is difficult to obtain a uniform silicide layer 61S. If the thickness of the first metal layer 61 is excessively thick, for example, the energy becomes excessively large in the injection of the first element 81 and / or the laser irradiation.

[0023] In the embodiment, the first element 81 may include at least one selected from the group consisting of Ar, B, P, and As. This makes it easier to form the mixed region 15M with an appropriate thickness. The compatibility with other processes is good. For example, an ion implantation device used for imparting electrical conductivity may be used.

[0024] The implantation of the first element 81 may include implantation of a first metallic element.

[0025] In the embodiment, the first element 81 may include Si. For example, a Si-rich mixed region 15M is obtained. For example, silicon can be easily introduced into the first metal layer 61. This allows a uniform silicide layer 61S to be efficiently formed. For example, a portion of silicon is introduced into the first metal layer 61. This forms a region in which the substrate 15, the region formed by knock-on, and the region where silicon is implanted into the first metal layer 61 are continuous with each other.

[0026] 1 and 7, after irradiation with the laser 80L, a first conductive layer 51 may be formed on the silicide layer 61S (step S140). The first conductive layer 51 functions as, for example, an electrode. The first conductive layer 51 may include, for example, a metal such as aluminum, copper, or gold. The first conductive layer 51 makes ohmic contact with the substrate 15 with low resistance via the silicide layer 61S.

[0027] As shown in FIG. 1, between the implantation (step S120) and the irradiation (step S130), a second metal layer 62 (see FIG. 8) may be formed (step S125). As shown in FIG. 8, the second metal layer 62 is formed on the first metal layer 61. The second metal layer 62 includes a second metal element. The second metal element may include at least one selected from the group consisting of Ti, Co, Ni, Mo, Ta, W, and Pt, for example. The second metal element may be the same as or different from the first metal element.

[0028] For example, a thin first metal layer 61 is formed, and then the first element 81 is injected. This efficiently forms the desired mixed region 15M. Then, the second metal layer 62 is formed. By irradiating the laser, the silicide layer 61S can be efficiently formed from the first metal layer 61 and the second metal layer 62. The silicide layer 61S of the desired thickness can be stably formed.

[0029] The second metal element may be the same as the first metal element, or the second metal element may be different from the first metal element.

[0030] As already described, the structure 18 may further include a semiconductor layer 10 containing SiC. By providing the semiconductor layer 10, higher quality can be obtained. The semiconductor layer 10 is an epitaxially grown layer. In the embodiment, laser irradiation is performed to form the silicide layer 61S. This allows the target region (the region including the first metal layer 61 and the mixed region 15M) to be locally and effectively heated. Damage to the surface device structure (semiconductor layer 10 and conductive layer 50) is suppressed. The temperature of the surface device structure (semiconductor layer 10 and conductive layer 50) that is increased by the laser irradiation is, for example, 50°C or higher and 1000°C or lower. The temperature may be, for example, 100°C or lower.

[0031] In an embodiment, the power of the laser 80L is, for example, 1.0 J / cm 2 More than 3.0J / cm 2 The following is the reason: Good ohmic contact can be obtained while suppressing damage to the surface device structure (the semiconductor layer 10 and the conductive layer 50).

[0032] Second embodiment FIG. 9 is a flowchart illustrating the method for manufacturing the semiconductor device according to the second embodiment. 10 to 14 are schematic cross-sectional views illustrating the method for manufacturing the semiconductor device according to the second embodiment. 9, in the second embodiment, after the implantation (step S210), the formation of the first metal layer 61 (step S220) is performed. Then, the irradiation of the laser 80L (step S230) is performed. Except for the order of such steps, the configuration described in relation to the first embodiment may be applied to the second embodiment.

[0033] For example, as shown in Fig. 10, for example, a structure 18 is prepared (step S105). As shown in Fig. 10, the structure 18 includes a substrate 15. The substrate 15 includes SiC. The substrate 15 includes a first surface 15a.

[0034] 10, a metal element 85 for implantation is implanted into the first surface 15a of the structure 18 (step S210). The metal element 85 for implantation includes at least one selected from the group consisting of, for example, Ti, Co, Ni, Mo, Ta, W, and Pt.

[0035] 11, a mixed region 15M is formed in the vicinity of the first surface 15a by implanting the metal element 85. The mixed region 15M is a region that includes the first surface 15a. The mixed region 15M includes Si, C, and the metal element 85 to be implanted.

[0036] As shown in Fig. 12, after the implantation, a first metal layer 61 containing a first metal element is formed on the first surface 15a (step S220). As shown in Fig. 13, a laser 80L is irradiated onto the first surface 15a through the first metal layer 61 (step S230).

[0037] In the second embodiment, the mixed region 15M is formed by injecting the metal element 85 before the formation of the first metal layer 61. The mixed region 15M can be efficiently formed by injecting the metal element 85 with low energy. The mixed region 15M including the metal element 85 and the first metal layer 61 including the first metal element are irradiated with the laser 80L to efficiently form the silicide layer 61S. At least a part of the silicide layer 61S may be formed from at least a part of the first metal layer 61. A part of the silicide layer 61S may be formed from at least a part of the mixed region 15M. In this manner, the irradiation of the laser 80L (step S230) may include forming at least a part of the silicide layer 61S from the first metal layer 61.

[0038] For example, a first reference example is conceivable in which the first metal layer 61 is formed after implanting Ar ions or the like, and then laser irradiation is performed. In the first reference example, an amorphous region is formed by implanting Ar ions or the like. This allows the formation of silicide by a low-power laser 80L. However, in the first reference example, a mixed region 15M is not formed. In the first reference example, in the silicide reaction, metal elements are supplied only from the first metal layer 61 formed on the surface. The reaction region is only in the vicinity of the first metal layer 61. For this reason, for example, there is a limit to the reduction in electrical resistance.

[0039] In contrast to this, in the embodiment, the mixed region 15M is formed by injecting the metal element 85. Thereafter, the first metal layer 61 is formed, and then the laser 80L is irradiated. The mixed region 15M and the first metal layer 61 are irradiated with the laser 80L to form a silicide layer 61S. The mixed region 15M functions as, for example, a transition region. When the silicide layer 61S is formed, stress and the like are alleviated. For example, the silicide layer 61S can be efficiently formed while maintaining good film quality. For example, good morphology is obtained. For example, a surface with good flatness is obtained.

[0040] As shown in FIGS. 9 and 14, after irradiation with the laser 80L (step S230), a first conductive layer 51 may be formed on the silicide layer 61S.

[0041] In the second embodiment, the first metal element includes at least one selected from the group consisting of Ti, Co, Ni, Mo, Ta, W, and Pt. In the second embodiment, the thickness of the first metal layer 61 may be 10 nm or more and 500 nm or less. In the second embodiment, the structure 18 may further include a semiconductor layer 10 including SiC. In the second embodiment, the structure 18 may include a conductive layer 50 and an insulating member 40.

[0042] In the first and second embodiments, after the laser irradiation or after the formation of the first conductive layer 51, the structure 18 may be separated from the support member 60. This results in a semiconductor device.

[0043] Third embodiment The third embodiment relates to a semiconductor device. FIG. 15 is a schematic cross-sectional view illustrating the semiconductor device according to the third embodiment. As shown in FIG. 15, the semiconductor device 110 according to the embodiment includes a first conductive layer 51, a semiconductor layer 10, a substrate 15, a silicide layer 61S, and a mixed region 15M. The semiconductor layer 10 includes SiC, and the substrate 15 includes SiC. The substrate 15 is provided between the first conductive layer 51 and the semiconductor layer 10. The silicide layer 61S is provided between the first conductive layer 51 and the substrate 15. The silicide layer 61S includes a first metal element and silicon. The mixed region 15M is provided between the silicide layer 61S and the substrate 15. The mixed region 15M includes a first metal element, silicon, and carbon.

[0044] The first metal element includes at least one selected from the group consisting of Ti, Co, Ni, Mo, Ta, W, and Pt. A good ohmic contact is obtained between the first conductive layer 51 and the substrate 15. A low electrical resistance is obtained. For example, a low on-resistance is obtained.

[0045] 15, in this example, the semiconductor device 110 includes a second conductive layer 52 and a third conductive layer 53. The semiconductor layer 10 includes a first semiconductor region 11, a second semiconductor region 12, a third semiconductor region 13, and a fourth semiconductor region 14. A first direction D1 from the first conductive layer 51 to the second conductive layer 52 is defined as the Z-axis direction. A direction perpendicular to the Z-axis direction is defined as the X-axis direction. A direction perpendicular to the Z-axis direction and the X-axis direction is defined as the Y-axis direction.

[0046] The first semiconductor region 11 has a first conductivity type (e.g., n-type). The first semiconductor region 11 includes a first partial region 11a, a second partial region 11b, and a third partial region 11c. A second direction D2 from the first partial region 11a to the second partial region 11b intersects with the first direction D1. The second direction D2 may be the X-axis direction. The third partial region 11c is provided between the first partial region 11a and the third conductive layer 53 in the first direction D1.

[0047] The second semiconductor region 12 is of a second conductivity type (e.g., p-type). The third semiconductor region 13 is of a first conductivity type. The fourth semiconductor region 14 is of a second conductivity type. The impurity concentration of the first conductivity type in the third semiconductor region 13 is higher than the impurity concentration of the first conductivity type in the first semiconductor region 11. The impurity concentration of the second conductivity type in the fourth semiconductor region 14 is higher than the impurity concentration of the second conductivity type in the second semiconductor region 12.

[0048] A part 12p of the second semiconductor region 12 is between the second partial region 11b and the third semiconductor region 13 in the first direction D1. The other part 12q of the second semiconductor region 12 is between the third partial region 11c and the fourth semiconductor region 14 in the second direction D2. The third semiconductor region 13 is between the other part 12q of the second semiconductor region 12 and the fourth semiconductor region 14 in the second direction D2.

[0049] The second conductive layer 52 is electrically connected to the third semiconductor region 13 and the fourth semiconductor region 14. The insulating member 40 may include a first insulating region 41 and a second insulating region 42. At least a portion of the first insulating region 41 is provided between the third partial region 11c and the third conductive layer 53. The second conductive layer 52 is provided between the semiconductor layer 10 and the second insulating region 42. The third conductive layer 53 may extend along a third direction D3 intersecting a plane including the first direction D1 and the second direction D2. The third direction D3 may be, for example, the Y-axis direction.

[0050] The current flowing between the first conductive layer 51 and the second conductive layer 52 can be controlled by the potential of the third conductive layer 53. The semiconductor device 110 is, for example, a transistor. The first conductive layer 51 may be, for example, a drain electrode. The second conductive layer 52 may be, for example, a source electrode. The third conductive layer 53 may be, for example, a gate electrode.

[0051] The semiconductor device 110 according to the embodiment may be, for example, a diode. The first conductive layer 51 may be any electrode layer. In the semiconductor device 110 according to the embodiment, good ohmic contact is obtained. A semiconductor device with improved characteristics can be provided. For example, low electrical resistance is obtained. For example, high flatness is obtained. For example, high flatness and low electrical resistance are obtained.

[0052] In embodiments, for example, substrate 15 may include at least one selected from the group consisting of 4H-SiC, 6H-SiC, and 3C-SiC.

[0053] For example, the impurities of the first conductivity type include at least one selected from the group consisting of N, P, and As. For example, the impurities of the second conductivity type include at least one selected from the group consisting of B, Al, and Ga.

[0054] In an embodiment, information regarding the length and thickness is obtained by observation using an electron microscope, etc. Information regarding the composition of the material is obtained by secondary ion mass spectrometry (SIMS) or energy dispersive X-ray spectroscopy (EDX), etc.

[0055] The embodiments may include the following technical solutions. (Technical proposal 1) forming a first metal layer including a first metal element on a first surface of a structure including a substrate including SiC and including a first surface; Injecting a first element including at least one selected from the group consisting of He, Ne, Ar, Kr, Xe, Rn, Si, N, P, As, B, Al, and Ga into the first surface through the first metal layer; After the implantation, the first surface is irradiated with a laser through the first metal layer.

[0056] (Technical proposal 2) The method for manufacturing a semiconductor device described in Technical Proposal 1, wherein the implantation includes moving a portion of the first metal element to a region including the first surface of the substrate.

[0057] (Technical proposal 3) the implantation forms a mixed region in a region of the substrate that includes the first surface; A method for manufacturing a semiconductor device described in Technical Proposal 1, wherein the mixed region contains Si, C and the first metal element.

[0058] (Technical proposal 4) The method for manufacturing a semiconductor device described in Technical Proposal 2 or 3, wherein the first metal element includes at least one selected from the group consisting of Ti, Co, Ni, Mo, W, Ta and Pt.

[0059] (Technical proposal 5) 5. The method for manufacturing a semiconductor device according to any one of Technical Schemes 2 to 4, wherein the first element includes at least one selected from the group consisting of Ar, B, P, and As.

[0060] (Technical proposal 6) 5. The method for manufacturing a semiconductor device according to any one of Technical Schemes 2 to 4, wherein the first element includes Si.

[0061] (Technical proposal 7) The method for manufacturing a semiconductor device according to any one of Technical Schemes 2 to 6, wherein the irradiation includes forming a silicide layer from the first metal layer.

[0062] (Technical proposal 8) The method for manufacturing a semiconductor device according to Technical Solution 7, further comprising forming a first conductive layer on the silicide layer after the irradiation.

[0063] (Technical proposal 9) The method for manufacturing a semiconductor device according to any one of Technical Schemes 1 to 8, wherein the first metal layer has a thickness of 10 nm or more and 100 nm or less.

[0064] (Technical proposal 10) The method for manufacturing a semiconductor device according to any one of Technical Schemes 1 to 9, further comprising forming a second metal layer containing a second metal element on the first metal layer between the implantation and the irradiation.

[0065] (Technical proposal 11) The method for manufacturing a semiconductor device according to Technical Proposal 10, wherein the second metal element is the same as the first metal element.

[0066] (Technical proposal 12) The structure further includes a semiconductor layer including SiC, the substrate further comprises a second surface; The method for manufacturing a semiconductor device according to any one of Technical Solutions 1 to 11, wherein the second surface is between the first surface and the semiconductor layer.

[0067] (Technical proposal 13) The method for manufacturing a semiconductor device described in Technical Proposal 12, wherein the temperature of the semiconductor layer increased by the irradiation is 100°C or less.

[0068] (Technical proposal 14) Injecting a metal element for injection into a structure including a substrate including SiC and including a first surface, the first surface; forming a first metal layer on the first surface after the implantation, the first metal layer including a first metal element; A method for manufacturing a semiconductor device, comprising: irradiating the first surface with a laser through the first metal layer.

[0069] (Technical proposal 15) the implantation includes forming an intermixed region in a portion of the substrate; the mixed region includes the first surface, The method for manufacturing a semiconductor device described in Technical Proposal 14, wherein the mixed region contains Si, C, and the metal element for injection.

[0070] (Technical proposal 16) The method for manufacturing a semiconductor device according to Technical Scheme 14 or 15, wherein the metal element for injection includes at least one selected from the group consisting of Ti, Co, Ni, Mo, Ta, W, and Pt.

[0071] (Technical proposal 17) 17. The method for manufacturing a semiconductor device according to any one of Technical Schemes 14 to 16, wherein the first metal element includes at least one selected from the group consisting of Ti, Co, Ni, Mo, Ta, W, and Pt.

[0072] (Technical proposal 18) The method for manufacturing a semiconductor device according to any one of Technical Schemes 14 to 17, wherein the irradiation includes forming a silicide layer from the first metal layer.

[0073] (Technical proposal 19) providing said structure; 19. The method for manufacturing a semiconductor device according to any one of Technical Schemes 1 to 18, wherein the preparation of the structure includes reducing the thickness of a base body that becomes the substrate.

[0074] (Technical proposal 20) A first conductive layer; A semiconductor layer including SiC; a substrate including SiC provided between the first conductive layer and the semiconductor layer; a silicide layer including a first metal element and silicon provided between the first conductive layer and the substrate; a mixed region including the first metal element, silicon, and carbon, the mixed region being provided between the silicide layer and the substrate; A semiconductor device comprising:

[0075] According to the embodiment, it is possible to provide a method for manufacturing a semiconductor device capable of improving characteristics.

[0076] The above describes the embodiments of the present invention with reference to specific examples. However, the present invention is not limited to these specific examples. For example, the specific configurations of each element, such as a substrate, a semiconductor layer, and a silicide layer, included in a semiconductor device or structure are included in the scope of the present invention as long as a person skilled in the art can implement the present invention in a similar manner and obtain similar effects by appropriately selecting from the known range.

[0077] Furthermore, any combination of two or more elements of each of the specific examples, within the scope of technical feasibility, is also included within the scope of the present invention as long as it includes the gist of the present invention.

[0078] In addition, all semiconductor device manufacturing methods that can be implemented by a person skilled in the art by making appropriate design modifications based on the semiconductor device manufacturing method described above as an embodiment of the present invention also fall within the scope of the present invention as long as they include the gist of the present invention.

[0079] In addition, within the scope of the concept of the present invention, a person skilled in the art may conceive of various modifications and alterations, and it will be understood that these modifications and alterations also fall within the scope of the present invention.

[0080] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0081] 10: semiconductor layer, 11-14: first to fourth semiconductor regions, 11a-11c: first to third partial regions, 12p: part, 12q: other part, 15: substrate, 15M: mixed region, 15a, 15b: first and second surfaces, 18: structure, 40: insulating member, 41, 42: first and second insulating regions, 50: conductive layer, 51-53: first to third conductive layers, 60: support member, 61, 62: first and second metal layers, 61S: silicide layer, 80L: laser, 81: first element, 85: metal element, 110: semiconductor device, D1-D3: first to third directions

Claims

1. forming a first metal layer including a first metal element on a first surface of a structure including a substrate including SiC and including a first surface; Injecting a first element including at least one selected from the group consisting of He, Ne, Ar, Kr, Xe, Rn, Si, N, P, As, B, Al, and Ga into the first surface through the first metal layer; After the implantation, the first surface is irradiated with a laser through the first metal layer.

2. 2. The method of claim 1, wherein the implantation includes moving a portion of the first metal element to a region of the substrate that includes the first surface.

3. the implantation forms a mixed region in a region of the substrate that includes the first surface; The method for manufacturing a semiconductor device according to claim 1 , wherein the mixed region contains Si, C and the first metallic element.

4. 3. The method of claim 2, wherein the first metal element includes at least one selected from the group consisting of Ti, Co, Ni, Mo, Ta, W, and Pt.

5. 3. The method for manufacturing a semiconductor device according to claim 2, wherein the first element includes at least one selected from the group consisting of Ar, B, P, and As.

6. The method for manufacturing a semiconductor device according to claim 2 , wherein the first element includes Si.

7. 7. The method for manufacturing a semiconductor device according to claim 1, further comprising the step of forming a second metal layer containing a second metal element on the first metal layer between the implantation and the irradiation.

8. Injecting a metal element for implantation into a structure including a substrate including SiC and including a first surface, the first surface being forming a first metal layer on the first surface after the implantation, the first metal layer including a first metal element; A method for manufacturing a semiconductor device, comprising: irradiating the first surface with a laser through the first metal layer.

9. the implantation includes forming an intermixed region in a portion of the substrate; the mixed region includes the first surface, The method for manufacturing a semiconductor device according to claim 8 , wherein the mixed region contains Si, C and the metal element for implantation.

10. 9. The method of claim 8, wherein the metal element for implantation includes at least one selected from the group consisting of Ti, Co, Ni, Mo, Ta, W, and Pt.

11. 11. The method for manufacturing a semiconductor device according to claim 8, wherein the first metal element includes at least one selected from the group consisting of Ti, Co, Ni, Mo, Ta, W, and Pt.

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