Pecvd method and apparatus

Abstract

To reduce a degree of bowing warpage of a semiconductor substrate.SOLUTION: Provided is a method of depositing a silicon nitride on a semiconductor substrate by a plasma enhanced chemical vapor deposition (PECVD), a structure including a semiconductor substrate, and a plasma enhanced chemical vapor deposition apparatus (PECVD) for depositing a silicon nitride on the semiconductor substrate by PECVD.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a plasma enhanced chemical vapor deposition (PECVD) method, in particular to a method for depositing silicon nitride on a semiconductor substrate by PECVD. The present invention also relates to an associated PECVD apparatus. Furthermore, the present invention relates to a structure comprising a semiconductor substrate with a silicon nitride deposition layer. [Background technology]

[0002] Keeping a semiconductor substrate relatively flat during processing is an important consideration. This is due in part to patterning requirements, but is also necessitated by the nature of the automated processes used to handle the substrate. As material is added to and removed from the substrate and it undergoes thermal cycling, stresses can build up in the substrate, causing it to deform. This problem is exacerbated after the wafer thinning step, as the stresses of the deposited layers on the substrate cause larger deformations as the substrate is reduced in thickness.

[0003] As is known, alternating layers of SiN and SiO are used in device fabrication to balance the stress of layers used in applications (e.g. 3D memory). The purpose of alternating compressive and tensile stress layers is to balance the total stress of many layers, potentially more than 128 layers. Alternatively, the stress balancing effect can be achieved by depositing materials on both sides of the substrate. This can be achieved by conventional physical vapor deposition (PVD), chemical vapor deposition (CVD) or PECVD deposition. Compressive or tensile stress on one side of the substrate can be balanced by an equal compressive or tensile stress on the other side of the substrate.

[0004] Highly stressed layers are highly undesirable because they are prone to cracking and particle generation, which can lead to defects and reliability concerns, therefore careful consideration of material deposition techniques and processes is essential when using stress control layers.

[0005] Typically, the front side of a semiconductor substrate is processed to create a number of desired structures. The front side is sometimes called the "device side" because the structures typically provide the desired functionality. After processing, the semiconductor substrate is typically divided into a number of devices by one of many known processes. In many cases, the structures on the device side are delicate, and the risk of damaging the structures means that touching the device side in the vicinity of the structures, such as performing further processing steps to reduce the stress to which the substrate is subjected, cannot be done. However, the stress can create substrate warp, which, if significant, can make it impossible to process the substrate without incurring a mishandling event in the substrate transfer system and modules. Recovery from mishandling often involves damaged parts and venting the system to the atmosphere for cleaning and reconditioning. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] U.S. Patent No. 6,774,059 Summary of the Invention [Problem to be solved by the invention]

[0007] The present invention, and at least some of its embodiments, seeks to address at least some of the problems and needs described above. In particular, the present invention uses a process that does not require contact with structures formed on the front side of a semiconductor substrate to reduce the stress to which the semiconductor substrate is subjected, thereby reducing the degree of bowing of the semiconductor substrate. [Means for solving the problem]

[0008] According to a first aspect of the present invention there is provided a method of depositing silicon nitride on a semiconductor substrate by plasma enhanced chemical vapor deposition (PECVD), comprising the steps of: providing a semiconductor substrate having a front and a back surface, the front surface having a central region having one or more structures formed thereon and an edge region surrounding the central region; placing a front side of the semiconductor substrate on a substrate support within a chamber, the substrate support contacting only an edge region of the front side of the semiconductor substrate; depositing a silicon nitride layer stack by PECVD on the rear surface of the semiconductor substrate, the silicon nitride layer stack comprising at least four silicon nitride layers alternating between tensile layers subjected to tensile stress and compressive layers subjected to compressive stress; It is a method having the following structure.

[0009] The silicon nitride layer stack may include at least eight silicon nitride layers. The silicon nitride layer stack may have a thickness of 3 μm or more. The silicon nitride layer stack may have a thickness of 5 μm or more. Each of the silicon nitride layers may have a thickness, and the thickness of the tensile layer may be greater than the thickness of the compressive layer. The tensile layer may be at least twice as thick as the compressive layer. The tensile layer may be at least four times as thick as the majority of the compressive layer. The tensile layer may have a thickness within the range of 0.5 to 2.7 μm.

[0010] In depositing silicon nitride layer stacks by PECVD, nitrogen, hydrogen, ammonia and silane can be used as precursors. Other precursor mixtures can also be used to deposit the SiN layers.

[0011] Before the step of depositing the silicon nitride layer stack, the semiconductor substrate may have a concave bow when viewed from the front side. By depositing the silicon nitride layer stack, the concave bow of the semiconductor substrate can be reduced. The concave bow of the semiconductor substrate can be reduced to less than 100 μm. The concave bow of the semiconductor substrate can be reduced to approximately 20 μm.

[0012] The step of depositing a silicon nitride layer stack on the rear surface of a semiconductor substrate by PECVD can be performed using a capacitively coupled parallel plate PECVD process. At least one gas inlet can be provided for introducing a gas or gas mixture into the chamber, and the semiconductor substrate can be positioned on a substrate support with the rear surface facing the at least one gas inlet. In one embodiment, the PECVD plasma is prevented from contacting the front surface of the semiconductor substrate during the step of depositing a silicon nitride layer stack on the rear surface of the semiconductor substrate by PECVD. The semiconductor substrate can have a periphery, and the substrate support can contact an edge region of the front surface of the semiconductor substrate only within an area of ​​3 mm or less inside the periphery.

[0013] The semiconductor substrate may be a silicon substrate.The semiconductor substrate may be a semiconductor wafer.

[0014] According to a second aspect of the present invention there is provided a method for producing a composition comprising the steps of: a semiconductor substrate having a front side and a back side, the front side comprising a central region and an edge region surrounding the central region; one or more structures formed on a central region of a front side of the semiconductor substrate; a silicon nitride layer stack deposited on the rear surface of the semiconductor substrate, the silicon nitride layer stack comprising at least four silicon nitride layers alternating between tensile layers subjected to tensile stress and compressive layers subjected to compressive stress; The structure is provided with:

[0015] The structure of the second aspect of the invention may be produced by the method according to the first aspect of the invention.

[0016] According to a third aspect of the present invention there is provided a plasma enhanced chemical vapour deposition (PECVD) apparatus for depositing silicon nitride on a semiconductor substrate by PECVD using a method according to the first aspect of the present invention, comprising: A chamber; a substrate support disposed within the chamber for supporting a substrate, the substrate support contacting only an edge region of the substrate; at least one gas inlet for introducing a gas or gas mixture into the chamber; a plasma device for generating and maintaining a plasma within the chamber; a controller configured to control the apparatus to deposit a silicon nitride layer stack on the semiconductor substrate by PECVD, the silicon nitride layer stack comprising at least four silicon nitride layers with alternating tensile layers subjected to a tensile stress and compressive layers subjected to a compressive stress; The device comprises:

[0017] The plasma device may include at least one power supply configured to provide an RF power signal to the at least one gas inlet.

[0018] For the avoidance of doubt, reference is made throughout this application to the terms "comprising" or "having" and similar terms, but for purposes of interpretation of the invention, more restrictive terms such as "consisting of" and "consisting essentially of" are also encompassed.

[0019] The invention as set forth above extends to any and all inventive combinations of the features set forth above or in the following description, drawings or claims. For example, any feature disclosed in connection with the first aspect of the invention may be combined with any feature disclosed in connection with the second aspect of the invention, and vice versa. Embodiments of the invention will now be described, by way of example only, with reference to the accompanying drawings in which: [Brief description of the drawings]

[0020] [Figure 1] FIG. 1 is a schematic cross-sectional view of a PECVD apparatus. [Diagram 2] 4 is a cross-sectional view of an edge of a substrate support. [Diagram 3] FIG. 1 shows a semiconductor substrate having a bow. [Figure 4] FIG. 13 shows the stress and wafer bow for various thicknesses of a single SiN layer. [Diagram 5] FIG. 2 is a schematic diagram of a substrate having a tension-compression alternating SiN layer stack. [Figure 6] FIG. 1 shows the bow of a single tensile SiN layer and the bow of a stack of SiN layers. [Figure 7] FIG. 13 shows the stress and wafer bow for various thicknesses of the SiN stack. [Figure 8] FIG. 13 shows deflection maps taken from the stress gauge a) before and b) after SiN stack deposition. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0021] FIG. 1 shows a PECVD apparatus 1 that can be used with the present invention to process a semiconductor substrate 2. The semiconductor substrate 2 can be a silicon wafer or other suitable substrate, with structures already formed on a central region of its front surface. The semiconductor substrate 2 is supported on a substrate support 3, 4. In this example, the substrate support essentially comprises a conventional wafer platen 3, to which a metallic wafer carrier 4 is attached. The wafer carrier 4 defines a central cavity having a diameter smaller than that of the substrate 2. When the substrate to be processed is in wafer form and has a diameter in the range of 150-300 mm, the diameter of the central cavity can be 6 mm smaller than that of the wafer. The substrate 2 is handled through a transfer system by an edge grip end effector (not shown) and placed in the center of the substrate support 3, 4 with its front surface (device surface) facing downwards, i.e., towards the substrate support 3, 4. The substrate 2 is held in place by several ceramic pins 5 located approximately 0.5 mm from the edge of the substrate 2. The wafer carrier 4 ensures that the substrate 2 is only contacted at its edge region, i.e. the peripheral region surrounding the central region in which the structures are located. This edge region can be associated with the so-called "edge exclusion" region, i.e. a peripheral band that typically extends from the edge of the wafer radially inwardly of the edge of the wafer with an inner diameter of about 2-3 mm.

[0022] The provision of the wafer carrier 4 avoids damage to the front side of the substrate 2, which would occur if a substrate with delicate structures on its front side were placed on a conventional wafer support 3 without a wafer carrier. Such damage would eventually result in yield loss and is highly undesirable. Contacting the substrate at its edge area allows the substrate to be handled safely and avoids damage to active and / or useful areas on the front side of the wafer.

[0023] Further components of the PECVD apparatus 1 of Figure 1 will now be described. Precursor process gases pass through gas lines 6, 7 and valves 8, 9 into showerhead gas inlet 10 where they expand and pass through optional gas distribution plate 11 before entering process chamber 14 through a group of small openings 12 in the front of showerhead 10. Exhaust gases are removed through openings 13 by a pumping system (not shown). Process pressure in chamber 14 is monitored and maintained by controlling gas flow and pumping speed. In use, a plasma is generated using RF power. RF power is provided by a high frequency (typically 13.56 MHz) RF source 15 and associated matching unit 16, and a low frequency (typically 380 kHz) RF source 17 and associated matching unit 18. A controller 19 controls the operation of the PECVD apparatus.

[0024] The substrate supports 3, 4 are grounded and use resistive heating to control the substrate temperature. The chamber 14 is also grounded and is made of aluminum or stainless steel. The showerhead 10 is made of aluminum and is isolated from the chamber 14 by a ceramic break. A gap of less than 0.7 mm is used to avoid unwanted plasma generation between the surface of the wafer carrier 4 and the front surface of the substrate 2. At the operating pressures and RF powers typically employed in normal use, this provides an effective dark space gap. Thus, deposition near the central cavity and on the front surface of the substrate 2 is avoided.

[0025] FIG. 2 shows an adapter arrangement that can be used with a conventional wafer platen. In FIG. 2, the substrate 20 is in an elevated position on edge lift pins 22, with a central cavity 24 visible below the substrate 20. In FIG. 2, the wafer carrier 26 and wafer platen 28 extend beyond the edge of the substrate 20 because the chamber being used can accommodate wafers up to 300 mm in diameter. The adapter shown in FIG. 2 is for a 150 mm diameter wafer, but it will be appreciated that the invention is not limited to substrates of any particular size or shape. Apparatus suitable for carrying out the method of the invention includes an adapted SPTS® Delta PECVD system with edge contact adapter hardware, commercially available from SPTS Technologies Limited, Newport, South Wales, UK. All of the examples described below were carried out using this apparatus. Other PECVD systems may also be used, such as other capacitively coupled parallel plate PECVD systems.

[0026] Since physical contact is made exclusively on the periphery of the substrate, RF coupling to the substrate and heat transfer from the wafer support are reduced compared to conventional wafer supporters. This in turn modifies the properties of the deposited layers. High tensile SiN deposition using edge contact hardware is more difficult than conventional full contact because non-uniform plasma coupling tends to result in brittle layers with lower crack initiation thresholds than can be achieved using conventional flat supporters. The inventors of the present invention have exploited these different operating conditions to provide improved PECVD deposited SiN layers. Despite these difficulties, the inventors of the present invention have devised a way to reduce the concave warp of the substrate using a stacked SiN-PECVD deposition process, thereby achieving acceptable total stress and acceptable bow. In certain examples, concave warp of more than 300 μm can be reduced to an acceptable bow of less than 100 μm. According to the invention, a silicon nitride layer stack is deposited by PECVD on the rear side of a semiconductor substrate, the silicon nitride layer stack comprising at least four silicon nitride layers with alternating tensile layers subjected to tensile stress and compressive layers subjected to compressive stress, which allows deposition to be performed up to larger thicknesses and to compensate for larger wafer bows while preserving the integrity of structures formed on the front side of the substrate.

[0027] 3 shows a schematic representation of a wafer 30 that, due to previous process steps, is concave when viewed from its front (device) side 30a, i.e., the side that carries certain structures. The term "concave" is used herein to describe the appearance of a semiconductor substrate when viewed from its front side, as shown in FIG 3. A SiN layer stack is deposited by PECVD on the rear side 30b of the wafer 30.

[0028] [example] Two types of 150 mm diameter silicon test wafers were used: very fine (flat) and concave with warp >300 μm. Wafer thickness was nominally 675 μm.

[0029] The PECVD-SiN film is not a pure Si3N4 layer, but contains significant amounts of H, potentially more than 10 at%, and would be more accurately described as Si x N y H z Or SiN:H.

[0030] Highly tensile stress films were deposited using the following parameters displayed in Table 1. [Table 1]

[0031] This resulted in the film properties displayed in Table 2. [Table 2]

[0032] The positive and negative signs next to the bow measurements in Tables 2 and 4 indicate an increase and decrease in bow deformation, respectively.

[0033] In Figure 4, wafer bow (μm) and stress (MPa) are plotted against SiN thickness (Angstroms) on silicon wafers using edge contact hardware with the process conditions film listed above. As is well known, as thickness increases beyond a certain value, the film begins to crack. The area below the dashed line (representing stress and marked with a black dashed line) is the region where the film shows no signs of cracking, beyond which crack initiation is observed. Cracking occurs at thicknesses greater than about 2.7 μm, at which a stress of +436 MPa results in only a bow of about 150 μm.

[0034] The crack initiation threshold is improved by depositing a stack of thin compressive and thick tensile SiN films (repeated until the desired thickness and bow condition is reached), thus reducing the very high total tensile stress of the SiN stack. This allows a significant increase in deposition thickness above the crack initiation threshold expected for a single tensile SiN layer at that stress. An O2 plasma treatment was used prior to the thin compressive SiN as an adhesion promoter. This process has been found to eliminate organic contamination and thus result in a better layer interface. The process parameters for the compressive film are given below in Table 3. [Table 3]

[0035] The film properties of the compressed SiN films can be found in Table 4. [Table 4]

[0036] The stack structure used can be seen in Figure 5 and the bow values ​​of the single tensile SiN film and stack are displayed in Figure 6. Tensile SiN layers 52 of 1 μm thickness and compressive SiN layers 53 of 200 nm thickness are alternated on the substrate 51 until the desired thickness and / or wafer bow requirements are achieved.

[0037] The final compressive SiN layer 54 is 400 nm thick instead of 200 nm thick, providing an effective protective layer over the outermost tensile layer 52. The thickness can be varied to achieve the required bow compensation. A tensile to compressive layer thickness ratio of about 5:1 has been found to give excellent results, with a maximum thickness of 2.5 μm at 400 MPa.

[0038] As can be seen in FIG. 6, the SiN stack thickness can be greater than 6 μm, resulting in a bow of about 250 μm without cracking, whereas a single SiN layer cracks at a thickness of about 2.7 μm.

[0039] FIG. 6 shows the wafer bow measured with a stress gauge (FLX 3300LR) at various thicknesses. The bulk tensile SiN membrane exhibits a larger wafer bow than the alternating compressive and tensile SiN layer stack because the total bow of the stack is the sum of all of its layers, while the bow of the compressive layers is opposite to the bow of the tensile layers. The critical thickness of 2.7 μm is also marked on the graph, i.e. the point at which microcrack initiation is observed on the wafer for bulk SiN. It is worth noting that crack initiation at that thickness is only observed under a microscope, and thus the crack initiation threshold for bulk SiN is below 2.7 μm. Since the wafer bow is directly related to the thickness, further increasing the stack thickness increases the wafer bow almost linearly, which is consistent with a wide range of end conditions. The bow and stress values ​​for the SiN stack structure can be seen in FIG. 7.

[0040] FIG. 8 shows deflection maps obtained with the stress gauge, a) before the stack deposition with a bow of 238 μm and b) after the SiN stack deposition where the bow has been successfully reduced to about 20 μm without cracking.

[0041] Both tensile and compressive PECVD-SiN layers were deposited in the same process chamber, although in principle these steps could also be performed in separate chambers, or even in a multi-wafer chamber.

Claims

1. 1. A method for depositing silicon nitride on a semiconductor substrate by plasma enhanced chemical vapor deposition (PECVD), comprising: providing a semiconductor substrate having a front side and a back side, the front side having a central region having one or more structures formed thereon and an edge region surrounding the central region; placing the front side of the semiconductor substrate on a substrate support within a chamber, the substrate support contacting only the edge region of the front side of the semiconductor substrate; depositing a silicon nitride layer stack on the rear surface of the semiconductor substrate by PECVD, the silicon nitride layer stack comprising at least four silicon nitride layers alternating tensile layers subjected to tensile stress and compressive layers subjected to compressive stress; The method according to claim 1,

2. 10. The method of claim 1, wherein the silicon nitride layer stack comprises at least eight silicon nitride layers.

3. 3. The method according to claim 1 or 2, wherein the silicon nitride layer stack has a thickness of 3 μm or more.

4. 4. The method of claim 3, wherein the silicon nitride layer stack has a thickness of 5 μm or greater.

5. 5. The method of claim 1, wherein each of the silicon nitride layers has a thickness, the thickness of the tensile layer being greater than the thickness of the compressive layer.

6. The method according to any one of claims 1 to 5, wherein the tensile layer is at least twice as thick as the compressive layer.

7. The method according to any one of claims 1 to 6, wherein the tensile layer is at least four times thicker than the majority of the compressive layer.

8. The method according to any one of claims 1 to 7, wherein the thickness of the tensile layer is in the range of 0.5 to 2.7 μm.

9. The method according to any one of claims 1 to 8, wherein the silicon nitride layer stack is deposited by PECVD using nitrogen, hydrogen, ammonia and silane as precursors.

10. 10. The method according to claim 1, wherein, prior to the step of depositing the silicon nitride layer stack, when viewed on the front side of the semiconductor substrate, the semiconductor substrate exhibits a concave bow.

11. The method of any one of claims 1 to 10, wherein the step of depositing the silicon nitride layer stack on the rear surface of the semiconductor substrate by PECVD is performed using a capacitively coupled parallel plate PECVD process.

12. 12. The method according to claim 1, further comprising providing at least one gas inlet for introducing a gas or a mixture of gases into the chamber, and positioning the semiconductor substrate on the substrate support with the rear surface facing towards the at least one gas inlet.

13. 13. The method of claim 1, wherein during the step of depositing a silicon nitride layer stack on the rear surface of the semiconductor substrate by PECVD, a plasma associated with the PECVD is not allowed to contact the front surface of the semiconductor substrate.

14. 14. The method of claim 1, wherein the semiconductor substrate has a periphery, and the substrate support contacts the edge region of the front side of the semiconductor substrate only within an area no greater than 3 mm inside the periphery.

15. A structure comprising: a semiconductor substrate having a front side and a back side, the front side comprising a central region and an edge region surrounding the central region; one or more structures formed on the central region of the front side of the semiconductor substrate; a silicon nitride layer stack deposited on the rear surface of the semiconductor substrate, the silicon nitride layer stack comprising at least four silicon nitride layers alternating between tensile layers subjected to tensile stress and compressive layers subjected to compressive stress; A structure comprising:

16. 16. A structure according to claim 15, produced using a method according to claim 1.

17. 10. A plasma enhanced chemical vapor deposition (PECVD) apparatus for depositing silicon nitride on a semiconductor substrate by PECVD using the method of claim 1, comprising: A chamber; a substrate support disposed within the chamber for supporting a substrate, the substrate support contacting only an edge region of the substrate; at least one gas inlet for introducing a gas or gas mixture into the chamber; a plasma device for generating and maintaining a plasma within the chamber; a controller configured to control the apparatus to deposit a silicon nitride layer stack on the semiconductor substrate by PECVD, the silicon nitride layer stack comprising at least four silicon nitride layers with alternating tensile layers subjected to a tensile stress and compressive layers subjected to a compressive stress; An apparatus comprising:

18. 20. The plasma enhanced chemical vapor deposition (PECVD) apparatus of claim 17, wherein the plasma apparatus comprises at least one power supply configured to provide an RF power signal to the at least one gas inlet.

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