Communication device and communication control method

Abstract

To provide a communication device and a communication control method that are capable of continuing synchronization with the same synchronization source in a synchronization system even when a reset without interruption occurs in the communication device.SOLUTION: A communication device according to one embodiment of the present disclosure is applicable to a synchronization system having a plurality of communication devices that exchange control packets related to synchronization control via a network. The communication device includes a control unit configured to be capable of a reset without interruption, which resets without stopping packet forwarding, and the control unit performs synchronization control by sending and receiving control packets. The communication device further includes a packet forwarding unit that immediately forwards control packets received from a synchronization source port to another synchronization port during the period of the reset without interruption of the control unit.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to a communication device and a communication control method. [Background technology]

[0002] Synchronous Ethernet (Ethernet is a registered trademark) technology is a technology for establishing synchronization on a packet network. For example, ITU-T G.8264 / Y.1364 (see Non-Patent Document 1) specifies the Ethernet Synchronization Message Channel (ESMC). ESMC is an interface that transmits the quality of a distributed clock, and devices communicate the quality of their own synchronization sources by exchanging packets called ESMC protocol data units (PDUs). Each device selects the clock with the best quality among the clocks received at an ESMC-enabled port as its own synchronization source. This enables high-quality synchronization of clock frequencies throughout the entire synchronization system.

[0003] Time synchronization, which is a synchronization method for matching absolute times, has also been proposed as a technology for establishing synchronization on a packet network. For example, PTP (Precision Time Protocol) is a communication protocol used to synchronize clocks across an entire network (see Non-Patent Documents 2 and 3). In PTP, each device performing synchronization has the role of master and slave. Each device exchanges PTP packets with time information attached to them. The slave calculates the delay between devices and the clock difference between the master and slave based on the transmission and reception times of the PTP packets, and synchronizes the slave's time with the master's. [Prior art documents] [Non-patent literature]

[0004] [Non-Patent Document 1] ITU-T G.8264 / Y.1364 Amendment 1, [online], March 2018, [Retrieved May 10, 2023], Internet <URL:https: / / www.itu.int / rec / dologin_pub.asp?lang=e&id=T-REC-G.8264-201803-I!Amd1!PDF-E&type=items> [Non-Patent Document 2] "Standardization Trends of High-Precision Time and Frequency Synchronization Technology for the Realization of 5G Mobile Networks", NTT Technical Journal, [online], November 2018, [Retrieved May 19, 2023], Internet<URL:https: / / journal.ntt.co.jp / wp-content / uploads / 2020 / 06 / JN20181144.pdf> [Non-Patent Document 3] "Development of high-precision time synchronization network equipment for the introduction of 3.5GHz band TD-LTE", NTT DOCOMO Technical Journal Vol. 24 No. 2, [online], 2016, [Retrieved May 19, 2023], Internet <URL:https: / / www.docomo.ne.jp / binary / pdf / corporate / technology / rd / technical_journal / bn / vol24_2 / vol24_2_006jp.pdf> Summary of the Invention [Problem to be solved by the invention]

[0005] For example, in order to avoid interrupting the provision of services, it is sometimes necessary to reset a communication device while maintaining the communication function of the main signal. Such a reset is hereinafter referred to as an "uninterrupted reset."

[0006] Normally, an uninterruptible reset is performed by a software reset of the control unit of the communication device. However, if the ESMC or PTP protocol processing is performed by software, the communication device cannot perform the ESMC or PTP protocol processing during the software reset.

[0007] In the synchronization control, the communication device transmits and receives control packets for the purpose of keeping alive the protocol processing. During a software reset, the communication device cannot transmit or receive control packets, so a timeout may occur in the reception of the control packets in a downstream communication device relative to the communication device. In the downstream communication device, if a timeout occurs in the reception of the control packets, a switching of the synchronization source occurs. However, since the communication device cannot keep up with the switching of the synchronization source during a software reset, it cannot inform other communication devices that the synchronization source has been switched in the downstream communication device. Therefore, a software reset of the communication device may not guarantee that the entire synchronization system is synchronized to one synchronization source.

[0008] An object of the present disclosure is to provide a communication device and a communication control method that enable continued synchronization with the same synchronization source in a synchronous system even if an uninterrupted reset occurs in the communication device in the synchronous system. [Means for solving the problem]

[0009] The communication device disclosed herein is a communication device applicable to a synchronization system having a plurality of communication devices that exchange control packets related to synchronization control via a network, and the communication device is equipped with a control unit configured to perform an uninterruptible reset that resets the communication device without stopping packet forwarding, the control unit performs synchronization control by sending and receiving control packets, and the communication device further includes a packet forwarding unit that immediately forwards control packets received from a synchronization source port to another synchronization port during the period of uninterruptible reset of the control unit. Effect of the Invention

[0010] According to the present disclosure, even if an uninterrupted reset occurs in a communication device in a synchronous system, synchronization with the same synchronization source can be continued in the synchronous system. [Brief description of the drawings]

[0011] [Figure 1] FIG. 1 is a diagram showing the configuration of a synchronization system including a communication device according to a first embodiment, and the internal configuration of the communication device. [Diagram 2] FIG. 2 is a diagram for explaining the operation of the synchronization system according to the first embodiment in a normal state. [Diagram 3] FIG. 3 is a diagram showing the format of the ESMC PDU according to ITU-T G.8264. [Figure 4] FIG. 4 is a diagram showing the format of the QL data. [Diagram 5] FIG. 5 shows an excerpt of the SSM Code. [Figure 6] FIG. 6 is a diagram illustrating a problem that may arise due to a software reset of a network element. [Figure 7] FIG. 7 is a diagram for explaining the synchronization control immediately before a reset according to the first embodiment. [Figure 8] FIG. 8 is a diagram illustrating synchronous control during a reset of the CPU in the first embodiment. [Figure 9] FIG. 9 is a sequence diagram of an uninterruptible reset executed in the communication device according to the first embodiment. [Figure 10] FIG. 10 is a sequence diagram illustrating a startup process after an uninterruptible reset executed in the communication device according to the first embodiment. [Figure 11] FIG. 11 is a sequence diagram illustrating a startup process after a normal reset, which is executed in the communication device according to the first embodiment. [Figure 12]FIG. 12 is a diagram showing a configuration for transferring an ESMC PDU indicating that the QL of the clock is DNU during an uninterruptible reset of the protocol processor. [Figure 13] FIG. 13 is a diagram showing the configuration of a synchronization system including a communication device according to the second embodiment, and the internal configuration of the communication device. [Figure 14] FIG. 14 is a diagram illustrating the operation of the synchronization system according to the second embodiment in a normal state. [Figure 15] FIG. 15 is a diagram showing the format of the Announce message defined in IEEE 1588-2008 (PTP V2). [Figure 16] FIG. 16 is a sequence diagram showing communication based on PTP. [Figure 17] FIG. 17 is a diagram illustrating the synchronization control immediately before a reset according to the second embodiment. [Figure 18] FIG. 18 is a diagram illustrating synchronous control during a CPU reset in the second embodiment. [Figure 19] FIG. 19 is a sequence diagram of an uninterruptible reset executed in a communication device according to the second embodiment. [Figure 20] FIG. 20 is a sequence diagram illustrating a startup process after an uninterruptible reset executed in a communication device according to the second embodiment. [Figure 21] FIG. 21 is a sequence diagram illustrating a start-up process after a normal reset executed in a communication device according to the second embodiment. [Figure 22] FIG. 22 is a diagram showing the configuration of a synchronization system including a communication device according to the third embodiment, and the internal configuration of the communication device. [Figure 23] FIG. 23 is a sequence diagram of an uninterruptible reset executed in a communication device according to the third embodiment. [Figure 24] FIG. 24 is a sequence diagram illustrating a startup process after an uninterruptible reset executed in a communication device according to the third embodiment. [Diagram 25]FIG. 25 is a sequence diagram illustrating a start-up process after a normal reset executed in a communication device according to the third embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] [Description of the embodiments of the present disclosure] First, the embodiments of the present disclosure will be listed and described.

[0013] (1) A communication device according to one embodiment of the present disclosure is a communication device applicable to a synchronization system having a plurality of communication devices that exchange control packets related to synchronization control via a network, the communication device comprising a control unit configured to perform an uninterruptible reset that resets the communication device without stopping packet forwarding, the control unit performs synchronization control by sending and receiving control packets, and the communication device further comprises a packet forwarding unit that immediately forwards control packets received from a synchronization source port to another synchronization port during the uninterruptible reset period.

[0014] According to the above configuration, even during an uninterruptible reset, a control packet is immediately transferred from a synchronization source port to another synchronization port, so that a timeout can be prevented from occurring in a communication device that receives the control packet. Therefore, even if an uninterruptible reset occurs in a communication device, the synchronous system can continue to synchronize with the same synchronization source.

[0015] (2) In the communication device described in (1) above, prior to the uninterruptible reset, the control unit sets a forwarding rule for the packet forwarding unit so that the packet forwarding unit forwards a control packet received from a port that is a synchronization source to another synchronization port, and after the uninterruptible reset, the forwarding rule for the packet forwarding unit is restored to the forwarding rule before the uninterruptible reset.

[0016] According to the above configuration, after an uninterruptible reset, the transfer rules of control packets in the communication device are restored to the rules before the uninterruptible reset, so that the synchronization system can continue to synchronize with the same synchronization source even after the uninterruptible reset state.

[0017] (3) The communication device described in (2) above further includes a memory unit, and prior to executing an uninterruptible reset of the control unit, the control unit writes reset information indicating whether the reset of the control unit corresponds to an uninterruptible reset into the memory unit, and upon startup after the reset, checks the reset information to determine whether the reset of the control unit was an uninterruptible reset or a normal reset.

[0018] In addition to an uninterruptible reset, a normal reset may be considered as a reset of the control unit. In the case of a normal reset, packet forwarding by the packet forwarding unit may be stopped. When the control unit is reset, the control unit cannot determine whether the reset was an uninterruptible reset or a normal reset. According to the above configuration, the control unit can determine whether the reset of the control unit was an uninterruptible reset by checking the reset information written in the storage unit.

[0019] (4) In the communication device according to any one of (1) to (3) above, the control unit is configured to execute protocol processing in accordance with a protocol relating to synchronization control and settings in the packet forwarding unit by software processing.

[0020] For example, the uninterrupted reset is executed when updating the software of the control unit. According to the above configuration, in the synchronization system, when updating the software of the control unit, the software can be updated while maintaining synchronization among the multiple communication devices.

[0021] (5) In a communication device described in any one of (1) to (4) above, the protocol processing includes a time synchronization process according to PTP, the control packet includes a message for notifying a time synchronization source of the time synchronization, and the communication device further includes a clock unit that is the target of time synchronization according to PTP.

[0022] According to the above configuration, it is possible to execute an uninterrupted reset of the communication device while continuing time synchronization according to the PTP.

[0023] (6) In a communication device described in any one of (1) to (4) above, the protocol processing includes frequency synchronization processing according to ESMC, the control packet includes information indicating a quality level of a clock that can be a frequency synchronization source for the synchronization control, and the protocol processing unit selects, as the frequency synchronization source, a clock from a clock source having the highest clock quality level among multiple clock supply sources in accordance with the information indicating the quality level of the control packet.

[0024] According to the above configuration, it is possible to execute an uninterrupted reset of the communication device while continuing frequency synchronization according to the ESMC protocol.

[0025] (7) In the communication device described in (6) above, when the packet forwarding unit receives a control packet from another synchronization port indicating that a clock supplied from a source other than the frequency synchronization source among multiple sources will not be used during an uninterrupted reset, the packet forwarding unit forwards the control packet to the port from which the synchronization originates.

[0026] According to the above configuration, it is possible to prevent the upstream communication device from detecting the ESMC timeout.

[0027] (8) In the communication device described in (5) above, the protocol processing includes time synchronization processing according to PTP, the control packet includes a packet for notifying the time indicated by a synchronization source of the time synchronization, and the communication device further includes a clock unit that generates a clock to be subject to time synchronization according to PTP, and during an uninterrupted reset of the control unit, the clock unit synchronizes the frequency of the clock generated by the clock unit to the frequency of the synchronization source selected by the protocol processing unit.

[0028] According to the above configuration, even if time correction by exchanging PTP messages is not possible during an uninterruptible reset, an increase in the time error of the PTP clock can be suppressed.

[0029] (9) A communication control method according to one embodiment of the present disclosure is a communication control method by a communication device applicable to a synchronous system having a plurality of communication devices exchanging control packets related to synchronization control via a network, wherein the communication devices are configured to be capable of performing an uninterruptible reset that resets the communication devices without stopping packet forwarding, and the communication control method includes the steps of performing synchronization control by sending and receiving control packets, performing an uninterruptible reset, and immediately forwarding, during the period of the uninterruptible reset, the control packets received by the communication devices via the network from a synchronization source port to another synchronization port.

[0030] According to the above configuration, even during an uninterruptible reset, the control packet is immediately transferred from the synchronization source port to another synchronization port, so that it is possible to prevent a timeout from occurring in the communication device receiving the control packet. Therefore, even if an uninterruptible reset occurs in the communication device, the synchronous system can continue to synchronize with the same synchronization source.

[0031] [Details of the embodiment of the present disclosure] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. In the drawings, the same or corresponding parts are designated by the same reference characters and their description will not be repeated.

[0032] <First embodiment> 1 is a diagram showing a configuration of a synchronization system including a communication device according to a first embodiment, and an internal configuration of the communication device. In the first embodiment, a synchronization system 100 is a synchronization system that realizes frequency synchronization by ESMC.

[0033] The synchronization system 100 includes network elements 101 to 103 as a plurality of communication devices that exchange control packets related to synchronization control via a network. In Fig. 1, the network elements 101 to 103 are represented as "NE1", "NE2", and "NE3", respectively.

[0034] The network element 102 is realized by a communication device according to the first embodiment. The network element 102 is connected to the network elements 101 and 103 via a network (not shown). The network elements 101 and 103 are supplied with a reference clock CL1 and a reference clock CL2, respectively. The network element 103 is not limited to being directly connected to the network element 102. A network element that is frequency-synchronized without a reference clock (i.e., a network element that operates similarly to the network element 102) may be connected between the network elements 102 and 103 via a network.

[0035] The network element 102 includes a CPU 10, a memory 21, a synchronization source selection unit 22, a reset cause holding unit 23, a transmission / reception unit 24, a switch unit 25, reception units 31 and 41, and transmission units 32 and .

[0036] The CPU 10 executes synchronization control by continuously transmitting and receiving an ESMC PDU, which is a control packet, and further sets a transfer rule for transfer of the ESMC PDU inside the network element 102.

[0037] The CPU 10 is a control unit that is subject to the uninterruptible reset. The CPU 10 is configured to include a protocol processing unit 11 and a management processing unit 12 by executing software processing. This software is stored in a non-volatile manner in the memory 21 and is read out from the memory 21 by the CPU 10. The software may be stored in the memory 21 in advance. When updating the software, the updated software may be provided to the network element 102 through the network and stored in the memory 21.

[0038] The protocol processor 11 performs protocol processing of the ESMC. The protocol processor 11 selects a port that has the best quality of the clock recovered from the received signal by exchanging ESMC PDUs with each of the network elements 101 and 103. The protocol processor 11 sets the selected port in the synchronization source selector 22.

[0039] The management processing unit 12 loads parameters required for protocol processing by the protocol processing unit 11 into the memory 21. Furthermore, the management processing unit 12 exchanges information with the management server 1 via the transmission / reception unit 24 and the switch unit 25. The management server 1 executes setting of the configuration of the network element 102 and control of the network element 102 from the outside. Specifically, the management server 1 executes setting related to SyncE-enabled ports, that is, which ports are set as ports for which SyncE (Synchronous Ethernet) is enabled, in response to a user operation. Furthermore, the management server 1 executes a command for uninterrupted reset of the network element 102 in response to a user operation.

[0040] In the example shown in Fig. 1, the transceiver 24 is not set as a SyncE-enabled port, and is therefore not divided into a transmitter and a receiver. Therefore, in Fig. 1, the port that transmits and receives information with the management server 1 is simply described as the "transmitter / receiver."

[0041] The management processor 12 sets a transfer rule in the switch unit 25 according to the setting from the management server 1. When the management processor 12 receives an uninterruptible reset command from the management server 1, it sets a transfer rule (described later) for ESMC PDU in the switch unit 25. After completing the uninterruptible reset, the management processor 12 deletes the transfer rule.

[0042] When an uninterruptible reset of the CPU 10 occurs, before the reset, the management processing unit 12 writes information indicating that the reset cause is an uninterruptible reset to the reset cause holding unit 23. The reset cause holding unit 23 is a storage unit realized by hardware, and can typically be realized by a register of an FPGA (Field Programmable Gate Array). Therefore, even if the CPU 10 is reset, the contents held in the reset cause holding unit 23 are held in a non-volatile manner.

[0043] When starting up after resetting the CPU 10, the management processing unit 12 refers to the reset cause holding unit 23 to determine whether the reset is an uninterruptible reset or a normal start. Specifically, the management processing unit 12 determines the cause of the reset by reading information indicating an uninterruptible reset from the reset cause holding unit 23. This information may be information (e.g., a flag) indicating that the reset cause is an uninterruptible reset.

[0044] The setting of the transfer rule in the switch unit 25 may be executed by the protocol processing unit 11. In such an embodiment, the protocol processing unit 11 performs the process of setting the transfer rule in accordance with the contents that the management processing unit 12 has loaded in the memory 21. Furthermore, the protocol processing unit 11 may delete the transfer rule after an uninterruptible reset.

[0045] The memory 21 is used for expanding parameters by the management processing unit 12. The memory 21 may also be used for expanding commands by the management processing unit 12.

[0046] Furthermore, the memory 21 is used by the protocol processor 11 to save data necessary for protocol processing before the uninterruptible reset. This data is stored in a non-volatile area of ​​the memory 21. After the uninterruptible reset, the protocol processor 11 reads the data stored in the memory 21 and restores the state of the network element 102 to the state before the uninterruptible reset. This restores the clock selection port, the contents of the received ESMC PDU, and the like, making it possible to realize protocol processing that takes over the state before the reset.

[0047] The synchronization source selection unit 22 receives an input of a clock recovered by the receiving unit of each SyncE-enabled port, and outputs the recovered clock of the selected port set by the protocol processing unit 11 to the transmitting unit of each SyncE-enabled port. The synchronization source selection unit 22 is realized by hardware.

[0048] Each of the receivers 31 and 41 is realized by hardware. The receivers 31 and 41 receive signals from the network elements 101 and 103, respectively, and recover a clock from the received signals. The receivers 31 and 41 output the recovered clock to the synchronization source selector 22. The receivers 31 and 41 further receive ESMC PDUs and user traffic (main signals) from the network elements 101 and 103, respectively.

[0049] Each of the transmitters 32, 42 is realized by hardware. Each of the transmitters 32, 42 transmits a signal such as user traffic (main signal) using the clock selected by the synchronization source selection unit 22. Furthermore, each of the transmitters 32, 42 transmits an ESMC PDU.

[0050] The switch unit 25 is a packet forwarding unit that forwards the ESMC PDU and other traffic including user traffic according to the forwarding rules and relay rules such as L2 set by the management processing unit 12. The switch unit 25 is implemented by hardware. Normally, the switch unit 25 forwards the received ESMC PDU to the CPU 10 (protocol processing unit 11). During an uninterruptible reset, the switch unit 25 immediately forwards the ESMC PDU received from the selected port (synchronization port) to a port that requires the ESMC PDU (i.e., another synchronization port that is a SyncE-enabled port other than the selected port). "Immediately" refers to a state in which the switch unit 25 forwards the received ESMC PDU without determining the timing of forwarding the ESMC PDU by itself. The switch unit 25 discards the ESMC PDU received from a port other than the selected port.

[0051] 2 is a diagram for explaining the operation of the synchronization system according to the first embodiment in a normal state. In the synchronization system 100, a reference clock CL1 is supplied to a network element 101. The network element 101 synchronizes a signal to be transmitted from the network element 101 with the reference clock CL1, and transmits the signal to the network element 102. Furthermore, the network element 101 conveys the quality of the clock transmitted by the signal transmitted from the network element 101 to the network element 102 by an ESMC PDU. Note that, as will be described in detail later, the ESMC PDU stores an SSM (Synchronization Status Message) code indicating the quality of the clock to be transmitted.

[0052] Similar to the network element 101, a reference clock CL2 is provided to the network element 103. The network element 103 synchronizes a signal to be transmitted from the network element 103 with the reference clock CL2 and transmits the signal to the network element 102. Furthermore, the network element 103 conveys the quality of the clock carried by the signal transmitted from the network element 101 to the network element 102 by means of an ESMC PDU.

[0053] The receiving unit 31 of the network element 102 receives a signal and an ESMC PDU from the network element 101. The receiving unit 31 recovers a clock from the signal received from the network element 101 and transfers the recovered clock, clock C11, to the synchronization source selection unit 22. The receiving unit 31 further transfers a control packet P11, which is an ESMC PDU received from the network element 101, to the switching unit 25. The switching unit 25 transfers the control packet P11 to the protocol processing unit 11 of the CPU 10 in accordance with a transfer rule.

[0054] Similarly, the receiving unit 41 of the network element 102 receives the signal and ESMC PDU transmitted from the network element 103 via the transmission path. The receiving unit 41 recovers a clock from the signal received from the network element 103 and transfers the recovered clock, clock C21, to the synchronization source selecting unit 22. The receiving unit 41 further transfers a control packet P21, which is an ESMC PDU received from the network element 103, to the switching unit 25. The switching unit 25 transfers the control packet P21 to the protocol processing unit 11 of the CPU 10 in accordance with the transfer rules.

[0055] Based on the control packets P11 and P21, the protocol processing unit 11 selects which of the clocks C11 and C21 to synchronize the transmission clock used for transmission from the network element 102. In the example of FIG. 2, when the quality levels (Quality Levels; QL) of the clocks C11 and C21 are both PRC (Primary Reference Clock), the protocol processing unit 11 selects one of the clocks C11 and C21 as the synchronization source according to the priority of the clock receiving port (corresponding to the receiving units 31 and 41). The protocol processing unit 11 sets the selection result indicating which of the clocks C11 and C21 has been selected as the synchronization source to the synchronization source selection unit 22. In this embodiment, the transfer rule of the ESMC PDU is set by the management processing unit 12. Therefore, the protocol processing unit 11 notifies the management processing unit 12 of the selection result.

[0056] The synchronization source selection unit 22 supplies the clock selected in accordance with the selection result of the protocol processing unit 11 to the transmission units 32 and 42. In Fig. 2, a clock C2 indicates the clock selected by the synchronization source selection unit 22 from the clocks C11 and C21.

[0057] The protocol processor 11 further generates ESMC PDUs for transmitting the quality of the transmission clock selected by itself to the network elements 101 and 103. The control packet P12 is an ESMC PDU transmitted from the network element 102 to the network element 101. The control packet P22 is an ESMC PDU transmitted from the network element 102 to the network element 103.

[0058] When the switch unit 25 receives the control packets P12 and P22 from the protocol processing unit 11, it transfers the control packets P12 and P22 to the transmitters 32 and 42, respectively, in accordance with the transfer rule. The transmitter 32 transmits the control packet P12 to the network element 101. The transmitter 42 transmits the control packet P22 to the network element 101.

[0059] Fig. 3 is a diagram showing the format of the ESMC PDU according to ITU-T G.8264. As shown in Fig. 3, the ESMC PDU has a Data and Padding area 311. The SSM code is stored in the Data and Padding area 311 as QL data.

[0060] Fig. 4 is a diagram showing the format of the QL data. As shown in Fig. 4, the QL data includes an SSM Code field 404. The SSM Code field 404 stores information about the clock quality.

[0061] Fig. 5 is a diagram showing an excerpt of the SSM code. As shown in Fig. 5, the SSM code is made up of 4 bits. For example, if the quality of the clock is so high that the quality level of the clock corresponds to PRC, the SSM code is set to "0010". On the other hand, the SSM code sent from the port selected as the synchronization source to the opposing device, i.e., the SSM code sent upstream on the synchronization path, is set to "1111", which indicates that the clock quality level corresponds to a level where the clock is not used (DNU (Do Not Use)).

[0062] In the state where the synchronous system 100 is operating as shown in FIG. 2, it is assumed that the synchronization source selection unit 22 selects the clock C11 as the transmission clock. In other words, it is assumed that the reference clock CL1 is selected as the overall synchronization source of the synchronous system 100. In the synchronous system 100, the clock that is the synchronization source is transferred from the upstream device to the downstream device. Therefore, the reference clock CL1 is distributed from the network element 101 to the network element 102, and further distributed from the network element 102 to the network element 103. The network element 103 receives the ESMC PDU and the reference clock CL1 from the network element 102. Since the clock quality level information included in the ESMC PDU indicates PRC, the network element 103 selects the reference clock CL1 as the synchronization source of the network element 103. Therefore, the operation of the network element 103 switches from the operation synchronized with the reference clock CL2 to the operation synchronized with the reference clock CL1.

[0063] In this state, the software of the CPU 10 is reset. For example, the software of the CPU 10 is updated, and the software of the CPU 10 is reset. In this case, the reset is an uninterrupted reset, so the transmission of the main signal continues. However, since the CPU 10 stops during the reset, the following problem may occur.

[0064] 6 is a diagram for explaining a problem that may occur due to a software reset of a network element. For the purpose of explaining the problem, the management processing unit 12 is omitted from the configuration of the CPU 10 of the network element 102 shown in FIG.

[0065] The CPU is reset in the network element 102. During the reset of the CPU 10, the protocol processor 11 cannot receive or transmit an ESMC PDU. As a result, exchange of ESMC PDUs between the network element 102 and each of the network elements 101 and 103 stops.

[0066] When the time during which the network element 103 is unable to receive an ESMC PDU reaches a preset time due to a long stop time of the CPU 10 in the network element 102, a timeout occurs in the network element 103. Due to the timeout in the network element 103, the network element 103 stops synchronizing with the reference clock CL1 via the network element 101 and starts synchronizing with the reference clock CL2. Meanwhile, since the CPU 10 in the network element 102 is stopped, even if the network element 103 transmits an ESMC PDU to the network element 102, the protocol processor 11 in the network element 102 cannot process the ESMC PDU. Therefore, the network element 102 cannot synchronize with the reference clock CL2. Meanwhile, since the synchronization selector 22 in the network element 102 maintains the state before the CPU 10 is reset, the network element 102 remains synchronized with the reference clock CL1. That is, in the synchronization system 100, the synchronization source is divided into two due to the resetting network element 102, and the synchronization of the entire synchronization system 100 is not maintained.

[0067] According to the first embodiment, the transfer rule of the switch unit 25 is set immediately before the uninterruptible reset. FIG. 7 is a diagram for explaining the synchronization control immediately before the reset according to the first embodiment. As shown in FIG. 7, the management processing unit 12 stops the transfer of the ESMC PDU received by the switch unit 25 to the protocol processing unit 11 (software) immediately before the software reset (uninterruptible reset) of the CPU 10, and sets the transfer rule in the switch unit 25 so that the transfer destination of the ESMC PDU received by the selected synchronization port (corresponding to the receiving unit 31 in FIG. 7) is a SyncE-enabled port (another synchronization port) other than the selected port. It is more preferable to set the transfer rule so that the transfer destination is only the port of the SyncE-enabled port whose QL (quality level) output immediately before the reset is equal to the QL input in the ESMC PDU received by the selected port. In addition, if there are multiple SyncE-enabled ports other than the selected port (more preferably, among the SyncE-enabled ports, a port whose most recently output QL before reset is equal to the QL input in the ESMC PDU received by the selected port), the management processing unit 12 sets a transfer rule so as to copy the ESMC PDU and transfer it by multicast to the SyncE-enabled ports (more preferably, among the SyncE-enabled ports, a port whose most recently output QL before reset is equal to the QL input in the ESMC PDU received by the selected port). Furthermore, the management processing unit 12 writes information indicating that the software reset of the CPU 10 is an uninterrupted reset to the reset cause holding unit 23.

[0068] FIG. 8 is a diagram for explaining synchronization control during a CPU reset in the first embodiment. As shown in FIG. 8, the processing of the protocol processing unit 11 is stopped by a software reset in the CPU 10. However, when the receiving unit 31 receives an ESMC PDU (control packet P11) from the network element 101, the switch unit 25 immediately transfers the ESMC PDU to the transmitting unit 42, which is another SyncE-enabled port (more preferably, a port among the SyncE-enabled ports whose QL output most recently before the reset is equal to the QL input in the ESMC PDU received at the selected port). By sending the ESMC PDU from the transmitting unit 42 to the network element 103, the network element 103 can obtain information on the QL of the clock generated by the network element 101. Since the network element 103 does not experience a reception timeout of the ESMC PDU, the network element 103 can continue synchronization with the reference clock CL1 via the network elements 101 and 102. Therefore, the entire synchronization system 100 can be kept synchronized with the same reference clock.

[0069] After the uninterruptible reset, the forwarding rule of the switch unit 25 is restored to the forwarding rule before the uninterruptible reset. Therefore, the switch unit 25 forwards the ESMC PDU received via each of the receiving units 31 and 41 to the protocol processing unit 11. As a result, the state of the network element 102 returns to the normal state shown in FIG.

[0070] 9 is a sequence diagram of an uninterruptible reset executed in the communication device according to the first embodiment. In step S1, a request for an uninterruptible reset is sent from the management server 1 to the management processing unit 12. In step S2, the management processing unit 12 requests the protocol processing unit 11 to prepare for the uninterruptible reset.

[0071] In step S3, the protocol processing unit 11 saves information related to protocol processing in the memory 21. "ESMC saved information" refers to information saved from the protocol processing unit 11 to the memory 21. In step S4, the protocol processing unit 11 notifies the management processing unit 12 that preparation for uninterruptible reset is complete.

[0072] In step S5, the management processing unit 12 sets a transfer rule for the ESMC PDU for the switch unit 25. A first rule of "transfer the received ESMC PDU to the CPU" is set in the switch unit 25. Therefore, the management processing unit 12 sets a second rule for transferring the ESMC PDU received at the selected port to all ESMC-enabled ports other than the selected port (more preferably, all ports among the ESMC-enabled ports whose QL output most recently before reset is equal to the QL input in the ESMC PDU received at the selected port), and sets the priority of the second rule higher than the first rule. In the switch unit 25, the second rule is set so that all ESMC-enabled ports other than the selected port (more preferably, all ports among the ESMC-enabled ports whose QL output most recently before reset is equal to the QL input in the ESMC PDU received at the selected port) are expanded into specific port numbers, and the ESMC PDU received at the selected port is transferred to the port corresponding to each expanded port number. When there are multiple ESMC-enabled ports (more preferably, among the ESMC-enabled ports, ports whose most recently output QL before reset is equal to the QL input in the ESMC PDU received at the selected port), the management processing unit 12 sets a forwarding rule of the switch unit 25 so that the switch unit 25 copies the received ESMC PDU and forwards it by multicast to all SyncE-enabled ports (more preferably, among the ESMC-enabled ports, all ports whose most recently output QL before reset is equal to the QL input in the ESMC PDU received at the selected port).

[0073] In step S6, the management processor 12 sets information indicating that the reset cause is an "uninterrupted reset" in the reset cause holding unit 23. Then, in step S7, the management processor 12 and the protocol processor 11 are reset.

[0074] 10 is a sequence diagram showing a startup process after an uninterrupted reset executed in the communication device according to the first embodiment. The process shown in FIG. 10 is a process following step S7 shown in FIG.

[0075] In step S11, the management processing unit 12 reads out the reset cause from the reset cause holding unit 23. Since the reset cause holding unit 23 holds information indicating that the reset cause is an "uninterruptible reset", the management processing unit 12 confirms that an uninterruptible reset has been performed. In step S12, the management processing unit 12 clears the information on the reset cause held in the reset cause holding unit 23 (information that the reset cause is an "uninterruptible reset").

[0076] In step S13, the management processing unit 12 executes startup after the uninterruptible reset for the protocol processing unit 11. When the protocol processing unit 11 starts up, in step S14, the protocol processing unit 11 reads out the protocol data saved in the memory 21 from the memory 21, thereby restoring the data in the protocol processing unit 11.

[0077] In step S15, the protocol processing unit 11 notifies the management processing unit 12 of the completion of the startup. In step S16, the management processing unit 12 sets a transfer rule for the switch unit 25 in response to the notification from the protocol processing unit 11. Specifically, the management processing unit 12 deletes from the switch unit 25 a second rule for transferring the ESMC PDU received at the selected port to all ESMC-enabled ports other than the selected port (more preferably, all ports among the ESMC-enabled ports whose most recently output QL before reset is equal to the QL input in the ESMC PDU received at the selected port). This enables the first rule stored in the switch unit 25.

[0078] 9, the management processing unit 12 may delete the first rule and set the second rule. In this case, in step S16, the management processing unit 12 may delete the second rule from the switch unit 25 and set the first rule.

[0079] When the setting of the transfer rule in the switch unit 25 is completed, in step S17, the management processing unit 12 notifies the management server 1 that the startup after the uninterruptible reset is completed.

[0080] Fig. 11 is a sequence diagram showing the startup process after a normal reset executed in the communication device according to the first embodiment. As can be understood from the comparison between Fig. 10 and Fig. 11, in the process flow shown in Fig. 11, the processes of steps S12, S14, and S17 shown in Fig. 10 are omitted, and the processes of steps S13, S14, S15, and S16 shown in Fig. 10 are replaced with the processes of steps S23, S24, S25, and S26, respectively. In this respect, the flow of the startup process after a normal reset is different from the startup process after an uninterrupted reset.

[0081] In step S11, the management processing unit 12 reads out the reset cause from the reset cause holding unit 23. Since the reset cause holding unit 23 does not hold information indicating that the reset cause is an "uninterrupted reset", the management processing unit 12 confirms that a normal reset has been performed.

[0082] In step S23, the management processor 12 executes a start-up after a normal reset for the protocol processor 11. In step S24, the protocol processor 11 initializes protocol data. When the start-up of the protocol processor 11 is completed, in step S25, the protocol processor 11 notifies the management processor 12 that the normal start-up has been completed.

[0083] In step S26, the management processing unit 12 sets a transfer rule for the switch unit 25 in response to the notification from the protocol processing unit 11. Specifically, the management processing unit 12 sets a first rule (a rule of "transfer the received ESMC PDU to the CPU") in the switch unit 25.

[0084] In the above description, an example has been shown in which a clock generated based on the reference clock CL1 is selected as the synchronization source of the synchronous system 100. In this case, a clock generated based on the reference clock CL2 is not used as the synchronization source. Therefore, the network element 103 sets the code to be set in the SSM Code field 404 in the ESMC PDU (corresponding to the control packet P21 shown in FIG. 2) to be transmitted to the network element 102 to "1111", which indicates DNU.

[0085] During the uninterruptible reset of the CPU 10, the protocol processing unit 11 cannot receive the ESMC PDU transmitted from the network element 103. For this reason, in step S5 shown in Fig. 9, the management processing unit 12 sets a second rule in the switch unit 25 (a rule for "transferring the ESMC PDU received at the selected port to all ESMC-enabled ports other than the selected port (more preferably, all ports among the ESMC-enabled ports whose most recently output QL before reset is equal to the QL input in the ESMC PDU received at the selected port)").

[0086] FIG. 12 is a diagram showing a configuration for transferring an ESMC PDU indicating that the QL of the clock is DNU during an uninterrupted reset of the protocol processing unit 11. As shown in FIG. 12, the switch unit 25 does not apply the second rule to the ESMC PDU (control packet D21) received from the receiver unit 41, which is a SyncE-enabled port. Here, consider a third rule that is set at the timing of setting the second rule and deleted at the timing of deleting the second rule. This third rule is that "an ESMC PDU received at one of the ports, among the ESMC-enabled ports, in which the QL input in the ESMC PDU received most recently before the reset was DNU, is transferred to a selected port." When this third rule is set, the switch unit 25 immediately transfers the ESMC PDU received from the receiver unit 41 to the transmitter unit 32, which is a SyncE-enabled port. This makes it possible to avoid the upstream device (network element 101) detecting an ESMC timeout. Even if the network element 101 detects an ESMC timeout, this does not affect the selection of the synchronization source. However, by having the network element 101 not detect events that do not need to be detected, the number of unnecessary logs or alarms can be reduced, resulting in an advantage of lowering the cost of network management.

[0087] After the uninterruptible reset is completed, the management processing unit 12 sets the transfer rule of the switch unit 25 to the transfer rule for the normal state. This process corresponds to the process of step S16 shown in FIG.

[0088] As described above, according to the first embodiment, even if an uninterrupted reset (software reset) occurs in a communication device constituting a synchronization system, the software can be reset without switching the synchronization source and causing the synchronization source to be disconnected as a result.

[0089] For example, when updating firmware of a communication device, an uninterruptible reset is performed. Therefore, according to the first embodiment, it is possible to update the firmware of the communication device without switching the synchronization source and causing the resulting interruption of the synchronization source.

[0090] <Second embodiment> FIG. 13 is a diagram showing the configuration of a synchronization system including a communication device according to a second embodiment, and the internal configuration of the communication device. In the second embodiment, a synchronization system 100A is a synchronization system that realizes time synchronization by PTP. The synchronization system 100A includes boundary clocks 101A to 103A, which are multiple communication devices that exchange control packets related to synchronization control via a network. In FIG. 13, the boundary clocks 101A to 103A are represented as "BC1", "BC2", and "BC3", respectively. The boundary clocks relay time information transmitted from a grand master.

[0091] The boundary clock 102A is realized by a communication device according to the second embodiment. The boundary clock 102A is connected to the boundary clock 101A and the boundary clock 103A via a network (not shown). The boundary clocks 101A and 103A are connected to the grand masters GM1 and GM2, respectively. The grand masters GM1 and GM2 are sources of reference time for the synchronous system 100A. As in the first embodiment, the network element 103A is not limited to being directly connected to the network element 102A. A network element that performs time synchronization without having a grand master (i.e., a network element that performs the same operation as the network element 102A) may be connected between the network element 102A and the network element 103A via a network.

[0092] The basic configuration of the boundary clock 102A is similar to the configuration of the network element 102 shown in Fig. 1. As can be seen from a comparison between Fig. 13 and Fig. 1, the boundary clock 102A differs from the communication device (network element 102) according to the first embodiment in that it includes a protocol processing unit 11A instead of the protocol processing unit 11 and includes a PTP clock 22A instead of the synchronization source selection unit 22.

[0093] The protocol processor 11A performs PTP protocol processing. The protocol processor 11A exchanges PTP Announce messages with other PTP boundary clocks (or ordinary clocks) to determine the state of the PTP port (master or slave), and selects a grand master from the grand masters GM1 and GM2 to be the synchronization source of the synchronization system 100A.

[0094] The protocol processor 11A calculates the correction amount of its own PTP clock and instructs the PTP clock 22A to correct the clock. The calculation of the correction amount will be described later.

[0095] The management processing unit 12 loads parameters required for protocol processing by the protocol processing unit 11A into the memory 21. Furthermore, the management processing unit 12 exchanges information with the management server 1 via the transmission / reception unit 24 and the switch unit 25. In the second embodiment, the management server 1 executes setting of the configuration of the boundary clock 102A and external control of the boundary clock 102A. Specifically, the management server 1 executes setting related to the PTP-enabled port, that is, which port is to be the PTP-enabled port, in response to the user's operation. Furthermore, the management server 1 executes a command for uninterrupted reset of the boundary clock 102A in response to the user's operation.

[0096] As in the example shown in Fig. 1, in the boundary clock 102A, the transmitting / receiving unit 24 is not set as a PTP-enabled port, and is therefore not divided into a transmitting unit and a receiving unit. For this reason, in Fig. 13, the port that transmits and receives information with the management server 1 is simply described as the "transmitting / receiving unit."

[0097] The management processing unit 12 sets a transfer rule in the switch unit 25 according to the setting from the management server 1. When the management processing unit 12 receives an uninterruptible reset command from the management server 1, it sets a transfer rule for PTP (described later) in the switch unit 25. After the uninterruptible reset is completed, the management processing unit 12 deletes the transfer rule.

[0098] When an uninterruptible reset of the CPU 10 occurs, the management processing unit 12 writes information indicating that the reset cause is an uninterruptible reset into the reset cause holding unit 23 before the reset.

[0099] When starting up after resetting the CPU 10, the management processing unit 12 determines whether the reset is an uninterrupted reset or a normal start-up by referring to the reset cause holding unit 23. Specifically, the management processing unit 12 determines the cause of the reset by reading information indicating an uninterrupted reset from the reset cause holding unit 23.

[0100] The setting of the transfer rule in the switch unit 25 may be executed by the protocol processing unit 11A. In such an embodiment, the protocol processing unit 11A performs the process of setting the transfer rule in accordance with the contents expanded in the memory 21 by the management processing unit 12. Furthermore, the protocol processing unit 11A may delete the transfer rule after an uninterruptible reset.

[0101] The memory 21 is used for expanding parameters by the management processing unit 12. The memory 21 may also be used for expanding commands by the management processing unit 12.

[0102] Furthermore, the memory 21 is used by the protocol processor 11A to save data necessary for protocol processing before the uninterruptible reset. This data is stored in a non-volatile area of ​​the memory 21. After the uninterruptible reset, the protocol processor 11A reads the data stored in the memory 21 and restores the state of the boundary clock 102A to the state before the reset. This restores the clock selection port and the contents of the received PTP message, etc., making it possible to realize protocol processing that takes over the state before the reset.

[0103] The PTP clock 22A is a clock (clock unit) that is the target of time synchronization, and provides the time that serves as the reference for the time stamps that are stamped and recorded by the receiving units 31, 41 and the transmitting units 32, 42. The PTP clock 22A is configured from hardware.

[0104] Each of the receivers 31 and 41 receives a main signal and a control packet including a PTP message, and records the time (timestamp) at which the PTP message was received. The timestamp recorded by the receiver 31 is read out by the protocol processor 11A and used to create a corresponding message (Delay-Resp).

[0105] Each of the transmitters 32 and 42 transmits a control packet including a main signal and a PTP message. In the case of the One-Step mode, when the transmitter 32 transmits a PTP message, it writes (stamps) the transmission time (timestamp) in the timestamp field of the message and recalculates the FCS (Frame Check Sequence). In the case of the Two-Step mode, the transmitter 32A records the time (timestamp) when the PTP message is transmitted. This timestamp is read by the protocol processor 11A and used to create the corresponding Follow-Up message.

[0106] The switch unit 25 transfers PTP messages and other traffic including user traffic according to transfer rules set by the management processing unit 12 and relay rules such as L2. Normally, the switch unit 25 transfers PTP messages received at a PTP port to the CPU 10 (protocol processing unit 11A). During an uninterruptible reset, the switch unit 25 transfers PTP messages received at an upstream port (slave port) to a downstream port (master port). The switch unit 25 may discard PTP messages received at a PTP port other than the upstream port (slave port).

[0107] 14 is a diagram for explaining the operation of the synchronous system according to the second embodiment in a normal state. The protocol processing unit 11A receives a control packet PT11 including a PTP message from the boundary clock 101A (BC1) via the receiving unit 31 and the switching unit 25. Similarly, the protocol processing unit 11A receives a control packet PT21 including a PTP message from the boundary clock 103A (BC3) via the receiving unit 41 and the switching unit 25.

[0108] On the other hand, the protocol processing unit 11A transmits a control packet PT12 including a PTP message to the boundary clock 101A via the switch unit 25 and the transmitter 32. Similarly, the protocol processing unit 11A transmits a control packet PT22 including a PTP message to the boundary clock 103A via the switch unit 25 and the transmitter 42.

[0109] For example, the message included in the control packets PT11 and PT21 is an Announce message for notifying the slave of various attribute information related to time synchronization. In this case, the protocol processing unit 11A selects the grand master with which to synchronize the PTP time from the grand master GM1 and the grand master GM2 based on the Announce message included in the control packets PT11 and PT21. For example, if the quality of the grand master GM1 is higher than that of the grand masters GM1 and GM2, the grand master GM1 is selected as the synchronization source. In this embodiment, the management processing unit 12 sets the transfer rule of the PTP message. Therefore, the protocol processing unit 11A notifies the management processing unit 12 of the selection result of the grand master.

[0110] The protocol processing unit 11A corrects the time provided by the PTP clock 22A based on the exchange of PTP messages with an upstream device (in this case, the boundary clock 101A, which is the selected grandmaster). In this case, the messages contained in the control packets PT11 and PT12 are PTP messages for time correction (see FIG. 16). Furthermore, the protocol processing unit 11A transmits a control packet PT22 to the downstream side (the boundary clock 103A in this case) via the switch unit 25 and the transmission unit 42 to the boundary clock 103A. The message contained in the control packet PT22 may be an Announce message for notifying that the grandmaster selected as the synchronization source is the grandmaster GM1.

[0111] Fig. 15 is a diagram showing the format of an Announce message defined in IEEE 1588-2008 (PTP V2). As shown in Fig. 15, the Announce message has the following fields: "Header", "originTimestamp", "currentUTCoffset", "reserved", "grandmasterPriority1", "grandmasterClockQuality", "grandmasterPriority2", "grandmasterIdentity", "stepsRemoved", and "timeSource".

[0112] Fig. 16 is a sequence diagram showing communication based on PTP. As shown in Fig. 16, the master first transmits a PTP packet including an Announce message to the slave, and notifies the slave of various attribute information related to time synchronization.

[0113] After sending the Announce message, the master sends a PTP packet including a Sync message to the slave. This PTP packet includes the master's transmission time T1. In the One-Step mode, the master sends a Sync message including information on the transmission time T1. In the Two-Step mode, the master sends a Follow_Up message including information on the re-measured transmission time T1 to the slave after the Sync message.

[0114] The slave receives the Sync message and records the reception time T2 of the Sync message, which is a time measured by the slave's own clock.

[0115] The slave then sends a PTP packet containing a Delay_Req message to the master. The Delay_Req message contains the time T3 when the slave sent the PTP packet. The time T3 is the time measured by the slave's own clock.

[0116] The master receives the Delay_Req message and records the reception time T4 of the Delay_Req message. Time T4 is the time measured by the master's own clock. The master sends a PTP packet including a Delay_Resp message to the slave. The Delay_Resp message includes the time T4.

[0117] The slave substitutes the values ​​of times T1 to T4 into the following equation (1) to calculate the time correction amount Toffset.

[0118] Toffset=(T2-T1)-{(T4-T1)-(T3-T2)} / 2...(1)

[0119] The slave corrects the time measured by its own clock based on the correction amount Toffset. As a result, the time of the slave is corrected to match the time of the master, and the times are synchronized between the master and the slave.

[0120] The sequence shown in FIG. 16 is performed between the master and the slave in sequence from the upstream side to the downstream side of the time synchronization path. That is, when the grand master GM1 is selected as the grand master of the synchronous system 100A, the boundary clock 101A becomes the master and the boundary clock 102A becomes the slave between the boundary clock 101A and the boundary clock 102A. Returning to FIG. 14, the boundary clock 102A is notified of the transmission time T1 of the Sync message from the boundary clock 101A by the Sync message (Follow_Up message in the case of Two-Step mode). Furthermore, the boundary clock 102A is notified of the reception time T4 of the Delay-Reply from the boundary clock 101A. When the Sync message is received, the receiver 31A of the boundary clock 102A records the reception time.

[0121] The transmitter 32A of the boundary clock 102A records the transmission time T3 when transmitting the Delay_Req. The protocol processor 11A calculates the correction amount of the PTP clock according to the above formula (1) based on the times T1 and T4 notified from the boundary clock 101A, the time T2 measured by the protocol processor 11A itself, and the time T3 notified to the boundary clock 101A.

[0122] Between the boundary clock 102A and the boundary clock 103A, the boundary clock 102A is the master, and the boundary clock 103A is the slave. By exchanging PTP messages between the boundary clock 102A and the boundary clock 103A according to the flow of communication shown in Fig. 16, the boundary clock 103A calculates the correction amount of the PTP clock.

[0123] Assume that an uninterruptible reset is executed in the state shown in FIG. 14. In this case, the CPU 10 (protocol processor 11A) of the boundary clock 102A cannot receive or transmit an Announce message during the reset. When the time during which the boundary clock 103A is unable to receive an Announce message reaches a preset time due to the long uninterruptible reset time, a timeout occurs in the boundary clock 103A. Because the boundary clock 103A times out, the boundary clock 103A cannot synchronize with the grand master GM1, and so starts synchronizing with the grand master GM2. Meanwhile, since the boundary clock 102A is being reset, even if a PTP message (Announce message) is transmitted from the boundary clock 103A, the protocol processor 11A of the boundary clock 102A cannot process the PTP message. Therefore, the boundary clock 102A cannot synchronize with the grand master GM2. However, the boundary clock 102A is synchronized with the grand master GM1 because the PTP clock 22A of the boundary clock 102A maintains the state before the CPU 10 was reset. Therefore, in the synchronous system 100A, the synchronization source is divided into two, and the synchronization of the entire synchronous system 100A is not maintained.

[0124] Fig. 17 is a diagram for explaining synchronization control immediately before a reset according to the second embodiment. As shown in Fig. 17, the management processing unit 12 stops forwarding the received PTP message to the protocol processing unit 11A (software) immediately before a software reset (uninterrupted reset) of the CPU 10. The management processing unit 12 sets a forwarding rule in the switch unit 25 so that the forwarding destination of the control packet PT11 (PTP message) received from the receiving unit 31 corresponding to the slave port that is the synchronization source port is all master ports (other synchronization ports). Furthermore, the management processing unit 12 writes information indicating that the software reset of the CPU 10 is an uninterrupted reset to the reset cause holding unit 23.

[0125] Fig. 18 is a diagram for explaining synchronous control during a CPU reset in the second embodiment. As shown in Fig. 18, the processing of the protocol processing unit 11A is stopped by the software of the CPU 10. However, when the receiving unit 31 (slave port) receives a control packet PT11 from the boundary clock 101A, the switch unit 25 immediately transfers the control packet PT11 to the transmitting unit 42, which corresponds to the master port.

[0126] During a reset of the CPU 10, the switch unit 25 does not necessarily need to transfer all types of PTP messages to the master port. During a reset of the CPU 10, the switch unit 25 must be able to transfer at least an Announce message to the master port. By sending an Announce message from the transmitter 42 to the boundary clock 103A, the boundary clock 103A can continue to select the grand master GM1 as the synchronization source. Therefore, even during a reset of the CPU 10, the entire synchronous system 100A can remain synchronized with the same grand master.

[0127] After the uninterruptible reset is completed, the transfer rule of the switch unit 25 is restored to the transfer rule before the reset. Therefore, the switch unit 25 transfers the received PTP packet to the protocol processor 11A. As a result, the state of the boundary clock 102A returns to the normal state shown in FIG.

[0128] Fig. 19 is a sequence diagram of an uninterruptible reset executed in a communication device according to the second embodiment. As can be understood by comparing Fig. 9 with Fig. 19, the process flow shown in Fig. 19 is basically the same as the process flow shown in Fig. 9. The processes of steps S2 to S5 shown in Fig. 9 are replaced with processes of steps S2A to S5A in Fig. 19.

[0129] In step S1, a request for an uninterruptible reset is sent from the management server 1 to the management processing unit 12. In step S2A, the management processing unit 12 requests the protocol processing unit 11A to prepare for an uninterruptible reset.

[0130] In step S3A, the protocol processing unit 11A saves information related to protocol processing (shown as "PTP save information" in FIG. 19) in the memory 21. In step S4A, the protocol processing unit 11A notifies the management processing unit 12 that preparations for an uninterruptible reset have been completed.

[0131] In step S5A, the management processing unit 12 sets a transfer rule for the PTP packet for the switch unit 25. In the second embodiment, a first rule of "transfer the received PTP packet to the CPU" is set in the switch unit 25. Therefore, the management processing unit 12 sets a second rule for transferring the PTP packet received at the slave port to all master ports in the switch unit 25, and sets the priority of the second rule higher than the first rule. In addition, the second rule is set in the switch unit 25 so that the master port is expanded to a specific port number and the PTP message received at the slave port is transferred to the port corresponding to each expanded port number.

[0132] In step S6, the management processing unit 12 sets information indicating that the reset cause is an "uninterruptible reset" in the reset cause holding unit 23. Then, in step S7, the management processing unit 12 and the protocol processing unit 11A are reset.

[0133] Fig. 20 is a sequence diagram showing a startup process after an uninterruptible reset executed in a communication device according to the second embodiment. The process shown in Fig. 20 is a process subsequent to step S7 shown in Fig. 19. As can be understood from a comparison between Fig. 20 and Fig. 10, the process flow shown in Fig. 20 is basically the same as the process flow shown in Fig. 10. The processes of steps S13 to S16 shown in Fig. 10 are replaced with the processes of steps S13A to S16A in Fig. 19.

[0134] In step S11, the management processing unit 12 reads out the reset cause from the reset cause holding unit 23. Since the reset cause holding unit 23 holds information indicating that the reset cause is an "uninterruptible reset", the management processing unit 12 confirms that an uninterruptible reset has been performed. In step S12, the management processing unit 12 clears the information on the reset cause ("uninterruptible reset") held in the reset cause holding unit 23.

[0135] In step S13A, the management processor 12 executes start-up after the uninterruptible reset for the protocol processor 11A. When the protocol processor 11A starts up, in step S14A, the protocol processor 11A reads out from the memory 21 the protocol data saved in the memory 21, thereby restoring the data in the protocol processor 11A.

[0136] In step S15A, the protocol processing unit 11A notifies the management processing unit 12 of the completion of the startup. In step S16A, the management processing unit 12 sets a transfer rule for the switch unit 25 in response to the notification from the protocol processing unit 11A. Specifically, the management processing unit 12 deletes the second rule of "transferring PTP packets received at a slave port to all master ports" from the switch unit 25. This enables the first rule stored in the switch unit 25. Note that, in step S5A shown in FIG. 19, the management processing unit 12 may delete the first rule and set the second rule. In this case, in step S16A, the management processing unit 12 deletes the second rule from the switch unit 25 and sets the first rule.

[0137] When the setting of the transfer rule in the switch unit 25 is completed, in step S17, the management processing unit 12 notifies the management server 1 that the startup after the uninterruptible reset is completed.

[0138] FIG. 21 is a sequence diagram showing a startup process after a normal reset executed in a communication device according to the second embodiment. As can be seen from a comparison between FIG. 20 and FIG. 21, in the process flow shown in FIG. 21, the processes of steps S12, S14A, and S17 shown in FIG. 20 are omitted, and the processes of steps S13A, S14A, S15A, and S16A are replaced with the processes of steps S23A, S24A, S25A, and S26A, respectively. In this respect, the startup process flow after a normal reset is different from the startup process after an uninterrupted reset. Also, as can be seen from a comparison between FIG. 21 and FIG. 11, the process flow shown in FIG. 21 is basically the same as the process flow shown in FIG. 11. The processes of steps S23 to S26 shown in FIG. 11 are replaced with the processes of steps S23A to S26A in FIG. 21.

[0139] In step S11, the management processing unit 12 reads out the reset cause from the reset cause holding unit 23. Since the reset cause holding unit 23 does not hold information indicating that the reset cause is an "uninterrupted reset", the management processing unit 12 confirms that a normal reset has been performed.

[0140] In step S23A, the management processor 12 executes a start-up after a normal reset for the protocol processor 11A. In step S24A, the protocol processor 11A initializes protocol data. When the start-up of the protocol processor 11A is completed, in step S25A, the protocol processor 11A notifies the management processor 12 that the normal start-up has been completed.

[0141] In step S26A, in response to the notification from the protocol processing unit 11A, the management processing unit 12 sets a transfer rule for the switch unit 25. Specifically, the management processing unit 12 sets a first rule (a rule of "transfer the received PTP packet to the CPU") in the switch unit 25.

[0142] As described above, according to the second embodiment, similarly to the first embodiment, even if an uninterrupted reset (software reset) occurs in a communication device constituting a synchronization system, the software can be reset without switching the synchronization source and causing the synchronization source to be disconnected as a result.

[0143] For example, when updating firmware of a communication device, an uninterruptible reset is performed. Therefore, according to the second embodiment, it is possible to update the firmware of the communication device without switching the synchronization source and causing the resulting interruption of the synchronization source.

[0144] In addition, even if a PTP message is transferred to the CPU during an uninterruptible reset, the CPU cannot process the message. However, from the viewpoint of the CPU processing load, it is not preferable for messages to be accumulated in the CPU queue at the time of restarting the CPU after an uninterruptible reset. Therefore, it is preferable to apply the discarding of PTP packets during an uninterruptible reset to all PTP messages, not just Announce messages.

[0145] <Third embodiment> 22 is a diagram showing the configuration of a synchronization system including a communication device according to a third embodiment and the internal configuration of the communication device. In the third embodiment, the time synchronization according to the first and second embodiments and the frequency synchronization according to the first embodiment are combined.

[0146] The synchronization system 100B includes network elements 101B to 103B. The network element 102B is connected to the network elements 101B and 103B via a network (not shown). The network element 101B is supplied with a reference clock CL1 and is connected to a grand master GM1. The network element 103B is supplied with a reference clock CL2 and is connected to a grand master GM2. As in the first embodiment, the network element 103 is not limited to being directly connected to the network element 102. A network element that performs frequency synchronization and time synchronization without having a reference clock and a grand master (i.e., a network element that performs the same operation as the network element 102) may be connected between the network elements 102 and 103 via a network.

[0147] The configuration of the network element 102B is a configuration in which a PTP clock 22A and a protocol processor 11A that executes PTP protocol processing are added to the configuration of the network element 102. In the network element 102B, the time (clock) provided by the PTP clock 22A is frequency-synchronized with the recovered clock selected by the synchronization source selector 22. During an uninterruptible reset, time correction by exchanging PTP messages with the upstream device is not possible. However, since the PTP clock is frequency-synchronized with the recovered clock before the uninterruptible reset is executed, it is possible to suppress an increase in the error of the PTP clock during the uninterruptible reset.

[0148] Fig. 23 is a sequence diagram of an uninterruptible reset executed in a communication device according to the third embodiment. As shown in Fig. 23, in the third embodiment, the processes of steps S1 to S7 shown in Fig. 9 are combined with the processes of steps S2A to S5A shown in Fig. 19. The contents of the processes of each step are similar to the processes of the corresponding steps in the first and second embodiments. Therefore, in the following, detailed descriptions of the processes of each step will not be repeated, and the flow of the processes will be mainly described.

[0149] First, in step S1, a request for an uninterruptible reset is sent from the management server 1 to the management processing unit 12. Next, in steps S2A to S4A, the protocol processing unit 11A, which is a PTP protocol processing unit, prepares for an uninterruptible reset in response to the uninterruptible reset preparation request from the management processing unit 12. When the protocol processing unit 11A completes preparation for an uninterruptible reset, in steps S2 to S4, the protocol processing unit 11, which is an ESMC protocol processing unit, prepares for an uninterruptible reset in response to the uninterruptible reset preparation request from the management processing unit 12.

[0150] When preparations for uninterruptible reset of the protocol processor 11A and the protocol processor 11 are completed, the management processor 12 sets a transfer rule for PTP packets and a transfer rule for ESMC PDUs for the switch unit 25 in steps S5A and S5, respectively.

[0151] When the setting of the switch unit 25 is completed, in step S6, the management processing unit 12 sets information indicating that the reset cause is an "uninterrupted reset" in the reset cause holding unit 23. Then, in step S7, the management processing unit 12, the protocol processing unit 11, and the protocol processing unit 11A are reset.

[0152] Fig. 24 is a sequence diagram showing a startup process after an uninterruptible reset executed in a communication device according to the third embodiment. The process shown in Fig. 24 is a process following step S7 shown in Fig. 23. As shown in Fig. 24, in the third embodiment, the processes of steps S11 to S17 shown in Fig. 10 are combined with the processes of steps S13A to S16A shown in Fig. 19.

[0153] In step S11, the management processing unit 12 reads out a reset cause from the reset cause holding unit 23. Since the reset cause holding unit 23 holds information indicating that the reset cause is an "uninterruptible reset", the management processing unit 12 confirms that an uninterruptible reset has been performed.

[0154] Next, in steps S13A to S15A, the protocol processing unit 11A (PTP protocol processing unit) performs startup after the uninterruptible reset in response to an instruction from the management processing unit 12. When the startup of the protocol processing unit 11A is completed, in steps S13 to S15, the protocol processing unit 11 (ESMC protocol processing unit) performs startup after the uninterruptible reset in response to an instruction from the management processing unit 12.

[0155] When the startup of the protocol processing unit 11A and the protocol processing unit 11 is completed, in steps S16A and S16, the management processing unit 12 sets a transfer rule for PTP packets and a transfer rule for ESMC PDU, respectively, in the switch unit 25. When the setting of the transfer rule in the switch unit 25 is completed, in step S17, the management processing unit 12 notifies the management server 1 that the startup after the uninterruptible reset is completed.

[0156] FIG. 25 is a sequence diagram showing a start-up process after a normal reset executed in a communication device according to the third embodiment. As shown in FIG. 25, in the third embodiment, the processes of steps S11, S23 to S26 shown in FIG. 11 are combined with the processes of steps S23A to S26A shown in FIG. 21. In step S11, the management processing unit 12 reads out a reset cause from the reset cause holding unit 23. Since the reset cause holding unit 23 does not hold information indicating that the reset cause is an "uninterrupted reset", the management processing unit 12 confirms that a normal reset has been performed. Therefore, the management processing unit 12 executes a start-up process after a normal reset for the protocol processing unit 11A (step S23A). The protocol processing unit 11A initializes protocol data (step S24A). When the start-up of the protocol processing unit 11A is completed, the protocol processing unit 11A notifies the management processing unit 12 that the normal start-up has been completed (step S25A).

[0157] Next, the management processor 12 instructs the protocol processor 11 to start up after the normal reset. The protocol processor 11 executes normal start-up in response to the instruction (step S23). The protocol processor 11 initializes protocol data (step S24). When the start-up of the protocol processor 11 is completed, the protocol processor 11 notifies the management processor 12 that the normal start-up has been completed (step S25).

[0158] In step S26A, the management processing unit 12 sets a rule that "a received PTP packet is transferred to the CPU" in the switch unit 25. Next, in step S26, the management processing unit 12 sets a rule that "a received ESMC PDU is transferred to the CPU" in the switch unit 25.

[0159] As described above, the network element 102B, which is a communication device according to the third embodiment, synchronizes the frequency of the PTP clock with the recovered clock by using the recovered clock selected by the synchronization source selection unit 22 as the reference clock for the PTP clock. This makes it possible to suppress an increase in the time error of the PTP clock even if time correction cannot be performed by exchanging PTP messages during an uninterrupted reset.

[0160] The embodiments disclosed herein are illustrative in all respects and should not be considered as limiting. The scope of the present invention is defined by the claims rather than the above-described embodiments, and it is intended to include the equivalent meaning of the claims and all modifications within the scope of the claims. [Explanation of symbols]

[0161] 1 Management Server 10 CPU (control unit) 11, 11A Protocol processing unit 12 Management department 21 Memory 22 Synchronization source selection unit 22A PTP Clock 23 Reset cause holding section 24 Transmitter / receiver 25 Switch section (packet forwarding section) 31, 31A, 41 Receiver 32, 32A, 42 Transmitter 100, 100A, 100B Synchronous System 101,102,103,101B,102B,103B network elements 101A, 102A, 103A Boundary Clock 311 areas 404 Field CL1,CL2 Reference Clock C2, C11, C21 Clock D21, P11, P12, P21, P22, PT11, PT12, PT21, PT22 control packets GM1, GM2 Grandmaster S1~S7, S11~S17, S23~S26, S2A~S5A, S13A~S16A, S23A~S26A Step T1,T3 Transmission time T2, T4 Reception time Toffset correction amount

Claims

1. A communication device applicable to a synchronization system having a plurality of communication devices that exchange control packets related to synchronization control via a network, The communication device includes a control unit configured to perform an uninterrupted reset that resets the communication device without stopping packet forwarding, The control unit performs the synchronization control by transmitting and receiving the control packet; The communication device further includes a packet forwarding unit that immediately forwards the control packet received from a synchronization source port to another synchronization port during the uninterruptible reset period of the control unit.

2. 2. The communication device according to claim 1, wherein the control unit sets a forwarding rule for the packet forwarding unit prior to the uninterruptible reset so that the packet forwarding unit forwards the control packet received from the synchronization source port to the other synchronization port, and after the uninterruptible reset, restores the forwarding rule for the packet forwarding unit to the forwarding rule before the uninterruptible reset.

3. The communication device further includes a storage unit. The communication device of claim 2, wherein the control unit writes reset information indicating whether the reset of the control unit corresponds to the uninterrupted reset into the memory unit prior to the uninterrupted reset of the control unit being executed, and checks the reset information upon startup after the reset to determine whether the reset of the control unit was the uninterrupted reset or a normal reset.

4. The communication device according to claim 1 , wherein the control unit is configured to execute a protocol process according to a protocol related to the synchronization control and the setting in the packet forwarding unit by software processing.

5. The protocol processing includes a time synchronization process according to the PTP, the control packet includes a message for notifying a time synchronization source of the time synchronization; The communication device includes: The communication device according to claim 4 , further comprising a clock unit that is a target of the time synchronization according to the PTP.

6. The protocol process includes a frequency synchronization process according to ESMC; the control packet includes information indicating a quality level of a clock that can be a frequency synchronization source for the synchronization control; 5. The communication device according to claim 4, wherein the protocol processing unit selects, as the frequency synchronization source, a clock from a supply source having a highest clock quality level among a plurality of clock supply sources according to information indicating a quality level of the control packet.

7. 7. The communication device according to claim 6, wherein when the packet forwarding unit receives from the other synchronization port the control packet indicating that a clock supplied from a source other than the frequency synchronization source among the multiple sources will not be used during the uninterrupted reset, the packet forwarding unit forwards the control packet to the synchronization source port.

8. The protocol processing includes a time synchronization process according to the PTP, the control packet includes a packet for notifying a time indicated by a synchronization source of the time synchronization, The communication device includes: A clock unit that generates a clock that is a target of the time synchronization according to the PTP, The communication device according to claim 5 , wherein the clock unit synchronizes the frequency of the clock generated by the clock unit with a frequency of a synchronization source selected by the protocol processing unit during the uninterrupted reset of the control unit.

9. A communication control method by a plurality of communication devices applicable to a synchronous system having the communication devices which exchange control packets related to synchronous control via a network, the communication devices being configured to be capable of performing an uninterrupted reset for resetting the communication devices without stopping packet transfer, the communication control method comprising the steps of: performing said synchronization control by transmitting and receiving said control packets; performing the uninterruptible reset; and immediately transferring the control packet received by the communication device from a synchronization source port via the network to another synchronization port during the uninterruptible reset period.

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