Three-dimensional semiconductor memory device and electronic system containing the same

Abstract

To provide a three-dimensional semiconductor memory device of which a data cancellation operation speed is improved, and an electronic system containing the same.SOLUTION: A three-dimensional semiconductor memory device contains: a circumference circuit structure body on a peripheral substrate; a lamination structure body that contains a plurality of gate electrodes laminated onto the circumference circuit structure body; an N doping pattern on the lamination structure body; a vertical structure pattern that is penetrated to the lamination structure body, and is extended into an internal part of the N doping pattern; a P doping pattern on the N doping pattern; and a non-doping pattern between the N doping pattern and the P doping pattern. The P doping pattern contains a P doping vertical pattern contacted to the vertical structure body while penetrating a P doping horizontal pattern on the non-doping pattern, the non-doping pattern, and the N doping pattern.SELECTED DRAWING: Figure 6

Description

[Technical field]

[0001] The present invention relates to a three-dimensional semiconductor memory device and an electronic system including the same, and more particularly to a three-dimensional semiconductor memory device including a peripheral circuit structure and a cell array structure coupled to each other through bonding pads, and an electronic system including the same. [Background technology]

[0002] There is a demand for semiconductor devices capable of storing high-capacity data in electronic systems that require data storage. There is a demand for increasing the integration degree of semiconductor devices in order to increase data storage capacity while satisfying the excellent performance and low price demanded by consumers. In the case of two-dimensional or planar semiconductor devices, the integration degree is mainly determined by the area occupied by a unit memory cell, and is greatly influenced by the level of fine pattern formation technology. However, since extremely expensive equipment is required to fine the pattern, the integration degree of two-dimensional semiconductor devices is increasing but remains limited. Therefore, a three-dimensional semiconductor memory device having memory cells arranged three-dimensionally has been proposed. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] U.S. Patent Application Publication No. 2023 / 0008539 A1 Summary of the Invention [Problem to be solved by the invention]

[0004] It is an object of the present invention to provide a three-dimensional semiconductor memory device having an improved data erase operation speed, and an electronic system including the same.

[0005] Another technical object of the present invention is to provide a three-dimensional semiconductor memory device having improved electrical characteristics and reliability, and an electronic system including the same.

[0006] The problems to be solved by the present invention are not limited to those mentioned above, and other problems not mentioned will be clearly understood by those having ordinary skill in the art from the description below. [Means for solving the problem]

[0007] The three-dimensional semiconductor memory device according to the present invention may include a peripheral circuit structure on a peripheral substrate, a stack structure including a plurality of gate electrodes stacked on the peripheral circuit structure, an N-doped pattern on the stack structure, a vertical structure penetrating the stack structure and extending into the N-doped pattern, a P-doped pattern on the N-doped pattern, and an undoped pattern between the N-doped pattern and the P-doped pattern. The P-doped pattern may include a P-doped horizontal pattern on the undoped pattern and a P-doped vertical pattern penetrating the undoped pattern and the N-doped pattern to contact the vertical structure.

[0008] A three-dimensional semiconductor memory device according to the present invention may include a peripheral circuit structure on a peripheral substrate, a stacked structure including a plurality of gate electrodes stacked on the peripheral circuit structure, an N-doped pattern on the stacked structure, a vertical structure extending through the stacked structure and into the N-doped pattern, an undoped pattern on the N-doped pattern, a P-doped pattern penetrating the undoped pattern and the N-doped pattern to contact the vertical structure, a metal contact electrically connected to the N-doped pattern, and a P contact plug electrically connected to the P-doped pattern.

[0009] The electronic system according to the present invention may include a three-dimensional semiconductor memory device, and a controller electrically connected to the three-dimensional semiconductor memory device through input / output pads and configured to control the three-dimensional semiconductor memory device. The three-dimensional semiconductor memory device may include a peripheral circuit structure on a peripheral substrate, a stack structure including a plurality of gate electrodes stacked on the peripheral circuit structure, an N-doped pattern on the stack structure, a vertical structure penetrating the stack structure and extending into the N-doped pattern, a P-doped pattern on the N-doped pattern, and an undoped pattern between the N-doped pattern and the P-doped pattern. The P-doped pattern may include a P-doped horizontal pattern on the undoped pattern and a P-doped vertical pattern penetrating the undoped pattern and the N-doped pattern to contact the vertical structure.

[0010] The three-dimensional semiconductor memory device according to the present invention may include a peripheral circuit structure on a peripheral substrate, a stack structure including a plurality of gate electrodes and a plurality of interlayer insulating films alternately stacked on the peripheral circuit structure, a vertical structure penetrating the stack structure, and a P-doped pattern covering the stack structure. The vertical structure may include a head structure penetrating an uppermost gate electrode among the plurality of gate electrodes, and a through structure below the head structure. The P-doped pattern may protrude into the head structure. Effect of the Invention

[0011] According to the concept of the present invention, a P doping pattern can be used in a data erase operation of a three-dimensional semiconductor memory device, and an erase operation can be performed simultaneously on a plurality of memory cell transistors, thereby improving the speed of an erase operation of a three-dimensional semiconductor memory device and an electronic system including the same.

[0012] In addition, by positioning a non-doped pattern between the P-doped pattern and the N-doped pattern, junction leakage between the P-doped pattern and the N-doped pattern can be minimized, thereby improving electrical characteristics and reliability of a three-dimensional semiconductor memory device and an electronic system including the same. [Brief description of the drawings]

[0013] [Figure 1] 1 is a schematic diagram of an electronic system including a three-dimensional semiconductor memory device according to an embodiment of the inventive concept; [Diagram 2] 1 is a perspective view illustrating a schematic diagram of an electronic system including a three-dimensional semiconductor memory device according to an embodiment of the present invention. [Diagram 3] 2A to 2C are cross-sectional views illustrating a semiconductor package including a three-dimensional semiconductor memory device according to an embodiment of the present invention, each of which corresponds to a cross-section taken along line II' in FIG. [Figure 4] 2A-2C are cross-sectional views illustrating a semiconductor package including a three-dimensional semiconductor memory device according to an embodiment of the present invention, each of which corresponds to a cross-section taken along line II-II' in FIG. [Diagram 5] 1 is a plan view illustrating a three-dimensional semiconductor memory device according to an embodiment of the inventive concept; [Figure 6] 6 is a cross-sectional view corresponding to lines AA' and BB' in FIG. 5. [Figure 7] FIG. 7 is an enlarged view corresponding to P2 in FIG. [Figure 8] FIG. 7 is an enlarged view corresponding to P2 in FIG. [Figure 9A] 5, and corresponds to showing P1 at the first level in FIG. 8. [Figure 9B] 5, and corresponds to showing P1 at the second level in FIG. 8. FIG. [Figure 10] FIG. 7 is an enlarged view corresponding to P2 in FIG. [Figure 11]FIG. 7 is an enlarged view corresponding to P2 in FIG. [Figure 12] 1 is a plan view illustrating a three-dimensional semiconductor memory device according to an embodiment of the inventive concept; [Figure 13] 6 is a cross-sectional view corresponding to lines AA' and BB' in FIG. 5. [Figure 14] FIG. 14 is an enlarged view corresponding to P3 in FIG. [Figure 15] FIG. 14 is an enlarged view corresponding to P3 in FIG. [Figure 16] FIG. 14 is an enlarged view corresponding to P3 in FIG. [Figure 17] 1A to 1C are cross-sectional views illustrating a method for manufacturing a three-dimensional semiconductor memory device according to an embodiment of the present invention. [Figure 18] 1A to 1C are cross-sectional views illustrating a method for manufacturing a three-dimensional semiconductor memory device according to an embodiment of the present invention. [Figure 19] 1A to 1C are cross-sectional views illustrating a method for manufacturing a three-dimensional semiconductor memory device according to an embodiment of the present invention. [Figure 20] 1A to 1C are cross-sectional views illustrating a method for manufacturing a three-dimensional semiconductor memory device according to an embodiment of the present invention. [Figure 21] 1A to 1C are cross-sectional views illustrating a method for manufacturing a three-dimensional semiconductor memory device according to an embodiment of the present invention. [Figure 22] 1A to 1C are cross-sectional views illustrating a method for manufacturing a three-dimensional semiconductor memory device according to an embodiment of the present invention. [Diagram 23] 1A to 1C are cross-sectional views illustrating a method for manufacturing a three-dimensional semiconductor memory device according to an embodiment of the present invention. [Figure 24] 1A to 1C are cross-sectional views illustrating a method for manufacturing a three-dimensional semiconductor memory device according to an embodiment of the present invention. [Diagram 25] 1A to 1C are cross-sectional views illustrating a method for manufacturing a three-dimensional semiconductor memory device according to an embodiment of the present invention. [Figure 26] 1A to 1C are cross-sectional views illustrating a method for manufacturing a three-dimensional semiconductor memory device according to an embodiment of the present invention. [Figure 27] 1A to 1C are cross-sectional views illustrating a method for manufacturing a three-dimensional semiconductor memory device according to an embodiment of the present invention. [Figure 28]1A to 1C are cross-sectional views illustrating a method of manufacturing a three-dimensional semiconductor memory device according to an embodiment of the present invention. [Figure 29] 1A to 1C are cross-sectional views illustrating a method of manufacturing a three-dimensional semiconductor memory device according to an embodiment of the present invention. [Diagram 30] 1A to 1C are cross-sectional views illustrating a method of manufacturing a three-dimensional semiconductor memory device according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In order to more specifically explain the present invention, embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0015] FIG. 1 is a schematic diagram of an electronic system including a three-dimensional semiconductor memory device according to an embodiment of the present invention.

[0016] 1, an electronic system 1000 according to an embodiment of the present invention may include a three-dimensional semiconductor memory device 1100 and a controller 1200 electrically connected to the three-dimensional semiconductor memory device 1100. The electronic system 1000 may be a storage device including one or more three-dimensional semiconductor memory devices 1100 or an electronic device including a storage device. For example, the electronic system 1000 may be a solid state drive device (SSD device), a Universal Serial Bus (USB), a computing system, a medical device, or a communication device including one or more three-dimensional semiconductor memory devices 1100.

[0017] The three-dimensional semiconductor memory device 1100 may be a non-volatile memory device, for example, a three-dimensional NAND flash memory device as described below. The three-dimensional semiconductor memory device 1100 may include a first region 1100F and a second region 1100S on the first region 1100F. However, unlike what is illustrated, the first region 1100F may be disposed beside the second region 1100S. The first region 1100F may be a peripheral circuit region including a decoder circuit 1110, a page buffer 1120, and a logic circuit 1130. The second region 1100S may be a memory cell region including a bit line BL, a common source line CSL, a word line WL, a first line LL1, LL2, a second line UL1, UL2, and a memory cell string CSTR between the bit line BL and the common source line CSL.

[0018] In the second region 1100S, each memory cell string CSTR may include first transistors LT1, LT2 adjacent to the common source line CSL, second transistors UT1, UT2 adjacent to the bit line BL, and a plurality of memory cell transistors MCT disposed between the first transistors LT1, LT2 and the second transistors UT1, UT2. The number of the first transistors LT1, LT2 and the number of the second transistors UT1, UT2 may be variously modified according to the embodiment. The memory cell string CSTR may be located between the common source line CSL and the first region 1100F.

[0019] For example, the second transistors UT1 and UT2 may include string selection transistors, and the first transistors LT1 and LT2 may include ground selection transistors. The first lines LL1 and LL2 may be gate electrodes of the first transistors LT1 and LT2. The word line WL may be a gate electrode of the memory cell transistor MCT, and the second lines UL1 and UL2 may be gate electrodes of the second transistors UT1 and UT2.

[0020] For example, the first transistors LT1 and LT2 may include a first erase control transistor and a ground selection transistor connected in series, and the second transistors UT1 and UT2 may include a string selection transistor and a second erase control transistor connected in series.

[0021] The common source line CSL, the first lines LL1 and LL2, the word lines WL, and the second lines UL1 and UL2 may be electrically connected to the decoder circuit 1110 through a first connecting line 1115 extending from the first region 1100F to the second region 1100S. The bit line BL may be electrically connected to the page buffer 1120 through a second connecting line 1125 extending from the first region 1100F to the second region 1100S.

[0022] In the first region 1100F, the decoder circuit 1110 and the page buffer 1120 may perform a control operation on at least one selected memory cell transistor among the plurality of memory cell transistors MCT. The decoder circuit 1110 and the page buffer 1120 may be controlled by a logic circuit 1130. The three-dimensional semiconductor memory device 1100 may communicate with the controller 1200 through an I / O pad 1101 electrically connected to the logic circuit 1130. The I / O pad 1101 may be electrically connected to the logic circuit 1130 through an I / O connection wiring 1135 extending from within the first region 1100F to the second region 1100S.

[0023] Controller 1200 may include processor 1210, NAND controller 1220, and host interface 1230. According to an embodiment, electronic system 1000 may include multiple three-dimensional semiconductor memory devices 1100, in which case controller 1200 may control multiple three-dimensional semiconductor memory devices 1100.

[0024] The processor 1210 may control the overall operation of the electronic system 1000 including the controller 1200. The processor 1210 may operate according to a predetermined firmware and may control the NAND controller 1220 to access the three-dimensional semiconductor memory device 1100. The NAND controller 1220 may include a NAND interface 1221 that processes communication with the three-dimensional semiconductor memory device 1100. A control command for controlling the three-dimensional semiconductor memory device 1100, data to be written in the memory cell transistors MCT of the three-dimensional semiconductor memory device 1100, data to be read from the memory cell transistors MCT of the three-dimensional semiconductor memory device 1100, etc. may be transmitted through the NAND interface 1221. The host interface 1230 may provide a communication function between the electronic system 1000 and an external host. When a control command is received from the external host through the host interface 1230, the processor 1210 may control the three-dimensional semiconductor memory device 1100 in response to the control command.

[0025] FIG. 2 is a schematic perspective view of an electronic system including a three-dimensional semiconductor memory device according to an embodiment of the present invention.

[0026] 2, an electronic system 2000 according to an embodiment of the present invention may include a main board 2001, a controller 2002 mounted on the main board 2001, one or more semiconductor packages 2003, and a DRAM 2004. The semiconductor packages 2003 and the DRAM 2004 may be connected to the controller 2002 by a wiring pattern 2005 provided on the main board 2001.

[0027] The main board 2001 may include a connector 2006 including a plurality of pins to be coupled to an external host. The number and arrangement of the plurality of pins in the connector 2006 may vary depending on a communication interface between the electronic system 2000 and the external host. The electronic system 2000 may communicate with the external host according to any one of interfaces such as Universal Serial Bus (USB), Peripheral Component Interconnect Express (PCI-Express), Serial Advanced Technology Attachment (SATA), M-Phy for Universal Flash Storage (UFS), etc. The electronic system 2000 may be operated by power supplied from the external host through the connector 2006, for example. The electronic system 2000 may further include a Power Management Integrated Circuit (PMIC) that distributes power supplied from the external host to the controller 2002 and the semiconductor package 2003.

[0028] The controller 2002 can write data to or read data from the semiconductor package 2003 , which can improve the operating speed of the electronic system 2000 .

[0029] The DRAM 2004 may be a buffer memory for mitigating the difference in speed between the semiconductor package 2003, which is a data storage space, and an external host. The DRAM 2004 included in the electronic system 2000 may also operate as a kind of cache memory and provide space for temporarily storing data in a control operation for the semiconductor package 2003. When the electronic system 2000 includes the DRAM 2004, the controller 2002 may further include a DRAM controller for controlling the DRAM 2004 in addition to a NAND controller for controlling the semiconductor package 2003.

[0030] The semiconductor package 2003 may include first and second semiconductor packages 2003a and 2003b spaced apart from each other. Each of the first and second semiconductor packages 2003a and 2003b may be a semiconductor package including a plurality of semiconductor chips 2200. Each of the first and second semiconductor packages 2003a and 2003b may include a package substrate 2100, a semiconductor chip 2200 on the package substrate 2100, an adhesive layer 2300 disposed on a lower surface of each of the semiconductor chips 2200, a connection structure 2400 that electrically connects the semiconductor chip 2200 and the package substrate 2100, and a molding layer 2500 that covers the semiconductor chip 2200 and the connection structure 2400 on the package substrate 2100.

[0031] The package substrate 2100 may be a printed circuit board including a package upper pad 2130. Each semiconductor chip 2200 may include an I / O pad 2210. Each of the I / O pads 2210 may correspond to the I / O pad 1101 of FIG. 1. Each of the semiconductor chips 2200 may include a gate stack structure 3210 and a memory channel structure 3220. Each of the semiconductor chips 2200 may include a three-dimensional semiconductor memory device, as described below.

[0032] The connecting structure 2400 may be, for example, a bonding wire electrically connecting the I / O pad 2210 and the package upper pad 2130. Therefore, in each of the first and second semiconductor packages 2003a and 2003b, the semiconductor chips 2200 may be electrically connected to each other in a bonding wire manner and may be electrically connected to the package upper pad 2130 of the package substrate 2100. According to an embodiment, in each of the first and second semiconductor packages 2003a and 2003b, the semiconductor chips 2200 may be electrically connected to each other by through silicon vias instead of the connecting structure 2400 in the bonding wire manner.

[0033] Unlike what is illustrated, the controller 2002 and the semiconductor chip 2200 may be included in one package. The controller 2002 and the semiconductor chip 2200 may be mounted on an interposer substrate different from the main substrate 2001, and the controller 2002 and the semiconductor chip 2200 may be connected to each other by wiring provided on the interposer substrate.

[0034] 3 and 4 are cross-sectional views illustrating a semiconductor package including a three-dimensional semiconductor memory device according to an embodiment of the present invention, and correspond to cross-sections taken along lines II' and II-II' in FIG. 2, respectively.

[0035] 3 and 4, a semiconductor package 2003 may include a package substrate 2100 , a plurality of semiconductor chips 2200 on the package substrate 2100 , and a molding layer 2500 covering the package substrate 2100 and the semiconductor chips 2200 .

[0036] The package substrate 2100 may include a package substrate body part 2120, an upper pad 2130 disposed on an upper surface of the package substrate body part 2120 or exposed through the upper surface, a lower pad 2125 disposed on a lower surface of the package substrate body part 2120 or exposed through the lower surface, and an internal wiring 2135 electrically connecting the upper pad 2130 and the lower pad 2125 inside the package substrate body part 2120. The upper pad 2130 may be electrically connected to a connecting structure 2400. The lower pad 2125 may be connected to a wiring pattern 2005 of a main substrate 2001 of the electronic system 2000 shown in FIG. 2 through a conductive connecting part 2800.

[0037] 2 and 3, one sidewall of the semiconductor chip 2200 may be misaligned, and other sidewalls of the semiconductor chip 2200 may be aligned. The semiconductor chips 2200 may be electrically connected to each other by a bonding wire-shaped connecting structure 2400. Each of the semiconductor chips 2200 may include substantially the same configuration.

[0038] Each of the semiconductor chips 2200 may include a semiconductor substrate 4010, a first structure 4100 on the semiconductor substrate 4010, and a second structure 4200 on the first structure 4100. The second structure 4200 may be bonded to the first structure 4100 by a wafer bonding method.

[0039] The first structure 4100 may include a peripheral circuit wiring 4110 and a first bonding pad 4150. The second structure 4200 may include a common source line 4205, a gate stack structure 4210 between the common source line 4205 and the first structure 4100, a memory channel structure 4220 and an isolation structure 4230 penetrating the gate stack structure 4210, and a second bonding pad 4250 electrically connected to the memory channel structure 4220 and the word line (WL in FIG. 1) of the gate stack structure 4210. For example, the second bonding pad 4250 may be electrically connected to the memory channel structure 4220 and the word line (WL in FIG. 1) through a gate connecting wiring 4235 electrically connected to the bit line 4240 electrically connected to the memory channel structure 4220 and the word line (WL in FIG. 1), respectively. The first bonding pad 4150 of the first structure 4100 and the second bonding pad 4250 of the second structure 4200 may be coupled while being in contact with each other. The coupled portions of the first bonding pad 4150 and the second bonding pad 4250 may include, for example, copper (Cu).

[0040] Each of the semiconductor chips 2200 may further include an I / O pad 2210 and an I / O connecting wire 4265 below the I / O pad 2210. The I / O connecting wire 4265 may be electrically connected to a portion of the second bonding pad 4250 and a portion of the peripheral circuit wire 4110.

[0041] Fig. 5 is a plan view of a three-dimensional semiconductor memory device according to an embodiment of the present invention, Fig. 6 is a cross-sectional view corresponding to lines AA' and BB' in Fig. 5, and Fig. 7 is an enlarged view corresponding to P2 in Fig. 6.

[0042] 5 to 7, a three-dimensional semiconductor memory device according to the present invention may include a peripheral circuit structure PS and a cell array structure CS stacked on a peripheral substrate 10. The peripheral substrate 10 may correspond to the semiconductor substrate 4010 of FIGS. 3 and 4. The peripheral circuit structure PS may correspond to the first structure 4100 of FIGS. 3 and 4. The cell array structure CS may correspond to the second structure 4200 of FIGS. 3 and 4.

[0043] By combining the cell array structure CS on the peripheral circuit structure PS, the cell capacity per unit area of ​​the three-dimensional semiconductor memory device according to the present invention can be increased. Also, the method of manufacturing and combining the peripheral circuit structure PS and the cell array structure CS can prevent damage to the peripheral transistor PTR, which will be described later, due to various heat treatment processes, thereby improving the electrical characteristics and reliability of the three-dimensional semiconductor memory device according to the present invention.

[0044] The peripheral substrate 10 may be, for example, a silicon substrate, a silicon-germanium substrate, a germanium substrate, or a monocrystalline epitaxial layer grown on a monocrystalline silicon substrate. The peripheral substrate 10 may have an upper surface perpendicular to a first direction D1. The upper surface of the peripheral substrate 10 may be parallel to a second direction D2 and a third direction D3 intersecting each other. The first to third directions D1, D2, and D3 may be, for example, perpendicular to each other. An isolation layer 15 may be provided in the peripheral substrate 10. The isolation layer 15 may define an active region of the peripheral substrate 10.

[0045] The peripheral circuit structure PS may include a peripheral transistor PTR on a peripheral substrate 10, a peripheral contact plug 31, a peripheral circuit wiring 33 electrically connected to the peripheral transistor PTR through the peripheral contact plug 31, a first bonding pad 35 electrically connected to the peripheral circuit wiring 33, and a first insulating film 30 surrounding them. The peripheral transistor PTR may be provided on an active region of the peripheral substrate 10. The peripheral circuit wiring 33 may correspond to the peripheral circuit wiring 4110 in FIGS. 3 and 4, and the first bonding pad 35 may correspond to the first bonding pad 4150 in FIGS. 3 and 4.

[0046] For example, the peripheral contact plug 31 may have a width in a second direction D2 or a third direction D3 that increases in a first direction D1. The peripheral contact plug 31 and the peripheral circuit wiring 33 may include a conductive material such as a metal.

[0047] The peripheral transistors PTR may constitute, for example, a decoder circuit (1110 in FIG. 1), a page buffer (1120 in FIG. 1), a logic circuit (1130 in FIG. 1), etc. The peripheral circuit wiring 33 and the first bonding pad 35 may be electrically connected to the peripheral transistors PTR through the peripheral contact plugs 31. Each of the peripheral transistors PTR may be, for example, an NMOS transistor or a PMOS transistor.

[0048] A first insulating film 30 may be provided on the peripheral substrate 10. The first insulating film 30 may cover the peripheral transistor PTR, the peripheral contact plug 31, and the peripheral circuit wiring 33 on the peripheral substrate 10. The first insulating film 30 may include a plurality of insulating films having a multi-layer structure. For example, the first insulating film 30 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low dielectric material. The first insulating film 30 may not cover the upper surface of the first bonding pad 35. The upper surface of the first interlayer insulating film 30 may be substantially coplanar with the upper surface of the first bonding pad 35.

[0049] A cell array structure CS may be provided on the peripheral circuit structure PS. The cell array structure CS may include second bonding pads 45, bit lines BL, and stack structures ST. The second bonding pads 45, bit lines BL, and stack structures ST may correspond to the second bonding pads 4250, bit lines 4240, and gate stack structures 4210 in FIGS. 3 and 4, respectively.

[0050] The cell array structure CS may include a cell array region CAR and a cell array extension region EXR, which may extend from the cell array region CAR in a second direction D2, a third direction D3, or an opposite direction thereto.

[0051] The second bonding pad 45 may contact the first bonding pad 35 of the peripheral circuit structure PS. The cell circuit wiring 43 may be electrically connected to the second bonding pad 45 through the cell contact plug 41. A second insulating layer 40 may surround the cell contact plug 41, the cell circuit wiring 43, and the second bonding pad 45. The second insulating layer 40, the cell contact plug 41, the cell circuit wiring 43, and the second bonding pad 45 may be provided on the first insulating layer 30.

[0052] The second insulating film 40 may include a plurality of insulating films having a multi-layer structure, for example, the second insulating film 40 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low dielectric material.

[0053] For example, the width of the cell contact plug 41 in the second direction D2 or the third direction D3 may decrease in the first direction D1. The cell contact plug 41 and the cell circuit wiring 43 may include a conductive material such as a metal.

[0054] Some of the cell contact plugs 41 may connect bit lines BL to vertical structures VS, which will be described later. Each of the bit lines BL may extend in, for example, a third direction D3 and may be spaced apart from each other in the second direction D2. The bit lines BL may include a conductive material, such as a metal.

[0055] The second insulating film 40 may not cover the lower surface of the second bonding pad 45. The lower surface of the second insulating film 40 may be substantially coplanar with the lower surface of the second bonding pad 45. The lower surface of each of the second bonding pads 45 may directly contact the upper surface of each of the first bonding pads 35. The first and second bonding pads 35, 45 may include a metal such as copper (Cu), tungsten (W), aluminum (Al), nickel (Ni), or tin (Sn). As an example, the first and second bonding pads 35, 45 may include copper (Cu). The first and second bonding pads 35, 45 may be integral with each other without an interface therebetween. Although the sidewalls of the first and second bonding pads 35, 45 are illustrated as being aligned side by side, the present invention is not limited thereto, and the sidewalls of the first and second bonding pads 35, 45 may be spaced apart from each other in a plan view.

[0056] A stack structure ST and a third insulating film (not shown) may be provided on the second insulating film 40. The third insulating film may surround the stack structure ST. The third insulating film may include a plurality of insulating films having a multi-layer structure. The third insulating film may include at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low dielectric material. For example, the third insulating film may include high density plasma oxide (HDP oxide) or TEOS (TetraEthylOrthoSilicate).

[0057] A plurality of stacked structures ST may be provided. As an example, in a plan view, the plurality of stacked structures ST may each extend in the second direction D2 and be spaced apart from each other in the third direction D3. The stacked structures ST may be spaced apart from each other in the third direction D3 by a separation trench STR, which will be described later. Although a single stacked structure ST will be described below for ease of description, the following description may be similarly applied to other stacked structures ST.

[0058] The stacked structure ST may include a first stacked structure ST1 and a second stacked structure ST2. The first stacked structure ST1 may include a first interlayer insulating film ILD1 and a first gate electrode GE1 that are alternately stacked, and the second stacked structure ST2 may include a second interlayer insulating film ILD2 and a second gate electrode GE2 that are alternately stacked (see FIG. 6).

[0059] The first stacked structure ST1 may be provided on the peripheral substrate 10, and the second stacked structure ST2 may be provided between the first stacked structure ST1 and the peripheral substrate 10. More specifically, the second stacked structure ST2 may be provided on the lower surface of the first interlayer insulating film ILD1 of the first stacked structure ST1, which is the lowest layer among the first interlayer insulating film ILD1 of the first stacked structure ST1. The second interlayer insulating film ILD2 of the uppermost layer among the second interlayer insulating film ILD2 of the second stacked structure ST2 and the first interlayer insulating film ILD1 of the lowermost layer of the first stacked structure ST1 may be in contact with each other, but the present invention is not limited thereto. For example, a single-layer interlayer insulating film may be provided between the uppermost layer among the second gate electrode GE2 of the second stacked structure ST2 and the first gate electrode GE1 of the first stacked structure ST1.

[0060] The first and second gate electrodes GE1 and GE2 may include at least one selected from a doped semiconductor (ex, doped silicon, etc.), a metal (ex, tungsten, copper, aluminum, etc.), a conductive metal nitride (ex, titanium nitride, tantalum nitride, etc.), or a transition metal (ex, titanium, tantalum, etc.). The first and second interlayer insulating films ILD1 and ILD2 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low dielectric material. For example, the first and second interlayer insulating films ILD1 and ILD2 may include high density plasma oxide (HDP oxide) or TEOS (TetraEthylOrthoSilicate).

[0061] As an example, although not shown, a third stacked structure may be further provided between the second stacked structure ST2 and the peripheral substrate 10. The characteristics of the third stacked structure may be the same / similar to the characteristics of the first stacked structure ST1 and the second stacked structure ST2.

[0062] Although not shown, in a cross-sectional view, the stacked structure ST may have a step structure along the second direction D2 on the cell array extension region EXR. In other words, the thickness of the stacked structure ST along the first direction D1 on the cell array extension region EXR may decrease as it moves away from the cell array region CAR. The first and second gate electrodes GE1 and GE2 may have an increased length in the second direction D2 as it moves away from the peripheral substrate 10. Among the first and second gate electrodes GE1 and GE2, the second gate electrode GE2 at the bottom may have the shortest length, and the first gate electrode GE1 at the top may have the longest length. The sidewalls of the first and second gate electrodes GE1 and GE2 may be spaced apart from each other by a predetermined distance along the second direction D2 in a plan view. Each of the first and second gate electrodes GE1 and GE2 may include a pad part PAD that is one end along the second direction D2. The pad part PAD may be a region of each of the first and second gate electrodes GE1 and GE2 constituting a step portion of the stacked structure ST. The through plugs TP may extend in a first direction D1 and be electrically connected to the pad parts PAD.

[0063] At least one of the first gate electrodes GE1 may be a ground selection line GSL. The ground selection line GSL may control a ground selection transistor among the first transistors LT1 and LT2 described with reference to FIG 1. As an example, the ground selection line GSL may be located on the upper portion of the stack structure ST.

[0064] The channel holes CH may penetrate the cell array structure CS in the cell array region CAR and the cell array extension region EXR. Each of the channel holes CH may penetrate at least one of the stack structure ST and the third insulating film in the first direction D1. As an example, each of the channel holes CH may include a first channel hole CH1 penetrating the first stack structure ST1 and a second channel hole CH2 penetrating the second stack structure ST2. Each of the first and second channel holes CH1 and CH2 may have a reduced width in the second direction D2 and / or the third direction D3 as it becomes farther from the peripheral substrate 10. The first and second channel holes CH1 and CH2 may be connected to each other and may have different diameters at the boundary where they are connected to each other. Specifically, the diameter of the upper part of the second channel hole CH2 may be smaller than the diameter of the lower part of the first channel hole CH1. The first and second channel holes CH1 and CH2 may have a step at the boundary where they are connected to each other. However, the present invention is not limited thereto, and as an example, different from that shown in the drawings, three or more channel holes each having a step at two or more boundaries may be provided. As another example, unlike that shown in the drawings, a channel hole may be provided that has flat sidewalls without a step.

[0065] In the cell array region CAR, the vertical structure VS may penetrate the stack structure ST in a first direction D1 and fill the channel hole CH. The vertical structure VS may correspond to the memory channel structure 4220 of FIGS. 3 and 4. A channel pad CHP may be provided under the vertical structure VS. The vertical structure VS may be electrically connected to the cell contact plug 41 and the bit line BL through the channel pad CHP. In the cell array extension region EXR, the dummy vertical structure DVS may penetrate at least one of the stack structure ST and the third insulating film in the first direction D1 and fill the channel hole CH. Each of the lower surfaces of the vertical structure and the dummy vertical structure VS and DVS may have, for example, a circular, elliptical, or bar shape.

[0066] Each of the vertical structures VS may include a data storage pattern DSP conformally covering an inner sidewall of the channel hole CH, a vertical semiconductor pattern VSP conformally covering a sidewall of the data storage pattern DSP, and a buried insulating pattern VI surrounded by the vertical semiconductor pattern VSP and the channel pad CHP and filling an inner space of the channel hole CH. The vertical semiconductor pattern VSP may be provided between the data storage pattern DSP and the buried insulating pattern VI. The vertical semiconductor pattern VSP may have a pipe shape or a macaroni shape with a closed upper end. The data storage pattern DSP may have a pipe shape with an open upper end. The vertical semiconductor pattern VSP may include, for example, a semiconductor material doped with impurities, an intrinsic semiconductor material not doped with impurities, or a polycrystalline semiconductor material. The channel pad CHP may include, for example, a semiconductor material doped with impurities or a conductive material.

[0067] The data storage pattern DSP may include a blocking insulating layer BLK, a charge storing layer CIL, and a tunneling insulating layer TIL, which are sequentially stacked on an inner sidewall of the channel hole CH (see FIG. 7). The charge storing layer CIL may be interposed between the blocking insulating layer BLK and the tunneling insulating layer TIL. The blocking insulating layer BLK, the charge storing layer CIL, and the tunneling insulating layer TIL may extend along an inner sidewall of the channel hole CH between the stacked structure ST and the vertical semiconductor pattern VSP. The data storage pattern DSP may not cover an upper portion of the vertical semiconductor pattern VSP in a channel contact hole CCH, which will be described later.

[0068] The data storage pattern DSP may store and / or change data by a Fowler-Nordheim tunneling phenomenon induced by a voltage difference between the vertical semiconductor pattern VSP and the first and second gate electrodes GE1 and GE2. For example, the blocking insulating layer BLK and the tunneling insulating layer TIL may include silicon oxide, and the charge storage layer CIL may include at least one of silicon nitride and silicon oxynitride.

[0069] An N-doped pattern ND may be provided on the stack structure ST. The N-doped pattern ND may cover the stack structure ST. The N-doped pattern ND may cover the uppermost first interlayer insulating film ILD1 among the first interlayer insulating films ILD1. The N-doped pattern ND may be provided on the cell array region CAR. As an example, although not shown, the N-doped pattern ND may be further provided on the cell array extension region EXR. The N-doped pattern ND may include a semiconductor material doped with N-type impurities. As an example, the N-doped pattern ND may include polysilicon doped with N-type impurities.

[0070] The undoped pattern UD may be provided on the N-doped pattern ND. The undoped pattern UD may cover the N-doped pattern ND. The undoped pattern UD may be provided on the cell array region CAR. As an example, the undoped pattern UD may be further provided on the cell array extension region EXR (not shown). The undoped pattern UD may include a semiconductor material that is not doped with impurities or is doped with a small amount of impurities. As an example, the undoped pattern UD may include polysilicon that is not doped with impurities. As another example, the undoped pattern UD may include polysilicon that is doped with a small amount of impurities compared to the N-doped pattern ND and a P-doped pattern PD to be described later. At this time, the impurities in the undoped pattern UD are diffused from the N-doped pattern ND or the P-doped pattern PD, and therefore the undoped pattern UD may include a relatively small amount of impurities.

[0071] A channel contact hole CCH may be provided in the N-doped pattern ND and the undoped pattern UD. The channel contact hole CCH may extend along a first direction D1 in the N-doped pattern ND and the undoped pattern UD. Each of the plurality of channel contact holes CCH may be provided on a corresponding vertical structure VS and may overlap the corresponding vertical structure VS in a vertical direction.

[0072] The vertical structure VS may be extended into the N-doped pattern ND, and an upper portion of the vertical structure VS may be located in the channel contact hole CCH. As an example, the vertical semiconductor pattern VSP and the buried insulation pattern VI may be extended into the N-doped pattern ND, and an upper portion thereof may be located in the channel contact hole CCH. In the channel contact hole CCH, an upper portion of the vertical semiconductor pattern VSP may surround an upper portion of the buried insulation pattern VI. An upper portion of the vertical semiconductor pattern VSP may contact a P-doped pattern PD, which will be described later, in the channel contact hole CCH. As an example, an upper portion of the vertical semiconductor pattern VSP may include P-type impurities.

[0073] A P-doped pattern PD may be provided on the undoped pattern UD. The P-doped pattern PD may cover the undoped pattern UD. The P-doped pattern PD may be provided on the cell array region CAR. As an example, although not shown, the P-doped pattern PD may be further provided on the cell array extension region EXR. The P-doped pattern PD may include a semiconductor material doped with P-type impurities. As an example, the P-doped pattern PD may include polysilicon doped with P-type impurities.

[0074] The P-doped pattern PD may include a P-doped horizontal pattern PDy and a P-doped vertical pattern PDx. The P-doped horizontal pattern PDy may cover the undoped pattern UD. The P-doped vertical pattern PDx may extend from the P-doped horizontal pattern PDy toward the vertical structure VS. The P-doped vertical pattern PDx may penetrate the undoped pattern UD and the N-doped pattern ND and fill the channel contact hole CCH. The P-doped vertical pattern PDx may contact the vertical structure VS within the channel contact hole CCH. For example, the P-doped vertical pattern PDx may contact the top of the vertical semiconductor pattern VSP within the channel contact hole CCH and may be electrically connected to the vertical semiconductor pattern VSP. For example, the P-doped vertical pattern PDx may contact the vertical semiconductor pattern VSP without an interface.

[0075] The undoped pattern UD may be interposed between the P-doped pattern PD and the N-doped pattern ND. As an example, the undoped pattern UD may be interposed between the P-doped horizontal pattern PDy and the N-doped pattern ND and may extend in the second direction D2 and the third direction D3. The undoped pattern UD may separate the P-doped horizontal pattern PDy and the N-doped pattern ND. The undoped pattern UD may separate the P-doped horizontal pattern PDy and the N-doped pattern ND, thereby minimizing junction leakage between the P-doped pattern PD and the N-doped pattern ND. Therefore, electrical characteristics and reliability of the three-dimensional semiconductor memory device may be improved.

[0076] The P doping pattern PD can be used as a path for providing holes to the vertical structure VS in a data erase operation of the three-dimensional semiconductor memory device. An erase operation for a plurality of memory cell transistors MCT can be simultaneously performed through the P doping pattern PD. Therefore, the speed of performing an erase operation of the three-dimensional semiconductor memory device can be improved, and as a result, the performance of the three-dimensional semiconductor memory device can be improved.

[0077] The isolation trenches STR may extend in the second direction D2. The isolation trenches STR may separate the stack structures ST from each other in the third direction D3. The isolation trenches STR may extend from the cell array region CAR toward the cell array extension region EXR.

[0078] As an example, each of the isolation trenches STR may include a first isolation trench STR1 penetrating the first stack structure ST1 and a second isolation trench STR2 penetrating the second stack structure ST2. The width of each of the first and second isolation trenches STR1 and STR2 in the second direction D2 and / or the third direction D3 may decrease as it becomes farther from the peripheral substrate 10. The first and second isolation trenches STR1 and STR2 may be connected to each other and may have different widths at the boundary where they are connected to each other. Specifically, the diameter of the upper part of the second isolation trench STR2 may be smaller than the diameter of the lower part of the first isolation trench STR1. The first and second isolation trenches STR1 and STR2 may have a step at the boundary where they are connected to each other. However, the present invention is not limited thereto, and as an example, unlike what is illustrated, three or more isolation trenches each having a step at two or more boundaries may be provided. As another example, unlike what is illustrated, an isolation trench having a flat sidewall without a step may be provided.

[0079] The isolation pattern SS may fill the isolation trench STR. The isolation pattern SS may correspond to the isolation structure 4230 in Figures 3 and 4. Sidewalls of the isolation pattern SS may contact at least a portion of the first and second gate electrodes GE1, GE2 and the first and second interlayer insulating films ILD1, ILD2 of the stack structure ST. The isolation pattern SS may be provided between a plurality of stack structures ST and may space the stack structures ST from each other in the third direction D3.

[0080] The separation pattern SS may include a metal contact MC extending in a first direction D1 between adjacent stacked structures ST, and a separation insulating pattern SI between the metal contact MC and the stacked structures ST. The metal contact MC may be further extended into the N-doped pattern ND and may be in contact with the N-doped pattern ND. The metal contact MC may be separated from the stacked structures ST by the separation insulating pattern SI. The metal contact MC may protrude further in the first direction D1 than the separation insulating pattern SI. The metal contact MC may include a metal and a conductive material. The separation insulating pattern SI may include at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low-k material.

[0081] The metal contact MC may be electrically connected to the N-doped pattern ND. The metal contact MC may provide electrons to the vertical structure VS through the N-doped pattern ND.

[0082] An upper insulating layer UI may be provided on the P doping pattern PD. A P contact hole PCH may be provided in the upper insulating layer UI and the P doping pattern PD. The P contact hole PCH may extend from an upper surface of the upper insulating layer UI to an upper portion of the P doping pattern PD. A P contact plug PC may fill the P contact hole PCH. The P contact plug PC may be electrically connected to and contact the P doping pattern PD. An upper circuit wiring UL may be provided on the upper insulating layer UI and the P contact plug PC. The upper circuit wiring UL may be electrically connected to the P doping pattern PD through the P contact plug PC. The upper circuit wiring UL may electrically control the P doping pattern PD. The P contact plug PC and the upper circuit wiring UL may include a conductive material such as a metal.

[0083] Hereinafter, various embodiments of a three-dimensional semiconductor memory device according to the concept of the present invention will be described with reference to Figures 8 to 16. For the sake of simplicity, descriptions that overlap with those described above will be omitted.

[0084] Figures 8, 10, and 11 are enlarged views corresponding to P2 in Figure 6. Figures 9A and 9B are enlarged views corresponding to P1 in Figure 5, which respectively correspond to P1 shown at the first and second levels in Figure 8. Figure 12 is a plan view showing a three-dimensional semiconductor memory device according to an embodiment of the present invention.

[0085] 8 to 9B, the doping concentration of each of the N-doping pattern ND and the P-doping pattern PD may be different for each region. In this specification, the doping concentration of the N-doping pattern ND means the doping concentration of the N-type impurity, and the doping concentration of the P-doping pattern PD means the doping concentration of the P-type impurity.

[0086] The doping concentration of the N-doped pattern ND may change downward. For example, the doping concentration of the N-doped pattern ND may increase continuously or discontinuously downward. In this specification, discontinuous change in doping concentration is defined to include a case where the doping concentration is continuous but shows a relatively large change amount compared to other regions.

[0087] The doping concentration of the N-doped pattern ND may decrease as it approaches the non-doped pattern UD. As an example, the N-doped pattern ND may include a first N-doped region ND1, a second N-doped region ND2, and a third N-doped region ND3 defined in sequence from the bottom. The second N-doped region ND2 may have a lower doping concentration than the first N-doped region ND1 and a higher doping concentration than the third N-doped region ND3. As an example, the doping concentration may decrease discontinuously at the boundary as moving from the first N-doped region ND1 to the second N-doped region ND2 or moving from the second N-doped region ND2 to the third N-doped region ND3. As another example, the third N-doped region ND3 may not be defined. As another example, a fourth N-doped region (not shown) may be further defined.

[0088] The doping concentration of the P-doped pattern PD may vary as it is adjacent to the undoped pattern UD or the N-doped pattern ND. For example, the doping concentration of the P-doped horizontal pattern PDy may decrease continuously or discontinuously as it goes downward. For example, the doping concentration of the P-doped vertical pattern PDx may decrease continuously or discontinuously as it is adjacent to the inner wall of the channel contact hole CCH.

[0089] As an example, the P doping pattern PD may include a first P doping region PD1 and a second P doping region PD2 having a doping concentration higher than the first P doping region PD1. The first P doping region PD1 may be defined on an inner wall of the channel contact hole CCH and on an upper surface of the undoped pattern UD. The second P doping region PD2 may fill the channel contact hole CCH and cover the first P doping region PD1 on an upper surface of the undoped pattern UD. As an example, the doping concentration may be discontinuously decreased at the boundary between the second P doping region PD2 and the first P doping region PD1. As another example, a third P doping region (not shown) may be further defined.

[0090] The lower portion of the P-doped vertical pattern PDx may be surrounded by an N-doped pattern ND, for example, the P-doped vertical pattern PDx may be surrounded by an N-doped pattern ND at the first level LV1. The upper portion of the P-doped vertical pattern PDx may be surrounded by a non-doped pattern UD, for example, the P-doped vertical pattern PDx may be surrounded by a non-doped pattern UD at the second level LV2.

[0091] In plan view, the doping concentration of the lower portion of the P-doped vertical pattern PDx may decrease continuously or discontinuously as it approaches the N-doped pattern ND (see FIG. 9A). As an example, in the first level LV1, the second P-doped region PD2 may fill the channel contact hole CCH, and the first P-doped region PD1 may be provided between the second P-doped region PD2 and the N-doped pattern ND. The doping concentration of the lower portion of the P-doped vertical pattern PDx may decrease discontinuously at the boundary as it moves from the second P-doped region PD2 to the first P-doped region PD1.

[0092] In plan view, the doping concentration of the upper part of the P-doped vertical pattern PDx may decrease continuously or discontinuously as it approaches the undoped pattern UD (see FIG. 9B). As an example, in the second level LV2, a second P-doped region PD2 may fill the channel contact hole CCH, and a first P-doped region PD1 may be provided between the second P-doped region PD2 and the N-doped pattern ND. The doping concentration of the upper part of the P-doped vertical pattern PDx may decrease discontinuously at the boundary as it moves from the second P-doped region PD2 to the first P-doped region PD1.

[0093] By controlling the doping concentrations of the N-doped pattern ND and the P-doped pattern PD, the junction leakage between them can be minimized, thereby improving the electrical characteristics and reliability of the three-dimensional semiconductor memory device.

[0094] Referring to FIG. 10, the P doping pattern PD may include an ohmic region OR. The ohmic region OR may be a region containing N-type impurities. The ohmic region OR may be adjacent to the P contact plug PC. As an example, the ohmic region OR may be provided along an outer wall of the P contact hole PCH. The P contact plug PC and the P doping pattern PD may form an ohmic junction through the ohmic region OR. As an example, the N doping concentration of the ohmic region OR may vary from region to region, but is not limited thereto.

[0095] 11 and 12, the metal contacts MC may be provided in a separate configuration from the separation pattern SS. As an example, the separation pattern SS may not include the metal contacts MC.

[0096] 11, a metal contact trench MTR may penetrate the P-doped pattern PD and the undoped pattern UD and may extend into the N-doped pattern ND. A metal contact MC may fill the metal contact trench MTR. The metal contact MC may contact and be electrically connected to the N-doped pattern ND. As an example, an insulating spacer IS may be further provided on an inner wall of the metal contact trench MTR. The insulating spacer IS may separate the metal contact MC from the P-doped pattern PD and the undoped pattern UD.

[0097] 12, the metal contact MC may be spaced apart from the separation pattern SS in a plan view. In this case, as an example, the metal contact MC may extend from the stack structure ST into the N-doped pattern ND. As another example, the metal contact MC may extend from the P-doped pattern PD and the undoped pattern UD into the N-doped pattern ND. Although the metal contact MC is illustrated as having a line shape in a plan view, the concept of the present invention is not limited thereto.

[0098] Fig. 13 is a cross-sectional view corresponding to lines AA' and BB' in Fig. 5. Figs. 14 to 16 are enlarged views corresponding to P3 in Fig. 13.

[0099] 13 and 14, a P-doped pattern PD may cover the stack structure ST. Unlike the description with reference to FIG. 6, an N-doped pattern ND and a non-doped pattern UD may not be provided between the P-doped pattern PD and the stack structure ST.

[0100] A channel contact hole CCH may be provided in the stack structure ST. The channel contact hole CCH may be defined on the channel hole CH and may vertically overlap the channel hole CH. The channel contact hole CCH may penetrate the uppermost first gate electrode GE1 and the uppermost first interlayer insulating film ILD1. For example, the channel contact hole CCH may penetrate two or more first gate electrodes GE1 in the first gate electrode GE1 and two or more first interlayer insulating films ILD1 in the first interlayer insulating film ILD1. For example, the two or more first gate electrodes GE1 may be ground selection lines GSL, and the two or more first interlayer insulating films ILD1 may be referred to as ground interlayer insulating films Ig. In other words, there may be two or more ground selection lines GSL. For example, some of the first gate electrodes GE1 under the channel contact hole CCH may also be ground selection lines GSL.

[0101] The width of the channel contact hole CCH in the second direction D2 and / or the third direction D3 may increase downward. The width of the bottom end of the channel contact hole CCH in the second direction D2 and / or the third direction D3 may be greater than the width of the top end of the channel hole CH. The channel contact hole CCH and the channel hole CH may be connected to each other and may have a step at the connected boundary.

[0102] The vertical structure VS may include a head structure HV in the channel contact hole CCH and a through structure PV in the first and second channel holes CH1 and CH2. The through structure PV may be located below the head structure HV. In the second direction D2 and / or the third direction D3, the width of the bottom end of the head structure HV may be greater than the width of the top end of the through structure PV.

[0103] The head structure HV may include a first head portion HV1 on an inner wall of the channel contact hole CCH, and a second head portion HV2 connecting the first head portion HV1 and the through structure PV on an inner lower wall of the channel contact hole CCH. The first head portion HV1, the second head portion HV2, and the through structure PV may have a step shape and be connected to each other. For example, the buried insulating pattern VI of the second head portion HV2 may protrude further in the first direction D1 than the vertical semiconductor pattern VSP of the second head portion HV2. For example, the lower surface of the second head portion HV2 may contact the first gate electrode GE1, but is not limited thereto.

[0104] The P-doped pattern PD may include a P-doped vertical pattern PDx filling the channel contact hole CCH and a P-doped horizontal pattern PDy covering the stack structure ST. The P-doped vertical pattern PDx may be surrounded by the head structure HV within the channel contact hole CCH. The P-doped vertical pattern PDx may be protruded into the head structure HV. The P-doped vertical pattern PDx may contact and be electrically connected to the vertical semiconductor pattern VSP.

[0105] A contact trench CTR may be provided on the isolation trench STR. The contact trench CTR may be provided in the stack structure ST. The contact trench CTR may penetrate the uppermost first gate electrode GE1 and the uppermost first interlayer insulating film ILD1. As an example, the contact trench CTR may penetrate the first gate electrode GE1 and the first interlayer insulating film ILD1 through which the channel contact hole CCH penetrates.

[0106] The width of the contact trench CTR in the third direction D3 may increase as it goes downward. The width of the bottom end of the contact trench CTR in the third direction D3 may be greater than the width of the top end of the isolation trench STR. The contact trench CTR and the isolation trench STR may be connected to each other and may have a step at the boundary where they are connected.

[0107] The isolation insulating pattern SI may cover the inner walls of the contact trench CTR and the isolation trench STR. The isolation insulating pattern SI may have a step-shaped profile at the boundary between the contact trench CTR and the isolation trench STR.

[0108] The metal contact MC may include a head contact HC in the contact trench CTR, and a through contact PC filling the isolation trench STR under the head contact HC. A width of a bottom end of the head contact HC may be greater than a width of a top end of the through contact PC. The head contact HC may protrude further in the first direction D1 than the isolation insulating pattern SI. The head contact HC may extend into the P doping pattern PD and may be electrically connected to the P doping pattern PD. A void VD may be provided inside the metal contact MC and may be surrounded by the metal contact MC.

[0109] The P doping pattern PD may have an inversion region INR located adjacent to the stack structure ST between the vertical structure VS and the metal contact MC. The inversion region INR may be controlled by a ground selection line GSL. The ground selection line GSL may put the inversion region INR in an inversion state, and the inversion region INR may function as a channel through which electrons move between the metal contact MC and the vertical structure VS.

[0110] The ground selection line GSL may have a first pitch PI1 in a first direction D1. In this specification, a pitch may be defined as a minimum unit thickness or width at which a specific configuration is repeatedly provided. The ground interlayer insulating film Ig may have a first thickness TK1 in the first direction D1, and the ground selection line GSL may have a second thickness TK2 in the first direction D1. The first pitch PI1 may be defined as the sum of the first thickness TK1 and the second thickness TK2.

[0111] The characteristics and effects of the ground selection line GSL can be adjusted by freely adjusting the values ​​of the first pitch PI1, the first thickness TK1, and the second thickness TK2. As an example, by making the first thickness TK1 thick or by making the second thickness TK2 thin, damage to the 3D semiconductor memory device due to breakdown can be minimized. As another example, by making the first thickness TK1 thin or by making the second thickness TK2 thick, the ground selection line GSL can effectively control the inversion region INR.

[0112] Among the gate electrodes GE1 and GE2, the gate electrode of the memory cell transistor MCT may have a second pitch PI2 in the first direction D1. Among the interlayer insulating films ILD1 and ILD2, the interlayer insulating films other than the ground interlayer insulating film Ig may have a third thickness TK3 in the first direction D1, and the gate electrode of the memory cell transistor MCT may have a fourth thickness TK4 in the first direction D1. The second pitch PI2 may be defined as the sum of the third thickness TK3 and the fourth thickness TK4. The first pitch PI1 and the second pitch PI2 may be the same or different from each other. The first thickness TK1 and the third thickness TK3 may be the same or different from each other. The second thickness TK2 and the fourth thickness TK4 may be the same or different from each other.

[0113] 15, the first interlayer insulating film ILD1 may further include an additional insulating film Ia. The additional insulating film Ia may cover a lower surface of the second head portion HV2 and may separate the second head portion HV2 from the first gate electrode GE1 thereunder. For example, the additional insulating film Ia may be connected to the first interlayer insulating film ILD1 adjacent to the first direction D1 without an interface. The additional insulating film Ia may adjust the pitch of the ground selection line GSL in a region adjacent to the lower end of the head structure HV.

[0114] 16, the P doping pattern PD may include an ohmic region OR. The ohmic region OR may be a region containing N-type impurities. The ohmic region OR may be adjacent to the P contact plug PC. As an example, the ohmic region OR may be provided along an outer wall of the P contact hole PCH. The P contact plug PC and the P doping pattern PD may form an ohmic junction through the ohmic region OR.

[0115] 17 to 23 are cross-sectional views illustrating a method for manufacturing a three-dimensional semiconductor memory device according to an embodiment of the present invention. Hereinafter, the method for manufacturing the three-dimensional semiconductor memory device described with reference to FIG. 6 will be described with reference to FIG.

[0116] 5 and 17, a peripheral circuit structure PS may be formed on a peripheral substrate 10. Forming the peripheral circuit structure PS may include forming an isolation film 15 within the peripheral substrate 10, forming a peripheral transistor PTR on an active region of the peripheral substrate 10 defined by the isolation film 15, and forming a peripheral contact plug 31 electrically connected to the peripheral transistor PTR, a peripheral circuit wiring 33, a first bonding pad 35, and a first insulating film 30 covering them.

[0117] The top surface of the first bonding pad 35 may be substantially coplanar with the top surface of the first insulating film 30. Hereinafter, being substantially coplanar means that a planarization process may be performed. The planarization process may be performed, for example, through a chemical mechanical polishing (CMP) process or an etch back process.

[0118] 18 and 19, 'top' may refer to 'bottom' in terms of the three-dimensional semiconductor memory device whose fabrication has been completed as described with reference to Fig. 6, and 'bottom' may refer to 'top' in terms of the three-dimensional semiconductor memory device whose fabrication has been completed as described with reference to Fig. 6. Similarly, 'top' and 'bottom' may refer to 'bottom' and 'top', respectively, in terms of the three-dimensional semiconductor memory device whose fabrication has been completed as described with reference to Fig. 6.

[0119] 5 and 18, a cell array substrate 100 may be provided. The cell array substrate 100 may include a first cell array substrate 110, a second cell array substrate 120, and a third cell array substrate 130, which are sequentially stacked.

[0120] The first cell array substrate 110 may be, for example, a silicon substrate, a silicon-germanium substrate, a germanium substrate, or a monocrystalline epitaxial layer grown on a monocrystalline silicon substrate. The second cell array substrate 120 may include a material having an etch selectivity with respect to the first cell array substrate 110. For example, the second cell array substrate 120 may include silicon oxide. The third cell array substrate 130 may include a semiconductor material, for example, polysilicon.

[0121] A mold structure ML may be formed on the cell array substrate 100. The mold structure ML may include a first mold structure ML1 and a second mold structure ML2 on the first mold structure ML1. Forming the mold structure ML may include sequentially forming the first mold structure ML1 and the second mold structure ML2.

[0122] In detail, first, a first mold structure ML1 may be formed on the cell array substrate 100. Forming the first mold structure ML1 may include alternately stacking a first interlayer dielectric film ILD1 and a first sacrificial film SL1. In the first mold structure ML1, the first sacrificial film SL1 may be formed of a material that has an etching selectivity with respect to the first interlayer dielectric film ILD1 and can be etched. For example, the first sacrificial film SL1 may be formed of a different insulating material than the first interlayer dielectric film ILD1. For example, the first sacrificial film SL1 may be formed of silicon nitride, and the first interlayer dielectric film ILD1 may be formed of silicon oxide.

[0123] Then, a first channel hole CH1 and a first isolation trench STR1 may be formed to penetrate the first interlayer insulating film ILD1 and the first sacrificial film SL1 in a first direction D1. The first channel hole CH1 and the first isolation trench STR1 may be formed through an anisotropic etching process on the first mold structure ML1. The first channel hole CH1 and the first isolation trench STR1 may extend into the third cell array substrate 130.

[0124] A second mold structure ML2 may be formed on the first mold structure ML1. The second mold structure may include alternately stacking a second interlayer dielectric film ILD2 and a second sacrificial film SL2. The characteristics of the second interlayer dielectric film ILD2 and the second sacrificial film SL2 may be the same / similar to those of the first interlayer dielectric film ILD1 and the first sacrificial film SL1.

[0125] Thereafter, a second channel hole CH2 and a second isolation trench STR2 may be formed to penetrate the second interlayer insulating film ILD2 and the second sacrificial film SL2 in the first direction D1. The second channel hole CH2 and the second isolation trench STR2 may be formed through an anisotropic etching process on the second mold structure ML2. The second channel hole CH2 and the second isolation trench STR2 may overlap the first channel hole CH1 and the first isolation trench STR1 in a vertical direction, respectively. The first channel hole CH1 and the second channel hole CH2 may constitute a channel hole CH. The first isolation trench STR1 and the second isolation trench STR2 may constitute an isolation trench STR.

[0126] 5 and 19, a vertical structure VS may be formed to fill the channel hole CH. Forming the vertical structure VS may include sequentially forming a data storage pattern DSP, a vertical semiconductor pattern VSP, and a buried insulating pattern VI in the channel hole CH. Then, a channel pad CHP may be formed to fill the upper portion of the channel hole CH. When forming the vertical structure VS, the isolation trench STR may be filled with an isolation sacrificial pattern (not shown) so that the vertical structure VS is not formed in the isolation trench STR. The isolation sacrificial pattern may be removed after the formation of the vertical structure VS, and the isolation trench STR may be exposed to the outside again.

[0127] An isotropic etching process may be performed using the isolation trenches STR as a path to remove the first and second sacrificial layers SL1 and SL2, and the first and second gate electrodes GE1 and GE2 may be formed at the removed portions, through which a stack structure ST may be formed.

[0128] An isolation pattern SS may be formed to fill the isolation trench STR. Forming the isolation pattern SS may include sequentially forming an isolation insulating pattern SI and a metal contact MC in the isolation trench STR. Then, a second insulating film 40, a cell contact plug 41, a cell circuit wiring 43, and a second bonding pad 45 may be formed on the stack structure ST. The cell contact plug 41, the cell circuit wiring 43, and the second bonding pad 45 may be electrically connected, and the second insulating film 40 may be formed to surround them.

[0129] 5 and 20, the peripheral circuit structure PS and the cell array structure CS may be bonded to each other. In particular, the first bonding pad 35 of the peripheral circuit structure PS and the second bonding pad 45 of the cell array structure CS may be bonded to each other so as to contact each other. Accordingly, the first insulating film 30 and the second insulating film 40 may also be bonded to each other.

[0130] The cell array structure CS may be inverted by bonding the first bonding pad 35 and the second bonding pad 45 to each other. Therefore, in describing the manufacturing method after bonding, the terms "upper surface", "lower surface", "upper portion", and "lower portion" may again refer to the "upper surface", "lower surface", "upper portion", and "lower portion" described with reference to FIG. 6.

[0131] 5 and 21, the cell array substrate 100 may be removed. Removing the cell array substrate 100 may include at least one of a grinding process, a planarization process, a dry etching process, and a wet etching process. As an example, removing the cell array substrate 100 may include sequentially removing the first to third cell array substrates 110, 120, and 130.

[0132] By removing the cell array substrate 100, the data storage pattern DSP of the vertical structure VS, the isolation insulation pattern SI of the isolation pattern SS, and the first interlayer insulating film ILD1 of the uppermost layer may be exposed to the outside. Then, the exposed portion of the data storage pattern DSP and the exposed portion of the isolation insulation pattern SI may be removed. Thus, the vertical semiconductor pattern VSP may be exposed on the channel hole CH, and the metal contact MC may be exposed on the isolation trench STR. The exposed portion of the vertical semiconductor pattern VSP may be further doped with P-type impurities, but is not limited thereto.

[0133] 5 and 22, an N-doped pattern ND may be formed on the stack structure ST. The N-doped pattern ND may be formed to cover an exposed portion of the vertical semiconductor pattern VSP and an exposed portion of the metal contact MC. As an example, the N-doped pattern ND may cover an upper surface of the vertical semiconductor pattern VSP and an upper surface of the metal contact MC. As an example, the N-doped pattern ND may be formed to have different doping concentrations by region as described with reference to FIG. 8. As an example, forming the N-doped pattern ND may include sequentially forming a first N-doped region ND1, a second N-doped region ND2, and a third N-doped region ND3 of FIG. 8.

[0134] An undoped pattern UD may be formed to cover the N-doped pattern ND. Then, a channel contact hole CCH may be formed penetrating the undoped pattern UD and the N-doped pattern ND. The channel contact hole CCH may be formed to overlap the channel hole CH in a vertical direction. A portion of the vertical semiconductor pattern VSP may be exposed to the outside again within the channel contact hole CCH.

[0135] 5 and 23, a P-doped pattern PD may be formed on the undoped pattern UD. The P-doped pattern PD may fill the channel contact hole CCH and cover an upper surface of the undoped pattern UD. The P-doped pattern PD may contact and be electrically connected to the vertical semiconductor pattern VSP in the channel contact hole CCH. As an example, the P-doped pattern PD may be formed to have different doping concentrations by region as described with reference to FIG. 8. As an example, forming the P-doped pattern PD may include sequentially forming a first P-doped region PD1 and a second P-doped region PD2 of FIG. 8. As an example, the first P-doped region PD1 may be formed to conformally cover an inner side surface of the channel contact hole CCH and an upper surface of the undoped pattern UD, and the second P-doped region PD2 may be formed to fill the channel contact hole CCH and cover the first P-doped region PD1.

[0136] For example, after the formation of the P doping pattern PD, laser annealing may be further performed, through which the semiconductor materials in the N doping pattern ND and the P doping pattern PD may be crystallized and the impurities may be activated.

[0137] An upper insulating layer UI may be formed on the P-doped pattern PD. Then, a P contact hole PCH may be formed penetrating the upper insulating layer UI and extending into the P-doped pattern PD. The P contact hole PCH may expose the P-doped pattern PD to the outside at a lower portion thereof.

[0138] As an example, after the formation of the P contact hole PCH, an ohmic region OR of FIG. 10 may be further formed in the exposed portion of the P doping pattern PD in the P contact hole PCH. Forming the ohmic region OR may include doping the exposed portion of the P doping pattern PD with N-type impurities.

[0139] 5 and 6, a P contact plug PC and an upper circuit wiring UL may be formed. The P contact plug PC may be formed to fill a P contact hole PC, and the upper circuit wiring UL may be formed on an upper insulating layer UI. As an example, the P contact plug PC and the upper circuit wiring UL may be formed through a damascene process, but are not limited thereto.

[0140] 24 to 30 are cross-sectional views illustrating a method for manufacturing a three-dimensional semiconductor memory device according to an embodiment of the present invention. Hereinafter, a method for manufacturing the three-dimensional semiconductor memory device described with reference to FIG. 13 will be described with reference to FIG.

[0141] 5 and 24, a portion of the first interlayer insulating film ILD1 and a portion of the first sacrificial film SL1 may be alternately stacked on the cell array substrate 100. The portion of the first interlayer insulating film ILD1 may be a ground interlayer insulating film Ig, and the portion of the first sacrificial film SL1 may be a ground sacrificial film SLg.

[0142] Then, the channel contact hole CCH and the contact trench CTR may be formed to penetrate the ground interlayer insulating film Ig and the ground sacrificial film SLg. The channel contact hole CCH and the contact trench CTR may extend to the inside of the cell array substrate 100 (e.g., to the inside of the third cell array substrate 130).

[0143] 5 and 25, a buried sacrificial pattern BS may be formed to fill the channel contact hole CCH and the contact trench CTR. Forming the buried sacrificial pattern BS may include depositing the buried sacrificial pattern BS to fill the channel contact hole CCH and the contact trench CTR and cover the ground interlayer insulating film Ig, and removing the buried sacrificial pattern BS covering the ground interlayer insulating film Ig. The removal process of the buried sacrificial pattern BS may include performing a planarization process. Through the removal process, the buried sacrificial pattern BS may expose an upper surface of the ground interlayer insulating film Ig and may remain in the channel contact hole CCH and the contact trench CTR. As an example, the buried sacrificial pattern BS may include a metal or a metal nitride.

[0144] Although not shown, after the formation of the buried sacrificial pattern BS, the additional insulating film Ia described with reference to Fig. 15 may be further formed on the buried sacrificial pattern BS and the ground interlayer insulating film Ig. Then, the additional insulating film Ia may be left or removed depending on the effect of the subsequent process or for the purpose of adjusting the pitch. Then, a first interlayer insulating film ILD1 and a first sacrificial film SL1 may be further formed on the buried sacrificial pattern BS and the ground interlayer insulating film Ig, thereby forming a first mold structure ML1.

[0145] 5 and 26, a first channel hole CH1 and a first isolation trench STR1 may be formed to penetrate a first interlayer insulating film ILD1 and a first sacrificial film SL1 in a first direction D1. The first channel hole CH1 and the first isolation trench STR1 may extend to an inside of the buried sacrificial pattern BS to expose the inside of the buried sacrificial pattern BS to the outside.

[0146] The second mold structure ML2 is formed on the first mold structure ML1, so that the mold structure ML may be formed on the cell array substrate 100. Then, the second channel hole CH2 and the second isolation trench STR2 may be formed to penetrate the second interlayer insulating film ILD2 and the second sacrificial film SL2 in the first direction D1. The second channel hole CH2 and the second isolation trench STR2 may vertically overlap the first channel hole CH1 and the first isolation trench STR1, respectively.

[0147] Thereafter, the buried sacrificial pattern BS exposed through the first channel hole CH1 may be removed, thereby making the insides of the channel contact hole CCH and the contact trench CTR empty, and the ground interlayer insulating film Ig and the ground sacrificial layer SLg may be exposed to the outside at the inner surfaces of each of the channel contact hole CCH and the contact trench CTR.

[0148] 5 and 27, a vertical structure VS may be formed to fill the channel hole CH and the channel contact hole CCH. In this process, a void VD may be formed in the vertical structure VS due to a step between the channel contact hole CCH and the channel hole CH. Then, a channel pad CHP may be formed to fill the upper portion of the channel hole CH. The vertical structure VS may include a head structure HV in the channel contact hole CCH, and a through structure PV in the first and second channel holes CH1 and CH2.

[0149] When forming the vertical structures VS, the isolation trenches STR and the contact trenches CTR may be filled with an isolation sacrificial pattern (not shown) so that the vertical structures VS are not formed in the isolation trenches STR and the contact trenches CTR. The isolation sacrificial pattern may be removed after the vertical structures VS are formed, and the isolation trenches STR and the contact trenches CTR may be exposed to the outside again.

[0150] Thereafter, the first and second sacrificial films SL1 and SL2 may be replaced with first and second gate electrodes GE1 and GE2 through a process similar to that described with reference to FIG. 19, and a stack structure ST may be formed. An isolation insulating pattern SI of the isolation pattern SS and a metal contact MC may be formed to fill the isolation trench STR. In this process, a void VD may be formed in the metal contact MC due to a step between the contact trench CTR and the isolation trench STR. The metal contact MC may include a head contact HC in the contact trench CTR and a through contact PC filling the isolation trench STR under the head contact HC. Then, a second insulating film 40, a cell contact plug 41, a cell circuit wiring 43, and a second bonding pad 45 may be formed on the stack structure ST.

[0151] 5 and 28, the peripheral circuit structure PS and the cell array structure CS may be coupled to each other. Thus, the head structure HV may be located on the vertical structure VS. After coupling, the head structure HV may include a third head portion HV3 covering the first head portion HV1.

[0152] 5 and 29, the cell array substrate 100 may be removed. By removing the cell array substrate 100, an upper portion of the head structure HV and an upper portion of the separation pattern SS may be exposed to the outside. Then, the exposed upper portion of the head structure HV may be removed. In particular, an upper portion of the first head part HV1 and a third head part HV3 located above the stack structure ST may be removed, and the void VD inside the head structure HV may be exposed. In this process, a part of the buried insulating pattern VI in the channel contact hole CH may be further removed. Therefore, the vertical semiconductor pattern VSP of the first head part HV1 may be exposed in the channel contact hole CH.

[0153] The exposed upper portion of the separation pattern SS may be removed. In particular, the separation insulating pattern SI may be removed from the exposed upper portion of the separation pattern SS, and the head contact HC may not be removed but may remain and be exposed to the outside. The upper portion of the head contact HC may protrude above the stacked structure ST. For example, a void VD inside the head contact HC may be isolated from the outside by the head contact HC.

[0154] 5 and 30, a P doping pattern PD may be formed on the stacked structure ST. The P doping pattern PD may fill the channel contact hole CCH and cover the top surface of the stacked structure ST and the top of the head contact HC. The P doping pattern PD may contact and be electrically connected to the vertical semiconductor pattern VSP in the channel contact hole CCH. The P doping pattern PD may contact and be electrically connected to the top of the head contact HC.

[0155] 5 and 13, an upper insulating layer UI may be formed on the P doping pattern PD. Then, a P contact hole PCH may be formed penetrating the upper insulating layer UI and extending into the P doping pattern PD. A P contact plug PC may be formed to fill the P contact hole PC, and an upper circuit wiring UL may be formed on the upper insulating layer UI.

[0156] The above description of the embodiments of the present invention provides examples to explain the present invention. Therefore, the present invention is not limited to the above embodiments, and it is clear that various modifications and changes can be made by those skilled in the art within the technical concept of the present invention, such as by combining the above embodiments. [Explanation of symbols]

[0157] 10 Peripheral board PS peripheral circuit structure CS Cell Array Structure ST laminated structure VS vertical structure SS Separation Pattern ND N doping pattern PD P doping pattern UD Undoped Pattern

Claims

1. a peripheral circuit structure on a peripheral substrate; a stacked structure including a plurality of gate electrodes stacked on the peripheral circuit structure; an N-doped pattern on the stacked structure; a vertical structure extending through the stacked structure and into the N-doped pattern; a P-doped pattern on the N-doped pattern; an undoped pattern between the N-doped pattern and the P-doped pattern; The P-doped pattern includes a P-doped horizontal pattern on the undoped pattern and a P-doped vertical pattern penetrating the undoped pattern and the N-doped pattern to contact the vertical structure.

2. 2. The three-dimensional semiconductor memory device of claim 1, wherein the undoped pattern vertically separates the P-doped horizontal pattern from the N-doped pattern.

3. The three-dimensional semiconductor memory device of claim 1 , wherein the undoped pattern covers an upper surface of the N-doped pattern.

4. the laminated structure includes a plurality of horizontally spaced laminated structures, 2. The three-dimensional semiconductor memory device of claim 1, further comprising an isolation structure separating the plurality of stacked structures and extending into the N-doped pattern.

5. 5. The three-dimensional semiconductor memory device of claim 4, wherein the isolation structure comprises a metal contact electrically connected to the N-doped pattern and an isolation insulating pattern between the metal contact and the stack structure.

6. 2. The three-dimensional semiconductor memory device of claim 1, further comprising a metal contact extending through the P-doped pattern and the undoped pattern and into the N-doped pattern.

7. 2. The three-dimensional semiconductor memory device of claim 1, wherein the doping concentration of the N-doped pattern increases continuously or discontinuously downward.

8. 2. The three-dimensional semiconductor memory device of claim 1, wherein the doping concentration of the P-doped horizontal pattern decreases continuously or discontinuously downward.

9. 2. The three-dimensional semiconductor memory device of claim 1, wherein an upper portion of the P-doped vertical pattern is surrounded by the undoped pattern and a lower portion of the P-doped vertical pattern is surrounded by the N-doped pattern.

10. 10. The three-dimensional semiconductor memory device of claim 9, wherein, in a plan view, a doping concentration of the upper portion of the P-doped vertical pattern decreases continuously or discontinuously as it approaches the undoped pattern.

11. 10. The three-dimensional semiconductor memory device of claim 9, wherein, in a plan view, a doping concentration of the lower portion of the P-doped vertical pattern decreases continuously or discontinuously as it approaches the N-doped pattern.

12. a P contact plug electrically connected to the P doping pattern, the P-doped pattern includes an ohmic region adjacent to the P-contact plug, The three-dimensional semiconductor memory device of claim 1 , wherein the ohmic region contains N-type impurities.

13. 2. The three-dimensional semiconductor memory device of claim 1, wherein the P-doped vertical pattern has a width in a horizontal direction that decreases downward.

14. a peripheral circuit structure on a peripheral substrate; a stacked structure including a plurality of gate electrodes stacked on the peripheral circuit structure; an N-doped pattern on the stacked structure; a vertical structure extending through the stacked structure and into the N-doped pattern; an undoped pattern on the N-doped pattern; a P-doped pattern penetrating the undoped pattern and the N-doped pattern and contacting the vertical structure; a metal contact electrically connected to the N-doped pattern; a P contact plug electrically connected to the P doping pattern.

15. The three-dimensional semiconductor memory device of claim 14 , wherein the P-doped pattern covers an upper surface of the undoped pattern.

16. the N-doped pattern includes a first N-doped region and a second N-doped region having a doping concentration lower than that of the first N-doped region; 15. The three-dimensional semiconductor memory device of claim 14, wherein the second N-doped region is more adjacent to the undoped pattern than the first N-doped region.

17. the P-doped pattern includes a first P-doped region and a second P-doped region having a doping concentration higher than that of the first P-doped region; 15. The three-dimensional semiconductor memory device of claim 14, wherein the first P doped region is more adjacent to the undoped pattern than the second P doped region.

18. 15. The three-dimensional semiconductor memory device of claim 14, wherein the metal contact extends from a lower end or an upper end of the N-doped pattern into the N-doped pattern.

19. A three-dimensional semiconductor memory device; a controller electrically connected to the three-dimensional semiconductor memory device through an input / output pad and configured to control the three-dimensional semiconductor memory device; The three-dimensional semiconductor memory device includes: a peripheral circuit structure on a peripheral substrate; a stacked structure including a plurality of gate electrodes stacked on the peripheral circuit structure; an N-doped pattern on the stacked structure; a vertical structure extending through the stacked structure and into the N-doped pattern; a P-doped pattern on the N-doped pattern; an undoped pattern between the N-doped pattern and the P-doped pattern; The P-doped pattern includes a P-doped horizontal pattern on the undoped pattern and a P-doped vertical pattern passing through the undoped pattern and the N-doped pattern and contacting the vertical structure.

20. 20. The electronic system of claim 19, wherein the undoped pattern vertically separates the P-doped horizontal pattern from the N-doped pattern.

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