Codependent physical unclonable function / random number generator pairing for physical provenance
Patent Information
- Application Number
- JP2024120931
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2024-05-10
- Filing Date
- 2024-07-26
- Publication Date
- 2025-02-14
Smart Images
Figure 2025022796000001_ABST
Abstract
Description
[Technical field]
[0001] (CROSS REFERENCE TO RELATED APPLICATIONS) This application claims priority to U.S. Provisional Patent Application No. 63 / 516,949, entitled "DUAL USE MICROELECTROMECHANICAL SYSTEM (MEMS) DEVICE," filed August 1, 2023, the contents of which are incorporated by reference in their entirety herein.
[0002] This application is related to U.S. patent application Ser. No. 18 / 661,373 (Attorney Docket No. H232672-US2), entitled "DUAL USE MICROELECTROMECHANICAL SYSTEM (MEMS) DEVICE", filed on the same day as this application, U.S. patent application Ser. No. 18 / 661,416 (Attorney Docket No. H233693-US), entitled "MEMS BASED PUF FOR MECHANICAL TRUST EXTENSION", filed on the same day as this application, U.S. patent application Ser. No. 18 / 661,426 (Attorney Docket No. H233694-US), entitled "ACTIVE TRANSISTOR PHYSICAL UNCLONABLE FUNCTION (PUF) CIRCUIT WITH MEMS UNIQUENESS", filed on the same day as this application, and U.S. patent application Ser. No. 18 / 661,426 (Attorney Docket No. H233694-US), entitled "ACTIVE TRANSISTOR RANDOM NUMBER GENERATOR (RNG) CIRCUIT WITH MEMS No. 18 / 661,437 (Attorney Docket No. H233699-US), entitled "METHOD FOR HYPERTENSION SYSTEMS AND METHOD FOR HYPERTENSION SYSTEMS ENTROPY," all of which are incorporated herein by reference in their entireties. [Background technology]
[0003] Systems are needed for cryptographic techniques that can provide certainty about both the identity of the hardware and the quality of the source randomness maintained within the system. These systems must both verify the identity of the hardware and provide a truly random source of numbers embedded within the system. One threat vector for an attacker to circumvent the cryptographic measures of such a system is for the attacker to disable or replace the random source (e.g., with a pseudorandom source), so that the random numbers become known and other variables can therefore be targeted for security compromise. Pseudorandom sequences can often spoof the best random number checkers implemented during execution. The system should be able to resist divide-and-conquer methods by separating the system into parts and attacking the parts. Summary of the Invention
[0004] In some aspects, a device is described herein. The device includes a physical unclonable function (PUF) circuit configured to generate a PUF output in response to an input. The device further includes a random number generator (RNG) circuit configured to output one or more random numbers. The PUF circuit and the RNG circuit share one or more components such that modifying the RNG circuit modifies the PUF circuit. The device is configured to determine whether the RNG circuit is an untainted source of random numbers based on an output of the PUF circuit.
[0005] In some aspects, a node is described herein. The node includes a physical unclonable function (PUF) circuit configured to generate a PUF output in response to an input. The node further includes a random number generator (RNG) circuit configured to output one or more random numbers. The PUF circuit and the RNG circuit share one or more components such that modifying the RNG circuit modifies the PUF circuit. The node further includes one or more additional circuits configured to utilize the PUF output and / or the one or more random numbers for one or more cryptographic processes. The node is configured to determine whether the RNG circuit is an untainted source of random numbers based on an output of the PUF circuit.
[0006] In some examples, a method is described herein. The method includes receiving a physical unclonable function (PUF) challenge at a device including a physical unclonable function (PUF) circuit and a random number generator (RNG) circuit that share one or more components. The method further includes determining, with the PUF circuit of the device, a PUF response output in response to the PUF challenge. The method further includes determining whether the PUF response output matches a valid PUF response. The method further includes validating one or more hardware resources for the RNG circuit in response to a determination that the PUF response output matches a valid PUF response. The method further includes denying one or more hardware resources for the RNG circuit in response to a determination that the PUF response output does not match a valid PUF response. [Brief description of the drawings]
[0007] Example embodiments are described with additional specificity and detail using the accompanying drawings, with the understanding that the drawings depict only some embodiments and therefore should not be considered limiting in scope.
[0008] [Figure 1A] FIG. 1 is a block diagram of an example device having a co-dependent physical unclonable function (PUF) and a random number generator (RNG). [Figure 1B] FIG. 1 is a block diagram of an example device having a co-dependent physical unclonable function (PUF) and a random number generator (RNG). [Figure 1C] FIG. 1 is a block diagram of an example device having a co-dependent physical unclonable function (PUF) and a random number generator (RNG). [Figure 1D] FIG. 1 is a block diagram of an example device having a co-dependent physical unclonable function (PUF) and a random number generator (RNG). [Figure 1E] FIG. 1 is a block diagram of an example device having a co-dependent physical unclonable function (PUF) and a random number generator (RNG). [Diagram 2] FIG. 1 is a flow diagram of an exemplary method for verifying the randomness of a random number generator (RNG) included in a combined PUF / RNG device. [Diagram 3] FIG. 1 is a block diagram of an exemplary system.
[0009] In accordance with common practice, the various features described are not drawn to scale but rather are drawn to emphasize specific features relevant to the exemplary embodiments. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0010] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which specific illustrative embodiments are shown by way of illustration. It is to be understood, however, that other embodiments may be utilized and that logical, mechanical, and electrical changes may be made. Further, the methods presented in the drawings and specification should not be construed as limiting the order in which individual steps may be performed. Thus, the following detailed description is not to be construed in a limiting sense.
[0011] The examples described herein combine the PUF circuit and the RNG circuit in the same device to avoid divide and conquer attacks. In the examples described herein, the PUF circuit and the RNG circuit share one or more components, such that changing the RNG changes the PUF. The random number output of the device will be guaranteed to have a good non-deterministic output as long as the PUF output remains consistent for a given challenge / response. Thus, if a valid PUF response is measured from the output of the PUF circuit 102, this also validates and proves the randomness of the RNG circuit 104. By using the combined PUF and RNG device architecture and the methods described herein, a more definitive way to prove that the RNG output is from an untainted source by measuring the PUF output is provided.
[0012] 1A is a block diagram of an example device 100 having a co-dependent physical unclonable function (PUF) and random number generator (RNG). The device 100 includes both a PUF circuit 102 and an RNG circuit 104 that are co-dependent such that modifying the RNG circuit 104 necessarily modifies the PUF circuit 102.
[0013] In the example shown in Figure 1A, the PUF circuit 102 is configured to receive a system input (e.g., an input from a user). In some examples, the system input includes one or more challenges (e.g., challenge bits), and the PUF circuit 102 is configured to output a response to the one or more challenges. In the example shown in Figure 1A, the PUF circuit 102 is configured to generate a PUF output corresponding to the response to the one or more challenges. The PUF circuit 102 can be selected and configured to implement a variety of PUF architectures (e.g., an arbiter, a ring oscillator, etc.) and can include a variety of different electronic components.
[0014] In the example shown in FIG. 1A, the RNG circuit 104 is configured to output a random number based on physical characteristics of the RNG circuit 104, among other factors. In some examples, the output of the RNG circuit 104 is also based on noise inherent to the PUF circuit 102, which may be provided to the RNG circuit 104 by one or more components of the PUF circuit 102 as a "seed" for the RNG circuit 104. The output of the RNG circuit 104 is random and non-deterministic. In some examples, the output of the RNG circuit 104 is affected over time due to aging or other factors. The RNG circuit 104 may be configured to implement a variety of RNG architectures (e.g., a ring oscillator, etc.) and may include a variety of different electronic components.
[0015] 1A, the PUF circuit 102 and the RNG circuit 104 share one or more components (shown as shared components 105), such that modifying the shared components 105 alters the PUF circuit 102, and therefore the PUF output. The types of components shared between the PUF circuit 102 and the RNG circuit 104 depend on the types of components used to implement the PUF circuit 102 and the RNG circuit 104. Furthermore, the particular number of shared components 105, and the identities of the shared components 105 that are sufficient to ensure that changes made to the RNG circuit 104 result in changes to the PUF circuit 102, will vary depending on the types of components used to implement the PUF circuit 102 and the RNG circuit 104.
[0016] In some examples, the PUF circuit 102 and the RNG circuit 104 are both implemented using only active transistor circuitry. In such examples, the PUF circuit 102 includes an active transistor PUF circuit, the RNG circuit 104 includes an active transistor RNG circuit, and one or more components of the active transistor PUF circuit are shared with the active transistor RNG circuit.
[0017] In some examples, the active transistor PUF circuit may include, but is not limited to, circuitry configured to generate a corresponding PUF response based on a particular PUF challenge input to a system. For example, if the active transistor PUF circuit is configured to implement a ring oscillator PUF, the active transistor PUF circuit may include an array of ring oscillator loops coupled to a multiplexer, a frequency counter, a comparison circuit, etc.
[0018] In some examples, the active transistor RNG circuit may include, but is not limited to, a circuit configured to generate a random number. In some examples, the active transistor RNG circuit may include, but is not limited to, an array of ring oscillator loops coupled to an exclusive-or component (XOR), a sampling circuit, or the like.
[0019] In the above examples of active-transistor PUF circuits and active-transistor RNG circuits, the ring oscillator loop and / or inverters may be shared between the PUF circuit 102 and the RNG circuit 104. It should be understood that other components not specifically described above may also be shared between the PUF circuit 102 and the RNG circuit 104.
[0020] In examples where the PUF circuit 102 is implemented using only active transistor circuitry, the uniqueness of the PUF output is affected by noise and uncontrollable factors inherent to the materials of construction, manufacturing process, etc. for the active transistor circuit components. In examples where the RNG circuit 104 is implemented using only active transistor circuitry, the randomness of the random number output is affected by the number of components for the active transistor circuit components (e.g., more ring oscillator loops may increase randomness), variation between components (e.g., ring oscillator loops of different lengths), noise (e.g., due to the manufacturing process), etc. In some examples, the randomness of the random number output is also affected by noise and / or uncontrollable factors inherent to the PUF circuit 102 (e.g., when noise from the PUF circuit 102 is used as a seed for the RNG circuit 104).
[0021] In some examples, such as the example devices 120, 130, 140, 150 described below with respect to FIGS. 1B-1E, the PUF circuit 102 and / or the RNG circuit 104 are implemented using a combination of one or more MEMS structures and active transistor circuits. In some examples, the one or more MEMS structures include a single MEMS sensor. In other examples, the one or more MEMS structures include multiple MEMS structures. The one or more MEMS structures can be any type of MEMS device, such as an accelerometer, a gyroscope, a pressure sensor, a temperature sensor, an airflow sensor, or other similar MEMS structures. When included in the PUF circuit 102, the one or more MEMS structures can serve as an additional source of uniqueness for the active transistor PUF circuit. When included in the RNG circuit 104, the parasitic resistance, capacitance, and / or inductance of the one or more MEMS sensors can serve as an additional entropy source for the active transistor RNG circuit. It should be understood that other entropy sources can be used in addition to or in place of the one or more MEMS structures. For example, noise and / or uncontrollable factors inherent in the PUF circuit 102, capacitor structures, resistor structures, photodetectors, photodetector / emitter pairs (e.g., using diodes), or other types of sources may also be used as sources of entropy for the RNG circuit 104.
[0022] In some examples, the PUF circuit 102 includes only active transistor circuitry, while the RNG circuit 104 includes one or more MEMS structures and active transistor circuitry. In other examples, the PUF circuit 102 includes one or more MEMS structures and active transistor circuitry, while the RNG circuit 104 includes only active transistor circuitry. In any of these other examples, the PUF circuit 102 and the RNG circuit 104 share one or more components of the active transistor circuitry, but do not share one or more MEMS structures.
[0023] In other examples, both the PUF circuit 102 and the RNG circuit 104 include active transistor circuitry and one or more MEMS structures. In such examples, the PUF circuit 102 and the RNG circuit 104 share one or more MEMS structures and / or one or more components of the active transistor circuitry.
[0024] In examples where the PUF circuit 102 is implemented using a combination of one or more MEMS structures and active transistor circuits, the uniqueness of the PUF output is affected by noise and uncontrollable factors inherent to the active transistor circuit and the one or more MEMS structures' materials of construction, manufacturing process, etc. In examples where the RNG circuit 104 is implemented using a combination of one or more MEMS structures and active transistor circuits, the randomness of the random number output is affected by the number of components of the active transistor circuit and the one or more MEMS structures (e.g., more ring oscillator loops or MEMS structures), variation between components (e.g., variation between ring oscillator loops of different lengths, or similar MEMS structures), noise (e.g., due to the manufacturing process), etc. In some examples, the randomness of the random number output is also affected by noise and / or uncontrollable factors inherent to the PUF circuit 102 (e.g., when noise from the PUF circuit 102 is used as a seed for the RNG circuit 104). In general, the uniqueness of the PUF output, and the randomness of the random number output, is increased when using one or more MEMS structures in addition to active transistor circuits.
[0025] As discussed above, the PUF circuit 102 and the RNG circuit 104 of the device 100 are co-dependent, such that a change to the RNG circuit 104 necessarily changes the PUF circuit 102. In the example shown in FIG. 1A, the co-dependency is created by the shared component 105. In particular, any modification of the RNG circuit 104 of the device 100 necessarily requires a modification to the shared component 105, and such a modification results in a change to the PUF circuit 102 and the RNG circuit 104. By testing the PUF output (e.g., as discussed below with respect to FIG. 2), a system that includes the device 100 can verify whether the RNG circuit 104 is an untainted source of random numbers.
[0026] 1B is a block diagram of an exemplary device 120 having a co-dependent physical unclonable function (PUF) and random number generator (RNG). Certain features of device 120 represent embodiments of device 100 described above with respect to FIG. 1A. In the example shown in FIG. 1B, device 120 includes a PUF circuit 102 and an RNG circuit 104, both of which include a shared active transistor circuit 106.
[0027] 1B, PUF circuit 102 includes active-transistor PUF circuit 107 in addition to shared active-transistor circuit 106. In contrast to shared active-transistor circuit 106, active-transistor PUF circuit 107 is used exclusively for PUF circuit 102. For example, active-transistor PUF circuit 107 may include, but is not limited to, circuitry used to implement receiving a challenge input, a frequency counter, or other circuit elements unique to the operation of PUF circuit 102.
[0028] In some examples, PUF circuit 102 optionally includes one or more PUF MEMS structures 109 in addition to shared active transistor circuitry 106 and active transistor PUF circuitry 107. One or more PUF MEMS structures 109 are used exclusively for PUF circuit 102. In such examples, one or more PUF MEMS structures 109, if included, are used as an additional source of uniqueness in combination with shared active transistor circuitry 106 and / or active transistor PUF circuitry 107.
[0029] 1B, the RNG circuit 104 includes an active transistor RNG circuit 108 in addition to the shared active transistor circuit 106. In contrast to the shared active transistor circuit 106, the active transistor RNG circuit 108 is used exclusively for the RNG circuit 104. For example, the active transistor RNG circuit 108 may include, but is not limited to, circuitry used to implement a sample clock, XOR functionality, or other circuit elements unique to the operation of the RNG circuit 104.
[0030] In some examples, the RNG circuit 104 optionally includes one or more RNG MEMS structures 110 in addition to the shared active transistor circuit 106 and the active transistor RNG circuit 108. The one or more RNG MEMS structures 110 are used exclusively for the RNG circuit 104. In such examples, the parasitic resistance, capacitance, and / or inductance of the one or more RNG MEMS structures 110 combine with the active logic implemented using the active transistor RNG circuit 108 to increase entropy. It should be understood that other entropy sources may be used in addition to or in place of the one or more RNG MEMS structures 110. For example, noise and / or uncontrollable factors inherent in the PUF circuit 102, capacitor structures, resistor structures, photodetectors, photodetector / emitter pairs (e.g., using diodes), or other types of sources may also be used as a source of entropy for the RNG circuit 104.
[0031] The PUF circuit 102 and RNG circuit 104 of device 120 are co-dependent such that a change to the RNG circuit 104 necessarily changes the PUF circuit 102. In the example shown in FIG. 1B , the co-dependency is created by the shared active transistor circuitry 106. In particular, any modification of the RNG circuit 104 of device 120 necessarily requires a modification to the shared active transistor circuitry 106, and such a modification results in a change to both the PUF circuit 102 and the RNG circuit 104. By testing the PUF output (e.g., as discussed below with respect to FIG. 2 ), a system that includes device 120 can verify whether the RNG circuit 104 is an untainted source of random numbers.
[0032] 1C is a block diagram of another example device 130 having a co-dependent physical unclonable function (PUF) and random number generator (RNG). Certain features of device 130 represent another embodiment of device 100 described above with respect to FIG. 1A.
[0033] In the example shown in Figure 1C, device 130 includes PUF circuitry 102 implemented using a combination of one or more MEMS structures and active transistor circuitry. In the example shown in Figure 1C, device 130 also includes RNG circuitry 104 implemented using a combination of one or more MEMS structures and active transistor circuitry. In the example shown in Figure 1C, PUF circuitry 102 and RNG circuitry 104 include one or more shared MEMS structures 111 instead of shared active transistor circuitry 106.
[0034] 1C, PUF circuit 102 includes active-transistor PUF circuit 107 in addition to one or more shared MEMS structures 111. Active-transistor PUF circuit 107 is used exclusively for PUF circuit 102. For example, active-transistor PUF circuit 107 may include, but is not limited to, circuitry used to implement receiving a challenge input, a frequency counter, or other circuit elements unique to the operation of PUF circuit 102.
[0035] In some examples, PUF circuit 102 optionally includes one or more PUF MEMS structures 109 in addition to one or more shared MEMS structures 111 and active transistor PUF circuit 107. In contrast to the one or more shared MEMS structures 111, the one or more PUF MEMS structures 109 are used exclusively for PUF circuit 102. In such examples, the one or more shared MEMS structures 111 and the one or more PUF MEMS structures 109, if included, are used as an additional source of uniqueness for active transistor PUF circuit 107.
[0036] 1C , the RNG circuit 104 includes an active transistor RNG circuit 108 in addition to one or more shared MEMS structures 111. The active transistor RNG circuit 108 is used exclusively for the RNG circuit 104. For example, the active transistor RNG circuit 108 may include, but is not limited to, circuitry used to implement a sample clock, XOR functionality, or other circuit elements unique to the operation of the RNG circuit 104.
[0037] In some examples, the RNG circuit 104 optionally includes one or more RNG MEMS structures 110 in addition to one or more shared MEMS structures 111. In contrast to the one or more shared MEMS structures 111, the one or more RNG MEMS structures 110 are used exclusively for the RNG circuit 104. In such examples, the parasitic resistance, capacitance, and / or inductance of the one or more shared MEMS structures 111 and / or the parasitic resistance, capacitance, and / or inductance of the one or more RNG MEMS structures 110 are combined with active logic implemented using active transistor RNG circuit 108.
[0038] The PUF circuit 102 and the RNG circuit 104 of the device 130 are co-dependent such that a change to the RNG circuit 104 necessarily changes the PUF circuit 102. In the example shown in FIG. 1C, the co-dependency is created by the one or more shared MEMS structures 111. In particular, any modification of the RNG circuit 104 of the device 130 necessarily requires a modification to the one or more shared MEMS structures 111, such a modification resulting in a change to both the PUF circuit 102 and the RNG circuit 104. By testing the PUF output (e.g., as discussed below with respect to FIG. 2), a system including the device 130 can verify whether the RNG circuit 104 is an untainted source of random numbers.
[0039] 1D is a block diagram of an example device 140 having a co-dependent physical unclonable function (PUF) and random number generator (RNG). Certain features of device 140 represent an embodiment of device 100 described above with respect to FIG. 1A.
[0040] In the example shown in Figure 1D, device 140 includes a PUF circuit 102 implemented using a combination of one or more MEMS structures and active transistor circuitry. In the example shown in Figure 1D, device 140 also includes a RNG circuit 104 implemented using a combination of one or more MEMS structures and active transistor circuitry. In the example shown in Figure 1D, PUF circuit 102 and RNG circuit 104 both include a shared active transistor circuit 106 and one or more shared MEMS structures 111.
[0041] 1D , PUF circuit 102 includes active-transistor PUF circuit 107 in addition to shared active-transistor circuit 106. In contrast to shared active-transistor circuit 106, active-transistor PUF circuit 107 is used exclusively for PUF circuit 102. For example, active-transistor PUF circuit 107 may include, but is not limited to, circuitry used to implement receiving a challenge input, a frequency counter, or other circuit elements unique to the operation of PUF circuit 102.
[0042] In some examples, PUF circuit 102 optionally includes one or more PUF MEMS structures 109 in addition to shared active transistor circuit 106, active transistor PUF circuit 107, and one or more shared MEMS structures 111. In contrast to the one or more shared MEMS structures 111, the one or more PUF MEMS structures 109 are used exclusively for PUF circuit 102. In such examples, the one or more PUF MEMS structures 109 and / or the one or more shared MEMS structures 111 are used as a unique source for the shared active transistor circuit 106 and / or the active transistor PUF circuit 107.
[0043] 1D , the RNG circuit 104 includes an active transistor RNG circuit 108 in addition to the shared active transistor circuit 106. In contrast to the shared active transistor circuit 106, the active transistor RNG circuit 108 is used exclusively for the RNG circuit 104. For example, the active transistor RNG circuit 108 may include, but is not limited to, circuitry used to implement a sample clock, XOR functionality, or other circuit elements unique to the operation of the RNG circuit 104.
[0044] In some examples, the RNG circuit 104 optionally includes one or more RNG MEMS structures 110 in addition to the shared active transistor circuit 106, the active transistor RNG circuit 108, and the one or more shared MEMS structures 111. In contrast to the one or more shared MEMS structures 111, the one or more RNG MEMS structures 110 are used exclusively for the RNG circuit 104. In such examples, the parasitic resistance, capacitance, and / or inductance of the one or more shared MEMS structures 111 and / or the parasitic resistance, capacitance, and / or inductance of the one or more RNG MEMS structures 110 are combined with active logic implemented using the shared active transistor circuit 106 and / or the active transistor RNG circuit 108.
[0045] The PUF circuit 102 and the RNG circuit 104 of the device 140 are co-dependent such that a change to the RNG circuit 104 necessarily changes the PUF circuit 102. In the example shown in FIG. 1D , the co-dependency is created by the shared active transistor circuit 106 and / or one or more shared MEMS structures 111. In particular, any modification of the RNG circuit 104 of the device 140 necessarily requires a modification to the shared active transistor circuit 106 and / or one or more shared MEMS structures 111. Such a modification results in a change to both the PUF circuit 102 and the RNG circuit 104. By testing the PUF output (e.g., as discussed below with respect to FIG. 2 ), a system including the device 140 can verify whether the RNG circuit 104 is an untainted source of random numbers.
[0046] 1E is a block diagram of an example device 150 having a co-dependent physical unclonable function (PUF) and random number generator (RNG). Certain features of device 150 represent an embodiment of device 100 described above with respect to FIG. 1A.
[0047] In the example shown in Figure 1E, device 150 includes a PUF / RNG circuit 151 that is used to implement PUF circuit 102 and RNG circuit 104, as described above with respect to Figures 1A-1D. PUF / RNG circuit 151 is implemented using a shared reconfigurable active transistor circuit 152. In some examples, shared reconfigurable active transistor circuit 152 is implemented using a field-programmable gate array (FPGA) or other reconfigurable circuit element.
[0048] In some examples, the shared reconfigurable active transistor circuit 152 has multiple configuration states, and only one configuration state is used at a particular time. The configuration states of the shared reconfigurable active transistor circuit 152 include a PUF configuration configured to generate a PUF output and an RNG configuration configured to generate an RNG output. In some examples, the reconfigurable circuit elements (e.g., of an FPGA) utilized for the PUF configuration are the same as those utilized for the RNG configuration. In some examples, the reconfigurable circuit elements (e.g., of an FPGA) utilized for the PUF configuration include some but not all of the circuit elements utilized for the RNG configuration, or vice versa.
[0049] In some examples, the configuration state of the shared reconfigurable active transistor circuit 152 is determined based on a time-dependent operation sequence in which the PUF configuration is performed during one or more periods and the RNG configuration is performed during other periods. In other examples, the configuration state of the shared reconfigurable active transistor circuit 152 is determined based on an input indicating a desired configuration state.
[0050] In some examples, the PUF / RNG circuitry 151 also includes one or more shared MEMS structures 111. In such examples, the parasitic resistance, capacitance, and / or inductance of the one or more shared MEMS structures 111 are combined with active logic implemented using shared reconfigurable active transistor circuitry 152 in a manner similar to that discussed herein.
[0051] 1A-1D, the PUF / RNG circuit 151 of device 150 implementing PUF circuit 102 and RNG circuit 104 provides a co-dependent PUF and RNG such that modification of PUF / RNG circuit 151 necessarily modifies the PUF output and the RNG output. In the example shown in FIG. 1E, the co-dependency is created by the shared reconfigurable active transistor circuit 152 (and one or more shared MEMS structures 111) that are used to generate both the PUF output and the RNG output. In particular, any modification of the PUF / RNG circuit 151 of device 150 necessarily requires modification to the shared reconfigurable active transistor circuit 152 and / or one or more shared MEMS structures 111, such modification resulting in a change to both the PUF output and the RNG output. By testing the PUF output (e.g., as discussed below with respect to FIG. 2), a system including device 150 can verify whether the RNG output is from an untainted source of random numbers. In the particular example shown in FIG. 1E, the source of the PUF output and the source of the RNG output are the same, which can provide a higher level of certainty that the sources are valid.
[0052] 1A-1D for each device 100, 120, 130, 140, and a single instance of a PUF / RNG circuit 151 is shown for device 150, it should be understood that other configurations are also possible. For example, two or more instances of a PUF circuit 102 and / or two or more instances of a RNG circuit 104 may be included in a single device, and co-dependencies of the various instances of the PUF circuit 102 and RNG circuit 104 may be created by sharing components in a similar manner as discussed above. Also, two or more instances of a PUF / RNG circuit 151 may be included in a single device, and co-dependencies of the various instances of the PUF / RNG circuit 151 may be created by sharing a shared reconfigurable active transistor circuit 152 and / or one or more shared MEMS structures 111.
[0053] Additionally, devices 100, 120, 130, 140, 150 may be standalone devices or may be integrated into a larger device or system. In examples where devices 100, 120, 130, 140, 150 are standalone devices, devices 100, 120, 130, 140, 150 may include additional circuitry beyond that shown in Figures 1A-1E to generate system inputs for devices 100, 120, 130, 140, 150, utilize the random number output for cryptographic processes, and / or perform additional functions that utilize the PUF output for cryptographic processes.
[0054] In some examples, the output of the PUF circuit 102, the RNG circuit 104, or the PUF / RNG circuit 151 is transmitted from the standalone device along with an authentication code. The authentication code can ensure that the numbers generated by the authenticated physical source have not been altered on the way between the standalone device including the PUF circuit 102, the RNG circuit 104, and / or the PUF / RNG circuit 151 and the device receiving or consuming the output. In some examples, the authenticated random number output and the authenticated PUF output are transmitted from the standalone device in an encrypted format, which can keep the random number output and PUF output values confidential as they are being transmitted and make it more difficult to alter the values on the way between the standalone device and the device receiving or consuming the output.
[0055] 2 illustrates a flow diagram of an example method 200 for verifying the randomness of a random number generator included in a combined PUF / RNG device. Common features discussed above with respect to the example devices 100, 120, 130, 140, 150 of FIGS. 1A-1E can include similar features as those discussed with respect to method 200, and vice versa. In some examples, blocks of method 200 are performed by circuitry or other components of a system communicatively coupled to the devices 100, 120, 130, 140, 150 discussed above with respect to FIGS. 1A-1E. In other examples, blocks of method 200 are performed by circuitry or other components of the devices 100, 120, 130, 140, 150 communicatively coupled to the PUF circuitry 102, the RNG circuitry 104, and / or the PUF / RNG circuitry 151, which are not shown in FIGS. 1A-1E for ease of illustration.
[0056] The method 200 includes receiving a PUF challenge at a combined PUF / RNG device (block 202). In some examples, receiving the PUF challenge at the combined PUF / RNG device includes inputting the PUF challenge to a PUF circuit included within the combined PUF / RNG device. The PUF circuit is configured to generate a unique PUF response to a given PUF challenge input.
[0057] The method 200 further includes determining a PUF response output by the combined PUF / RNG device in response to the PUF challenge (block 204). In some examples, the PUF circuitry is configured to output the PUF response in response to the PUF challenge. In some examples, the PUF response output from the combined PUF / RNG device includes a series of bits. In other examples, the PUF response output from the combined PUF / RNG device includes a single bit output.
[0058] The method 200 further includes determining whether the PUF response output by the combined PUF / RNG device corresponds to a valid PUF response (block 206). In some examples, a valid PUF response to a particular PUF challenge is determined during pre-deployment testing of the combined PUF / RNG device. In some examples, the PUF response may include bit errors or fluctuations in the PUF output that are corrected at a later stage. In such examples, a PUF response generated by the PUF circuitry may be determined to correspond to a valid PUF response if the response is within a particular threshold range of values that are observable during pre-deployment testing of the combined PUF / RNG device. The threshold range of valid PUF responses may be determined during testing to include a particular range of values (including bit errors or fluctuations) that are observable during pre-deployment testing of the combined PUF / RNG device. It should be understood that the width of the particular range of values depends on the particular components that make up the combined PUF / RNG device.
[0059] The method 200 further includes verifying a hardware source of the RNG in response to the PUF response output by the combined PUF / RNG device matching a valid PUF response (block 208). In some examples, verifying the hardware source of the RNG includes outputting an indication that the random numbers output by the RNG circuitry have been verified to be provided from an untainted source. In some examples, if the hardware source of the RNG is verified, the RNG is used for further cryptographic processes performed by a system including the combined PUF / RNG device.
[0060] The method 200 further includes rejecting the hardware source of the RNG in response to the PUF response output by the combined PUF / RNG device not matching a valid PUF response (block 210). In some examples, rejecting the hardware source of the RNG includes outputting an indication that the random numbers output by the RNG circuit were likely provided from a compromised source or that tampering with the RNG circuit was detected. In some examples, if the hardware source of the RNG is rejected, the RNG is no longer used for further cryptographic processes performed by a system that includes the combined PUF / RNG device.
[0061] 3 is a block diagram of a system 300 including secure communication between nodes 301 in an exclusive community over a network 303 using unique and random components generated by devices 302 in the nodes 301. Example protocols for creating unique and random components from devices are described in more detail herein.
[0062] In the example shown in Figure 3, system 300 is illustrated with two nodes 301, labeled node 301-A and node 301-B. It should be understood that system 300 may include any suitable number of nodes 301, and thus system 300 is not limited to a system having two nodes 301. Figure 3 further illustrates node 301-A coupled to node 301-B via network 303. It should be understood that network 303 may comprise one or more of wireless access points, communication lines, a wide area network (WAN), a local area network (LAN) such as an Ethernet network, cable groups, optical fiber, direct connections, or any other suitable system for communicatively coupling nodes 301 of system 300.
[0063] 3, node 301-A and node 301-B each include similar components for secure communications in system 300. Thus, for the sake of brevity and simplicity, only node 301-A will be described in detail using reference numbers for each component followed by the designator "-A." It should be understood that similar components are also included in node 301-B, identified by the same reference numbers followed by the designator "-B."
[0064] In the example shown in FIG. 3, node 301-A includes device 302-A. In some examples, device 302-A may be implemented as device 100, device 120, device 130, device 140, or device 150, as discussed above with respect to FIGS. 1A-1E. In some examples, device 302-A supports two or more functions for node 301-A by providing one or more outputs. In some examples, the outputs may include a standard component, a unique component, and a random component. In some examples, the unique component includes a PUF output and the random component includes one or more random numbers, as discussed above.
[0065] A first function supported by the device 302-A uses a standard component of the output from the device 302-A. For example, the device 302-A may include a sensor (e.g., a MEMS sensor) and the standard component may be a measurement of acceleration, rotational speed, pressure, temperature, airflow, or other measurement associated with the sensor.
[0066] A second function supported by device 302-A uses unique and / or random components for secure communication with other nodes 301 of system 300. In some examples, device 302-A allows for collection of (1) a unique component due to process variations during manufacturing that create unique aspects for device 302-A, and (2) a random component from noise within device 302-A. In some examples, the unique and random components output by device 302-A can be derived from active transistor circuitry and / or one or more MEMS structures included in device 302-A.
[0067] In some examples, node 301-A also includes one or more processors and memory for storing software or instructions for implementing functions for node 301-A. In the example shown in Figure 3, node 301-A includes standard function 307-A to support a first function of node 301-A. Standard function 307-A, among other things, uses standard components of the output of device 302-A to implement the standard function that node 301-A implements based on the output of device 302-A.
[0068] Node 301-A also includes instructions or software for implementing a second function of node 301-A. In the example shown in FIG. 3, node 301-A includes provenance function 308-A, encryption / decryption circuitry 312-A, and verification / authentication function 314-A. In some examples, device 302-A is configured to output random numbers from the RNG circuitry, which are used to generate random numbers used by encryption / decryption circuitry 312-A to securely transmit and receive data over network 303. In some examples, device 302-A is configured to output a PUF output from the PUF circuitry, which is used in conjunction with verification / authentication function 314-A to perform authentication that data received or transmitted by node 301-A is from an authorized node in system 300. In some examples, provenance function 308-A implements a physical unclonable function (PUF) for node 301-A using unique components from device 302-A, and provenance function 308-A is used in conjunction with verification / authentication function 314-A to perform authentication that data received or transmitted by node 301-A is from an authorized node in system 300.
[0069] 3, the system 300 also includes a master node 320 that is used to set up trust relationships between the nodes 301 of the system 300 that are within the exclusive community. The master node 320 is communicatively coupled to each of the nodes 301 via the network 303.
[0070] In some examples, each respective node 301 uses the provenance function 308 and unique components of the output of the device 302-A of each node 301 to generate multiple registries (e.g., thousands or tens of thousands of registries). These registries uniquely identify the particular node 301 as part of the trusted system 300. The master node 320 takes the registries generated by each node 301 (e.g., when the node 301 is configured) and provides the registries to all other nodes 301 in the system 300. These registries are stored as part of the provenance function 308 of each node 301 in the exclusive community, and effectively become a library of authorized users in the exclusive community of the system 300. By using these registry values, a given node 301 will only recognize data received from similarly equipped nodes 301. When data is received over the network 303, the receiving node 301 uses the registry in the provenance function 308 in conjunction with the verification / authentication function 314 to authenticate the input as originating from an authorized user. For example, the receiving node 301 can verify that the node 301 sending the data generated an output of an origin function 308 that corresponds to one of the registries provided by the master node 320 and included in its own origin function 308.
[0071] In another example, the master node 320 is configured to act as a certificate / certification authority (CA) for applications that use asymmetric cryptography. In such an example, the master node 320 is configured to issue digital certificates to the nodes 301, and the verification / authentication function 314 uses the issued digital certificates to authenticate inputs as originating from authorized users.
[0072] In the example shown in Figure 3, node 301-A also includes a transceiver 316-A that provides an interface for communicating with other nodes 301, such as node 301-B, over network 303. Although a single transceiver 316-A is shown in Figure 3, it should be understood that the single transceiver 316-A may be replaced with separate and distinct transmitter and receiver components.
[0073] In various aspects, the system elements, method steps, or examples (e.g., devices, systems, or components thereof) described throughout this disclosure may be implemented on one or more computer systems, including central processing units (CPUs), graphics processing units (GPUs), field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), and / or similar devices with hardware to execute code to implement those elements, processes, or examples, which code is stored in non-transitory data storage devices. These devices include or function with software programs, firmware, or other computer-readable instructions to perform various methods, process tasks, computations, and control functions.
[0074] These instructions are typically stored on any suitable computer-readable medium used for storing computer-readable instructions or data structures. Computer-readable media can be implemented as any available medium that can be accessed by a general purpose or specialized computer or processor, or any programmable logic device. Suitable processor-readable media can include storage or memory media, such as magnetic or optical media. For example, storage or memory media can include volatile or non-volatile media, such as conventional hard disks, Compact Disk-Read Only Memory (CD-ROM), Random Access Memory (RAM) (including, but not limited to, Synchronous Dynamic Random Access Memory (SDRAM), Double Data Rate (DDR) RAM, RAMBUS Dynamic RAM (RDRAM), Static RAM (SRAM), etc.), Read Only Memory (ROM), Electrically Erasable Programmable ROM (EEPROM), and Flash memory. Suitable processor-readable media may also include transmission media, such as electrical, electromagnetic, or digital signals transmitted over a communications medium, such as a network and / or wireless link.
[0075] The methods and techniques described herein may be implemented in part in digital electronic circuitry, or with a programmable processor (e.g., a special purpose processor, or a general purpose processor such as a computer), firmware, software, or a combination thereof. Apparatus embodying these techniques may include suitable input and output devices, a programmable processor, and a storage medium tangibly embodying program instructions for execution by the programmable processor. Processes embodying these techniques may be performed by a programmable processor executing a program of instructions to perform a desired function by operating on input data and generating appropriate output. The techniques may be advantageously implemented in one or more programs executable on a programmable system including at least one programmable processor coupled to receive data and instructions from and transmit data and instructions to a data storage system, at least one input device, and at least one output device. In general, the processor receives instructions and data from a read-only memory and / or a random access memory. Suitable storage devices for tangibly embodying computer program instructions and data include all forms of non-volatile memory, including, for example, semiconductor memory devices (EPROM, EEPROM, and flash memory devices), magnetic disks (internal hard disk or removable disk), magneto-optical disks, and DVD disks. Any of the foregoing may be supplemented by, or incorporated in, specially designed application-specific integrated circuits (ASICs). Exemplary embodiments
[0076] Example 1 includes a device, the device comprising a PUF circuit configured to generate a physical unclonable function PUF output in response to an input, and a random number generator (RNG) circuit configured to output one or more random numbers, the PUF circuit and the RNG circuit sharing one or more components such that modifying the RNG circuit modifies the PUF circuit, and the device configured to determine, based on the output of the PUF circuit, whether the RNG circuit is an untainted source of random numbers.
[0077] Example 2 includes the device of example 1, wherein the one or more components shared by the PUF circuitry and the RNG circuitry include one or more components of an active transistor circuit.
[0078] Example 3 includes the device of any one of examples 1-2, wherein the one or more components shared by the PUF circuitry and the RNG circuitry include one or more micro-electromechanical system (MEMS) structures.
[0079] Example 4 includes the device of any one of Examples 1 to 3, wherein the one or more components shared by the PUF circuit and the RNG circuit include one or more components of an active transistor circuit and one or more microelectromechanical systems (MEMS) structures.
[0080] Example 5 includes the device of any one of examples 1-4, wherein the PUF circuitry includes an active-transistor PUF circuitry that is separate from the one or more components shared by the PUF circuitry and the RNG circuitry.
[0081] Example 6 includes the device of any one of examples 1-5, wherein the RNG circuitry includes an active transistor RNG circuitry that is separate from the one or more components shared by the PUF circuitry and the RNG circuitry.
[0082] Example 7 includes the device of any one of examples 1-6, wherein the one or more components shared by the PUF circuitry and the RNG circuitry include a reconfigurable active transistor circuit.
[0083] Example 8 includes the device of any one of examples 1 to 7, wherein noise inherent to the PUF circuit is used as a seed for the RNG circuit.
[0084] Example 9 includes the device of any one of examples 1-8, wherein the device is configured to receive a PUF challenge and generate an output of the PUF circuit in response to the PUF challenge.
[0085] Example 10 includes the device of example 9, wherein the device is further configured to determine whether an output of the PUF circuit matches a valid PUF response to the PUF challenge; and in response to determining that the output of the PUF circuit matches the valid PUF response for the PUF challenge, verifying that the RNG circuit is an untainted source of random numbers, and in response to determining that the output of the PUF circuit does not match the valid PUF response for the PUF challenge, rejecting the RNG circuit as an untainted source of random numbers.
[0086] Example 11 includes the device of any one of examples 1-10, wherein the PUF circuitry and / or the RNG circuitry are implemented using only active transistor circuitry.
[0087] Example 12 includes a node comprising a physical unclonable function (PUF) circuit configured to generate a PUF output in response to an input; and a random number generator (RNG) circuit configured to output one or more random numbers, wherein the PUF circuit and the RNG circuit share one or more components such that modifying the RNG circuit modifies the PUF circuit, and one or more additional circuits are configured to utilize the PUF output and / or the one or more random numbers for one or more cryptographic processes, and the node is configured to determine whether the RNG circuit is an untainted source of random numbers based on the output of the PUF circuit.
[0088] Example 13 includes the node of example 12, wherein the one or more components shared by the PUF circuit and the RNG circuit include one or more components of an active transistor circuit and / or one or more microelectromechanical systems (MEMS) structures.
[0089] Example 14 includes the node of any one of Examples 12 to 13, wherein the PUF circuit includes an active transistor PUF circuit that is separate from one or more components shared by the PUF circuit and the RNG circuit, and / or the RNG circuit includes an active transistor RNG circuit that is separate from one or more components shared by the PUF circuit and the RNG circuit.
[0090] Example 15 includes the node of any one of Examples 12 to 14, wherein the one or more components shared by the PUF circuitry and the RNG circuitry include a reconfigurable active transistor circuit.
[0091] Example 16 includes the node of any one of examples 12-15, wherein the node is configured to receive a PUF challenge and generate an output of the PUF circuit in response to the PUF challenge.
[0092] Example 17 includes the node of Example 16, wherein the node is further configured to determine whether an output of the PUF circuit matches a valid PUF response to the PUF challenge; and in response to a determination that the output of the PUF circuit matches the valid PUF response for the PUF challenge, verifying that the RNG circuit is an untainted source of random numbers, and in response to a determination that the output of the PUF circuit does not match the valid PUF response for the PUF challenge, rejecting the RNG circuit as an untainted source of random numbers.
[0093] Example 18 includes a method, the method including receiving a physical unclonable function (PUF) challenge at a device including a PUF circuit and a random number generator (RNG) circuit that share one or more components; determining, with the PUF circuit of the device, a PUF response output in response to the PUF challenge; determining whether the PUF response output matches a valid PUF response; validating one or more hardware resources for the RNG circuit in response to a determination that the PUF response output matches the valid PUF response; and denying one or more hardware resources for the RNG circuit in response to a determination that the PUF response output does not match the valid PUF response.
[0094] Example 19 includes the method of example 18, further including using the one or more random numbers generated by the PUF response output and / or the one or more validated hardware resources for the RNG circuit for the one or more cryptographic processes.
[0095] Example 20 includes the method of any one of Examples 18 or 19, wherein determining whether the PUF response output matches a valid PUF response includes determining whether the PUF response output is within a threshold range of values.
[0096] Although specific embodiments have been illustrated and described herein, it will be understood by those skilled in the art that any configuration expected to achieve the same purpose may be substituted for the specific embodiment shown. Therefore, it is manifestly intended that this invention be limited only by the claims and the equivalents thereof.
Claims
1. A device (100, 120, 130, 140, 150, 302), a PUF circuit (102) configured to generate a physical unclonable function (PUF) output in response to an input; a random number generator (RNG) circuit configured to output one or more random numbers; the PUF circuit (102) and the RNG circuit (104) share one or more components (105) such that modification of the RNG circuit (104) modifies the PUF circuit (102); The device (100, 120, 130, 140, 150, 302) is configured to determine whether the RNG circuit (104) is an untainted source of random numbers based on the output of the PUF circuit (102).
2. the one or more components (105) shared by the PUF circuit (102) and the RNG circuit (104) include one or more components of an active transistor circuit (106); and / or The device of claim 1 , wherein the one or more components shared by the PUF circuit and the RNG circuit include one or more microelectromechanical systems (MEMS) structures.
3. The device of claim 1 , wherein the one or more components shared by the PUF circuit and the RNG circuit include a reconfigurable active transistor circuit.