Multi-resolution overlay metrology targets
Patent Information
- Application Number
- JP2024207254
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2021-06-17
- Filing Date
- 2024-11-28
- Publication Date
- 2025-02-14
- Estimated Expiration
- Not applicable · inactive patent
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Figure 2025023083000001_ABST
Abstract
Description
[Technical field]
[0001] The present invention relates generally to semiconductor device manufacturing, and more particularly to methods and target features for semiconductor circuit metrology. [Background technology]
[0002] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit of U.S. Provisional Patent Application No. 63 / 176,888, filed April 20, 2021.
[0003] Semiconductor circuits are typically manufactured using a process called photolithography, in which a semiconductor substrate is patterned by depositing a thin layer of a light-sensitive polymer (photoresist) and using light or other radiation to leave portions of the substrate covered by the photoresist. After patterning, the substrate is modified by processes such as etching or ion bombardment that change its physical properties and surface shape (topography), but the portions of the substrate covered by the photoresist are unaffected.
[0004] The properties of the patterned photoresist, such as the surface shape and position of the patterned features, are measured using semiconductor circuit metrology. To ensure high yields in the photolithography process, it is important that the position of the patterned features in the photoresist is accurate with respect to the previously processed layer. The error (misalignment) of the patterned photoresist with respect to the processed layer below is called the "overlay error". As an example, for a typical semiconductor circuit with a minimum line width of 10-14 nm (the so-called 10 nm design rule), the maximum allowable overlay error is 2-3 nm. In cutting-edge semiconductor circuits, line widths have narrowed to 5 nm, and the maximum allowable overlay error has decreased accordingly.
[0005] Overlay error is typically measured using optical overlay metrology tools because optical radiation at visible and infrared wavelengths can pass through not only the photoresist layer but also the dielectric layers underneath. In addition, infrared wavelengths can pass through semiconductor substrates such as silicon, allowing measurements through the semiconductor substrate. Optical overlay metrology tools, such as KLA Corporation's (Milpitas, Calif., USA) Archer® series of tools, image overlay targets (such as KLA's AIM® overlay targets) located at the scribe lines (lines separating adjacent dies) of the semiconductor substrate. Image analysis algorithms are applied to the resulting image to determine the location of the center of symmetry (CoS) of the target features in the fabricated layer and the CoS of the target features in the patterned photoresist layer. The overlay error is calculated as the distance between the centers of symmetry of the target features in the two layers.
[0006] US Patent No. 5,399,633 describes an overlay mark and a method for determining overlay error, and is incorporated herein by reference. One aspect of US Patent No. 5,399,633 relates to a continuously varying offset mark. A continuously varying offset mark is a single mark that includes superimposed periodic structures whose offset from one another varies with position. As an example, the periodic structures may correspond to gratings with different grating properties, such as pitch. Another aspect of US Patent No. 5,399,633 relates to a method for determining overlay error from the continuously varying offset mark.
[0007] As used herein and in the claims, the terms "light ray," "optical radiation," "light," and "radiation beam" generally refer to all visible, infrared, and ultraviolet radiation. [Prior art documents] [Patent documents]
[0008] [Patent Document 1] U.S. Patent No. 7,440,105 Summary of the Invention [Problem to be solved by the invention]
[0009] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The embodiments of the present invention described below provide improved target features and methods for semiconductor circuit metrology. [Means for solving the problem]
[0010] Thus, according to one embodiment of the present invention, there is provided an article of manufacture including at least one semiconductor substrate, a plurality of thin film layers deposited on the at least one substrate, and an overlay target formed on at least one of the thin film layers, the overlay target including a first sub-target having a first center of symmetry and including a first target feature having a first linewidth, and a second sub-target having a second center of symmetry coinciding with the first center of symmetry and including a second target feature having a second linewidth greater than the first linewidth and adjacent to but not overlapping the first target feature.
[0011] In some embodiments, the first sub-target spans a first region of the at least one semiconductor substrate, the second sub-target spans a second region of the at least one semiconductor substrate, the second region being larger than and including the first region, and the first sub-target is surrounded by the second sub-target.
[0012] In some embodiments, the plurality of thin film layers includes a first layer and a second layer overlying the first layer, the first target features include a first set of the first target features formed in the first layer and a second set of the first target features formed in the second layer, and the second target features include a third set of the second target features formed in the first layer and a fourth set of the second target features formed in the second layer.
[0013] In some embodiments, the first and second target features comprise line gratings. In one embodiment, the first set of the first target features comprises a first line grating in the first layer and the second set of the first target features comprises a second line grating in the second layer, each of the first line gratings being adjacent to but not overlapping the second line grating, the third set of the second target features comprises a third line grating in the first layer, and the fourth set of the second target features comprises a fourth line grating in the second layer, each of the third line gratings being adjacent to but not overlapping the fourth line grating.
[0014] In another embodiment, the line gratings of each of the first and second sub-targets include a first line grating having a first orientation and a second line grating having a second orientation orthogonal to the first orientation.
[0015] In some embodiments, the first and second target features include line features. In one embodiment, the line features are arranged to define a line grid. Alternatively, the line features are arranged to define a square frame, such that the square frame of the first sub-target is contained within the square frame of the second sub-target.
[0016] In another embodiment, the first and second target features include respective matrices of square features.
[0017] According to an embodiment of the present invention, there is also provided a method for measuring overlay error, comprising depositing and patterning a plurality of thin film layers on at least one semiconductor substrate, thereby defining a matrix of integrated circuit chips, and forming an overlay target on at least one of the thin film layers, the overlay target comprising a first sub-target having a first center of symmetry, the first sub-target including a first target feature having a first line width, and a second sub-target having a second center of symmetry coinciding with the first center of symmetry, the second sub-target including a second target feature having a second line width greater than the first line width and adjacent to but not overlapping the first target feature. The method further comprises capturing an image of the overlay target and processing the image to measure the overlay error between the thin film layers.
[0018] In some embodiments, capturing the image includes capturing a first image of the first sub-target using first inspection optics having a first field of view, and capturing a second image of the second sub-target using second inspection optics having a second field of view that is wider than the first field of view.
[0019] In another embodiment, the step of depositing and patterning the plurality of thin film layers includes forming the first sub-target in a first region of the at least one semiconductor substrate corresponding to the first field of view, and forming the second sub-target in a second region of the at least one semiconductor substrate that is larger than the first region and corresponds to the second field of view.
[0020] The present invention will be better understood by reading the following detailed description of the embodiments in conjunction with the drawings. [Brief description of the drawings]
[0021] [Figure 1a] 1 is a schematic side view of an optical metrology apparatus for measuring overlay error of a semiconductor substrate, in accordance with one embodiment of the present invention; [Figure 1b] FIG. 1b is a schematic side view of an optical subsystem within the optical metrology device of FIG. 1a, in accordance with one embodiment of the present invention. [Figure 2a] 1 is a schematic front view of an overlay target according to one embodiment of the present invention; [Figure 2b] FIG. 2b is a schematic front view of a sub-target used in constructing the overlay target of FIG. 2a, in accordance with one embodiment of the present invention. [Figure 2c] FIG. 2b is a schematic front view of a sub-target used in constructing the overlay target of FIG. 2a, in accordance with one embodiment of the present invention. [Figure 3a] 1 is a schematic front view of an overlay target according to an alternative embodiment of the present invention. [Figure 3b] FIG. 3b is a schematic front view of a sub-target used in constructing the overlay target of FIG. 3a, in accordance with one embodiment of the present invention. [Figure 3c] FIG. 3b is a schematic front view of a sub-target used in constructing the overlay target of FIG. 3a, in accordance with one embodiment of the present invention. [Figure 4a] 1 is a schematic front view of an overlay target according to another embodiment of the present invention. [Figure 4b] 1 is a schematic front view of an overlay target according to another embodiment of the present invention. [Figure 4c] 2 is a schematic front view of an overlay target according to another embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0022] Overlay metrology overlay targets are typically used to precisely and accurately measure the overlay error between successive pattern layers on a semiconductor substrate. Such successive pattern layers may include, for example, a working layer and a resist layer (photoresist), or two working layers in post-etch applications. Thus, although the following description of some exemplary embodiments is given in terms of a working layer and a resist layer, the principles of these embodiments may also be applied, mutatis mutandis, to a first working layer and a second working layer.
[0023] Some semiconductor manufacturing processes use two overlay metrology tools with vastly different sized fields of view (FOV). For example, in a process where two silicon substrates are bonded together, one overlay tool can be used to measure the alignment of the two substrates to each other during the bonding step. The overlay tool uses illumination that includes infrared (IR) radiation, since IR wavelengths of optical radiation pass through the silicon substrate, and the FOV can be fixed wide or adjustable (zoom) (the illumination spectrum can also include visible optical radiation, since some of the overlay target features can be located on the substrate surface facing the overlay metrology tool). After the substrates are bonded and polished, another overlay tool can be used to verify the achieved wafer-to-wafer (or die-to-wafer) alignment, using visible illumination and a narrow FOV. Alternatively, a single overlay metrology tool can be used to both measure the overlay error through the substrate and then verify it. Provided that this single tool has the required combination of field of view and a broad illumination spectrum covering both visible and infrared wavelengths. Two separate optical metrology tools or a single tool with the required capabilities could cover the required working distance, focus accuracy, and illumination options.
[0024] In other semiconductor processes, more than two substrates may be bonded together, and in still other processes, individual semiconductor dies may be bonded to a substrate.
[0025] The performance of image-based overlay metrology is highly dependent on the size of the overlay target in relation to the FOV of the overlay metrology tool. If the overlay target is significantly smaller than the FOV, the metrology tool will collect overlay error measurement signals from only a portion of the FOV. This will reduce the signal-to-noise ratio of the measurements and possibly impair the resolution of individual target features. Furthermore, the small features of a small overlay target may not be well matched to the optical resolution of a wide FOV metrology tool. However, if the overlay target is significantly larger than the FOV, the measurement results may be distorted or even missed because the large target features may cause some of the data required for the measurement to fall outside the capture area. For example, if an overlay target is matched to an IR overlay metrology tool with a typical wide FOV of 60 μm × 60 μm, it will fall outside the typical narrow FOV of a visible overlay metrology tool with a 30 μm × 30 μm FOV, and the target features may be too coarse for the visible tool. If an overlay target is aligned with the 30 μm × 30 μm FOV of a visible metrology tool, then the IR tool will only use a portion of the 60 μm × 60 μm FOV, resulting in poor signal-to-noise ratio, and the target features may be too small for the IR tool's optimal resolution.
[0026] A promising solution is to use two separate side-by-side overlay targets, one aligned with the wide FOV tool and the other aligned with the narrow FOV tool. However, this solution requires that the overlay error be measured at two spatially separated positions, and comparison between the measurements can be affected by the overlay error's dependence on the spatial position of the overlay target. Furthermore, this type of solution makes inefficient use of valuable "real estate" on the semiconductor substrate.
[0027] The mismatch between the various sizes of the field of view and the size of the overlay target is addressed by the embodiments of the invention described herein by providing a synthetic overlay target. The synthetic overlay target includes a small first sub-target and a large second sub-target, the first sub-target being concentrically surrounded by the second sub-target. The first sub-target matches well with a narrow FOV overlay tool, both in terms of its overall dimensions and feature size. Similarly, the dimensions and feature size of the second sub-target match with a wide FOV overlay tool. Thus, when measuring the overlay error with a narrow FOV overlay tool, an image of the first sub-target is captured in the tool and the overlay error is measured with the accuracy that can be achieved with this target. When measuring the overlay error with a wide FOV overlay tool, an image of the entire target is captured. The wide FOV overlay tool can ignore the portion of the first sub-target that is in the center of the FOV and measure the overlay error only from the second sub-target that is optimized for the wide FOV.
[0028] The concentricity of the first and second sub-targets allows accurate matching of the overlay errors measured by the narrow and wide FOV overlay metrology tools, for example by directly comparing the overlay errors measured by the two tools and / or by comparing overlay error models between the two tools. The accuracy of the measurement is further improved by taking into account the correlation of the overlay errors measured separately by each tool as well as the modeled overlay errors. A quality metric of the overlay error measurements can be obtained separately for each sub-target, to validate the overlay error measurements from each tool and to ensure their consistency.
[0029] In embodiments disclosed herein, multiple thin film layers are deposited and patterned on one or more semiconductor substrates, whereby overlay targets are formed on the thin film layers. Each overlay target includes first and second sub-targets, with two sub-targets having coincident centers of symmetry. The two sub-targets are formed adjacent but non-overlapping within the area of the overlay target. The first sub-target includes a first target feature having a first line width, and the second sub-target includes a target feature having a second line width.
[0030] In the context of this description and the claims, the term "linewidth" refers to the narrower lateral dimension of a feature, e.g., the width of a line-shaped feature rather than its length. (The "lateral" dimension is the dimension of the feature in the plane of the thin film layer in which it is formed.) For symmetrical features, such as square or circular features, the lateral dimensions of the features are equal to each other, so "linewidth" refers to either of those dimensions.
[0031] System Description Reference is now made to Figures 1a and 1b, which diagrammatically illustrate an optical metrology apparatus 10 for measuring overlay error on a semiconductor substrate 12, in accordance with one embodiment of the present invention. Figure 1a illustrates a side view of apparatus 10 including optical subsystems 11 and 13, while Figure 1b illustrates a side view showing details of subsystem 11. Although Figures 1a and 1b illustrate apparatus 10 with illumination directed to substrate 12 from the same side as the collection optics of optical subsystems 11 and 13, in an alternative embodiment illumination may be directed from below the substrate through a suitably transmissive motion assembly 20.
[0032] With reference to FIG. 1a, an optical metrology device 10 comprises two optical subsystems 11 and 13, referred to as OPT1 and OPT2, respectively, for measuring overlay errors on a semiconductor substrate 12. OPT1 has a narrow field of view FOV1, e.g., with dimensions 30 μm×30 μm, and OPT2 has a wide field of view FOV2, e.g., with dimensions 60 μm×60 μm. In this example, OPT1 uses visible light illumination for measuring overlay errors, and OPT2 uses IR illumination. The dimensions of FOV1 and FOV2 and the spectral ranges of OPT1 and OPT2 used here are merely exemplary. Other dimensions and spectral ranges can be used instead to illustrate narrow and wide FOV devices for various metrology applications. For example, in an alternative embodiment, the optical subsystem 13 (OPT2) can include a light source emitting optical radiation and a measurement optics (zoom optics) with a variable FOV. In another alternative embodiment, optical subsystems 11 and 13 (OPT1 and OPT2) may comprise a single optical system with an appropriately adjustable FOV, illumination spectrum, and collection mechanism.
[0033] The device 10 further comprises a controller 18 and one or more motion assemblies 20. The controller 18 is coupled to receive images from the sensors of OPT1 and OPT2 (shown in detail in FIG. 1b) and adjusts the position and orientation of the motion assemblies 20. The controller 18 typically comprises a programmable processor and digital and / or analog interfaces suitable for connection to other elements of the device 10. The programmable processor is programmed in software and / or firmware to perform the functions described herein. Alternatively or additionally, the controller 18 comprises hardwired and / or programmable hardware logic circuits performing at least a part of its functions. In FIGS. 1a and 1b, the controller 18 is shown as a single monolithic functional block for simplicity, but in practice it may include several control units, which are interconnected by interfaces suitable for receiving / outputting signals as shown in the figures and described in the text.
[0034] In the illustrated embodiment, the motion assembly 20 comprises a suitable stage equipped with actuators whose purpose is to linearly move the stage in x, y, and z directions, and to rotate about the z axis, relative to Cartesian coordinates 36, under the control of the controller 18. Cartesian coordinates 36 are shown in this and subsequent figures for clarity of orientation of the figures relative to the apparatus 10.
[0035] A number of thin film layers are deposited and patterned on the semiconductor substrate 12 to define a matrix of integrated circuit chips, and an overlay target is formed on at least one of the thin film layers. In the illustrated embodiment, a first thin film layer 38 and a second thin film layer 40 are deposited on the semiconductor substrate 12 and patterned in a photolithographic process. For example, the first layer 38 may be a processing layer and the second layer 40 may be a resist layer deposited on the processing layer. Alternatively, both layers 38 and 40 may be processing layers. In order to measure the overlay error between the pattern of the layer 40 on the substrate 12 and the pattern of the layer 38 below it, the layers 38 and 40 are photolithographically formed with an overlay target including first and second sub-targets suitable for two fields of view as shown in the following figures.
[0036] When measuring overlay error in the apparatus 10, the controller 18 moves the motion assembly 20 to bring the semiconductor substrate 12 closer to, for example, OPT1 so that the overlay target is within FOV1, and the overlay error is measured using OPT1. For another manufacturing step, such as bonding two semiconductor substrates together, the controller 18 may move the motion assembly 20 in the xy plane, as indicated by arrow 15, to bring the semiconductor substrate 12 closer to OPT2 so that the overlay target is within FOV2, and the overlay error is measured using OPT2. (For simplicity, only one substrate 12 is shown.) Alternatively, the optical subsystems 11 and 13 may include two separate motion assemblies 20 for OPT1 and OPT2. When a new overlay error measurement is to be performed with OPT1, the substrate 12 may be moved back to OPT1. As will be explained in more detail below, each of the optical subsystems utilizes a particular portion of the overlay target, which is aligned with the FOV of each optical subsystem.
[0037] Referring to FIG. 1b, the optical subsystem 11 (OPT1) includes an imaging assembly 14 and an illumination assembly 16. The imaging assembly 14 includes an objective lens 22, a cube beam splitter 24, and an imaging lens 26, which together form the measurement optics of the optical subsystem 11. The imaging assembly 14 further includes a sensor 28, which may include, for example, a complementary metal oxide semiconductor (CMOS) detector including a two-dimensional array of pixels 30. As another example, for sensing under short-wave IR illumination, the sensor 28 may include an InGaAs-based focal plane array (FPA) detector including a two-dimensional array of pixels 30. The field of view of the imaging assembly 14 is FOV1, which has a dimension of 30 μm×30 μm, referring to FIG. 1a. The illumination assembly 16 includes a light source 32 for emitting optical radiation, and a lens 34. Additionally, in some embodiments, light source 32 and / or imaging assembly 14 may include polarizing optics to control the polarization of the optical radiation they emit / collect, respectively.
[0038] When OPT1 is used to measure the overlay error between a pattern in layer 40 on substrate 12 and a pattern in layer 38 below, controller 18 commands motion assembly 20 to move the substrate under objective lens 22. This movement brings a central portion of the overlay target into the field of view FOV1 of OPT1 and causes the combined optics of objective lens 22 and lens 26 to image the substrate onto sensor 28, i.e., the substrate and the sensor are located in an optically conjugate plane.
[0039] To capture an image of the first sub-target, a beam of optical radiation is projected from the light source 32 onto the lens 34, from which it is further projected onto the cube beam splitter 24, reflected by the beam splitter 24 to the objective lens 22, and projected by the objective lens 22 onto the substrate 12. The radiation incident on the substrate 12 is scattered back into the objective lens 22, passes through the beam splitter 24, and is directed to the lens 26 where it is focused onto the sensor 28. The image captured by the sensor 28 is read and processed by the controller 18, as described in more detail below, to identify the centres of symmetry of the respective first sub-targets in the layer 40 and the layer 38 below on the substrate 12. The controller 18 measures the overlay error between these two pattern layers based on the offset between the centres of symmetry of the first sub-targets in the respective layers.
[0040] The optical subsystem 13 (OPT2) is also similar to the optical subsystem 11 (OPT2) described above. The relevant differences between these optical subsystems are their field of view and the wavelength of optical radiation they use for measurement. These differences are caused by the different designs of the imaging and illumination assemblies of these two optical subsystems.
[0041] Alternatively, the apparatus 10 may be configured to measure overlay error in a scatterometry mode, in which the lens 26 is altered and / or moved to image an exit pupil (not shown) of the objective lens 22 onto the sensor array 28. This scatterometry image indicates the angular distribution of optical radiation scattered from the target features, and the controller 18 in this case is configured to process this angular distribution to measure the overlay error.
[0042] Example of an overlay target Figures 2a-2c show an overlay target 200 and its structure according to one embodiment of the present invention. Figure 2a is a schematic front view of the overlay target 200, while Figures 2b and 2c are schematic front views of a first sub-target 202 and a second sub-target 204, respectively, within the target 200. Sub-target 202 spans a narrow FOV and therefore can be imaged by optical subsystem 11 (Figure 1a), while sub-target 204 spans a wider FOV and therefore can be imaged by optical subsystem 13.
[0043] As shown in Fig. 2b, the first sub-target 202 includes eight gratings 206, 208, 210, 212, 214, 216, 218, and 220 arranged in pairs adjacent to each other (but without overlapping). Gratings 206, 210, 214, and 218 are formed in thin-film layer 38, and gratings 208, 212, 216, and 220 are formed in thin-film layer 40. Each grating includes a number of parallel lines with equal line widths, with half of the grating pairs having grating lines oriented in the x-direction and the other half having grating lines oriented in the y-direction. Thus, in the illustrated embodiment, gratings 206, 208, 214, and 216 are orthogonally oriented to gratings 210, 212, 218, and 220.
[0044] For example, the first sub-target 202 has a dashed square 222 with dimensions 30 μm×30 μm superimposed to indicate the FOV1 of OPT1, showing that the grid of the first sub-target spans the 30 μm×30 μm FOV (with a portion of the grid "spills" beyond FOV1). The line width of the grids 206, 208, 210, 212, 214, 216, 218, and 220 of the first sub-target 202 is, for example, 1 μm, so that when an image of the first sub-target is captured by OPT1, the image has good contrast.
[0045] 1b, when measuring the overlay error between layers 38 and 40 from the first sub-target 202 using the optical subsystem 11, the controller 18 reads out an image of the first sub-target (within the FOV1 of OPT1) captured by the sensor 28. The controller 18 further processes the image to identify a center of symmetry 221 of the pattern formed by the gratings 206, 210, 214, and 218 and a center of symmetry 223 of the pattern formed by the gratings 208, 212, 216, and 220. The controller 18 measures the overlay error between the two pattern layers as the deviation between the centers of symmetry 221 and 223 of the first sub-target 202 of the respective layers.
[0046] As shown in Fig. 2c, the second sub-target 204 includes eight gratings 224, 226, 228, 230, 232, 234, 236, and 238, which are arranged in pairs adjacent to each other. As with the first sub-target 202, the gratings 224, 228, 232, and 236 are formed in the thin-film layer 38, and the gratings 226, 230, 234, and 238 are formed in the thin-film layer 40. Each grating includes a number of parallel lines with equal line widths, with half of the grating pairs having grating lines oriented in the x-direction and the other half having grating lines oriented in the y-direction. Thus, the gratings 224, 226, 232, and 234 are orthogonal to the gratings 228, 230, 236, and 238. However, the line width of the grid of the second sub-target 204 is, for example, 2 μm (rather than 1 μm as in the first sub-target 202) to provide good contrast in the image of the second sub-target when it is captured by OPT2. For example, the second sub-target 204 is overlaid with a dashed square 240 having dimensions of 60 μm×60 μm to indicate the FOV2 of OPT2, showing that the grid of the second sub-target spans FOV2.
[0047] When using OPT2 to measure the overlay error between layers 38 and 40 from the second sub-target 204, controller 18 reads an image of the second sub-target from OPT2 (which image includes an image of the first sub-target 202 at the center of FOV2). Controller 18 processes the image (blocking or ignoring the portion of the image from the first sub-target 202) to identify a center of symmetry 242 of the pattern formed by gratings 224, 228, 232, and 236 and a center of symmetry 244 of the pattern formed by gratings 226, 230, 234, and 238. Controller 18 measures the overlay error between the two pattern layers as the deviation between the centers of symmetry 242 and 244 of the second sub-target 204 of the respective layers.
[0048] Figures 3a-3c show an overlay target 300 and its structure according to an alternative embodiment of the present invention. Figure 3a is a schematic front view of the overlay target 300, while Figures 3b and 3c are schematic front views of a first sub-target 302 and a second sub-target 304, respectively, within the target 300.
[0049] As shown in FIG. 3b, the first sub-target 302 includes eight gratings 306, 308, 310, 312, 314, 316, 318, and 320 arranged adjacent to each other in pairs. Gratings 306, 310, 314, and 318 are formed in thin-film layer 38, and gratings 308, 312, 316, and 320 are formed in thin-film layer 40. Each grating includes multiple parallel lines with equal line widths, with half of the grating pairs having grating lines oriented in the x-direction and the other half having grating lines oriented in the y-direction. For example, the first sub-target 302 is overlaid with a dashed square 322 having dimensions of 30 μm×30 μm to indicate the FOV1 of OPT1, showing that the gratings of the first sub-target span just over and just below FOV1. The line width of the gratings 306, 308, 310, 312, 314, 316, 318, and 320 of the first sub-target 302 is, for example, 1 μm, to provide good contrast in the image of the first sub-target when it is captured with OPT1. The first sub-target 302 differs from the first sub-target 202 in that its grating does not extend outside of FOV1.
[0050] When using OPT1 to measure the overlay error between layers 38 and 40, controller 18 measures the offset between centers of symmetry 324 and 326 of the first subtarget 302 of each layer, as well as the first subtarget 202. Center of symmetry 324 is for the pattern formed by gratings 306, 310, 314, and 318, and center of symmetry 326 is for the pattern formed by gratings 308, 312, 316, and 320.
[0051] As shown in Fig. 3c, the second sub-target 304 includes eight gratings 330, 332, 334, 336, 338, 340, 342, and 344 arranged in pairs adjacent to each other. As with the first sub-target 302, the gratings 330, 334, 338, and 342 are formed in the thin film layer 38, and the gratings 332, 336, 340, and 344 are formed in the thin film layer 40. As with the first sub-target 302, each grating includes multiple parallel lines with equal line widths, with half of the grating pairs having grating lines oriented in the x-direction and the other half having grating lines oriented in the y-direction. However, the line width of the gratings of the second sub-target 304 is, for example, 2 μm, to provide good image contrast when captured by OPT2. For example, the second sub-target 304 has a dotted square 346 with dimensions 60 μm×60 μm superimposed on it to indicate FOV2, indicating that the grid of the second sub-target spans FOV2. The second sub-target 304 differs from the second sub-target 204 in that its grid spans the entire area outside the central 30 μm×30 μm FOV.
[0052] When using OPT2 to measure the overlay error between layers 38 and 40, controller 18 measures the offset between centers of symmetry 348 and 350 of second subtarget 304 of each layer as well as first subtarget 302. Center of symmetry 348 is for the pattern formed by gratings 330, 334, 338, and 342, and center of symmetry 350 is for the pattern formed by gratings 332, 336, 340, and 344.
[0053] In an alternative embodiment (not shown), each sub-target in overlay targets 200 and 300 may include grating-like structures. These structures are formed by disposing two superimposed gratings with slightly different pitches in layers 38 and 40. Overlay targets of this type are described in the above-mentioned U.S. Pat. No. 7,440,105, and the method described therein may be used to measure the overlay error between layers 38 and 40.
[0054] 4a-4c are schematic front views of overlay targets 400, 402 and 404 according to another embodiment of the present invention.
[0055] As shown in FIG. 4a, the overlay target 400 includes a first sub-target 410 and a second sub-target 412. The first sub-target 410 and the second sub-target 412 are outlined by dotted squares 406 and 408, which correspond to the fields of view of, for example, OPT1 and OPT2, respectively. The first sub-target 410 is formed by a matrix of squares 414 and 416 contained within the dotted square 406. The second sub-target 412 is formed by a matrix of squares 418 and 420 in the area between the dotted squares 406 and 408. In the first sub-target 410, the square 414 is formed in the first layer 38, and the square 416 is formed in the second layer 40. The dimensions of each of the squares 414 and 416 are, for example, 1 μm×1 μm (corresponding to a line width of 1 μm) to match the optical resolution of OPT1. In the second sub-target 412, a square 418 is formed in the first layer 38 and a square 420 is formed in the second layer 40. The dimensions of each of the squares 418 and 420 are, for example, 2 μm×2 μm (corresponding to a line width of 2 μm) to match the optical resolution of OPT2.
[0056] Alternatively, sub-targets 410 and 412 may each comprise a rectangular matrix having an appropriate line width.
[0057] The apparatus 10 measures the overlay error between layers 38 and 40 using OPT1 in a manner similar to the measurement of the overlay error from overlay target 200 (FIGS. 2a-2c) by measuring the offset between the respective centers of symmetry of the matrix of squares 414 and the matrix of squares 416 of the first sub-target 410 (for simplicity, the centers of symmetry are not shown). Similarly, the apparatus 10 measures the overlay error between layers 38 and 40 using OPT2 by measuring the offset between the respective centers of symmetry of the matrix of squares 418 and the matrix of squares 420 of the second sub-target 412.
[0058] As shown in Fig. 4b, the overlay target 402 includes a first sub-target 426 and a second sub-target 428, which are outlined by dashed squares 422 and 424, which correspond to the fields of view of, for example, OPT1 and OPT2, respectively. The first sub-target 426 is formed by two square frames 430 and 432 within the square 422, and the second sub-target 428 is formed by two square frames 434 and 436 within the area between the squares 422 and 424. The frames 430 and 434 are formed in layer 38, and the frames 432 and 436 are formed in layer 40. The line width of frames 430 and 432 of the first sub-target 426 is, for example, 1 μm to match the optical resolution of OPT1, and the line width of frames 434 and 436 of the second sub-target 428 is, for example, 2 μm to match the optical resolution of OPT2.
[0059] Apparatus 10 measures the overlay error between layers 38 and 40 using OPT1 by measuring the offset between the centers of symmetry of frames 430 and 432 of the first sub-target 426 (for simplicity, the centers of symmetry are not shown). Similarly, apparatus 10 measures the overlay error between layers 38 and 40 using OPT2 by measuring the offset between the centers of symmetry of frames 434 and 436 of the second sub-target 428.
[0060] As shown in FIG. 4c, the overlay target 404 includes a first sub-target 444 and a second sub-target 446, which are outlined by dashed squares 440 and 442, corresponding to the fields of view of, for example, OPT1 and OPT2, respectively. The first sub-target 444 is formed by lines 448 and 450, and the second sub-target 446 is formed by lines 452 and 454. In the first sub-target 444, the line 448 is formed in layer 38, the line 450 is formed in layer 40, and all lines are formed within the square 440 (i.e., within the FOV1 of OPT1). Half of the lines 448 and 450 are oriented in the x-direction and the other half are oriented in the y-direction. The widths of the lines 448 and 450 are selected to match the optical resolution of OPT1. In the second subtarget 446, lines 452 are formed in layer 38 and lines 454 are formed in layer 40, with all lines formed in the area between squares 440 and 442. Half of the lines 452 and 454 point in the x-direction and the other half point in the y-direction. The widths of the lines 452 and 454 are selected to match the optical resolution of OPT2.
[0061] Apparatus 10 measures the overlay error between layers 38 and 40 by OPT1 by measuring the offset between the centers of symmetry of the pattern formed by lines 448 and 450 of the first sub-target 444 (centers of symmetry not shown for simplicity). Similarly, apparatus 10 measures the overlay error between layers 38 and 40 by OPT2 by measuring the offset between the centers of symmetry of the pattern formed by lines 452 and 454 of the second sub-target 446.
[0062] In the above-described embodiments, sub-target dimensions of 30 μm×30 μm and 60 μm×60 μm and line widths of 1 μm and 2 μm were selected to match the characteristic fields of view and resolution levels of the exemplary optical subsystems OPT1 and OPT2. Alternatively, larger or smaller sub-target dimensions and larger or smaller feature line widths can be used depending on the characteristics of the inspection optics used to measure the overlay error.
[0063] Additionally, while the foregoing figures show particular types of target features and configurations as examples, the principles of the present invention may likewise be practiced with overlay targets and sub-targets including other types of features and configurations, and all such alternative embodiments are considered to be within the scope of the present invention.
[0064] Additional Applications of Multi-Resolution Overlay Targets By including target features with different design parameters (e.g., different spatial frequencies) in the same layer (e.g., thin film layer 40), overlay error metrology can be used to measure the apparent shift between these different target features. For example, referring to Figs. 2b and 2c, the patterns of the first sub-target 202 and the second sub-target 204 in layer 40 are formed in the same photolithography step. Therefore, no shift should be expected between the positions of the symmetry centers 223 and 244 measured by OPT1 and OPT2, respectively. However, due to errors caused by optical aberrations or obstacles in each of the optical subsystems OPT1 and OPT2, the shift between the measured positions of the symmetry centers may be non-zero. Characterization of these errors can be used to correct for errors in the overlay error measurement. These errors can also be fed forward to the manufacturing process to reduce measurement errors in subsequent manufacturing stages, specifically due to the alignment system used to align and bond two semiconductor substrates.
[0065] Additionally or alternatively, the controller 18 can determine a modeled overlay error for each set in order to compare the two sets of overlay errors measured by the optical subsystems OPT1 and OPT2, respectively. Comparisons of both measured and modeled overlay errors within and between each optical subsystem can be used to improve the accuracy of the metrology results. Additionally or alternatively, a quality metric of the overlay error measurements can be obtained separately for each sub-target, in order to validate and align the overlay error measurements from each tool.
[0066] Additionally or alternatively, similar measurements of offset between target features in the same layer may indicate pattern placement errors due to optical aberrations in the photolithography system (scanner), as these aberrations can cause printed features of different spatial frequencies to be offset from one another. Knowledge of these placement errors may allow for the reduction of their effects in electronic devices formed by photolithography processes.
[0067] By analyzing the characteristics of the angular spectra obtained from two different target features, or from two different measurement configurations of a particular feature, it may be possible to reduce errors in overlay error measurements due to asymmetry in the target features.
[0068] Combining measurements of overlay error from multiple overlay targets, such as those shown in Figures 2a, 3a, and 4a-4c, can reduce the total measurement uncertainty (TMU) of those measurements.
[0069] The multi-resolution overlay target described above can be adapted to span three or more thin film layers, thus allowing measurement of the overlay error between any pair of those layers.
[0070] It will be understood that the above-described embodiments are cited by way of example, and that the present invention is not limited to what has been particularly shown and described above. Rather, the scope of the present invention includes combinations and sub-combinations of the various features described above, as well as variations and modifications thereof not disclosed in the prior art that would occur to one skilled in the art upon reading the above description.
Claims
1. At least one semiconductor substrate; a plurality of thin film layers deposited on the at least one substrate; an overlay target formed on at least one of the thin film layers, the overlay target comprising: a first sub-target having a first center of symmetry, the first sub-target including a first target feature having a first linewidth; a second sub-target having a second center of symmetry that coincides with the first center of symmetry, the second sub-target having a second line width greater than the first line width and including a second target feature adjacent to but not overlapping the first target feature; the second target feature and the first target feature have the same shape; the plurality of thin film layers includes a first layer and a second layer overlying the first layer; the first target features include a set of the first target features formed in the first layer and a set of the first target features formed in the second layer, the second target features include a set of the second target features formed in the first layer and a set of the second target features formed in the second layer, and further The article, wherein the first and second target features include a line grating.
2. the set of first target features includes a first line grating in the first layer and a second line grating in the second layer, the first line grating and the second line grating being adjacent but non-overlapping; the set of second target features includes a third line grating in the first layer and a fourth line grating in the second layer, the third line grating and the fourth line grating being adjacent but non-overlapping; 2. The article of manufacture of claim 1.
3. 2. The article of manufacture of claim 1, wherein the line grating of each of the first and second sub-targets includes a line grating having a first orientation and a line grating having a second orientation orthogonal to the first orientation.
4. 1. A method for measuring overlay error, comprising the steps of: depositing and patterning a plurality of thin film layers on at least one semiconductor substrate, thereby defining a matrix of integrated circuit chips; forming an overlay target on at least one of the thin film layers, the overlay target comprising: a first sub-target having a first center of symmetry, the first sub-target including a first target feature having a first linewidth; a second sub-target having a second center of symmetry that coincides with the first center of symmetry, the second sub-target having a second line width greater than the first line width and including a second target feature adjacent to but not overlapping the first target feature; capturing an image of the overlay target, the step of capturing the image comprising: capturing a first image of the first sub-target using a first inspection optical system having a first field of view and a first wavelength; capturing a second image of the second sub-target using second inspection optics having a second field of view wider than the first field of view and having a second wavelength longer than the first wavelength; processing the images to measure overlay error between the thin film layers; Including, the second target feature and the first target feature have the same shape; the plurality of thin film layers includes a first layer and a second layer overlying the first layer; the first target features include a set of the first target features formed in the first layer and a set of the first target features formed in the second layer, the second target features include a set of the second target features formed in the first layer and a set of the second target features formed in the second layer, and further the first and second target features include a line grating; method.
5. forming the set of first target features includes forming a first line grating in the first layer and a second line grating in the second layer, the first line grating and the second line grating being adjacent but non-overlapping; forming the set of second target features includes forming a third line grating in the first layer and a fourth line grating in the second layer, the third line grating and the fourth line grating being adjacent but non-overlapping. The method according to claim 4.
6. 5. The method of claim 4, wherein the line gratings of each of the first and second sub-targets include a line grating having a first orientation and a line grating having a second orientation orthogonal to the first orientation.
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