Semiconductor memory device and electronic system including the same

Abstract

To provide a three-dimensional semiconductor memory device with improved electrical characteristics and reliability and an electronic system including the same.SOLUTION: A semiconductor memory device including a cell array structure and a peripheral circuit structure is provided. The cell array structure includes a first stack structure, a second stack structure and a third stack structure each of the first to third stack structures including a plurality of word lines, vertical channel structures extending into the first to third stack structures, and a second cell contact plug extending into the first to third stack structures and connected to a second contact plug at an end of the second word line in the second stack structure. The second cell contact plug includes a first horizontal protrusion having a diameter that increases discontinuously at a connection portion of the first stack structure and the second stack structure.SELECTED DRAWING: Figure 8

Description

[Technical field]

[0001] The present invention relates to a semiconductor memory device and an electronic system including the same, and more particularly to a semiconductor memory device including a peripheral circuit structure and a cell array structure coupled to each other through bonding pads, and an electronic system including the same. [Background technology]

[0002] Electronic systems requiring data storage require semiconductor devices capable of storing large amounts of data. 2. Description of the Related Art There is a demand for increasing integration density of semiconductor devices to meet consumer demands for superior performance and low cost while increasing data storage capacity. In the case of a two-dimensional or planar semiconductor device, the degree of integration is determined mainly by the area occupied by a unit memory cell, and is therefore greatly influenced by the level of fine pattern formation technology.

[0003] However, miniaturization of patterns requires extremely expensive equipment, which remains limiting even as the integration density of two-dimensional semiconductor devices increases. Therefore, a three-dimensional semiconductor memory device having memory cells arranged three-dimensionally has been proposed. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] U.S. Pat. No. 11,626,417 Summary of the Invention [Problem to be solved by the invention]

[0005] The present invention has been made in consideration of the above-mentioned problems in conventional semiconductor memory devices, and an object of the present invention is to provide a 3D semiconductor memory device and an electronic system including the same, which have improved electrical characteristics and reliability. [Means for solving the problem]

[0006] In order to achieve the above object, the present invention provides a semiconductor memory device comprising a cell array structure and a peripheral circuit structure, the cell array structure including a first stacked structure, a second stacked structure and a third stacked structure each including a plurality of word lines, a vertical channel structure penetrating the first to third stacked structures, and a second cell contact plug penetrating the first to third stacked structures and a second contact pad provided at an end of a second word line in the second stacked structure, the second cell contact plug including a first horizontal protrusion having a diameter that discontinuously increases at a connection portion between the first stacked structure and the second stacked structure.

[0007] In order to achieve the above object, a semiconductor memory device according to the present invention includes a peripheral circuit structure and a cell array structure on the peripheral circuit structure, the cell array structure including a semiconductor layer, a first stacked structure, a second stacked structure, and a third stacked structure each including a plurality of word lines, the first stacked structure, and a third stacked structure each including a plurality of word lines, a vertical channel structure penetrating the first to third stacked structures, a first cell contact plug penetrating the first to third stacked structures and connected to a first contact pad provided at an end of a first word line in the first stacked structure, a second cell contact plug penetrating the first to third stacked structures and connected to a second contact pad provided at an end of a second word line in the second stacked structure, and a third cell contact plug penetrating the first to third stacked structures and connected to a third contact pad provided at an end of a third word line in the third stacked structure, the second cell contact plug including a first horizontal protrusion having a diameter that discontinuously increases at a connection portion between the first stacked structure and the second stacked structure.

[0008] In order to achieve the above object, an electronic system according to the present invention includes a three-dimensional semiconductor memory device including a peripheral circuit structure, a cell array structure provided on the peripheral circuit structure and including a cell array region and a cell array contact region, and a controller electrically connected to the three-dimensional semiconductor memory device through an input / output pad and controlling the three-dimensional semiconductor memory device, wherein the cell array structure includes a first stacked structure, a second stacked structure, and a third stacked structure each including a plurality of word lines, a vertical channel structure penetrating the first to third stacked structures, and a second cell contact plug penetrating the first to third stacked structures and a second contact pad provided at an end of a second word line in the second stacked structure, and the second cell contact plug includes a first horizontal protrusion having a diameter that discontinuously increases at a connection portion between the first stacked structure and the second stacked structure. Effect of the Invention

[0009] Advantageous Effects of Invention According to a semiconductor memory device and an electronic system including the same according to the present invention, leakage current and short circuits between a contact plug and an adjacent word line can be prevented by a contact plug including a horizontal protrusion. In addition, since the horizontal protrusion can be disposed only at the closest interface among the interfaces of the laminated structure disposed between the contact pad and the semiconductor layer, the process can be simplified and the degree of integration can be increased. [Brief description of the drawings]

[0010] [Figure 1] 1 is a block diagram showing a schematic configuration of an electronic system including a three-dimensional semiconductor memory device according to an embodiment of the inventive concept. [Diagram 2] 1 is a perspective view illustrating a schematic configuration of an electronic system including a three-dimensional semiconductor memory device according to an embodiment of the inventive concept. [Diagram 3] 2 is a cross-sectional view illustrating a semiconductor package including a three-dimensional semiconductor memory device according to an embodiment of the present invention; FIG. [Figure 4] 2 is a cross-sectional view illustrating a semiconductor package including a three-dimensional semiconductor memory device according to an embodiment of the present invention; FIG. [Diagram 5] 9 is a plan view illustrating a three-dimensional semiconductor memory device according to an embodiment of the inventive concept, taken along line LV1 of FIG. [Figure 6] 9 is a plan view illustrating a three-dimensional semiconductor memory device according to an embodiment of the inventive concept, taken along line LV2 of FIG. 8; [Figure 7] 9 is a plan view illustrating a three-dimensional semiconductor memory device according to an embodiment of the inventive concept, taken along line LV3 of FIG. 8; [Figure 8] 6 is a cross-sectional view illustrating a three-dimensional semiconductor memory device according to an embodiment of the present invention, taken along line II' of FIG. 5; [Figure 9] FIG. 9 is an enlarged view of the ZR region in FIG. [Figure 10] FIG. 9 is an enlarged view of region R in FIG. [Figure 11] 6 is a cross-sectional view taken along line II' of FIG. 5, illustrating a method for manufacturing a three-dimensional semiconductor memory device according to an embodiment of the present invention; [Figure 12] FIG. 12 is an enlarged view of region Q1 in FIG. [Figure 13] FIG. 12 is an enlarged view of region Q1 in FIG. [Figure 14] FIG. 12 is an enlarged view of region Q1 in FIG. [Figure 15] 6 is a cross-sectional view taken along line II' of FIG. 5, illustrating a method for manufacturing a three-dimensional semiconductor memory device according to an embodiment of the present invention; [Figure 16] 6 is a cross-sectional view taken along line II' of FIG. 5, illustrating a method for manufacturing a three-dimensional semiconductor memory device according to an embodiment of the present invention; [Figure 17] 6 is a cross-sectional view taken along line II' of FIG. 5, illustrating a method for manufacturing a three-dimensional semiconductor memory device according to an embodiment of the present invention; [Figure 18] 6 is a cross-sectional view taken along line II' of FIG. 5 for explaining a method of manufacturing a three-dimensional semiconductor memory device according to an embodiment of the present invention; [Figure 19] FIG. 19 is an enlarged view of region Q2 in FIG. [Figure 20] FIG. 19 is an enlarged view of region Q2 in FIG. [Figure 21] FIG. 19 is an enlarged view of region Q2 in FIG. [Figure 22] FIG. 19 is an enlarged view of region Q2 in FIG. [Diagram 23] 6 is a cross-sectional view taken along line II' of FIG. 5, illustrating a method for manufacturing a three-dimensional semiconductor memory device according to an embodiment of the present invention; [Figure 24] 6 is a cross-sectional view taken along line II' of FIG. 5, illustrating a method for manufacturing a three-dimensional semiconductor memory device according to an embodiment of the present invention; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a semiconductor memory device and an electronic system including the same according to the present invention will be described with reference to the accompanying drawings.

[0012] FIG. 1 is a block diagram showing a schematic configuration of an electronic system including a three-dimensional semiconductor memory device according to an embodiment of the present invention. Referring to FIG. 1, an electronic system 1000 according to an embodiment of the present invention includes a three-dimensional semiconductor memory device 1100 and a controller 1200 electrically connected to the three-dimensional semiconductor memory device 1100 .

[0013] The electronic system 1000 may be a storage device including one or more three-dimensional semiconductor memory devices 1100 or an electronic device including a storage device. For example, the electronic system 1000 may be a solid state drive device (SSD) that includes one or more three-dimensional semiconductor memory devices 1100, a universal serial bus (USB), a computing system, a medical device, or a communications device.

[0014] 3D semiconductor memory device 1100 is a non-volatile memory device, for example a 3D NAND flash memory device. The three-dimensional semiconductor memory device 1100 includes a first region 1100F and a second region 1100S on the first region 1100F. However, instead of what is shown in the figure, the first region 1100F may be disposed next to the second region 1100S.

[0015] The first region 1100F is a peripheral circuit region including a decoder 1110, a page buffer 1120, and a logic circuit 1130. The second region 1100S is a memory cell region including bit lines BL, a common source line CSL, word lines WL, first lines (LL1, LL2), second lines (UL1, UL2), and memory cell strings CSTR between the bit lines BL and the common source line CSL. In the second region 1100S, each memory cell string CSTR includes a first transistor (LT1, LT2) adjacent to a common source line CSL, a second transistor (UT1, UT2) adjacent to a bit line BL, and a plurality of memory cell transistors MCT arranged between the first transistor (LT1, LT2) and the second transistor (UT1, UT2).

[0016] The number of first transistors (LT1, LT2) and the number of second transistors (UT1, UT2) may vary according to the embodiment. The memory cell string CSTR is disposed between the common source line CSL and the first region 1100F. For example, the second transistors (UT1, UT2) include string selection transistors, and the first transistors (LT1, LT2) include ground selection transistors. The first lines (LL1, LL2) are the gate electrodes of the first transistors (LT1, LT2). The word line WL is the gate electrode of the memory cell transistor MCT, and the second line (UL1, UL2) is the gate electrode of the second transistor (UT1, UT2).

[0017] The common source line CSL, the first lines (LL1, LL2), the word lines WL, and the second lines (UL1, UL2) are electrically connected to the decoder 1110 through the first connection wiring 1115 that extends to the second region 1100S in the first region 1100F. The bit lines BL are electrically connected to the page buffer 1120 through second connection lines 1125 extending from within the first region 1100F to the second region 1100S. In the first region 1100F, a decoder 1110 and a page buffer 1120 perform a control operation on at least one selected memory cell transistor among the multiple memory cell transistors MCT.

[0018] The decoder 1110 and the page buffer 1120 are controlled by a logic circuit 1130 . The three-dimensional semiconductor memory device 1100 communicates with a controller 1200 through input / output pads 1101 that are electrically connected to logic circuits 1130 . The input / output pads 1101 are electrically connected to the logic circuit 1130 through input / output connecting wiring 1135 that extends from within the first region 1100F to the second region 1100S. The controller 1200 includes a processor 1210, a NAND controller 1220, and a host interface 1230. Depending on the embodiment, electronic system 1000 may include multiple three-dimensional semiconductor memory devices 1100, in which case controller 1200 controls multiple three-dimensional semiconductor memory devices 1100.

[0019] The processor 1210 controls the overall operation of the electronic system 1000 , including the controller 1200 . The processor 1210 operates according to predetermined firmware and controls the NAND controller 1220 to access the three-dimensional semiconductor memory device 1100. The NAND controller 1220 includes a NAND interface 1221 that handles communication with the three-dimensional semiconductor memory device 1100 . Through the NAND interface 1221, control commands for controlling the three-dimensional semiconductor memory device 1100, data to be recorded in the memory cell transistors MCT of the three-dimensional semiconductor memory device 1100, data to be read from the memory cell transistors MCT of the three-dimensional semiconductor memory device 1100, etc. are transmitted. The host interface 1230 provides communication between the electronic system 1000 and an external host. When a control command is received from an external host through the host interface 1230, the processor 1210 controls the three-dimensional semiconductor memory device 1100 in response to the control command.

[0020] FIG. 2 is a perspective view illustrating a schematic configuration of an electronic system including a three-dimensional semiconductor memory device according to an embodiment of the present invention. Referring to FIG. 2, an electronic system 2000 according to an embodiment of the present invention includes a main board 2001 , a controller 2002 mounted on the main board 2001 , one or more semiconductor packages 2003 , and a DRAM 2004 . The semiconductor package 2003 and the DRAM 2004 are connected to the controller 2002 by a wiring pattern 2005 provided on the main board 2001 .

[0021] The main board 2001 includes a connector 2006 that includes a number of pins for coupling with an external host. The number and arrangement of pins in connector 2006 can vary depending on the communication interface between electronic system 2000 and an external host. The electronic system 2000 communicates with an external host according to one of the following interfaces: Universal Serial Bus (USB), Peripheral Component Interconnect Express (PCI-Express), Serial Advanced Technology Attachment (SATA), M-Phy for Universal Flash Storage (UFS), etc. The electronic system 2000 operates on power provided by an external host, for example, through a connector 2006 . The electronic system 2000 may further include a Power Management Integrated Circuit (PMIC) that distributes power supplied from an external host to the controller 2002 and the semiconductor package 2003.

[0022] The controller 2002 writes data to or reads data from the semiconductor package 2003 to improve the operating speed of the electronic system 2000 . The DRAM 2004 is a buffer memory for reducing the difference in speed between the semiconductor package 2003, which is a data storage space, and the external host. The DRAM 2004 included in the electronic system 2000 can also operate as a kind of cache memory, providing space for temporarily storing data in control operations for the semiconductor package 2003 . If the electronic system 2000 includes a DRAM 2004 , the controller 2002 may further include a DRAM controller for controlling the DRAM 2004 in addition to a NAND controller for controlling the semiconductor package 2003 .

[0023] The semiconductor package 2003 includes first and second semiconductor packages (2003a, 2003b) spaced apart from each other. The first and second semiconductor packages (2003a, 2003b) are semiconductor packages each including a plurality of semiconductor chips 2200. Each of the first and second semiconductor packages (2003a, 2003b) includes a package substrate 2100, a semiconductor chip 2200 on the package substrate 2100, an adhesive layer 2300 disposed on the bottom surface of each of the semiconductor chips 2200, a connecting structure 2400 that electrically connects the semiconductor chip 2200 and the package substrate 2100, and a molding layer 2500 that covers the semiconductor chip 2200 and the connecting structure 2400 on the package substrate 2100.

[0024] The package substrate 2100 may be a printed circuit board that includes package top pads 2130 . Each semiconductor chip 2200 includes input / output pads 2210 . Each of the input / output pads 2210 corresponds to the input / output pads 1101 in FIG. Each of the semiconductor chips 2200 includes a gate stack structure 3210 and a memory channel structure 3220 . Each of the semiconductor chips 2200 includes a three-dimensional semiconductor memory device as described below.

[0025] The connecting structure 2400 may be, for example, a bond wire that electrically connects the I / O pad 2210 and the package top pad 2130 . Therefore, in each of the first and second semiconductor packages 2003a and 2003b, the semiconductor chips 2200 are electrically connected to each other by means of bonding wires and to the upper package pads 2130 of the package substrate 2100. According to an embodiment, in each of the first and second semiconductor packages (2003a, 2003b), the semiconductor chips 2200 may be electrically connected to each other by through silicon vias instead of the bonding wire type connecting structure 2400. Unlike what is shown in the figure, the controller 2002 and the semiconductor chip 2200 may be included in one package. The controller 2002 and the semiconductor chip 2200 may be mounted on an interposer substrate different from the main substrate 2001, and the controller 2002 and the semiconductor chip 2200 may be connected to each other by wiring provided on the interposer substrate.

[0026] 3 and 4 are cross-sectional views illustrating a semiconductor package including a three-dimensional semiconductor memory device according to an embodiment of the present invention, taken along lines II' and II-II' of FIG. 2. FIG. 3 and 4, a semiconductor package 2003 includes a package substrate 2100 , a plurality of semiconductor chips 2200 on the package substrate 2100 , and a molding layer 2500 covering the package substrate 2100 and the semiconductor chips 2200 .

[0027] The package substrate 2100 includes a package substrate body portion 2120, upper pads 2130 disposed on an upper surface of the package substrate body portion 2120 or exposed through the upper surface, lower pads 2125 disposed on a lower surface of the package substrate body portion 2120 or exposed through the lower surface, and internal wiring 2135 electrically connecting the upper pads 2130 and the lower pads 2125 inside the package substrate body portion 2120. The upper pad 2130 is electrically connected to the connecting structure 2400 . The lower pad 2125 is connected to the wiring pattern 2005 of the main board 2001 of the electronic system 2000 shown in FIG.

[0028] 2 and 3, one sidewall of the semiconductor chip 2200 is not aligned with one another, and the other sidewall of the semiconductor chip 2200 is aligned with one another. The semiconductor chips 2200 are electrically connected to one another by interconnect structures 2400 in the form of bond wires. Each of the semiconductor chips 2200 may include substantially identical components. Each of the semiconductor chips 2200 includes a semiconductor substrate 4010 , a first structure 4100 on the semiconductor substrate 4010 , and a second structure 4200 on the first structure 4100 . The second structure 4200 is bonded to the first structure 4100 by a wafer bonding method. The first structure 4100 includes a peripheral circuit wiring 4110 and a first bonding pad 4150 .

[0029] The second structure 4200 includes a common source line 4205, a gate stack structure 4210 between the common source line 4205 and the first structure 4100, a memory channel structure 4220 and an isolation structure 4230 penetrating the gate stack structure 4210, and a second bonding pad 4250 electrically connected to the word line (WL in FIG. 1) of the memory channel structure 4220 and the gate stack structure 4210, respectively. For example, the second bonding pad 4250 is electrically connected to the memory channel structure 4220 and the word line (WL in FIG. 1) through a gate connecting wiring 4235 electrically connected to the bit line 4240 and the word line (WL in FIG. 1), respectively, which are electrically connected to the memory channel structure 4220.

[0030] The first bonding pad 4150 of the first structure 4100 and the second bonding pad 4250 of the second structure 4200 are bonded while in contact with each other. The coupled portions of the first bonding pad 4150 and the second bonding pad 4250 include, for example, copper (Cu). Each of the semiconductor chips 2200 further includes an I / O pad 2210 and an I / O connecting wire 4265 below the I / O pad 2210 . The input / output connecting wiring 4265 is electrically connected to a portion of the second bonding pad 4250 and a portion of the peripheral circuit wiring 4110 .

[0031] FIG. 5 is a plan view for explaining a three-dimensional semiconductor memory device according to an embodiment of the present invention, which is a plan view based on LV1 of FIG. 8, FIG. 6 is a plan view for explaining a three-dimensional semiconductor memory device according to an embodiment of the present invention, which is a plan view based on LV2 of FIG. 8, FIG. 7 is a plan view for explaining a three-dimensional semiconductor memory device according to an embodiment of the present invention, which is a plan view based on LV3 of FIG. 8, FIG. 8 is a cross-sectional view for explaining a three-dimensional semiconductor memory device according to an embodiment of the present invention, which is a cross-sectional view cut along line I-I' of FIG. 5, FIG. 9 is an enlarged view of the ZR area of ​​FIG. 8, and FIG. 10 is an enlarged view of the R area of ​​FIG. 8.

[0032] 5 to 10, a three-dimensional semiconductor memory device according to the present invention includes a peripheral circuit structure PS and a cell array structure CS. By combining the cell array structure CS on the peripheral circuit structure PS, the cell capacity per unit area of ​​the three-dimensional semiconductor memory device according to the present invention is increased. In addition, the method of manufacturing and bonding the peripheral circuit structure PS and the cell array structure CS can prevent damage to the peripheral transistors PTR caused by various heat treatment processes, thereby improving the electrical characteristics and reliability of the three-dimensional semiconductor memory device according to the present invention.

[0033] The peripheral circuit structure PS includes a first substrate 10 . The first substrate 10 can be, for example, a silicon substrate, a silicon-germanium substrate, a germanium substrate, or a monocrystalline epitaxial layer grown on a monocrystalline silicon substrate. The first substrate 10 has a first conductivity type. As an example, the first conductivity type is p-type. The first substrate 10 has an upper surface that is parallel to a first direction D1 and a second direction D2 that is perpendicular to the first direction D1, and is perpendicular to a third direction D3. The first to third directions (D1, D2, D3) are, for example, directions perpendicular to each other. An isolation layer 11 is provided in a first substrate 10 . The element isolation film 11 defines an active region of the first substrate 10 .

[0034] Provided on a first substrate 10 are a peripheral transistor PTR, a peripheral contact plug 31, a peripheral circuit wiring 33 electrically connected to the peripheral transistor PTR through the peripheral contact plug 31, a first bonding pad 35 electrically connected to the peripheral circuit wiring 33, and a peripheral insulating film 30 surrounding these. The peripheral transistor PTR is provided on the active area of ​​the first substrate 10 . The peripheral circuit wiring 33 corresponds to the peripheral circuit wiring 4110 in FIGS. 3 and 4, and the first bonding pad 35 corresponds to the first bonding pad 4150 in FIGS. For example, the width of the peripheral contact plug 31 in the first direction D1 or the second direction D2 decreases toward the third direction D3. The peripheral contact plugs 31 and the peripheral circuit wiring 33 include a conductive material such as a metal.

[0035] The peripheral transistor PTR constitutes, for example, a decoder (1110 in FIG. 1), a page buffer (1120 in FIG. 1), a logic circuit (1130 in FIG. 1), and the like. More specifically, each of the peripheral transistors PTR includes a peripheral gate insulating layer, a peripheral gate electrode, a peripheral capping pattern, a peripheral gate spacer, and peripheral source / drain regions. A peripheral gate insulating film is provided between the peripheral gate electrode and the first substrate 10 . A peripheral capping pattern is provided on the peripheral gate electrode. The peripheral gate spacer covers the sidewalls of the peripheral gate insulating film, the peripheral gate electrode, and the peripheral capping pattern. Peripheral source / drain regions are provided within the first substrate 10 adjacent either side of the peripheral gate electrode.

[0036] The peripheral circuit wiring 33 and the first bonding pad 35 are electrically connected to the peripheral transistor PTR through the peripheral contact plug 31 . Each of the peripheral transistors PTR is, for example, an NMOS transistor or a PMOS transistor. A peripheral insulating layer 30 is provided on the first substrate 10 . The peripheral insulating film 30 covers the peripheral transistors PTR, the peripheral contact plugs 31, and the peripheral circuit wiring 33 on the first substrate 10. The peripheral insulating film 30 includes a plurality of insulating films having a multi-layer structure. For example, the peripheral insulating film 30 may include silicon oxide, silicon nitride, silicon oxynitride, and / or low-k materials. The peripheral insulating film 30 does not cover the upper surface of the first bonding pad 35 . The upper surface of the peripheral insulating film 30 is substantially coplanar with the upper surface of the first bonding pad 35 .

[0037] A cell array structure CS including second bonding pads 45, bit lines BL, a stack structure ST, and a semiconductor layer 191 is provided on the peripheral circuit structure PS. The cell array structure CS includes a cell array region CAR and an extension region EXR. The extension region EXR extends from the cell array region CAR in a direction opposite to the first direction D1 (or in the first direction D1). The second bonding pad 45, the bit line BL, and the stack structure ST correspond to the second bonding pad 4250, the bit line 4240, and the gate stack structure 4210 in FIGS. Provided on the peripheral insulating film 30 are a second bonding pad 45 in contact with the first bonding pad 35 of the peripheral circuit structure PS, a connecting contact plug 41, a first wiring 43 electrically connected to the second bonding pad 45 through the connecting contact plug 41, and a cell insulating film 40 surrounding these.

[0038] The cell insulating film 40 includes a plurality of insulating films having a multi-layer structure. For example, the cell insulating layer 40 may include silicon oxide, silicon nitride, silicon oxynitride, and / or low dielectric materials. For example, the width of the interconnection contact plug 41 in the first direction D1 or the second direction D2 increases in the third direction D3. The interconnect contact plug 41 and the first wiring 43 include a conductive material such as a metal. The cell insulating film 40 does not cover the lower surface of the second bonding pad 45 . The lower surface of the cell insulating film 40 is substantially coplanar with the lower surface of the second bonding pad 45 .

[0039] The bottom surface of each of the second bonding pads 45 is in direct contact with the top surface of each of the first bonding pads 35 . The first and second bond pads (35, 45) may include a metal such as copper (Cu), tungsten (W), aluminum (Al), nickel (Ni), or tin (Sn). As an example, the first and second bonding pads (35, 45) include copper (Cu). The first and second bonding pads (35, 45) are integral with each other with no interface therebetween. Although the sidewalls of the first and second bonding pads (35, 45) are shown in the figures as being aligned parallel to one another, the present invention is not limited thereto, and in a plan view, the sidewalls of the first and second bonding pads (35, 45) may be spaced apart from one another.

[0040] A bit line BL and a second wiring CL are provided on the cell insulating layer 40 and in contact with the connecting contact plug 41 . The bit lines BL and the second wirings CL are extended in a first direction D1 and spaced apart from each other in a second direction D2. The bit line BL and the second wiring CL include a conductive material such as a metal. On the cell insulating film 40, a stacked structure ST is provided. On the laminate structure ST, a semiconductor layer 191 and an upper insulating layer 192 are provided in sequence. The semiconductor layer 191 may be provided on the cell array region CAR, but not on the extension region EXR. The stacked structure ST includes a first stacked structure ST1, a second stacked structure ST2, and a third stacked structure ST3, which are sequentially provided between the semiconductor layer 191 and the cell insulating film 40. For ease of explanation, the present specification will be described based on a three-layered structure, but the number of layers may be three or more. The laminated structure ST may include a structure in which interlayer insulating films and conductive patterns are alternately laminated.

[0041] The first stacked structure ST1 includes an interlayer insulating film 111 and a first word line EL1 that are alternately stacked, the second stacked structure ST2 includes an interlayer insulating film 111 and a second word line EL2 that are alternately stacked, and the third stacked structure ST3 includes an interlayer insulating film 111 and a third word line EL3 that are alternately stacked. The first stacked structure ST1 is provided between the second stacked structure ST2 and the semiconductor layer 191. More specifically, the uppermost interlayer insulating film 111 of the second stacked structure ST2 contacts the lowermost interlayer insulating film 111 of the first stacked structure ST1. Similarly, the second laminate structure ST2 is provided between the third laminate structure ST3 and the first laminate structure ST1. More specifically, the uppermost interlayer insulating film 111 of the third stacked structure ST3 contacts the lowermost interlayer insulating film 111 of the second stacked structure ST2.

[0042] The first to third word lines (EL1, EL2, EL3) are simultaneously formed of the same material. The first to third word lines (EL1, EL2, EL3) include at least one selected from, for example, a doped semiconductor (e.g., doped silicon, etc.), a metal (e.g., tungsten, molybdenum, nickel, copper, aluminum, etc.), a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.), or a transition metal (e.g., titanium, tantalum, etc.). The interlayer dielectric 111 includes silicon oxide, silicon nitride, silicon oxynitride, and / or a low-k material. For example, the interlayer insulating film 111 includes high density plasma oxide (HDP oxide) or tetra ethyl ortho silicate (TEOS).

[0043] In the extension region EXR, each of the first laminated structure ST1, the second laminated structure ST2, and the third laminated structure ST3 includes an end portion having an inverted staircase shape. At the ends of the stepped shape, contact pads RP are provided which are exposed by open areas VL. The first stack structure ST1 includes a buried insulating layer 131a filling an open region VL that penetrates the entire first word line EL1, and a buried insulating layer 131b that penetrates a portion of the first word line EL1. The 1a buried insulating film 131a covers the 1a contact pad RP1a in the first word line EL1, and the 1b buried insulating film 131b covers the 1b contact pad RP1b in the first word line EL1.

[0044] The second stack structure ST2 includes a seconda buried insulating film 132a filling an open region VL that penetrates the entire second word line EL2, and a secondb buried insulating film 132b that penetrates a portion of the second word line EL2. The 2a-th buried insulating film 132a covers the 2a-th contact pad RP2a in the second word line EL2, and the 2b-th buried insulating film 132b covers the 2b-th contact pad RP2b in the second word line EL2. The third stack structure ST3 includes a buried insulating layer 133a filling an open region VL that penetrates the entire third word line EL3, and a buried insulating layer 133b that penetrates a portion of the third word line EL3. The 3a-th buried insulating film 133a covers the 3a-th contact pad RP3a in the third word line EL3, and the 3b-th buried insulating film 133b covers the 3b-th contact pad RP3b in the third word line EL3.

[0045] In the cell array region CAR, a vertical channel structure VS is provided in a vertical channel hole CH passing through the stack structure ST in a third direction D3. The vertical channel structure VS corresponds to the memory channel structure 4220 in FIGS. The bottom of the vertical channel structure VS is connected to a bit line BL. As an example, a bit line contact plug is provided between the vertical channel structure VS and the bit line BL. The upper portion of the vertical channel structure VS is connected to the semiconductor layer 191 . The semiconductor layer 191 includes a polycrystalline silicon layer. The semiconductor layer 191 includes a common source region that electrically connects the vertical channel structures VS in the stack structure ST. As an example, the semiconductor layer 191 includes a p-type doped region in an area adjacent to the vertical channel structure VS. The upper insulating layer 192 includes a silicon oxide film.

[0046] In the extension region EXR, a support structure DV is provided which passes through the laminate structure ST. The support structure DV may alternatively comprise silicon oxide and insulating material, but may have a similar structure to the vertical channel structure VS. The vertical channel hole CH has a reduced width in the first direction D1 and / or the second direction D2 as it moves away from the peripheral circuit structure PS. The vertical channel hole CH has steps whose width changes discontinuously at the boundary between the first laminated structure ST1 and the second laminated structure ST2 and at the boundary between the second laminated structure ST2 and the third laminated structure ST3.

[0047] Each of the vertical channel structures VS includes a conductive pad adjacent to the cell insulating film 40, a data storage pattern, a vertical semiconductor pattern, and a buried insulating pattern, which are sequentially provided in the vertical channel hole CH. The vertical semiconductor patterns may include, for example, a semiconductor material doped with impurities, an intrinsic semiconductor material not doped with impurities, or a polycrystalline semiconductor material. The conductive pads may, for example, comprise a semiconductor material or a conductive material doped with impurities. The buried insulating pattern includes a silicon oxide film and an insulating material.

[0048] The data storage pattern includes a blocking insulating layer, a charge storing layer, and a tunneling insulating layer, which are sequentially stacked on a sidewall of the vertical channel hole CH. The data storage pattern stores and / or changes data by Fowler-Nordheim tunneling induced by a voltage difference between the vertical semiconductor pattern and the first to third word lines (EL1, EL2, EL3). For example, the blocking insulating layer and the tunneling insulating layer may include silicon oxide, and the charge storing layer may include silicon nitride or silicon oxynitride.

[0049] In the plan view according to FIGS. 5, 6 and 7, a first trench TR1 and a second trench TR2 are provided which extend in a first direction D1 and cross the stacked structure ST. A first trench TR1 is provided in the cell array region CAR and the extension region EXR, and a second trench TR2 is provided in the extension region EXR. A first isolation pattern SP1 and a second isolation pattern SP2 are provided to fill the inside of each of the first and second trenches TR1, TR2. The first and second isolation patterns (SP1, SP2) correspond to the isolation structure 4230 in FIG.

[0050] The length of the first separated pattern SP1 in the first direction D1 is greater than the length of the second separated pattern SP2 in the first direction D1. The sidewalls of the first and second isolation patterns (SP1, SP2) contact at least a part of the first to third word lines (EL1, EL2, EL3) of the stacked structure ST and the interlayer insulating film 111. The first and second isolated patterns (SP1, SP2) comprise an oxide, for example a silicon oxide. When a plurality of laminated structures ST are provided, the first separation patterns SP1 are provided between the laminated structures ST arranged along the second direction D2. In other words, the stacked structures ST are spaced apart from one another in the second direction D2 via the first separation patterns SP1.

[0051] The cell contact plug and its adjacent structures will now be described in more detail. As shown in FIGS. 5 to 8, a cell contact plug CP is provided which penetrates the stacked structure ST. Each of the cell contact plugs CP has a width or diameter that increases continuously along the third direction D3. The cell contact plug CP includes a metal material such as tungsten, titanium, or tantalum. Each of the cell contact plugs CP is connected to one of the first to third word lines (EL1, EL2, EL3) and is separated from the other word lines except the connected word line by an insulating spacer 141 provided between the interlayer insulating films 111.

[0052] As an example, the insulating spacer 141 includes a silicon oxide film. Each of the cell contact plugs CP is connected to the upper insulating layer 192 by penetrating all of the first stacked structure ST1, the second stacked structure ST2, and the third stacked structure ST3. Each of the cell contact plugs CP includes one continuous conductor having no interface between the first stacked structure ST1 and the second stacked structure ST2, and between the second stacked structure ST2 and the third stacked structure ST3.

[0053] The cell contact plug CP includes a first cell contact plug (CP1a, CP1b) connected to the contact pads (RP1a, RP1b) of the first word line EL1, a second cell contact plug (CP2a, CP2b) connected to the contact pads (RP2a, RP2b) of the second word line EL2, and a third cell contact plug (CP3a, CP3b) connected to the contact pads (RP3a, RP3b) of the third word line EL3. The second cell contact plugs CP2a, CP2b include a 2a cell contact plug CP2a connected to the 2a contact pad RP2a and a 2b cell contact plug CP2b connected to the 2b contact pad RP2b.

[0054] As shown in FIGS. 5 and 8, the second cell contact plugs CP2a and CP2b include a first horizontal protrusion LP1 whose diameter increases discontinuously at a connection portion between the first stacked structure ST1 and the second stacked structure ST2. More specifically, as shown in FIGS. 9 and 10, the first horizontal protrusion portion LP1 is provided in the lowermost interlayer insulating film 111 of the first stacked structure ST1. The first horizontal protrusion portion LP1 vertically overlaps with the 2b contact pad RP2b or the 2a contact pad RP2a. The first horizontal protrusion LP1 is provided between the 2b contact pad RP2b and the semiconductor layer 191 or between the 2a contact pad RP2a and the upper insulating layer 192. The first horizontal protrusion LP1 is not provided between the second laminated structure ST2 and the third laminated structure ST3. The first horizontal protrusion portion LP1 is not provided between the 2b contact pad RP2b and the second wiring CL, and between the 2a contact pad RP2a and the second wiring CL.

[0055] As shown in FIG. 10, the second cell contact plugs (CP2a, CP2b) have a first width W1 in a region adjacent to the first horizontal protrusion portion LP1, and the first horizontal protrusion portion LP1 has a second width W2 larger than the first width W1. As an example, the second width W2 is 1.2 to 3.0 times the first width W1. The first horizontal protrusion LP1 has a ring shape surrounding each of the second cell contact plugs (CP2a, CP2b), but is not limited to this. The thickness t1 of the horizontal protrusion LP1 is smaller than the second width W2. The third cell contact plugs CP3a, CP3b include a third cell contact plug CP3a connected to a third contact pad RP3a and a third cell contact plug CP3b connected to a third contact pad RP3b.

[0056] As shown in FIGS. 6 and 8, the third cell contact plugs CP3a and CP3b include a second horizontal protrusion LP2 whose diameter increases discontinuously at a connection portion between the second stacked structure ST2 and the third stacked structure ST3. More specifically, as shown in FIG. 9, the second horizontal protrusion portion LP2 is provided in the lowermost interlayer insulating film 111 of the second stacked structure ST2. The second horizontal protrusion portion LP2 vertically overlaps the 3a-th contact pad RP3a or the 3b-th contact pad RP3b. The second horizontal protrusion LP2 is provided between the 3b contact pad RP3b and the semiconductor layer 191 or between the 3a contact pad RP2a and the upper insulating layer 192. The second horizontal protrusion LP2 is not provided between the second laminate structure ST2 and the first laminate structure ST1. The second horizontal protrusion portion LP2 is not provided between the 2b contact pad RP2b and the second wiring CL and between the 2a contact pad RP2a and the second wiring CL.

[0057] The first cell contact plugs CP1a and CP1b connected to the first word line EL1 in the first stack structure ST1 closest to the upper insulating layer 192 do not include a horizontal protrusion. The first cell contact plugs (CP1a, CP1b), the second cell contact plugs (CP2a, CP2b), and the third cell contact plugs (CP3a, CP3b) are sequentially and repeatedly arranged along a first direction D1 as shown in FIGS. In the opposite direction to the first direction D1, which is the direction away from the vertical channel structure VS, the third cell contact plugs (CP3a, CP3b), the second cell contact plugs (CP2a, CP2b), and the first cell contact plugs (CP1a, CP1b) are repeatedly arranged multiple times. As an example, a 3b cell contact plug CP3b, a 2b cell contact plug CP2b, a 1b cell contact plug CP1b, a 3a cell contact plug CP3a, a 2a cell contact plug CP2a, and a 1a cell contact plug CP1a are sequentially arranged along the opposite direction to the first direction D1. The 2b cell contact plug CP2b is disposed between the 3b cell contact plug CP3b and the 1b cell contact plug CP1b, and the 2a cell contact plug CP2a is disposed between the 3a cell contact plug CP3a and the 1a cell contact plug CP1a.

[0058] The first and second horizontal protrusions LP1 and LP2 can prevent leakage current and short circuit between the contact plug CP and an adjacent word line due to misalignment of a contact hole during a process of forming the contact plug CP described below. The first and second horizontal protrusions (LP1, LP2) are not formed at all interfaces between the laminated structures, but are arranged only at the closest interface among the interfaces of the laminated structures that are arranged between the contact pad RP and the semiconductor layer 191. That is, the first and second horizontal protrusions (LP1, LP2) are disposed only at the interface of the laminated structure immediately above them, which makes it possible to simplify the process and increase the degree of integration.

[0059] Figures 11, 15 to 18, and 23 to 24 are cross-sectional views for explaining a manufacturing method of a three-dimensional semiconductor memory device according to an embodiment of the present invention, and are cross-sectional views cut along line I-I' in Figure 5, Figures 12 to 14 are enlarged views of region Q1 in Figure 11, and Figures 19 to 22 are enlarged views of region Q2 in Figure 18.

[0060] Referring to FIG. 11, on the second substrate 100, a first preliminary laminate structure STp1 is formed. The second substrate 100 may be, for example, a silicon substrate, a silicon-germanium substrate, a germanium substrate, or a monocrystalline epitaxial layer grown on a monocrystalline silicon substrate. The second substrate 100 has a first conductivity type. As an example, the first conductivity type is p-type. Before forming the first preliminary laminate structure STp1, a buffer insulating film and / or an etch stop film is formed on the second substrate 100.

[0061] The first preliminary laminated structure STp1 includes an interlayer insulating film 111 and a sacrificial film 121 that are alternately and repeatedly laminated. The interlayer insulating film 111 and the sacrificial film 121 are formed of different insulating materials. The sacrificial layer 121 has an etching selectivity with respect to the interlayer insulating layer 111 and is formed of a material that can be etched. For example, the sacrificial film 121 is made of silicon nitride, and the interlayer insulating film 111 is made of silicon oxide. Each of the sacrificial films 121 has substantially the same thickness. The uppermost layer of the interlayer insulating film 111 is thicker than the other layers.

[0062] An open region VL that exposes the upper surface of the sacrificial film 121 is formed in the extension region EXR. For example, the open region VL is formed by performing a plurality of etching processes through a mask pattern formation and a mask pattern trimming process. As a result, the sidewall of the open region VL is formed to have a step shape defined by the upper surface of the sacrificial film 121. A plurality of open regions VL are provided, and the number of sacrificial films 121 penetrating through each open region VL varies depending on the position of each open region VL. For example, in the cell array region CAR, the greater the separation distance, the deeper the open region VL.

[0063] 11 and 12, a first pad sacrificial pattern 171 is formed on an upper surface of the sacrificial layer 121 exposed in the open region VL. The first pad sacrificial pattern 171 is formed by forming a sacrificial layer covering the open region VL and then removing the sacrificial layer except for the top surface of the exposed sacrificial layer 121. The first pad sacrificial pattern 171 has an etch selectivity with respect to the interlayer insulating film 111 and is formed of a material that can be etched. For example, the first pad sacrificial pattern 171 is formed of the same material as the sacrificial layer 121, for example, silicon nitride. Thereafter, the 1a buried insulating film 131a and the 1b buried insulating film 131b are formed to fill the open region VL. The 1a buried insulating film 131a and the 1b buried insulating film 131b include a silicon oxide film.

[0064] Through holes (TH1 to TH6) penetrating the first preliminary laminated structure STp1 are formed in the extension region EXR, and a vertical channel hole CH penetrating the first preliminary laminated structure STp1 is formed in the cell array region CAR. The through holes (TH1 to TH6) and the vertical channel holes CH are simultaneously formed by an anisotropic etching process. The second substrate 100 is exposed through the through holes (TH1 to TH6) and the vertical channel holes CH. A first through sacrificial pattern SF1 is formed to fill the through holes TH1 to TH6 and the vertical channel hole CH. The first through sacrificial pattern SF1 has an over-etching selectivity with respect to the interlayer insulating film 111 and the sacrificial film 121 and is formed of a material that can be etched. As an example, the first penetrating sacrificial pattern SF1 may include one of polycrystalline silicon or silicon carbide.

[0065] 11 and 13, a mask pattern 116 is formed to cover the upper surface of the first preliminary laminate structure STp1 and to expose a part of the through holes TH1 to TH6. The mask pattern 116 includes photoresist and / or silicon nitride. As an example, the mask pattern 116 includes openings overlapping the second through hole TH2 and the fifth through hole TH5. By the opening, the upper part of the first through sacrificial pattern SF1 exposed and a part of the uppermost interlayer insulating film 111 are removed to form a recess region PH.

[0066] 11 and 14, a first extension pattern AP1 is formed to fill the recess region PH. The first extension pattern AP1 is formed of the same material as the first through sacrificial pattern SF1. The mask pattern 116 is then removed.

[0067] Referring to FIG. 15, a second pre-laminate structure STp2 and a third pre-laminate structure STp3 are sequentially formed on a first pre-laminate structure STp1. The second pre-laminate structure STp2 is formed by repeating the same steps as those for the first pre-laminate structure STp1. As a result, in the second preliminary laminated structure STp2, a second pad sacrificial pattern 172, a seconda buried insulating film 132a, and a secondb buried insulating film 132b are formed in the open region VL, and a second through sacrificial pattern SF2 is formed on each of the first through sacrificial patterns SF1. A second extension pattern AP2 is formed on a portion of the second through sacrificial pattern SF2. Similarly, a third pad sacrificial pattern 173, a thirda buried insulating film 133a, and a thirdb buried insulating film 133b are formed in the open region VL of the third preliminary laminated structure STp3, and a third penetrating sacrificial pattern SF3 is formed on each of the second penetrating sacrificial patterns SF2. No extension pattern is formed in the third through sacrificial pattern SF3.

[0068] Referring to FIG. 16, after removing the first to third sacrificial through patterns (SF1, SF2, SF3) in the vertical channel holes CH of the first to third preliminary laminate structures (STp1, STp2, STp3), a vertical channel structure VS is formed. Hereinafter, each of the vertical channel holes CH refers to one hole passing through the first to third preliminary laminated structures (STp1, STp2, STp3) in sequence. The formation of the vertical channel structure VS includes a process of forming a data storage pattern and a vertical semiconductor pattern conformally covering the inner sidewall of the vertical channel hole CH, and a process of forming a buried insulating pattern in a space surrounded by the vertical semiconductor pattern.

[0069] Referring to FIG. 17, in the extension region EXR, the first to third through sacrificial patterns SF1, SF2, and SF3 are removed to expose the first to sixth through holes TH1 to TH6. Hereinafter, each of the first to sixth through holes (TH1 to TH6) refers to one hole that passes through the first to third preliminary laminate structures (STp1, STp2, STp3) in sequence. When the first to third through sacrificial patterns (SF1, SF2, SF3) are removed, the first extension pattern AP1 and the second extension pattern AP2 are also removed, forming a first gap region GP1 and a second gap region GP2.

[0070] 18, 19, and 20, a portion of the sacrificial film 121 exposed by the first to sixth through holes (TH1 to TH6) is removed. The sacrificial film 121 is not entirely removed, but only the portions close to the first to sixth through holes (TH1 to TH6) are horizontally etched. As a result, a first horizontal recess region EH1 is formed in which the first to sixth through holes (TH1 to TH6) are horizontally expanded. The first to third pad sacrificial patterns (171, 172, 173) are removed together with the sacrificial film 121. As a result, a part of the first horizontal recess region EH1 becomes a second horizontal recess region EH2 whose width in the third direction D3 is further expanded.

[0071] 18 and 21, an insulating spacer 141 is formed in the first horizontal recess region EH1. The insulating spacer 141 includes the same material as the interlayer insulating film 111, for example, a silicon oxide film. The process of forming the insulating spacer 141 includes a process of forming an insulating film covering the first horizontal recess region EH1 and the second horizontal recess region EH2, and then performing anisotropic etching to remove the remaining insulating film in the first to sixth through holes (TH1 to TH6). Since the width of the second horizontal recess region EH2 in the third direction D3 is greater than that of the first horizontal recess region EH1, the insulating film in the second horizontal recess region EH2 is also removed when the remaining insulating film is removed.

[0072] After forming the insulating spacer 141, fourth to sixth pad sacrificial patterns (176, 177, 178) are formed in the second horizontal recess region EH2. The fourth to sixth pad sacrificial patterns (176, 177, 178) are formed of a material that can be removed together with the sacrificial film 121. As an example, the fourth to sixth pad sacrificial patterns (176, 177, 178) are formed of silicon nitride. Thereafter, a vertical sacrificial pattern 144 is formed to fill the first to sixth through holes (TH1 to TH6). The vertical sacrificial pattern 144 is formed of a material that has an over-etch selectivity with respect to the interlayer insulating film 111 and the sacrificial film 121 and can be etched. As an example, the vertical sacrificial pattern 144 comprises one of polycrystalline silicon or silicon carbide. The vertical sacrificial pattern 144 fills the first gap region GP1 and the second gap region GP2.

[0073] 5 and 23, first and second trenches (TR1, TR2) are formed penetrating the first to third preliminary laminated structures (STp1, STp2, STp3). The first and second trenches TR1 and TR2 extend from the cell array region CAR to the extension region EXR. The sacrificial layer 121 is removed through the first and second trenches TR1 and TR2. The process of removing the sacrificial film 121 is performed, for example, through a wet etching process using a hydrofluoric acid (HF) and / or phosphoric acid (H3PO4) solution. The fourth to sixth pad sacrificial patterns (176, 177, 178) are also removed together with the sacrificial film 121. The first to third word lines (EL1, EL2, EL3) are formed to fill the spaces where the sacrificial film 121 has been removed. Contact pads RP are formed in the spaces where the sacrificial patterns (176, 177, 178) have been removed. Thus, a laminate structure ST including a first laminate structure ST1, a second laminate structure ST2, and a third laminate structure ST3 is formed. Thereafter, a first isolation pattern SP1 and a second isolation pattern SP2 are formed to fill the insides of the first and second trenches TR1 and TR2, respectively.

[0074] 5 to 7 and 24, after removing the vertical sacrificial patterns 144, cell contact plugs CP are formed to fill the spaces where the vertical sacrificial patterns 144 have been removed. The cell contact plug CP is made of a metal material such as tungsten, titanium, or tantalum. A first horizontal protrusion LP1 is formed in the first gap region GP1, and a second horizontal protrusion LP2 is formed in the second gap region GP2.

[0075] Referring again to FIG. 8, the bit lines BL, the second wirings CL, the connecting contact plugs 41, the first wirings 43, the second bonding pads 45, and the cell insulating film 40 covering them are formed on the stacked structure ST. Thus, the formation of the cell array structure CS is completed. Thereafter, the cell array structure CS and the peripheral circuit structure PS are coupled to each other. More specifically, the cell array structure CS and the peripheral circuit structure PS are bonded together such that the second bonding pads 45 contact the first bonding pads 35 . Thereafter, the second substrate 100 is removed to expose the tops of the vertical channel structures VS and the tops of the cell contact plugs CP. A semiconductor layer 191 is formed covering the exposed upper portion of the vertical channel structure VS. The semiconductor layer 191 is not formed on the cell contact plug CP. An upper insulating layer 192 is formed to cover the cell contact plugs CP. An upper insulating layer 192 covers the semiconductor layer 191 .

[0076] The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the technical scope of the present invention. [Explanation of symbols]

[0077] 10 First board 30 Peripheral insulating film 31 Peripheral contact plug 33 Peripheral circuit wiring 35 1st Bonding Pad 40 Cell insulating film 41 Interlocking contact plug 43 1st wiring 45 2nd Bonding Pad 111 (top, bottom) Interlayer insulating film 131a 1a buried insulating film 131b 1b buried insulating film 132a 2a buried insulating film 132b second buried insulating film 133a 3a buried insulating film 133b 3b buried insulating film 141 Insulating spacer 191 Semiconductor Layer 192 Upper insulating layer 1000, 2000 Electronic Systems 1100 3D Semiconductor Memory Device 1100F 1st area 1100S 2nd area 1101 I / O pad 1110 Decoder 1115 1st connection wiring 1120 Page Buffer 1125 2nd connection wiring 1130 Logic Circuit 1135 Input / output connection wiring 1200 Controller 1210 Processor 1220 NAND Controller 1221 NAND interface 1230 Host Interface 2001 Main Board 2002 Controller 2003 Semiconductor Package 2003a, 2003b (1st, 2nd) Semiconductor Packages 2004 DRAM 2005 Wiring pattern 2006 Connectors 2100 Package Substrate 2120 Package board body 2125 Package Bottom Pad 2130 Package Top Pad 2135 Internal Wiring 2200 Semiconductor Chips 2210 I / O pad 2300 Adhesive layer 2400 Concatenated structure 2500 Molding Layer 2800 Conductive connection part 3210 Gate stack structure 3220 Memory Channel Structure 4010 Semiconductor substrate 4100 First structure 4110 Peripheral circuit wiring 4150 1st Bonding Pad 4200 Second structure 4205 Common Source Line 4210 Gate stack structure 4220 Memory Channel Structure 4230 Separation structure 4235 Gate connection wiring 4240 bit lines 4250 2nd Bonding Pad 4265 Input / output connection wiring CAR cell array area CH Vertical Channel Hole CL 2nd Wiring CP Cell Contact Plug CP1a, CP1b First cell contact plug CP2a, CP2b Second cell contact plug CP3a, CP3b 3rd cell contact plug CS Cell Array Structure DV support structure EL1, EL2, EL3 (1st to 3rd) word lines EXR extension area LP1 1st horizontal protrusion PS peripheral circuit structure PTR peripheral transistor RP1a, RP1b Contact pads of the first word line EL1 RP2a, RP2b Contact pads of the second word line EL2 RP3a, RP3b Contact pads of the third word line EL3 SP1, SP2 (1st, 2nd) separation pattern ST laminated structure ST1, ST2, ST3 (1st to 3rd) laminated structure TR1, TR2 (1st, 2nd) trenches RP Contact Pad VS Vertical Channel Structure

Claims

1. a cell array structure; a peripheral circuit structure; The cell array structure includes: a first stack structure, a second stack structure, and a third stack structure, each of which includes a plurality of word lines; a vertical channel structure penetrating the first to third stacked structures; a second cell contact plug penetrating the first to third stacked structures and a second contact pad provided at an end of a second word line in the second stacked structure; the second cell contact plug includes a first horizontal protrusion having a diameter that discontinuously increases at a connection portion between the first stacked structure and the second stacked structure.

2. the cell array structure further includes a third cell contact plug penetrating the first to third stacked structures and a third contact pad provided at an end of a third word line in the third stacked structure; 2. The semiconductor memory device of claim 1, wherein the third cell contact plug includes a second horizontal protrusion having a diameter that discontinuously increases at a connection portion between the third stack structure and the second stack structure.

3. 3. The semiconductor memory device of claim 2, wherein the third cell contact plug is a connection portion between the first stacked structure and the second stacked structure and does not include a horizontal protrusion.

4. the cell array structure further includes a first cell contact plug penetrating the first to third stacked structures and a first contact pad provided at an end of a first word line in the first stacked structure; 3. The semiconductor memory device of claim 2, wherein the first cell contact plug does not include a horizontal protrusion.

5. the second cell contact plug is disposed between the first cell contact plug and the vertical channel structure; 5. The semiconductor memory device of claim 4, wherein the third cell contact plug is disposed between the second cell contact plug and the vertical channel structure.

6. 5. The semiconductor memory device of claim 4, wherein the third cell contact plug, the second cell contact plug, and the first cell contact plug are repeatedly arranged in a direction away from the vertical channel structure.

7. 2. The semiconductor memory device of claim 1, wherein the first horizontal protrusion is spaced apart from the peripheral circuit structure by the second contact pad.

8. 2. The semiconductor memory device of claim 1, wherein the first horizontal protrusion vertically overlaps the second contact pad.

9. 2. The semiconductor memory device of claim 1, wherein the second cell contact plug is a connection portion between the second stacked structure and the third stacked structure and does not include a horizontal protrusion.

10. the second cell contact plug has a first width adjacent the horizontal protrusion; the first horizontal projection has a second width; 2. The semiconductor memory device of claim 1, wherein the second width is 1.2 to 3.0 times the first width.

11. 11. The semiconductor memory device of claim 10, wherein the thickness of the first horizontal protrusion is less than the second width.

12. 2. The semiconductor memory device of claim 1, wherein the cell array structure further comprises an insulating spacer that separates the second cell contact plug from a first word line of the first stack structure and a third word line of the third stack structure.

13. A peripheral circuit structure; a cell array structure on the peripheral circuit structure; The cell array structure includes: A semiconductor layer; a first stack structure, a second stack structure, and a third stack structure provided between the semiconductor layer and the peripheral circuit structure, each stack structure including a plurality of word lines; a vertical channel structure penetrating the first to third stacked structures; a first cell contact plug passing through the first to third stacked structures and connected to a first contact pad provided at an end of a first word line in the first stacked structure; a second cell contact plug passing through the first to third stacked structures and connected to a second contact pad provided at an end of a second word line in the second stacked structure; a third cell contact plug penetrating the first to third stacked structures and connected to a third contact pad provided at an end of a third word line in the third stacked structure; the second cell contact plug includes a first horizontal protrusion having a diameter that discontinuously increases at a connection portion between the first stacked structure and the second stacked structure.

14. 14. The semiconductor memory device of claim 13, wherein the third cell contact plug includes a second horizontal protrusion having a diameter that discontinuously increases at a connection portion between the third stack structure and the second stack structure.

15. 15. The semiconductor memory device of claim 14, wherein the third cell contact plug is a connection portion between the first stacked structure and the second stacked structure and does not include a horizontal protrusion.

16. 15. The semiconductor memory device of claim 14, wherein the first cell contact plug does not include a horizontal protrusion.

17. 15. The semiconductor memory device of claim 14, wherein the third cell contact plug, the second cell contact plug, and the first cell contact plug are repeatedly arranged in a direction away from the vertical channel structure.

18. 14. The semiconductor memory device of claim 13, wherein the first horizontal protrusion is provided between the second contact pad and the semiconductor layer.

19. 14. The semiconductor memory device of claim 13, wherein the second cell contact plug is a connection portion between the second stacked structure and the third stacked structure and does not include a horizontal protrusion.

20. a three-dimensional semiconductor memory device including: a peripheral circuit structure; and a cell array structure provided on the peripheral circuit structure, the cell array structure including a cell array region and a cell array contact region; a controller electrically connected to the three-dimensional semiconductor memory device through an input / output pad and controlling the three-dimensional semiconductor memory device; The cell array structure includes: a first stack structure, a second stack structure, and a third stack structure, each of which includes a plurality of word lines; a vertical channel structure penetrating the first to third stacked structures; a second cell contact plug penetrating the first to third stacked structures and a second contact pad provided at an end of a second word line in the second stacked structure; The second cell contact plug comprises a first horizontal protrusion having a diameter that discontinuously increases at a connection portion between the first stacked structure and the second stacked structure.

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