Heat treatment method

Abstract

To provide a heat treatment method to develop good ferroelectricity in thin films that develop ferroelectricity in a metastable phase while suppressing the increase in the amount of heat given.SOLUTION: Millisecond annealing is performed by irradiating the surface of a semiconductor wafer on which a hafnium oxide base film that develops ferroelectricity in a metastable phase is formed, with flash light from a flash lamp, and heating the surface for one second or less. Millisecond annealing includes two stages of flash heating, consisting of a first flash heating in which the surface of the semiconductor wafer is heated at a first rate and a second flash heating in which the surface is heated at a higher second rate. This allows the hafnium oxide base film to be raised to a high temperature to develop good ferroelectricity while suppressing the increase in the amount of heat given to the semiconductor wafer.SELECTED DRAWING: Figure 12

Description

[Technical field]

[0001] The present invention relates to a heat treatment method for heating a substrate having a thin film, such as a hafnium oxide-based film, which exhibits ferroelectricity when it reaches a metastable phase, by irradiating the substrate with light. Substrates to be treated include, for example, semiconductor wafers, substrates for liquid crystal display devices, substrates for flat panel displays (FPDs), substrates for optical disks, substrates for magnetic disks, and substrates for solar cells. [Background technology]

[0002] In recent years, there has been active research into utilizing the properties of ferroelectrics in memory. Ferroelectrics are insulators that exhibit a property of polarization (residual polarization) when an external electric field is applied, and the polarization remains even when the external electric field is removed to zero. Attempts are being made to develop high-speed non-volatile memory that utilizes the polarization properties of ferroelectrics.

[0003] As an example of a ferroelectric material, materials based on hafnium oxide (HfO2) have been attracting attention. Patent documents 1 and 2 disclose that a hafnium oxide film in an amorphous phase is formed and then heat-treated to crystallize the hafnium oxide film into a ferroelectric film. Patent documents 1 and 2 show that in order for a hafnium oxide film to exhibit ferroelectricity, it is necessary to form a specific crystal phase called an orthorhombic crystal. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2018-195767 A [Patent Document 2] JP 2019-201172 A Summary of the Invention [Problem to be solved by the invention]

[0005] The amount of heat applied when applying heat treatment to a hafnium oxide film in an amorphous phase determines the crystal phase that is obtained. The orthorhombic crystal, which is the crystal phase required to exhibit ferroelectricity, is an unstable metastable phase. In other words, ingenuity is required in the heat treatment to obtain a crystal phase that exhibits ferroelectricity, and control of the thermal history when applying heat treatment to a hafnium oxide film is an important technological element for exhibiting ferroelectricity.

[0006] On the other hand, it has been reported that there is a correlation between the size of crystal grains obtained by heat treatment of a hafnium oxide film and the polarization characteristics of the ferroelectric, and that larger crystal grains have better polarization characteristics and exhibit good ferroelectricity. In order to obtain large crystal grains, it is necessary to apply a correspondingly large amount of heat to the hafnium oxide film.

[0007] In addition, in memories that utilize ferroelectrics, the thinner the ferroelectric film, the higher the performance of the memory (for example, lower power consumption). However, the thinner the hafnium oxide film, the greater the amount of heat required to express the ferroelectric properties.

[0008] Thus, in order to impart good ferroelectricity to the hafnium oxide film, it is necessary to apply a relatively large amount of heat, but the application of such a large amount of heat may cause a deterioration in the characteristics of wiring and transistors formed prior to the deposition of the hafnium oxide film.

[0009] The present invention has been made in view of the above problems, and has an object to provide a heat treatment method for causing a thin film that exhibits ferroelectricity in a metastable phase to exhibit good ferroelectricity while suppressing an increase in the amount of heat applied. [Means for solving the problem]

[0010] In order to solve the above problems, a first aspect of the present invention is a heat treatment method for heating a substrate having a thin film formed thereon that exhibits ferroelectricity when in a metastable phase by irradiating the substrate with light, the method comprising a millisecond annealing step of irradiating a surface of the substrate with light to heat the surface.

[0011] In a second aspect, in the heat treatment method according to the first aspect, the millisecond annealing step includes a first annealing step of heating the surface of the substrate to a first temperature at a first heating rate, and a second annealing step of heating the surface of the substrate to a second temperature higher than the first temperature at a second heating rate higher than the first temperature, following the first annealing step.

[0012] A third aspect is the heat treatment method according to the second aspect, wherein the heating time of the first annealing step is longer than the heating time of the second annealing step.

[0013] In addition, a fourth aspect is the heat treatment method according to the third aspect, wherein the heating time in the first annealing step is 3 milliseconds or more, and the heating time in the second annealing step is 2 milliseconds or less.

[0014] In addition, a fifth aspect is the heat treatment method according to any one of the second to fourth aspects, wherein the first temperature is 400°C or more and 900°C or less, and the second temperature is 600°C or more and 1200°C or less.

[0015] In a sixth aspect, in the heat treatment method according to any one of the second to fifth aspects, in the first annealing step and the second annealing step, a flash light is irradiated from a flash lamp onto the surface of the substrate to heat the surface.

[0016] In addition, a seventh aspect is the heat treatment method according to the sixth aspect, further comprising a preheating step of heating the substrate to 100° C. or higher and 400° C. or lower by irradiating the substrate with light from a continuously lit lamp before the first annealing step.

[0017] In addition, an eighth aspect is a heat treatment method according to any one of the second to seventh aspects, further comprising a temperature reduction step of reducing the temperature of the substrate after the second annealing step, wherein the temperature reduction rate in the temperature reduction step is 20% or more higher than the temperature reduction rate when the surface of the substrate is heated to the second temperature in one stage.

[0018] A ninth aspect is the heat treatment method according to any one of the first to eighth aspects, wherein the thin film is a hafnium oxide-based film containing hafnium oxide as a main component. Effect of the Invention

[0019] According to the heat treatment methods of the first to ninth aspects, a surface of a substrate on which a thin film that exhibits ferroelectricity when it enters a metastable phase is formed is irradiated with light and the surface is heated by millisecond annealing, so that the thin film can be heated to a high temperature and exhibit good ferroelectricity while suppressing an increase in the amount of heat applied to the substrate.

[0020] In particular, according to the heat treatment method of the second aspect, in the millisecond annealing step, the surface of the substrate is heated to a first temperature at a first heating rate, and then heated to a second temperature higher than the first temperature at a second heating rate higher than the first heating rate, thereby making it possible to reduce the amount of heat applied to the substrate. [Brief description of the drawings]

[0021] [Figure 1] 1 is a vertical cross-sectional view showing a configuration of a heat treatment apparatus for carrying out a heat treatment method according to the present invention; [Diagram 2] FIG. 2 is a perspective view showing the overall appearance of a holding portion. [Diagram 3] FIG. [Figure 4] FIG. [Diagram 5] FIG. [Figure 6] FIG. [Figure 7] FIG. 2 is a plan view showing an arrangement of a plurality of halogen lamps. [Figure 8] FIG. 2 is a diagram showing a driving circuit for a flash lamp. [Figure 9] 2 is a flowchart showing a processing procedure of a heat treatment method according to the present invention. [Figure 10] FIG. 1 is a diagram showing an example of a semiconductor wafer on which a hafnium oxide-based film is formed. [Figure 11] FIG. 1 is a diagram showing temperature changes of a semiconductor wafer. [Figure 12] FIG. 1 is a diagram showing temperature changes on the surface of a semiconductor wafer due to two-stage flash heating. [Figure 13] FIG. 4 is a diagram showing the polarization characteristics exhibited in a hafnium oxide-based film by the heat treatment method according to the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0022] Hereinafter, the embodiments of the present invention will be described in detail with reference to the drawings. In the following, expressions indicating relative or absolute positional relationships (e.g., "in one direction," "along one direction," "parallel," "orthogonal," "center," "concentric," "coaxial," etc.) not only strictly indicate the positional relationship, but also indicate a state in which the relative angle or distance is displaced within a range in which a tolerance or similar function is obtained, unless otherwise specified. Furthermore, expressions indicating an equal state (e.g., "same," "equal," "homogeneous," etc.) not only indicate a state in which the relative position is strictly equal quantitatively, but also indicate a state in which there is a difference in which a tolerance or similar function is obtained, unless otherwise specified. Furthermore, expressions indicating a shape (e.g., "circular," "square," "cylindrical," etc.) not only indicate a geometrically strict shape, but also indicate a shape within a range in which a similar effect is obtained, and may have, for example, unevenness or chamfering. Furthermore, each expression such as "comprises," "includes," "has," "includes," and "has" for a component is not an exclusive expression that excludes the presence of other components. In addition, the expression "at least one of A, B, and C" includes "A only," "B only," "C only," "any two of A, B, and C," and "all of A, B, and C."

[0023] Fig. 1 is a vertical cross-sectional view showing the configuration of a heat treatment apparatus 1 for carrying out a heat treatment method according to the present invention. The heat treatment apparatus 1 in Fig. 1 is a flash lamp annealing apparatus that heats a disk-shaped semiconductor wafer W as a substrate by irradiating the semiconductor wafer W with flash light. The size of the semiconductor wafer W to be treated is not particularly limited, but is, for example, φ300 mm or φ450 mm (φ300 mm in this embodiment). In Fig. 1 and the subsequent figures, the dimensions and number of each part are exaggerated or simplified as necessary for ease of understanding.

[0024] The heat treatment apparatus 1 includes a chamber 6 that accommodates a semiconductor wafer W, a flash heating unit 5 that incorporates a plurality of flash lamps FL, and a halogen heating unit 4 that incorporates a plurality of halogen lamps HL. The flash heating unit 5 is provided on the upper side of the chamber 6, and the halogen heating unit 4 is provided on the lower side. The heat treatment apparatus 1 also includes, inside the chamber 6, a holding unit 7 that holds the semiconductor wafer W in a horizontal position, and a transfer mechanism 10 that transfers the semiconductor wafer W between the holding unit 7 and the outside of the apparatus. The heat treatment apparatus 1 also includes a control unit 3 that controls the respective operating mechanisms provided in the halogen heating unit 4, the flash heating unit 5, and the chamber 6 to perform heat treatment of the semiconductor wafer W.

[0025] The chamber 6 is configured by mounting quartz chamber windows on the top and bottom of a cylindrical chamber side portion 61. The chamber side portion 61 has a roughly cylindrical shape with openings at the top and bottom, with an upper chamber window 63 mounted and closed at the upper opening, and a lower chamber window 64 mounted and closed at the lower opening. The upper chamber window 63 constituting the ceiling of the chamber 6 is a disk-shaped member made of quartz, and functions as a quartz window that transmits the flash light emitted from the flash heating unit 5 into the chamber 6. The lower chamber window 64 constituting the floor of the chamber 6 is also a disk-shaped member made of quartz, and functions as a quartz window that transmits the light from the halogen heating unit 4 into the chamber 6.

[0026] In addition, a reflective ring 68 is attached to the upper part of the inner wall surface of the chamber side part 61, and a reflective ring 69 is attached to the lower part. Both of the reflective rings 68, 69 are formed in an annular shape. The upper reflective ring 68 is attached by fitting it from the upper side of the chamber side part 61. On the other hand, the lower reflective ring 69 is attached by fitting it from the lower side of the chamber side part 61 and fastening it with screws (not shown). In other words, both of the reflective rings 68, 69 are detachably attached to the chamber side part 61. The inner space of the chamber 6, i.e., the space surrounded by the upper chamber window 63, the lower chamber window 64, the chamber side part 61, and the reflective rings 68, 69, is defined as a heat treatment space 65.

[0027] By mounting the reflecting rings 68, 69 on the chamber side portion 61, a recess 62 is formed on the inner wall surface of the chamber 6. That is, the recess 62 is formed by a central portion of the inner wall surface of the chamber side portion 61 where the reflecting rings 68, 69 are not mounted, the lower end surface of the reflecting ring 68, and the upper end surface of the reflecting ring 69. The recess 62 is formed in an annular shape along the horizontal direction on the inner wall surface of the chamber 6, and surrounds the holder 7 that holds the semiconductor wafer W. The chamber side portion 61 and the reflecting rings 68, 69 are formed from a metal material (e.g., stainless steel) that has excellent strength and heat resistance.

[0028] Further, a transfer opening (furnace port) 66 for carrying a semiconductor wafer W into and out of the chamber 6 is formed in the chamber side portion 61. The transfer opening 66 can be opened and closed by a gate valve 185. The transfer opening 66 is connected in communication with the outer circumferential surface of the recess 62. Therefore, when the gate valve 185 opens the transfer opening 66, the semiconductor wafer W can be carried into and out of the heat treatment space 65 through the transfer opening 66 and the recess 62. Furthermore, when the gate valve 185 closes the transfer opening 66, the heat treatment space 65 in the chamber 6 becomes an airtight space.

[0029] Further, through holes 61a and 61b are formed in the chamber side 61. The through hole 61a is a cylindrical hole for guiding infrared light radiated from the upper surface of the semiconductor wafer W held on the susceptor 74 to the infrared sensor 29 of the upper radiation thermometer 25, which will be described later. On the other hand, the through hole 61b is a cylindrical hole for guiding infrared light radiated from the lower surface of the semiconductor wafer W to the lower radiation thermometer 20. The through holes 61a and 61b are provided at an incline with respect to the horizontal direction so that the axis of the through hole 61a intersects with the main surface of the semiconductor wafer W held on the susceptor 74. A transparent window 26 made of a calcium fluoride material that transmits infrared light in a wavelength range that can be measured by the upper radiation thermometer 25 is attached to the end of the through hole 61a facing the heat treatment space 65. Further, at the end of the through hole 61b facing the heat treatment space 65, a transparent window 21 made of a barium fluoride material that transmits infrared light in the wavelength range that the lower radiation thermometer 20 can measure is attached.

[0030] Further, a gas supply hole 81 is formed in the upper part of the inner wall of the chamber 6 to supply a processing gas to the heat treatment space 65. The gas supply hole 81 is formed at a position above the recessed portion 62, and may be provided in the reflecting ring 68. The gas supply hole 81 is connected to a gas supply pipe 83 through a buffer space 82 formed in an annular shape inside the side wall of the chamber 6. The gas supply pipe 83 is connected to a processing gas supply source 85. A valve 84 is inserted in the middle of the gas supply pipe 83. When the valve 84 is opened, the processing gas is supplied from the processing gas supply source 85 to the buffer space 82. The processing gas that has flowed into the buffer space 82 flows in a spreading manner in the buffer space 82, which has a smaller fluid resistance than the gas supply hole 81, and is supplied from the gas supply hole 81 to the heat treatment space 65. As the processing gas, for example, an inert gas such as nitrogen (N2), a reactive gas such as hydrogen (H2) or ammonia (NH3), or a mixed gas of these gases can be used (nitrogen gas in this embodiment).

[0031] On the other hand, a gas exhaust hole 86 is formed in the lower part of the inner wall of the chamber 6 to exhaust the gas in the heat treatment space 65. The gas exhaust hole 86 is formed at a position lower than the recessed portion 62, and may be provided in the reflecting ring 69. The gas exhaust hole 86 is connected to a gas exhaust pipe 88 through a buffer space 87 formed in an annular shape inside the side wall of the chamber 6. The gas exhaust pipe 88 is connected to an exhaust unit 190. A valve 89 is inserted in the middle of the gas exhaust pipe 88. When the valve 89 is opened, the gas in the heat treatment space 65 is exhausted from the gas exhaust hole 86 through the buffer space 87 to the gas exhaust pipe 88. The gas supply hole 81 and the gas exhaust hole 86 may be provided in a plurality of holes along the circumferential direction of the chamber 6, or may be slit-shaped. The process gas supply source 85 and the exhaust unit 190 may be mechanisms provided in the heat treatment apparatus 1, or may be utilities of a factory in which the heat treatment apparatus 1 is installed.

[0032] A gas exhaust pipe 191 for discharging gas from within the heat treatment space 65 is also connected to the tip of the transfer opening 66. The gas exhaust pipe 191 is connected to an exhaust unit 190 via a valve 192. By opening the valve 192, the gas from within the chamber 6 is exhausted via the transfer opening 66.

[0033] 2 is a perspective view showing the overall appearance of the holder 7. The holder 7 is configured to include a base ring 71, a connecting portion 72, and a susceptor 74. The base ring 71, the connecting portion 72, and the susceptor 74 are all made of quartz. That is, the entire holder 7 is made of quartz.

[0034] The base ring 71 is an arc-shaped quartz member with a portion missing from the annular shape. This missing portion is provided to prevent interference between the base ring 71 and a transfer arm 11 of the transfer mechanism 10, which will be described later. The base ring 71 is placed on the bottom surface of the recess 62, and is supported by the wall surface of the chamber 6 (see FIG. 1). A plurality of connecting portions 72 (four in this embodiment) are erected on the upper surface of the base ring 71 along the circumferential direction of the annular shape. The connecting portions 72 are also quartz members, and are fixed to the base ring 71 by welding.

[0035] The susceptor 74 is supported by four connecting portions 72 provided on the base ring 71. FIG. 3 is a plan view of the susceptor 74. FIG. 4 is a cross-sectional view of the susceptor 74. The susceptor 74 includes a holding plate 75, a guide ring 76, and a plurality of substrate support pins 77. The holding plate 75 is a substantially circular flat member made of quartz. The diameter of the holding plate 75 is larger than the diameter of the semiconductor wafer W. In other words, the holding plate 75 has a larger planar size than the semiconductor wafer W.

[0036] A guide ring 76 is installed on the periphery of the upper surface of the holding plate 75. The guide ring 76 is an annular member having an inner diameter larger than the diameter of the semiconductor wafer W. For example, when the diameter of the semiconductor wafer W is φ300 mm, the inner diameter of the guide ring 76 is φ320 mm. The inner circumference of the guide ring 76 is a tapered surface that widens from the holding plate 75 upward. The guide ring 76 is made of quartz, similar to the holding plate 75. The guide ring 76 may be fused to the upper surface of the holding plate 75, or may be fixed to the holding plate 75 by a separately processed pin or the like. Alternatively, the holding plate 75 and the guide ring 76 may be processed as an integrated member.

[0037] The area of ​​the upper surface of the holding plate 75 inside the guide ring 76 is a flat holding surface 75a that holds the semiconductor wafer W. A plurality of substrate support pins 77 are provided on the holding surface 75a of the holding plate 75. In this embodiment, a total of 12 substrate support pins 77 are provided at 30° intervals along a circumference concentric with the outer circumferential circle of the holding surface 75a (the inner circumferential circle of the guide ring 76). The diameter of the circle on which the 12 substrate support pins 77 are arranged (the distance between the opposing substrate support pins 77) is smaller than the diameter of the semiconductor wafer W, and is φ270 mm to φ280 mm (φ270 mm in this embodiment) if the diameter of the semiconductor wafer W is φ300 mm. Each substrate support pin 77 is made of quartz. The substrate support pins 77 may be provided on the upper surface of the holding plate 75 by welding, or may be processed integrally with the holding plate 75.

[0038] Returning to FIG. 2, four connecting parts 72 erected on the base ring 71 and the peripheral part of the holding plate 75 of the susceptor 74 are fixed by welding. That is, the susceptor 74 and the base ring 71 are fixedly connected by the connecting parts 72. The base ring 71 of the holding part 7 is supported on the wall surface of the chamber 6, and the holding part 7 is attached to the chamber 6. When the holding part 7 is attached to the chamber 6, the holding plate 75 of the susceptor 74 is in a horizontal position (a position in which the normal line coincides with the vertical direction). That is, the holding surface 75a of the holding plate 75 is a horizontal plane.

[0039] The semiconductor wafer W carried into the chamber 6 is placed and held in a horizontal position on the susceptor 74 of the holder 7 attached to the chamber 6. At this time, the semiconductor wafer W is supported by twelve substrate support pins 77 standing on a holding plate 75 and held on the susceptor 74. More precisely, the upper ends of the twelve substrate support pins 77 contact the lower surface of the semiconductor wafer W to support the semiconductor wafer W. The heights of the twelve substrate support pins 77 (the distance from the upper ends of the substrate support pins 77 to the holding surface 75a of the holding plate 75) are uniform, so that the twelve substrate support pins 77 can support the semiconductor wafer W in a horizontal position.

[0040] Furthermore, the semiconductor wafer W is supported by a plurality of substrate support pins 77 at a predetermined distance from the holding surface 75a of the holding plate 75. The thickness of the guide ring 76 is greater than the height of the substrate support pins 77. Therefore, the guide ring 76 prevents the semiconductor wafer W supported by the plurality of substrate support pins 77 from shifting in the horizontal direction.

[0041] 2 and 3, an opening 78 is formed in the holding plate 75 of the susceptor 74, penetrating vertically. The opening 78 is provided so that the lower radiation thermometer 20 can receive radiation light (infrared light) emitted from the lower surface of the semiconductor wafer W. That is, the lower radiation thermometer 20 receives light emitted from the lower surface of the semiconductor wafer W through the opening 78 and a transparent window 21 attached to the through hole 61b of the chamber side part 61, and measures the temperature of the semiconductor wafer W. Furthermore, the holding plate 75 of the susceptor 74 is provided with four through holes 79 through which lift pins 12 of the transfer mechanism 10, which will be described later, pass to transfer the semiconductor wafer W.

[0042] FIG. 5 is a plan view of the transfer mechanism 10. FIG. 6 is a side view of the transfer mechanism 10. The transfer mechanism 10 includes two transfer arms 11. The transfer arms 11 are formed in an arc shape that is aligned with the generally annular recess 62. Two lift pins 12 are provided upright on each of the transfer arms 11. The transfer arms 11 and the lift pins 12 are made of quartz. Each transfer arm 11 is rotatable by a horizontal movement mechanism 13. The horizontal movement mechanism 13 horizontally moves the pair of transfer arms 11 between a transfer operation position (solid line position in FIG. 5) where the semiconductor wafer W is transferred to the holder 7 and a retracted position (double-dashed line position in FIG. 5) where the pair of transfer arms 11 do not overlap the semiconductor wafer W held by the holder 7 in a plan view. The horizontal movement mechanism 13 may be a mechanism that rotates each transfer arm 11 using an individual motor, or a mechanism that uses a link mechanism to rotate a pair of transfer arms 11 in unison using a single motor.

[0043] The pair of transfer arms 11 are raised and lowered together with the horizontal movement mechanism 13 by the lifting mechanism 14. When the lifting mechanism 14 raises the pair of transfer arms 11 to the transfer operation position, the total of four lift pins 12 pass through the through holes 79 (see FIGS. 2 and 3) formed in the susceptor 74, and the upper ends of the lift pins 12 protrude from the upper surface of the susceptor 74. On the other hand, when the lifting mechanism 14 lowers the pair of transfer arms 11 to the transfer operation position to remove the lift pins 12 from the through holes 79, and the horizontal movement mechanism 13 moves the pair of transfer arms 11 to open them, each transfer arm 11 moves to a retracted position. The retracted position of the pair of transfer arms 11 is directly above the base ring 71 of the holder 7. Since the base ring 71 is placed on the bottom surface of the recess 62, the retracted position of the transfer arms 11 is inside the recess 62. In addition, an exhaust mechanism (not shown) is provided near the location where the drive part of the transfer mechanism 10 (horizontal movement mechanism 13 and lifting mechanism 14) is located, and is configured to exhaust the atmosphere around the drive part of the transfer mechanism 10 to the outside of the chamber 6.

[0044] Returning to FIG. 1, the flash heating unit 5 provided above the chamber 6 is configured to include a light source consisting of multiple (30 in this embodiment) xenon flash lamps FL inside a housing 51, and a reflector 52 provided to cover the light source from above. A lamp light emission window 53 is attached to the bottom of the housing 51 of the flash heating unit 5. The lamp light emission window 53 forming the floor of the flash heating unit 5 is a plate-shaped quartz window made of quartz. By installing the flash heating unit 5 above the chamber 6, the lamp light emission window 53 faces the upper chamber window 63. The flash lamps FL irradiate flash light from above the chamber 6 through the lamp light emission window 53 and the upper chamber window 63 into the heat treatment space 65.

[0045] The multiple flash lamps FL are rod-shaped lamps each having a long cylindrical shape, and are arranged in a plane such that their longitudinal directions are parallel to each other along the main surface of the semiconductor wafer W held by the holder 7 (i.e., along the horizontal direction). Therefore, the plane formed by the arrangement of the flash lamps FL is also a horizontal plane.

[0046] Fig. 8 is a diagram showing a drive circuit for a flash lamp FL. As shown in the figure, a capacitor 93, a coil 94, a flash lamp FL, and an IGBT (insulated gate bipolar transistor) 96 are connected in series. Also, as shown in Fig. 8, the control unit 3 includes a pulse generator 31 and a waveform setting unit 32, and is connected to an input unit 33. As the input unit 33, various known input devices such as a keyboard, a mouse, a touch panel, etc. The waveform setting unit 32 sets the waveform of a pulse signal based on the input contents from the input unit 33, and the pulse generator 31 generates a pulse signal according to the waveform.

[0047] The flash lamp FL comprises a rod-shaped glass tube (discharge tube) 92 filled with xenon gas and having an anode and a cathode disposed at both ends, and a trigger electrode 91 provided on the outer circumferential surface of the glass tube 92. A predetermined voltage is applied to the capacitor 93 by a power supply unit 95, and an electric charge corresponding to the applied voltage (charging voltage) is stored in the capacitor 93. A high voltage can be applied to the trigger electrode 91 from a trigger circuit 97. The timing at which the trigger circuit 97 applies a voltage to the trigger electrode 91 is controlled by the control unit 3.

[0048] The IGBT 96 is a bipolar transistor with a MOSFET (Metal Oxide Semiconductor Field effect transistor) built into the gate, and is a switching element suitable for handling large power. A pulse signal is applied to the gate of the IGBT 96 from the pulse generator 31 of the control unit 3. When a voltage equal to or greater than a predetermined value (high voltage) is applied to the gate of the IGBT 96, the IGBT 96 is turned on, and when a voltage less than a predetermined value (low voltage) is applied, the IGBT 96 is turned off. In this way, the drive circuit including the flash lamp FL is turned on and off by the IGBT 96. By turning the IGBT 96 on and off, the connection between the flash lamp FL and the corresponding capacitor 93 is interrupted, and the current flowing through the flash lamp FL is controlled to be on and off.

[0049] Even if the IGBT 96 is turned on and a high voltage is applied to both ends of the glass tube 92 while the capacitor 93 is charged, xenon gas is an electrical insulator, so under normal conditions no electricity flows through the glass tube 92. However, when the trigger circuit 97 applies a high voltage to the trigger electrode 91 and breaks down the insulation, a current flows instantaneously through the glass tube 92 due to a discharge between the electrodes at both ends, and light is emitted due to the excitation of the xenon atoms or molecules at that time.

[0050] A drive circuit as shown in Fig. 8 is provided individually for each of the multiple flash lamps FL provided in the flash heating unit 5. In this embodiment, 30 flash lamps FL are arranged in a plane, and therefore 30 drive circuits as shown in Fig. 8 are provided corresponding to the 30 flash lamps FL. Therefore, the current flowing through each of the 30 flash lamps FL is individually on / off controlled by the corresponding IGBT 96.

[0051] Moreover, the reflector 52 is provided above the multiple flash lamps FL so as to cover them entirely. The basic function of the reflector 52 is to reflect the flash light emitted from the multiple flash lamps FL toward the heat treatment space 65. The reflector 52 is made of an aluminum alloy plate, and its surface (the surface facing the flash lamps FL) is roughened by blasting.

[0052] The halogen heating unit 4 provided below the chamber 6 has a plurality of halogen lamps HL (40 in this embodiment) built inside the housing 41. The halogen heating unit 4 is a light irradiation unit that heats the semiconductor wafer W by irradiating light from the plurality of halogen lamps HL into a heat treatment space 65 from below the chamber 6 through a lower chamber window 64.

[0053] FIG. 7 is a plan view showing the arrangement of a plurality of halogen lamps HL. 40 halogen lamps HL are arranged in two tiers, upper and lower. 20 halogen lamps HL are arranged in the upper tier close to the holder 7, and 20 halogen lamps HL are also arranged in the lower tier farther from the holder 7 than the upper tier. Each halogen lamp HL is a rod-shaped lamp having a long cylindrical shape. The 20 halogen lamps HL in both the upper and lower tiers are arranged so that their longitudinal directions are parallel to each other along the main surface of the semiconductor wafer W held by the holder 7 (i.e., along the horizontal direction). Therefore, the plane formed by the arrangement of the halogen lamps HL in both the upper and lower tiers is a horizontal plane.

[0054] 7, the halogen lamps HL are arranged at a higher density in the region facing the periphery of the semiconductor wafer W held by the holder 7 in both the upper and lower tiers than in the region facing the center of the semiconductor wafer W. That is, in both the upper and lower tiers, the arrangement pitch of the halogen lamps HL is shorter in the periphery of the lamp arrangement than in the center. This makes it possible to irradiate a greater amount of light to the periphery of the semiconductor wafer W, which is prone to temperature drop during heating by light irradiation from the halogen heating unit 4.

[0055] The lamp group consisting of the halogen lamps HL in the upper row and the lamp group consisting of the halogen lamps HL in the lower row are arranged to intersect in a lattice pattern. That is, a total of 40 halogen lamps HL are arranged so that the longitudinal direction of the 20 halogen lamps HL arranged in the upper row and the longitudinal direction of the 20 halogen lamps HL arranged in the lower row are perpendicular to each other.

[0056] The halogen lamp HL is a filament type light source that emits light by passing electricity through a filament disposed inside a glass tube, which becomes incandescent. A gas consisting of an inert gas such as nitrogen or argon with a small amount of halogen elements (iodine, bromine, etc.) is sealed inside the glass tube. By introducing halogen elements, it is possible to set the temperature of the filament at a high temperature while suppressing filament breakage. Therefore, the halogen lamp HL has the characteristics of having a longer life than a normal incandescent light bulb and being able to continuously irradiate strong light. In other words, the halogen lamp HL is a continuous lighting lamp that emits light continuously for at least one second or more. In addition, since the halogen lamp HL is a rod-shaped lamp, it has a long life, and by arranging the halogen lamp HL along the horizontal direction, the radiation efficiency to the semiconductor wafer W above is excellent.

[0057] Also, a reflector 43 is provided below the two-tiered halogen lamps HL within the housing 41 of the halogen heating unit 4 (FIG. 1). The reflector 43 reflects the light emitted from the multiple halogen lamps HL toward the heat treatment space 65.

[0058] As shown in Fig. 1, the heat treatment apparatus 1 includes an upper radiation thermometer 25 and a lower radiation thermometer 20. The upper radiation thermometer 25 is installed diagonally above the semiconductor wafer W held on the susceptor 74, and receives infrared light radiated from the upper surface of the semiconductor wafer W to measure the temperature of the upper surface. The infrared sensor 29 of the upper radiation thermometer 25 includes an InSb (indium antimonide) optical element so as to be able to respond to a sudden temperature change of the upper surface of the semiconductor wafer W at the moment when the flash light is irradiated. On the other hand, the lower radiation thermometer 20 is installed diagonally below the semiconductor wafer W held on the susceptor 74, and receives infrared light radiated from the lower surface of the semiconductor wafer W to measure the temperature of the lower surface.

[0059] The control unit 3 controls the above-mentioned various operating mechanisms provided in the heat treatment device 1. The hardware configuration of the control unit 3 is similar to that of a general computer. That is, the control unit 3 includes a CPU, which is a circuit that performs various arithmetic processing, a ROM, which is a read-only memory that stores a basic program, a RAM, which is a readable and writable memory that stores various information, and a storage unit (e.g., a magnetic disk or SSD) that stores control software, data, and the like. The CPU of the control unit 3 executes a predetermined processing program, and the processing in the heat treatment device 1 proceeds. The control unit 3 also includes a pulse generator 31 and a waveform setting unit 32 (FIG. 8), and the waveform setting unit 32 sets the waveform of a pulse signal based on the input contents from the input unit 33, and the pulse generator 31 outputs a pulse signal to the gate of the IGBT 96 accordingly.

[0060] In addition to the above configuration, the heat treatment apparatus 1 is provided with various cooling structures to prevent an excessive temperature rise in the halogen heating unit 4, the flash heating unit 5, and the chamber 6 due to the thermal energy generated from the halogen lamps HL and the flash lamps FL during the heat treatment of the semiconductor wafer W. For example, a water-cooling pipe (not shown) is provided in the wall of the chamber 6. The halogen heating unit 4 and the flash heating unit 5 are also of an air-cooled structure that forms a gas flow inside to remove heat. Air is also supplied to the gap between the upper chamber window 63 and the lamp light emission window 53 to cool the flash heating unit 5 and the upper chamber window 63.

[0061] Next, the procedure of the heat treatment method according to the present invention will be described. Fig. 9 is a flow chart showing the procedure of the heat treatment method according to the present invention. First, prior to heat treatment in the heat treatment apparatus 1, a hafnium oxide-based film is formed on the semiconductor wafer W (step S1). The process of step S1 is performed by a film forming apparatus different from the heat treatment apparatus 1.

[0062] FIG. 10 is a diagram showing an example of a semiconductor wafer W on which a hafnium oxide-based film 103 is formed. After a natural oxide film (SiO2) is removed from the surface of a silicon substrate 101 by a cleaning process, a lower electrode 102 made of titanium nitride (TiN) is formed on the surface. A hafnium oxide-based film 103 is formed on the lower electrode 102. The hafnium oxide-based film 103 is a thin film made of a material containing hafnium oxide (HfO2: hafnia) as a main component and additional elements, and exhibits ferroelectricity when it reaches a metastable phase (orthorhombic crystal). Examples of the additional elements include zirconium (Zr), silicon (Si), aluminum (Al), and lanthanum (La). The inclusion of these additional elements is expected to improve the polarization characteristics of hafnium oxide. In this embodiment, the material of the hafnium oxide-based film 103 is HfO2, which is hafnium oxide with zirconium added. 0.5 Zr 0.5 O2(HZO). Hafnium, zirconium, and oxygen are bonded to one another in the hafnium oxide-based film 103. An upper electrode 104 of titanium nitride is further formed on the hafnium oxide-based film 103.

[0063] The hafnium oxide-based film 103 is formed by using PVD (Physical Vapor Deposition) or ALD (Atomic Layer Deposition). Regardless of which method is used, the hafnium oxide-based film 103 after film formation is in an amorphous state and does not have a crystalline structure. The thickness of the hafnium oxide-based film 103 formed on the semiconductor wafer W is, for example, about 5 nm or 10 nm. In the following description, the entire layer structure of FIG. 10 including the formed hafnium oxide-based film 103 is referred to as the semiconductor wafer W. That is, the semiconductor wafer W includes the hafnium oxide-based film 103 formed on the surface. The surface of the semiconductor wafer W includes the lower electrode 102, the hafnium oxide-based film 103, and the upper electrode 104 formed thereon.

[0064] Next, the semiconductor wafer W on which the hafnium oxide base film 103 is formed is loaded into the chamber 6 (step S2). When the wafer is loaded, the valve 84 for supplying air is opened, and the valves 89, 192 for exhausting air are also opened to start supplying and exhausting air to and from the chamber 6. When the valve 84 is opened, nitrogen gas is supplied to the heat treatment space 65 from the gas supply hole 81. When the valve 89 is opened, the gas in the chamber 6 is exhausted from the gas exhaust hole 86. As a result, the nitrogen gas supplied from the upper part of the heat treatment space 65 in the chamber 6 flows downward and is exhausted from the lower part of the heat treatment space 65.

[0065] Furthermore, by opening the valve 192, the gas in the chamber 6 is also exhausted from the transfer opening 66. Furthermore, the atmosphere around the drive unit of the transfer mechanism 10 is also exhausted by an exhaust mechanism (not shown). Note that, during the heat treatment of the semiconductor wafer W in the heat treatment apparatus 1, nitrogen gas is continuously supplied to the heat treatment space 65, and the supply amount is appropriately changed depending on the treatment process.

[0066] Next, the gate valve 185 is opened to open the transport opening 66, and the semiconductor wafer W on which the hafnium oxide base film 103 has been formed is carried into the heat treatment space 65 in the chamber 6 through the transport opening 66 by a transport robot outside the apparatus. At this time, there is a risk that the atmosphere outside the apparatus may be drawn in with the carrying in of the semiconductor wafer W, but since nitrogen gas is continuously supplied to the chamber 6, the nitrogen gas flows out from the transport opening 66, making it possible to minimize the entrainment of such external atmosphere.

[0067] The semiconductor wafer W carried in by the transport robot advances to a position directly above the holder 7 and stops there. Then, the pair of transfer arms 11 of the transfer mechanism 10 move horizontally from the retreated position to the transfer operation position and rise, causing the lift pins 12 to pass through the through holes 79 and protrude from the upper surface of the holding plate 75 of the susceptor 74 to receive the semiconductor wafer W. At this time, the lift pins 12 rise to a position above the upper ends of the substrate support pins 77.

[0068] After the semiconductor wafer W is placed on the lift pins 12, the transport robot leaves the heat treatment space 65, and the transport opening 66 is closed by the gate valve 185. Then, the pair of transfer arms 11 descend, and the semiconductor wafer W is transferred from the transfer mechanism 10 to the susceptor 74 of the holder 7, where it is held from below in a horizontal position. The semiconductor wafer W is supported by a plurality of substrate support pins 77 erected on the holding plate 75 and held by the susceptor 74. The semiconductor wafer W is held by the holder 7 with the surface on which the hafnium oxide base film 103 is formed as the upper surface. A predetermined gap is formed between the back surface (the main surface opposite to the front surface) of the semiconductor wafer W supported by the plurality of substrate support pins 77 and the holding surface 75a of the holding plate 75. The pair of transfer arms 11 that descend to below the susceptor 74 are retreated to a retreat position, that is, inside the recess 62, by the horizontal movement mechanism 13.

[0069] After the semiconductor wafer W is held from below in a horizontal position by the susceptor 74 of the holder 7 made of quartz, the 40 halogen lamps HL of the halogen heating unit 4 are turned on all at once to start preheating (assisted heating) (step S3). The halogen light emitted from the halogen lamps HL passes through the lower chamber window 64 and the susceptor 74, both made of quartz, and is irradiated onto the underside of the semiconductor wafer W. The semiconductor wafer W is preheated by being irradiated with light from the halogen lamps HL, and its temperature rises. Note that the transfer arm 11 of the transfer mechanism 10 is retracted inside the recess 62, and does not interfere with heating by the halogen lamps HL.

[0070] FIG. 11 is a diagram showing a change in temperature of the semiconductor wafer W. At time t1, the halogen lamps HL are turned on and the temperature of the semiconductor wafer W starts to rise. When preheating is performed by the halogen lamps HL, the temperature of the semiconductor wafer W is measured by the lower radiation thermometer 20. That is, the lower radiation thermometer 20 receives infrared light radiated from the lower surface of the semiconductor wafer W held by the susceptor 74 through the opening 78 through the transparent window 21 and measures the wafer temperature during heating. The measured temperature of the semiconductor wafer W is transmitted to the control unit 3. The control unit 3 controls the output of the halogen lamps HL while monitoring whether the temperature of the semiconductor wafer W, which is heated by the light irradiation from the halogen lamps HL, has reached a predetermined preheating temperature T1. That is, the control unit 3 feedback-controls the output of the halogen lamps HL based on the measured value by the lower radiation thermometer 20 so that the temperature of the semiconductor wafer W becomes the preheating temperature T1. In this way, the lower radiation thermometer 20 is a radiation thermometer for controlling the temperature of the semiconductor wafer W during preheating. The preheating temperature T1 is 100° C. or more and 400° C. or less. If the preheating temperature T1 is less than 100° C., the surface of the semiconductor wafer W does not reach a required temperature during the subsequent flash heating. On the other hand, if the preheating temperature T1 exceeds 400° C., recrystallization occurs in the amorphous hafnium oxide-based film 103 during the preheating stage.

[0071] After the temperature of the semiconductor wafer W reaches the preheating temperature T1 at time t2, the control unit 3 temporarily maintains the semiconductor wafer W at the preheating temperature T1. Specifically, when the temperature of the semiconductor wafer W measured by the lower radiation thermometer 20 reaches the preheating temperature T1, the control unit 3 adjusts the output of the halogen lamps HL to maintain the temperature of the semiconductor wafer W at approximately the preheating temperature T1.

[0072] By performing such preheating with the halogen lamps HL, the entire semiconductor wafer W including the hafnium oxide base film 103 is uniformly heated to the preheating temperature T1. During the preheating stage with the halogen lamps HL, the temperature of the peripheral portion of the semiconductor wafer W, where heat dissipation is more likely to occur, tends to be lower than that of the central portion, but the arrangement density of the halogen lamps HL in the halogen heating unit 4 is higher in the region facing the peripheral portion than in the region facing the central portion of the semiconductor wafer W. As a result, the amount of light irradiated to the peripheral portion of the semiconductor wafer W, where heat dissipation is more likely, is increased, and the in-plane temperature distribution of the semiconductor wafer W during the preheating stage can be made uniform.

[0073] At time t3, when a predetermined time has elapsed since the temperature of the semiconductor wafer W reached the preheating temperature T1, the flash lamps FL of the flash heating unit 5 irradiate the surface of the semiconductor wafer W held on the susceptor 74 with flash light. At this time, part of the flash light emitted from the flash lamps FL heads directly into the chamber 6, and the other part is reflected by the reflector 52 and then heads into the chamber 6, and the semiconductor wafer W is flash-heated by the irradiation of these flash lights.

[0074] When the flash lamp FL emits a flash of light, a charge is stored in advance in the capacitor 93 at a predetermined charging voltage by the power supply unit 95. Then, with a charge stored in the capacitor 93, a pulse signal is output from the pulse generator 31 of the control unit 3 to the IGBT 96 to turn the IGBT 96 on and off.

[0075] The waveform of the pulse signal can be specified by inputting a recipe from the input unit 33 in which the time of the pulse width (on time) and the time of the pulse interval (off time) are sequentially set as parameters. When an operator inputs such a recipe from the input unit 33 to the control unit 3, the waveform setting unit 32 of the control unit 3 sets a pulse waveform that repeats on and off accordingly. Then, the pulse generator 31 outputs a pulse signal according to the pulse waveform set by the waveform setting unit 32. As a result, a pulse signal of the set waveform is applied to the gate of the IGBT 96, and the on / off drive of the IGBT 96 is controlled. Specifically, when the pulse signal input to the gate of the IGBT 96 is on, the IGBT 96 is in the on state, and when the pulse signal is off, the IGBT 96 is in the off state.

[0076] Moreover, in synchronization with the timing at which the pulse signal output from the pulse generator 31 turns on, the control unit 3 controls the trigger circuit 97 to apply a high voltage (trigger voltage) to the trigger electrode 91. With charge stored in the capacitor 93, a pulse signal is input to the gate of the IGBT 96, and in synchronization with the timing at which the pulse signal turns on, a high voltage is applied to the trigger electrode 91. When the pulse signal is on, a current flows between both electrodes in the glass tube 92, and light is emitted by the excitation of xenon atoms or molecules at that time.

[0077] In this way, the 30 flash lamps FL of the flash heating unit 5 emit light, and the surface of the semiconductor wafer W held by the holding unit 7 is irradiated with a flash of light. If the flash lamps FL are made to emit light without using the IGBT 96, the charge stored in the capacitor 93 is consumed in one emission, and the output waveform from the flash lamps FL becomes a simple single pulse with a width of about 0.1 milliseconds to 10 milliseconds. In contrast, in this embodiment, the IGBT 96, which is a switching element, is connected in the circuit and a pulse signal is output to the gate of the IGBT 96, so that the supply of charge from the capacitor 93 to the flash lamps FL is intermittently controlled by the IGBT 96, and the current flowing through the flash lamps FL is on and off controlled. As a result, the light emission of the flash lamps FL is chopper-controlled, so that the charge stored in the capacitor 93 is divided and consumed, and the flash lamps FL repeatedly blink in an extremely short time. Note that before the current value flowing through the circuit becomes completely "0", the next pulse is applied to the gate of the IGBT 96, and the current value increases again, so that the light emission output does not become completely "0" even while the flash lamps FL are repeatedly blinking.

[0078] By controlling the on / off of the current flowing through the flash lamp FL with the IGBT 96, the light emission pattern of the flash lamp FL (time waveform of the light emission output) can be freely defined, and the light emission time and light emission intensity can be freely adjusted. The on / off drive pattern of the IGBT 96 is defined by the pulse width and pulse interval input from the input unit 33. In other words, by incorporating the IGBT 96 in the drive circuit of the flash lamp FL, the light emission pattern of the flash lamp FL can be freely defined simply by appropriately setting the pulse width and pulse interval input from the input unit 33.

[0079] Specifically, for example, when the ratio of the time of the pulse width to the time of the pulse interval input from the input unit 33 is increased, the current flowing through the flash lamp FL increases, and the light emission intensity becomes stronger. Conversely, when the ratio of the time of the pulse width to the time of the pulse interval input from the input unit 33 is decreased, the current flowing through the flash lamp FL decreases, and the light emission intensity becomes weaker. Furthermore, by appropriately adjusting the ratio of the time of the pulse interval to the time of the pulse width input from the input unit 33, the light emission intensity of the flash lamp FL is maintained constant. Furthermore, by lengthening the total time of the combination of the time of the pulse width and the time of the pulse interval input from the input unit 33, the current continues to flow through the flash lamp FL for a relatively long period of time, and the light emission time of the flash lamp FL becomes longer. The light emission time of the flash lamp FL is appropriately set between 0.1 milliseconds and 100 milliseconds. The maximum temperature reached on the surface of the semiconductor wafer W and the amount of heat input to the semiconductor wafer W are determined by the charging voltage to the capacitor 93 and the waveform of the light emission pattern of the flash lamp FL.

[0080] In this embodiment, the pulse signal applied to the gate of the IGBT 96 is set so that the light emission pattern of the flash lamp FL performs two-stage flash heating, namely, a first flash heating in which the surface of the semiconductor wafer W is heated at a first heating rate, and a second flash heating in which the surface is heated at a second heating rate. Fig. 12 is a diagram showing the temperature change of the surface of the semiconductor wafer W due to two-stage flash heating. This figure is an enlarged view of the vicinity of time t3 in Fig. 11. Since the surface of the semiconductor wafer W includes a hafnium oxide-based film 103, the temperature shown in Fig. 12 is also the temperature of the hafnium oxide-based film 103.

[0081] A first flash heating is performed in which the surface of the semiconductor wafer W is heated at a first temperature rise rate by irradiating a first stage of flash light from the flash lamps FL from time t31 to time t32 (step S4). In the first flash heating, the surface of the semiconductor wafer W including the hafnium oxide base film 103 is heated from the preheating temperature T1 to the intermediate temperature T2 at the first temperature rise rate. That is, the surface temperature of the semiconductor wafer W reaches the intermediate temperature T2 at time t32. By applying a pulse signal having a first ratio of the pulse width time to the pulse interval time to the IGBT 96, the current flowing through the flash lamps FL gradually increases, and the first flash heating is realized in which the surface of the semiconductor wafer W is heated at the first temperature rise rate.

[0082] The heating time ta of the first flash heating from time t31 to time t32 is 3 milliseconds or more. Preferably, the heating time ta of the first flash heating is 3 milliseconds or more and 40 milliseconds or less. The intermediate temperature T2 is 400° C. or more and 900° C. or less. It is believed that the first flash heating causes crystal nucleation in the amorphous hafnium oxide-based film 103.

[0083] Next, a second flash heating is performed in which the surface of the semiconductor wafer W is heated at a second temperature rise rate by irradiating a second stage of flash light from the flash lamps FL from time t32 to time t33 (step S5). In the second flash heating, the surface of the semiconductor wafer W including the hafnium oxide base film 103 is heated from the intermediate temperature T2 to the processing temperature T3 at the second temperature rise rate. That is, the surface temperature of the semiconductor wafer W reaches the processing temperature T3 at time t33. The second temperature rise rate is higher than the first temperature rise rate. The processing temperature T3 is the maximum temperature reached by the surface of the semiconductor wafer W in a series of heat treatments, and is naturally higher than the preheating temperature T1 and the intermediate temperature T2. By applying a pulse signal to the IGBT 96, in which the ratio of the time of the pulse width to the time of the pulse interval is a second ratio greater than the first ratio, the current flowing through the flash lamps FL is further increased, and the second flash heating is realized in which the surface of the semiconductor wafer W is heated at the second temperature rise rate.

[0084] The heating time tb of the second flash heating from time t32 to time t33 is 2 milliseconds or less. Preferably, the heating time tb of the second flash heating is 0.1 milliseconds or more and 2 milliseconds or less. That is, the heating time ta of the first flash heating is longer than the heating time tb of the second flash heating. The processing temperature T3 is 600°C or more and 1200°C or less. It is considered that the second flash heating causes grain growth of the crystal nuclei generated in the hafnium oxide base film 103 by the first flash heating, resulting in an increase in grain size. Note that while the horizontal axis (time axis) of FIG. 11 is in seconds, the horizontal axis of FIG. 12 is in milliseconds, so that t31 to t33 of FIG. 12 are displayed superimposed on time t3 in FIG. 11.

[0085] At time t33, the pulse signal applied to the IGBT 96 is turned off, the flash lamps FL stop emitting the flash light, and the surface temperature of the semiconductor wafer W drops rapidly (step S6). After that, the halogen lamps HL are also turned off. As a result, the temperature of the semiconductor wafer W drops rapidly from the preheating temperature T1 (FIG. 11). The temperature of the semiconductor wafer W during the temperature drop is measured by the lower radiation thermometer 20, and the measurement result is transmitted to the control unit 3. The control unit 3 monitors whether the temperature of the semiconductor wafer W has dropped to a predetermined temperature based on the measurement result of the lower radiation thermometer 20. Then, after the temperature of the semiconductor wafer W drops to a predetermined temperature or lower, the pair of transfer arms 11 of the transfer mechanism 10 again move horizontally from the retracted position to the transfer operation position and rise, so that the lift pins 12 protrude from the upper surface of the susceptor 74 and receive the heat-treated semiconductor wafer W from the susceptor 74. Next, the transfer opening 66, which had been closed by the gate valve 185, is opened, and the semiconductor wafer W placed on the lift pins 12 is carried out by a transfer robot outside the apparatus, completing the heat treatment of the semiconductor wafer W in the heat treatment apparatus 1 (step S7). The surface temperature of the semiconductor wafer W, which rapidly increases and then decreases in temperature, may be measured by the upper radiation thermometer 25. The upper radiation thermometer 25 measures the surface temperature of the semiconductor wafer W at extremely short sampling intervals, and therefore is able to follow any sudden changes in the surface temperature of the semiconductor wafer W during flash light irradiation.

[0086] In this embodiment, millisecond annealing is performed by irradiating the surface of the semiconductor wafer W on which the hafnium oxide-based film 103 is formed with a flash light from a flash lamp FL to heat the surface for 1 second or less. If flash heating is performed by irradiating a flash light with an extremely short irradiation time, the surface of the semiconductor wafer W including the hafnium oxide-based film 103 can be heated to a considerably high temperature without applying a large amount of heat. The polarization characteristics of the hafnium oxide-based film 103 in an amorphous state are largely dependent on the temperature reached, and generally, the higher the maximum temperature reached by the hafnium oxide-based film 103 during the heating process, the more improved the polarization characteristics are, and the better the ferroelectricity is. That is, as in this embodiment, millisecond annealing is performed by irradiating the surface of the semiconductor wafer W on which the hafnium oxide-based film 103 is formed with a flash light to heat the surface for 1 second or less, and the hafnium oxide-based film 103 can be heated to a high temperature and exhibit good ferroelectricity while suppressing an increase in the amount of heat applied to the semiconductor wafer W.

[0087] In particular, in this embodiment, two-stage flash heating is performed, which is composed of a first flash heating in which the surface of the semiconductor wafer W is heated at a first heating rate and a second flash heating in which the surface is heated at a higher second heating rate. When the surface of the semiconductor wafer W is heated from the preheating temperature T1 to the processing temperature T3 by one-stage flash heating, the temperature of the surface changes as shown by the dotted line in FIG. 12. According to the two-stage flash heating of this embodiment (solid line in FIG. 12), the amount of heat given to the surface of the semiconductor wafer W can be reduced by an amount equivalent to the area of ​​the hatched triangle in FIG. 12, compared to one-stage flash heating (dotted line in FIG. 12). Furthermore, in the two-stage flash heating, the light irradiated from the flash lamp is reflected by the semiconductor wafer W, and the degree of heating of the surrounding environment including the atmosphere containing the processing gas and the members such as the inner wall of the chamber 6 is low, so that heat dissipation from the semiconductor wafer W is further promoted, compared to one-stage flash heating. As a result, in the temperature decreasing stage after time t33, the temperature decreasing rate of the semiconductor wafer W when two-stage flash heating is performed can be increased by 20% or more, preferably 20% or more and 50% or less, compared to the temperature decreasing rate when the surface of the semiconductor wafer W is heated to the processing temperature T3 by one-stage flash heating. By increasing the temperature decreasing rate, a phase exhibiting ferroelectricity is more likely to appear in the hafnium oxide-based film 103.

[0088] FIG. 13 is a diagram showing the polarization characteristics of the hafnium oxide-based film 103 produced by the heat treatment method according to the present invention. In the figure, the horizontal axis shows the maximum temperature reached on the surface of the semiconductor wafer W during flash heating. The vertical axis shows the remnant polarization of the hafnium oxide-based film 103 after heat treatment. The remnant polarization is the value of polarization remaining when an external electric field is made zero after an electric field is applied to the hafnium oxide-based film 103 from the outside to cause polarization. It can be said that the larger the value of the remnant polarization, the better the ferroelectricity. In addition, in FIG. 13, the area surrounded by the dotted line shows the case where two-stage flash heating was performed, and the area outside the area shows the case where one-stage flash heating was performed. In the dotted line area, the triangle shows the case where the heating time ta of the first flash heating is 10 milliseconds, and the circle shows the case where the heating time ta of the first flash heating is 5 milliseconds. Outside the dotted frame, triangles indicate the case where the heating time of one-stage flash heating is 10 milliseconds, and circles indicate the case where the heating time of one-stage flash heating is 5 milliseconds.

[0089] Regardless of whether the heating time of the flash heating is 5 milliseconds or 10 milliseconds, as the maximum temperature reached on the surface of the semiconductor wafer W (i.e., the hafnium oxide-based film 103) during flash heating increases, the hafnium oxide-based film 103 tends to enter a metastable phase, and the remanent polarization of the hafnium oxide-based film 103 tends to increase. This is believed to be due to the fact that as the maximum temperature reached in flash heating increases, the size of the crystal grains in the hafnium oxide-based film 103 increases. However, as the maximum temperature reached by the hafnium oxide-based film 103 reaches 900° C. or higher, the value of the remanent polarization tends to saturate.

[0090] In any case, as shown in Fig. 13, by irradiating the surface of the semiconductor wafer W on which the hafnium oxide-based film 103 is formed with a flash light and heating the surface for 1 second or less, the crystal grain size of the hafnium oxide-based film 103 can be increased and the polarization characteristics can be improved while minimizing the increase in the amount of heat given to the semiconductor wafer W, and as a result, good ferroelectricity can be obtained. Therefore, there is no risk of applying a large heat load to wiring and transistors formed before the formation of the hafnium oxide-based film 103, which would deteriorate their characteristics. In particular, by performing two-stage flash heating, good ferroelectricity can be expressed by the hafnium oxide-based film 103. Also, Fig. 13 shows the polarization characteristics of the hafnium oxide-based film 103 with a thickness of 5 nm, and good ferroelectricity can be expressed even in such a thin hafnium oxide-based film 103 by flash heating. In addition, in the hafnium oxide base film 103 having a thickness of 5 nm shown in FIG. 13, ferroelectricity is obtained at a maximum temperature of 800° C. or higher, but in the case of a film thickness of 10 nm, the polarization characteristics are improved and ferroelectricity can be obtained at a maximum temperature of 600° C. or higher.

[0091] Although the embodiment of the present invention has been described above, various modifications can be made to the present invention without departing from the spirit of the present invention. For example, in the above embodiment, two stages of flash heating are performed, but three or more stages of flash heating may be performed. In this case, the temperature rise rate is increased in the later stages of flash heating. In this way, the amount of heat given to the surface of the semiconductor wafer W can be reduced compared to one stage of flash heating, and the temperature drop rate of the semiconductor wafer W after heating can be increased to exhibit better ferroelectricity.

[0092] In the above embodiment, the flash lamps FL irradiate the surface of the semiconductor wafer W with flash light to heat the surface for 1 second or less, and millisecond annealing is performed. However, the millisecond annealing is not limited to flash lamp annealing, and may be laser annealing. Laser annealing is a heat treatment technique in which a laser is irradiated onto the surface of the semiconductor wafer W to heat the surface for 1 second or less. As in the above embodiment, millisecond annealing using laser annealing can also cause the hafnium oxide-based film 103 to exhibit good ferroelectricity while suppressing an increase in the amount of heat given to the semiconductor wafer W.

[0093] Furthermore, the thin film formed on the semiconductor wafer W is not limited to the hafnium oxide-based film 103, but may be any thin film that exhibits ferroelectricity when in a metastable phase. Examples of such thin films include thin films based on barium titanate (BaTiO3) in addition to hafnium oxide.

[0094] In the above embodiment, the flash heating unit 5 is provided with 30 flash lamps FL, but this is not limited to this and the number of flash lamps FL can be any number. The flash lamps FL are not limited to xenon flash lamps and may be krypton flash lamps. The number of halogen lamps HL provided in the halogen heating unit 4 is not limited to 40 and can be any number.

[0095] In the above embodiment, the semiconductor wafer W is preheated using a filament-type halogen lamp HL as a continuously lit lamp that emits light continuously for one second or more. However, this is not limited to this, and preheating may be performed using a discharge-type arc lamp (e.g., a xenon arc lamp) or an LED lamp as a continuously lit lamp instead of the halogen lamp HL. [Industrial Applicability]

[0096] The technique according to the present invention can be suitably applied to the manufacture of ferroelectric random access memory (FeRAM) using hafnium oxide-based materials. [Explanation of symbols]

[0097] 1 Heat treatment equipment 3. Control Unit 4 Halogen heating section 5 Flash heating section 6 Chambers 7 Holding part 10 Transfer mechanism 20 Lower radiation thermometer 25 Upper radiation thermometer 31 Pulse Generator 32 Waveform setting section 33 Input section 63 Upper chamber window 64 Lower chamber window 65 Heat Treatment Space 74 Susceptor 93 Capacitor 96 IGBT 103 Hafnium oxide based film FL Flash lamp HL Halogen Lamp W Semiconductor wafer

Claims

1. A heat treatment method for heating a substrate on which a thin film that exhibits ferroelectricity when in a metastable phase is formed by irradiating the substrate with light, the method comprising the steps of: A heat treatment method comprising a millisecond annealing step of irradiating a surface of the substrate with light to heat the surface.

2. The heat treatment method according to claim 1, The millisecond annealing step comprises: a first annealing step of heating the surface of the substrate to a first temperature at a first heating rate; a second annealing step of heating the surface of the substrate at a second heating rate higher than the first heating rate to a second temperature higher than the first temperature, following the first annealing step; A heat treatment method comprising:

3. The heat treatment method according to claim 2, A heat treatment method in which a heating time in the first annealing step is longer than a heating time in the second annealing step.

4. The heat treatment method according to claim 3, The heating time of the first annealing step is 3 milliseconds or more; The heat treatment method, wherein the heating time of the second annealing step is 2 milliseconds or less.

5. The heat treatment method according to claim 2, The first temperature is equal to or higher than 400° C. and equal to or lower than 900° C. The heat treatment method, wherein the second temperature is 600° C. or more and 1200° C. or less.

6. The heat treatment method according to claim 2, In the first annealing step and the second annealing step, the surface of the substrate is heated by irradiating the surface with flash light from a flash lamp.

7. The heat treatment method according to claim 6, The heat treatment method further comprises a preheating step of heating the substrate to 100° C. or more and 400° C. or less by light irradiation from a continuously lit lamp before the first annealing step.

8. The heat treatment method according to claim 2, The method further includes a temperature reducing step of reducing the temperature of the substrate after the second annealing step, A heat treatment method, wherein the temperature lowering rate in the temperature lowering step is 20% or more higher than the temperature lowering rate when the surface of the substrate is heated to the second temperature in one step.

9. The heat treatment method according to any one of claims 1 to 8, The heat treatment method, wherein the thin film is a hafnium oxide-based film containing hafnium oxide as a main component.

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