Method for manufacturing semiconductor element from wafer with selective application of edge insulation
Patent Information
- Application Number
- JP2024131049
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2023-08-11
- Filing Date
- 2024-08-07
- Publication Date
- 2025-02-25
Smart Images
Figure 2025026802000001_ABST
Abstract
Description
[Technical field]
[0001] The present invention relates to a method for manufacturing semiconductor devices from a wafer, in which selective application of edge insulation of semiconductor devices or power electronics is performed by an additive manufacturing process. [Background technology]
[0002] It is generally known that power semiconductors can be produced on a large scale using known production methods by clean room or microsystem techniques on so-called wafer substrates. To produce power semiconductors or semiconductor chips, wafers of material such as silicon (Si) or silicon carbide, typically having a diameter of, for example, 150 mm, 200 mm or 300 mm, are processed in several individual steps.
[0003] Power semiconductors or chips processed on wafers require an insulator at the edge in the area of the sawing edge provided for separation, the so-called edge insulator, to protect against electrical flashover. This further serves as a seal of the wafer against grinding fluids during backside thinning. Furthermore, the insulator passivates the edge area of the chip and protects it from contamination or moisture over the chip's lifetime. The material for the edge insulator is usually applied by means of spin coating and developed by an exposure process with UV light. This lithographic coating and structuring process takes place in semiconductor manufacturing in the so-called BEOL (Back-End-Of-Line).
[0004] The disadvantage of the known method is that several process steps are required and only a portion of the applied material is ultimately needed, which makes the process cost- and resource-intensive. Furthermore, the edge insulator is applied to the entire wafer and thus also to semiconductor chips that turn out to be defective during wafer testing in the later back-end process. Due to the manufacturing complexity, such defective semiconductor chips occupy a significant portion of the chips on the wafer. Furthermore, depending on the product, different layer thicknesses of, for example, 5 μm and 12 μm are required for the insulator, and separate equipment must be provided during manufacturing, including spin coaters, exposure devices, cleaning devices for the different layer thicknesses. Also, due to the inaccuracy of the alignment at the wafer edge, the process cannot be carried out all the way to the edge, which results in loss of wafer area and therefore fewer chips per wafer. Summary of the Invention
[0005] The present invention relates to a method for manufacturing a plurality of semiconductor devices, in particular power semiconductor devices, from a wafer, comprising the steps of: Providing a wafer substrate; treating the structured wafer surface; applying edge insulation onto the wafer surface; Separating the wafer into individual semiconductor devices; A method comprising: According to the invention, the edge insulation is applied to the wafer surface as a printed electrical insulator using digital printing techniques. It concerns the method.
[0006] Advantageous developments of the method according to the invention for producing a plurality of semiconductor components from a wafer are set forth in the dependent claims.
[0007] The inventive configuration of the edge insulation as a printed electrical insulator, in addition to a significant saving of material and resources, in particular a minimization of chemical waste, also offers the advantage of an easier process control compared to methods known from the prior art. Thus, the production of various layer geometries and / or layer thicknesses is possible in one facility and can be selected individually for each incoming wafer. Thanks to the printing technique, changes in chip size and layout can be introduced and adapted quickly and simply. Furthermore, no complex and costly mask changes and the introduction of new masks are necessary. Furthermore, the processing or application of the edge insulation can be realized over the entire wafer surface with consistent precision.
[0008] Preferably, the edge insulation is selectively applied to predefined areas of the wafer surface, in particular to the area of the sawing edge of the wafer provided for the separation of the individual semiconductor components or chips, where the edge insulation is preferably applied to the wafer surface according to a predefined layout, which allows selective and precise application of the edge insulation while reducing material consumption compared to the prior art.
[0009] The application of the edge insulation preferably involves the application of an organic or inorganic ink, after which the ink is cured. The ink preferably consists of a photosensitive material composition, in particular a polymer mixture, which can be cured by irradiation with UV light or a suitable energy and / or heat source.
[0010] Here, the application or coating of the ink can be carried out in a manner known per se by means of a corresponding print head which is movably arranged relative to the wafer surface or to a work surface supporting the wafer, whereby the application of the ink can be carried out layer by layer from nozzles of the print head provided for this purpose, and each applied layer can be cured immediately or periodically.
[0011] In a preferred embodiment, the application of the edge insulation comprises the application of at least one layer having a layer thickness of 5 to 30 μm. To achieve or apply edge insulation with greater layer thicknesses, repeated material applications can be carried out. Here, the application of the edge insulation may in particular comprise the application of several layers, which are applied one on top of the other on the wafer surface, preferably each with a subsequent curing.
[0012] Advantageously, the method may comprise a levelling step after application of the edge insulation, in which a defined, preferably uniform layer thickness of the edge insulation is created or achieved on the wafer surface, for example by means of a squeegee, in which, in particular, excess ink can be removed or the surface of the applied layer can be smoothed.
[0013] After application of the edge insulation is complete, an optional additional step can be a final cure with UV light or a suitable heat treatment to ensure complete cure and fixation of the edge insulation material.
[0014] The step of applying edge insulation on the wafer surface is preferably performed prior to a backside thinning process of the wafer, in which the wafer is reduced from its original wafer thickness to a component thickness desired or required for subsequent use of the semiconductor device or chip. Depending on the particular requirements of the manufacturing process and the desired thickness of the wafer, this can be done, for example, by polishing, chemical mechanical polishing (CMP), or etching.
[0015] The step of applying the edge insulation is alternatively carried out together with the application of a wafer support (so-called carrier wafer), in particular together with the application of a print wafer support (or print carrier wafer), which serves to support and protect the wafer during handling and further process steps. Here, the print wafer support can likewise be applied using digital printing techniques.
[0016] Here, preferably, first the edge insulation is applied in a first process step, and then the printing wafer support is applied. Advantageously, a support layer or support material can now be applied in the areas where the edge insulation is not applied or printed. The support layer or support material can be applied with a layer thickness equal to the layer thickness of the edge insulation and / or can be configured such that its surface lies in the same plane as the surface of the edge insulation. Here, the support layer can likewise be applied using digital printing techniques.
[0017] Further alternatively, the step of applying edge insulation can be performed after a backside thinning process and an electrical wafer test in which the functionality and quality of the wafer is inspected, after which the wafer is further processed and cut or singulated into individual semiconductor devices or chips. Typically, the wafer test is performed after the BEOL process in which the circuits and connections are made on the wafer, and here consists of a series of electrical and functional tests to ensure that the wafer functions properly and corresponds to a given specification. The edge insulation is preferably applied only, i.e. exclusively, to semiconductor devices that are determined to function well in the wafer test or that correspond to a given specification. This can further significantly reduce the use of material.
[0018] Furthermore, the invention relates to a semiconductor component, in particular a power semiconductor component, produced or producible according to the method described above, the semiconductor component having an edge insulation formed by a printed electrical insulator, in particular the edge insulation being applied by means of digital printing techniques or additive manufacturing methods.
[0019] To avoid repetition, reference is now made to the above description of the method according to the invention, which is considered to be likewise disclosed and claimable with respect to the device according to the invention.
[0020] Further advantages and details of the invention will become apparent from the following description of preferred embodiments of the invention and from the drawings, which are shown only diagrammatically. [Brief description of the drawings]
[0021] [Figure 1] 1A is a plan view of a structured top surface of a wafer with multiple wafer cells for subsequent separation into semiconductor devices, (b) is a detailed view of (a) with multiple wafer cells arranged adjacently, and (c) is a detailed view of (b) of a wafer cell of the wafer before singulation or a semiconductor device according to the invention with edge insulation applied. [Figure 2a] 1A-1D are cross-sectional views of wafer cells or functional blocks of a wafer to illustrate individual method steps of a preferred embodiment of the method according to the invention; [Figure 2b] 1A-1D are cross-sectional views of wafer cells or functional blocks of a wafer to illustrate individual method steps of a preferred embodiment of the method according to the invention; [Figure 2c] 1A-1D are cross-sectional views of wafer cells or functional blocks of a wafer to illustrate individual method steps of a preferred embodiment of the method according to the invention; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0022] In the figures, identical elements or elements having identical functions are provided with the same reference numbers.
[0023] In FIG. 1(a), a wafer 100 is shown in a perspective plan view, with a top surface 101 on which are arranged or structured a number of wafer cells or functional blocks 102a, b, c which will later form semiconductor devices or chips.
[0024] As shown in Figures 1(b) and 1(c), an edge insulation 103 is applied or printed on the wafer top surface 101, which isolates the individual chips 102a, 102b, 102c from each other and protects them from external influences, in particular preventing undesired electrical interactions or short circuits between the chips 102a, 102b, 102c.
[0025] Here, edge insulation 103 is selectively applied or deposited using the method according to the invention in predefined areas of the wafer top surface 101 including in particular the area of the sawing edge 106 of the wafer 100 provided for the separation of the individual chips. The edge insulation 103 is formed by an electrical insulator printed using digital printing techniques.
[0026] Here, the edge insulation 103 can be applied to the wafer surface 101 before the backside thinning process of the wafer. Alternatively to this, the edge insulation 103 can be applied after the backside thinning process, and in particular after electrical wafer testing. Here, preferably, the selective application of the edge insulation 103 is only performed on those wafer cells or chips 102a, 102b, 102c that are determined to function well or meet a given specification in the wafer testing.
[0027] 2a-c show method steps of a further preferred embodiment of the method according to the invention, in which the application of an edge insulation 103 takes place together with a wafer support 107, in particular a printing wafer support.
[0028] As shown in Fig. 2a, first a wafer substrate 108, for example made of silicon (Si), silicon carbide (SiC) or gallium nitride (GaN), is prepared as a basis for processing semiconductor elements that may be formed on the wafer. In a manner known per se, desired layers and structures 104 or layers and structures 104 given in a process are then formed on the wafer substrate surface 108a in order to produce semiconductor elements such as transistors, diodes or integrated circuits.
[0029] As shown in FIG. 2b, the next step is the application of an edge insulation 103 to the surface 105 of the treated or structured wafer 100. Here, preferably, the edge insulation 103 is applied as an organic or inorganic ink only in predetermined areas of the surface using a corresponding printhead. In particular, here, the edge insulation 103 is applied in the area of the sawing edge 106 of the wafer 100, which is provided for separating the individual semiconductor elements or semiconductor chips. Here, the edge insulation 103 is applied to the wafer surface in particular in a layer, preferably with a layer thickness of 5 to 30 μm, and is subsequently cured by irradiation with UV light or a suitable energy and / or heat source. To achieve greater layer thicknesses, several layers can also be applied one on top of the other and each subsequently cured.
[0030] In order to achieve a uniform surface for the subsequent application of the printing wafer support 107, a support layer 109 is preferably applied to the wafer surface 105 in addition to the edge insulation 103. The support layer 109 is applied in particular to those areas of the wafer where the wafer support 107 is to be applied and where the edge insulation 103 has not yet been applied. Here, the support layer is preferably applied to the wafer surface 105 and the formed semiconductor structures 104 such that its surface 109a lies flush with the surface 103a of the edge insulation 103. The support layer 109 is preferably applied using digital printing techniques as well.
[0031] As shown in Fig. 2c, in a further step the application of a printed wafer support 107 takes place on the edge insulation 103 and on the areas provided for this on the surface of the support layer 109. The wafer support 107 is also applied in a manner known per se using digital printing techniques.
[0032] In a subsequent manufacturing step (not shown), separation or singulation of the wafer 100 is performed by separating the semiconductor elements 102a, 102b, 102c with a provided sawing edge 106. [Explanation of symbols]
[0033] 100 wafers 101 Wafer top surface 102a, 102b, 102c Semiconductor elements 103 Edge Insulation 104 Layers and Structure 105 Wafer surface 106 Sewing Edge 107 Wafer support 108 Wafer Substrate 108a Wafer substrate surface 109 Supporters 109a Surface of supporting layer
Claims
1. A method for manufacturing a plurality of semiconductor devices, in particular power semiconductor devices, from a wafer (100), comprising the steps of: Providing a wafer substrate (108); - treating the structured wafer surface (105); applying an edge insulation (103) onto said wafer surface (105); separating the wafer (100) into individual semiconductor devices (102a, 102b, 102c); In a method comprising: The edge insulation (103) is applied to the wafer surface (105) as a printed electrical insulator using digital printing techniques. A method comprising:
2. The edge insulation (103) is selectively applied to predetermined areas of the sawing edge (106) of the wafer (100) that are prepared for separation.
2. The method of claim 1 .
3. The application of the edge insulation (103) comprises the application of an organic or inorganic ink followed by curing.
3. The method according to claim 1 or 2.
4. The application of the edge insulation (103) comprises the application of at least one layer having a layer thickness of 5 to 30 μm.
4. The method according to claim 1, wherein the first and second electrodes are arranged in a first direction.
5. The application of the edge insulation (103) includes the application of multiple layers, the layers being applied one on top of the other on the wafer surface (105), preferably each with a subsequent curing.
5. The method according to claim 1, wherein the first and second electrodes are arranged in a first direction.
6. The method includes a leveling step, in which a uniform layer thickness of the edge insulation (103) is produced on the wafer surface (105).
6. The method according to claim 1, wherein the first and second electrodes are arranged in a first direction.
7. The application of the edge insulation (103) onto the wafer surface (105) is performed prior to a backside thinning process of the wafer.
7. The method according to any one of claims 1 to 6.
8. The application of the edge insulation (103) onto the wafer surface (105) is performed after a backside thinning process and electrical wafer testing.
7. The method according to any one of claims 1 to 6.
9. The application of the edge insulation (103) onto the wafer surface (105) is performed together with the application of a wafer support (107), in particular together with the application of a print wafer support.
7. The method according to any one of claims 1 to 6.
10. In particular, a semiconductor component manufactured according to the method of any one of claims 1 to 9, having edge insulation (103) formed by printed electrical insulation A semiconductor element (102a, 102b, 102c).