Electronic device and method for manufacturing the same

Abstract

To achieve good bonding between a functional part and a substrate even if warping occurs in the functional part.SOLUTION: An electronic device (10) includes: a functional part (102); a substrate (130) which supports the functional part (102); a first metal film (110) which is formed on the substrate (130) side of the functional part (102) and serves as an electrode; and a second metal film (140) which is formed on the substrate (130) and to which the first metal film (110) is bonded. The functional part (102) has a first surface (102a) that faces the substrate (130) with the first metal film (110) interposed therebetween, and a second surface (102b) that extends from the first surface (102a) in a direction different from the extending direction of the first surface (102a). The first metal film (110) is formed from the first surface (102a) to a portion of the second surface (102b) of the functional unit (102).SELECTED DRAWING: Figure 7

Description

[Technical field]

[0001] The present disclosure relates to electronic devices and methods for manufacturing the same. [Background technology]

[0002] There is known a technique in which a functional portion (functional layer) such as a piezoelectric element layer or a semiconductor layer is grown on a growth substrate, and then the functional portion (functional layer) is peeled off from the growth substrate and bonded to another substrate (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2022-152676 A (see abstract) Summary of the Invention [Problem to be solved by the invention]

[0004] In the above-mentioned conventional techniques, when warping occurs in the functional portion, there is a possibility that the functional portion cannot be joined satisfactorily to the substrate.

[0005] An object of the present disclosure is to enable a functional portion to be satisfactorily joined to a substrate even when the functional portion is warped. [Means for solving the problem]

[0006] The electronic device of the present disclosure has a functional unit, a substrate supporting the functional unit, a first metal film as an electrode formed on the substrate side of the functional unit, and a second metal film formed on the substrate and to which the first metal film is bonded. The functional unit has a first surface facing the substrate via the first metal film, and a second surface extending from the first surface in a direction different from the extending direction of the first surface. The first metal film is formed from the first surface to a part of the second surface of the functional unit.

[0007] The method for manufacturing an electronic device disclosed herein includes forming a first metal film on a first surface and a part of a second surface in a functional portion having a first surface and a second surface extending from the first surface in a direction different from the extension direction of the first surface, and bonding the first metal film formed on the functional portion to a second metal film formed on a substrate. Effect of the Invention

[0008] According to the present disclosure, even if warping occurs in the functional part, the functional part can be satisfactorily bonded to the substrate by bonding a first metal film formed on the functional part to a second metal film formed on the substrate. [Brief description of the drawings]

[0009] [Figure 1] FIG. 1A is a cross-sectional view showing a growth substrate used in the manufacturing method of an electronic device of embodiment 1, FIG. 1B is a cross-sectional view showing a step of forming a functional layer on the growth substrate, and FIG. 1C is a cross-sectional view showing a step of patterning the growth substrate and the functional layer. [Diagram 2] 5A and 5B are cross-sectional views showing a step of etching a growth substrate in the method for manufacturing the electronic device according to the first embodiment, and FIG. 5C is a cross-sectional view showing another example of the etching step. [Diagram 3] 4A is a cross-sectional view showing a step of separating a functional layer from a growth substrate, and FIG. 4B is a cross-sectional view showing a step of forming a first metal film on the functional layer, in the method for manufacturing the electronic device according to the first embodiment. [Figure 4] FIG. 1 shows an enlarged cross-sectional view (A) of a functional layer and a first metal film in a manufacturing method for an electronic device of embodiment 1, and a schematic diagram (B) showing the angle between the first and second surfaces of the functional layer. [Diagram 5] 4A is a cross-sectional view showing a step of transferring a functional layer to a device substrate in the method for manufacturing the electronic device according to the first embodiment, and FIG. 4B is an enlarged cross-sectional view showing a second metal film on the device substrate. [Figure 6]4A is a cross-sectional view showing a step of bonding metal films of a functional layer and a device substrate, and FIG. 4B is a cross-sectional view showing a step of forming an electrode layer on the functional layer, in the method for manufacturing the electronic device of the first embodiment. [Figure 7] Schematic diagrams (A) and (B) showing the state in which peeling of the functional layer occurs in a comparative example, and schematic diagrams (C) and (D) showing the effect of suppressing peeling of the functional layer in embodiment 1. [Figure 8] FIG. 13A is a cross-sectional view showing a growth substrate used in a manufacturing method for an electronic device of embodiment 2; FIG. 13B is a cross-sectional view showing a process of forming a buffer layer and a functional part on the growth substrate; and FIG. 13C is a cross-sectional view showing a process of patterning the growth substrate, the buffer layer, and the functional part. [Figure 9] 13A is a cross-sectional view showing a step of forming a Schottky electrode and a photoresist on a functional portion, and FIG. 13B is a cross-sectional view showing a step of patterning the Schottky electrode in a manufacturing method for an electronic device according to a second embodiment. [Figure 10] 13A is a cross-sectional view showing a step of etching a growth substrate, and FIG. 13B is a cross-sectional view showing a step of separating a functional portion from the growth substrate, in the method for manufacturing an electronic device according to the second embodiment. [Figure 11] 13A is a cross-sectional view showing a step of removing a buffer layer, and FIG. 13B is a cross-sectional view showing a step of forming a first metal film on the n+GaN layer of the functional portion, in the method for manufacturing an electronic device according to the second embodiment. [Figure 12] 11A to 11E are cross-sectional views illustrating a step of forming a first metal film in a method for manufacturing an electronic device according to a second embodiment. [Figure 13] 13A is a cross-sectional view showing a step of transferring a functional section to a device substrate in a manufacturing method for an electronic device according to a second embodiment, and FIG. 13B is an enlarged cross-sectional view showing a second metal film on the device substrate. [Figure 14] FIG. 11 is a cross-sectional view (A) showing a step of bonding metal films of a functional section and a device substrate in a manufacturing method for an electronic device of embodiment 2, and a cross-sectional view (B) showing a step of forming an insulating layer and a wiring layer on the functional section. [Figure 15]FIG. 11 is a cross-sectional view (A) showing a step of forming a buffer layer and a functional section on a growth substrate in a manufacturing method for an electronic device of embodiment 3, and a cross-sectional view (B) showing a step of patterning the growth substrate, the buffer layer, and the functional section. [Figure 16] 13A is a cross-sectional view showing a step of etching a growth substrate, and FIG. 13B is a cross-sectional view showing a step of separating a functional portion from the growth substrate, in a manufacturing method for an electronic device according to a third embodiment. [Figure 17] FIG. 11 is a cross-sectional view (A) showing a step of removing a buffer layer in a manufacturing method for an electronic device of embodiment 3, a cross-sectional view (B) showing a step of forming a first metal film on a functional section, and a cross-sectional view (C) showing an enlarged view of the first metal film. [Figure 18] 13A is a cross-sectional view showing a step of transferring a functional section to a device substrate in a manufacturing method for an electronic device according to a third embodiment, and FIG. 13B is an enlarged cross-sectional view showing a second metal film on the device substrate. [Figure 19] 13A is a cross-sectional view showing a step of bonding metal films of a functional section and a device substrate, and FIG. 13B is a cross-sectional view showing a step of forming a p-electrode and an n-electrode, in a manufacturing method for an electronic device according to a third embodiment. [Figure 20] FIG. 13 is a cross-sectional view (A) showing a step of forming a buffer layer and a functional section on a growth substrate in a manufacturing method for an electronic device of embodiment 4, and a cross-sectional view (B) showing a step of patterning the growth substrate, the buffer layer, and the functional section. [Figure 21] 13A is a cross-sectional view showing a step of etching a growth substrate, and FIG. 13B is a cross-sectional view showing a step of separating a functional portion from the growth substrate, in a manufacturing method for an electronic device according to a fourth embodiment. [Figure 22] FIG. 13 is a cross-sectional view (A) showing a step of removing a buffer layer in a manufacturing method for an electronic device of embodiment 4, a cross-sectional view (B) showing a step of forming a first metal film on a functional section, and a cross-sectional view (C) showing an enlarged view of the first metal film. [Diagram 23] 13A to 13H are cross-sectional views illustrating another example of the step of forming a first metal film in the method for manufacturing an electronic device according to the fourth embodiment. [Figure 24] 13A is a cross-sectional view showing a step of transferring a functional section to a device substrate in a method for manufacturing an electronic device according to a fourth embodiment, and FIG. 13B is a cross-sectional view showing an enlarged view of a second metal film on the device substrate. [Diagram 25] 13A is a cross-sectional view showing a step of bonding metal films of a functional section and a device substrate, and FIG. 13B is a cross-sectional view showing a step of forming an oxide film on the functional section, in a manufacturing method for an electronic device according to embodiment 4. [Figure 26] 13A is a cross-sectional view showing a step of forming an opening in an oxide film, and FIG. 13B is a cross-sectional view showing a step of forming a trench in a functional portion in a manufacturing method for an electronic device according to a fourth embodiment. [Figure 27] 13A is a cross-sectional view showing a step of forming an oxide film and a photoresist in a trench, and FIG. 13B is a cross-sectional view showing a step of forming an opening in the photoresist in a manufacturing method for an electronic device in accordance with a fourth embodiment. [Figure 28] 13A is a cross-sectional view showing a step of exposing a pGaN layer in a functional portion, and FIG. 13B is a cross-sectional view showing a step of forming an opening in a photoresist, in a manufacturing method for an electronic device according to a fourth embodiment. [Figure 29] 13A is a cross-sectional view showing a step of forming a source electrode and a gate electrode, and FIG. 13B is a cross-sectional view showing a step of removing a photoresist in a manufacturing method for an electronic device in accordance with a fourth embodiment. [Diagram 30] FIG. 13 is a cross-sectional view (A) showing a step of forming a buffer layer and a functional section on a growth substrate in a manufacturing method for an electronic device of embodiment 5, and a cross-sectional view (B) showing a step of patterning the growth substrate, the buffer layer, and the functional section. [Diagram 31] 13A is a cross-sectional view showing a step of forming a photoresist on a functional portion, and FIG. 13B is a cross-sectional view showing a step of forming a trench in the functional portion, in the method for manufacturing an electronic device according to the fifth embodiment. [Diagram 32]13 is a cross-sectional view showing a step (A) of forming an oxide film and a photoresist in a trench, and a cross-sectional view (B) of etching a growth substrate in a manufacturing method for an electronic device according to a fifth embodiment. FIG. [Diagram 33] 13A is a cross-sectional view showing a step of separating a functional portion from a growth substrate, and FIG. 13B is a cross-sectional view showing a step of removing a buffer layer in a manufacturing method for an electronic device according to a fifth embodiment. [Diagram 34] 13A is a cross-sectional view showing a step of forming a first metal film on a functional section, and FIGS. 13A and 13B are cross-sectional views showing a step of transferring the functional section to a device substrate in a manufacturing method for an electronic device according to a fifth embodiment. [Diagram 35] 23A is a cross-sectional view showing a step of forming a buffer layer and a functional portion on a growth substrate, and FIG. 23B is a cross-sectional view showing a first patterning step for the functional portion in the method for manufacturing an electronic device in accordance with the sixth embodiment. [Diagram 36] 23A is a cross-sectional view showing a second stage of a second patterning step for a growth substrate, a buffer layer and a functional section in a manufacturing method for an electronic device according to the sixth embodiment, and FIG. 23B is a cross-sectional view showing a step of etching the growth substrate. [Figure 37] 13A is a cross-sectional view showing a step of separating a functional portion from a growth substrate, and FIG. 13B is a cross-sectional view showing a step of removing a buffer layer in a manufacturing method for an electronic device according to a sixth embodiment. [Figure 38] 13A is a cross-sectional view showing a step of forming a first metal film on a functional portion in a manufacturing method for an electronic device according to a sixth embodiment, and FIG. 13B is an enlarged cross-sectional view showing the first metal film. [Figure 39] 20A is a cross-sectional view showing a step of transferring a functional section to a device substrate in a manufacturing method for an electronic device according to a sixth embodiment, and FIG. 20B is an enlarged view of a second metal film on the device substrate. [Diagram 40] 13A is a cross-sectional view showing a step of bonding metal films of a functional section and a device substrate, and FIG. 13B is a cross-sectional view showing a step of forming an oxide film on the functional section, in a manufacturing method for an electronic device according to a sixth embodiment. [Diagram 41]23A is a cross-sectional view showing a step of forming an opening in an oxide film, and FIG. 23B is a cross-sectional view showing a step of forming a trench in a functional portion in a manufacturing method for an electronic device according to a sixth embodiment. [Diagram 42] 23A is a cross-sectional view showing a step of forming an oxide film and a photoresist in a trench, and FIG. 23B is a cross-sectional view showing a step of forming an opening in the photoresist in a manufacturing method for an electronic device according to a sixth embodiment. [Diagram 43] 13A is a cross-sectional view showing a step of exposing a pGaN layer in a functional portion, and FIG. 13B is a cross-sectional view showing a step of forming an opening in a photoresist, in a manufacturing method for an electronic device according to a sixth embodiment. [Diagram 44] 23A is a cross-sectional view showing a step of forming a source electrode and a gate electrode, and FIG. 23B is a cross-sectional view showing a step of removing a photoresist in a manufacturing method for an electronic device in accordance with a sixth embodiment. [Diagram 45] FIG. 13 is a cross-sectional view (A) showing a step of forming a buffer layer and a functional section on a growth substrate in a manufacturing method for an electronic device of embodiment 7, and a cross-sectional view (B) showing a step of patterning the growth substrate, the buffer layer, and the functional section. [Figure 46] 13A is a cross-sectional view showing a step of forming an oxide film on a functional portion, and FIG. 13B is a cross-sectional view showing a step of forming a groove in the functional portion, in a manufacturing method for an electronic device according to the seventh embodiment. [Figure 47] 13A is a cross-sectional view showing a step of growing an n-GaN layer in a groove of a functional section, and FIG. 13B is a cross-sectional view showing a step of forming an opening in an insulating film in a manufacturing method for an electronic device according to a seventh embodiment. [Figure 48] 13A is a cross-sectional view showing a step of implanting ions into a p-GaN layer of a functional section, and FIG. 13B is a cross-sectional view showing a step of forming an oxide film on the functional section, in a manufacturing method for an electronic device according to a seventh embodiment. [Figure 49] 13A is a cross-sectional view showing a step of etching a growth substrate, and FIG. 13B is a cross-sectional view showing a step of separating a functional portion from the growth substrate, in a manufacturing method for an electronic device according to a seventh embodiment. [Figure 50]FIG. 13 is a cross-sectional view (A) showing a step of removing a buffer layer in a manufacturing method for an electronic device of embodiment 7, a cross-sectional view (B) showing a step of forming a first metal film in a functional section, and a cross-sectional view (C) showing an enlarged view of the first metal film. [Figure 51] 13A is a cross-sectional view showing a step of transferring a functional section to a device substrate in a manufacturing method for an electronic device according to a seventh embodiment, and FIG. 13B is a cross-sectional view showing an enlarged view of a second metal film on the device substrate. [Figure 52] 13A is a cross-sectional view showing a step of forming an insulating film in a functional section, and FIG. 13B is a cross-sectional view showing a step of patterning the insulating film, in a manufacturing method for an electronic device according to a seventh embodiment. [Diagram 53] 13 is a cross-sectional view showing a step of forming a source electrode and a gate electrode in a manufacturing method of an electronic device according to a seventh embodiment. FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Hereinafter, an electronic device and a manufacturing method thereof according to an embodiment will be described with reference to the drawings. The electronic device is, for example, a piezoelectric device, a photoelectric conversion device, a semiconductor device, etc. The photoelectric conversion device is, for example, an LED (light emitting diode) device, etc. The semiconductor device is, for example, a Schottky barrier diode, a field effect transistor, etc.

[0011] First Embodiment The first embodiment relates to an electronic device 10 as an AlN piezoelectric device and a method for manufacturing the same.

[0012] Fig. 1(A) is a cross-sectional view showing a growth substrate 101 as a first substrate used in the manufacturing method of an electronic device according to the first embodiment. The growth substrate 101 shown in Fig. 1(A) is, for example, a Si(111) substrate. Note that the growth substrate 101 is not limited to Si(111) and may be any substrate on which a functional layer 102, which will be described next, can be grown.

[0013] In the following description, the surface of growth substrate 101 (the upper surface in FIG. 1(A)) is used as a reference, and the stacking direction of each layer stacked on this surface is the upward direction.

[0014] Fig. 1(B) is a cross-sectional view showing a step of forming the functional layer 102. As shown in Fig. 1(B), the functional layer 102, which is an AlN (aluminum nitride) layer, is epitaxially grown on the surface of the growth substrate 101. The thickness of the functional layer 102 is 2 to 50 µm.

[0015] Fig. 1(C) is a cross-sectional view (C) showing a step of patterning the growth substrate 101 and the functional layer 102. As shown in Fig. 1(C), the growth substrate 101 and the functional layer 102 are patterned into an element shape. The patterning is performed by forming a photoresist (mask) (not shown) on the functional layer 102 and dry etching.

[0016] Dry etching is performed on the growth substrate 101 until the depth t from the surface reaches 50 to 10,000 nm. The depth t is also called the overetching amount. As a result, a sacrificial layer 101a having approximately the same area as the lower surface of the functional layer 102 is formed on the surface of the growth substrate 101. The dry etching conditions are set so that the side surface of the functional layer 102 becomes an inclined surface.

[0017] 2(A) and (B) are cross-sectional views showing a process of etching the growth substrate 101. As shown in Fig. 2(A), the growth substrate 101 is etched in the surface direction, i.e., in the (100) direction, by wet etching using KOH (potassium hydroxide).

[0018] As the etching progresses, the area of ​​the sacrificial layer 101a of the growth substrate 101 decreases. As shown in Fig. 2(B), the etching is terminated in a state where the sacrificial layer 101a of the growth substrate 101 remains at the center of the lower surface of the functional layer 102. As a result, the functional layer 102 is supported at its center by a part (referred to as a connection portion 101b) of the sacrificial layer 101a of the growth substrate 101.

[0019] Since the connection portion 101b is to be broken in a separation step (FIG. 3(A)) described later, it is desirable that the area W1 of the connection portion 101b be 10% or less of the area of ​​the lower surface of the functional layer .

[0020] 2B, a part of the sacrificial layer 101a of the growth substrate 101 is left as the connection portion 101b, but the sacrificial layer 101a may be completely removed as shown in FIG 2C. In this case, the removal of the sacrificial layer 101a causes the functional layer 102 to drop onto the surface of the growth substrate 101 and be supported on the surface of the growth substrate 101.

[0021] Fig. 3(A) is a cross-sectional view showing a step of separating the functional layer 102 from the growth substrate 101. As shown in Fig. 3(A), a stamp 120 is attached as a holding member to the upper surface of the functional layer 102 (the surface opposite to the growth substrate 101). The stamp 120 is formed of an organic material, and as an example, is formed of an organic resist. It is desirable for the stamp 120 to have an adhesive or tacky surface.

[0022] By moving the stamp 120 in a direction away from the growth substrate 101, the connection portion 101b (FIG. 2(B)) breaks, and the lower surface 102a of the functional layer 102 separates from the surface of the growth substrate 101. In other words, the functional layer 102 separates from the growth substrate 101.

[0023] Here, the a-axis lattice constant L of the Si(111) substrate constituting the growth substrate 101 is 101 The a-axis lattice constant L of AlN constituting the functional layer 102 is 3.89 [Å]. 102 is 3.11[Å]. These lattice constants are L 101 >L 102 This is in a relationship.

[0024] In addition, the thermal expansion coefficient T 101 is 2.4 × 10 -6 ~4.4×10 -6 [ / K]. The thermal expansion coefficient T 102 is 4.3 x 10-6 ~4.8×10 -6 [ / K]. These thermal expansion coefficients are T 102 >T 101 This is in a relationship.

[0025] In the epitaxial growth process described above (FIG. 1(B)), the functional layer 102 grows epitaxially under a tensile stress so that its lattice constant matches that of the growth substrate 101. When the functional layer 102 is subsequently cooled to room temperature, the functional layer 102 shrinks more than the growth substrate 101 due to the difference in thermal expansion, causing the functional layer 102 to warp. The warping of the functional layer 102 becomes evident when the functional layer 102 is separated from the growth substrate 101, as shown in FIG. 3(A).

[0026] Fig. 3(B) is a cross-sectional view showing a step of forming the first metal film 110. As shown in Fig. 3(B), the first metal film 110 is formed on the lower surface 102a of the functional layer 102 (i.e., the surface separated from the growth substrate 101).

[0027] The first metal film 110 is an electrode for the functional layer 102, and is, for example, a single layer of Mo (molybdenum), and is formed by sputtering or vapor deposition. For example, as shown in Fig. 3(A), in a state where the functional layer 102 is separated from the growth substrate 101, metal atoms for forming the first metal film are attached toward the lower surface 102a, so that the first metal film 110 is formed from the lower surface 102a to the side surface 102b. Therefore, the first metal film 110 can be formed without high temperature, and the stress on the functional layer 102 can be reduced.

[0028] The first metal film 110 is not limited to a single layer of Mo, and may be formed of two layers of Mo and Ti (titanium), or may be formed of two layers of Ti and Au (gold). The thickness of the first metal film 110 is, for example, 100 nm to 10 μm.

[0029] Fig. 4(A) is an enlarged view of the portion surrounded by the symbol A in Fig. 3(B). The lower surface 102a of the functional layer 102 is a surface separated from the growth substrate 101. The side surface 102b of the functional layer 102 is a surface extending from the lower surface 102a in a direction different from the extending direction of the lower surface 102a. Here, the side surface 102b of the functional layer is an inclined surface inclined with respect to the lower surface 102a.

[0030] The inclination direction of the functional layer 102 is a direction in which the size of the functional layer 102 in a plane parallel to the lower surface 102a decreases as the distance from the lower surface 102a increases (ie, upward in FIGS. 4(A) and 4(B)).

[0031] The first metal film 110 is formed so as to wrap around from the lower surface 102a to the side surface 102b of the functional layer 102. The first metal film 110 acts to hold the lower surface 102a and the side surface 102b of the functional layer 102. This improves the integrity of the first metal film 110 and the functional layer 102, and prevents peeling of the functional layer 102 (FIGS. 7(A) to (D) described below).

[0032] The first metal film 110 covers the entire bottom surface 102a, but it is sufficient for the first metal film 110 to cover only the portion of the side surface 102b that is close to the bottom surface 102a.

[0033] 4(B) is a schematic diagram showing the angle between the lower surface 102a and the side surface 102b of the functional layer 102. The angle R between the lower surface 102a and the side surface 102b of the functional layer 102 is preferably in the range of 45 to 90 degrees, and more preferably is equal to or greater than 60 degrees and less than 90 degrees.

[0034] If the angle R is greater than 90 degrees, it becomes difficult to obtain the effect of the first metal film 110 gripping the lower surface 102a and the side surface 102b of the functional layer 102. If the angle R is less than 45 degrees, the area of ​​the upper surface of the functional layer 102 becomes smaller than the lower surface 102a, and the device area becomes smaller. Therefore, the angle R is desirably 45 to 90 degrees as described above.

[0035] The angle R can be adjusted by setting the dry etching conditions in the patterning step of Fig. 1(C) such as the type and flow rate of the etching gas, the plasma density, the bias voltage, or the material and thickness of the mask.

[0036] Fig. 5(A) is a cross-sectional view showing a step of transferring the functional layer 102 to the device substrate 130. As shown in Fig. 5(A), the functional layer 102 held by the stamp 120 is transferred to the device substrate 130 as a second substrate. The device substrate 130 is a substrate separate from the growth substrate 101, and is, for example, a Si substrate. However, the device substrate 130 is not limited to Si, and may be, for example, SiC (silicon carbide), glass, etc.

[0037] A second metal film 140 is formed on the surface of the device substrate 130. The second metal film 140 is a multilayer film having a plurality of metal layers. FIG. 5(B) is an enlarged cross-sectional view of the second metal film 140. As shown in FIG. 5(B), the second metal film 140 has, in order from the device substrate 130 side (lower side), a first layer 141 made of Ti, a second layer 142 made of Pt (platinum), and a third layer 143 made of Au.

[0038] The third layer 143 (Au) is a layer that has good bonding with the above-mentioned first metal film 110. The first layer 141 (Ti) is a layer that has high adhesion to the device substrate 130. In addition, the second layer 142 (Pt) is provided between the Au of the third layer 143 and the Ti of the first layer 141 to prevent them from reacting with each other.

[0039] The first layer 141 and the second layer 142 have a thickness of, for example, 100 nm. The third layer 143 has a thickness of, for example, 100 nm to 10 μm. The first layer 141, the second layer 142, and the third layer 143 are formed by sputtering or deposition. These are not formed at high temperatures as in epitaxial growth, so warping is unlikely to occur. The second metal film 140 is not limited to the combination of a Ti layer, a Pt layer, and an Au layer, and other combinations are also possible.

[0040] When transferring the functional layer 102 to the device substrate 130, the first metal film 110 and the second metal film 140 are bonded together by applying a predetermined pressure. Then, the stamp 120 is peeled off from the upper surface of the functional layer 102 and removed.

[0041] Fig. 6(A) is a cross-sectional view showing a process of bonding the metal films 110, 140 of the functional layer 102 and the device substrate 130. As shown in Fig. 6(A), in a state where the first metal film 110 and the second metal film 140 are bonded together, an annealing treatment is performed at 500 to 800 degrees.

[0042] This bonds the first metal film 110 and the second metal film 140. Even if the functional layer 102 is warped, the first metal film 110 and the second metal film 140 are bonded well without any gaps due to the pressure applied during bonding and the subsequent annealing treatment.

[0043] 6(B) is a cross-sectional view showing a step of forming an electrode layer 151 on the functional layer 102. The electrode layer 151 is, for example, Pt, and is formed by sputtering or vapor deposition. By connecting wiring to the electrode layer 151 and the second metal film 140 (third layer 143), respectively, and connecting to a driving circuit or the like, the electronic device 10, which is a piezoelectric device (more specifically, a vertical AlN piezoelectric device), is completed.

[0044] <effect> The operation of the first embodiment will be described. In general, when the functional layer 102 is peeled (separated) from the growth substrate 101 and transferred to the device substrate 130, warping may occur in the functional layer 102 during peeling. Such warping occurs when the functional layer 102 is made of AlN, PZT (lead zirconate titanate), LN (lithium niobate), or LT (lithium tantalate), or when the functional layer 102 is a semiconductor layer other than a piezoelectric element that is based on GaN (gallium nitride) or GaAs (gallium arsenide).

[0045] When a warped functional layer 102 is bonded to the device substrate 130, a gap is generated between the functional layer 102 and the device substrate 130, which results in poor bonding and degradation of electrical characteristics.

[0046] 6A, in the first embodiment, the first metal film 110 formed on the functional layer 102 and the second metal film 140 formed on the device substrate 130 are bonded by pressure and annealing. Therefore, even if the functional layer 102 is warped, the first metal film 110 and the second metal film 140 can be bonded well.

[0047] Furthermore, in the first embodiment, the first metal film 110 is formed so as to wrap around from the lower surface 102a to the side surface 102b of the functional layer 102. The effect of this will be described with reference to Figures 7(A) to (D).

[0048] 7A and 7B are schematic diagrams showing a device substrate 130, a first metal film 110, and a functional layer 102 in a comparative example. In the comparative example, the first metal film 110 covers only the lower surface 102a of the functional layer 102. Residual stress from epitaxial growth remains in the functional layer 102, and acts in a direction that causes warping of the functional layer 102. In the comparative example, warping of the functional layer 102 cannot be suppressed, and there is a possibility that the functional layer 102 will peel off from the first metal film 110, as indicated by the symbol E in FIG. 7B.

[0049] 7(C) and (D) are schematic diagrams showing the device substrate 130, the first metal film 110, and the functional layer 102 in the first embodiment. In the first embodiment, the first metal film 110 is formed so as to wrap around from the lower surface 102a to the side surface 102b of the functional layer 102, and acts to hold the lower surface 102a and the side surface 102b. Therefore, it is possible to suppress warping due to residual stress in the functional layer 102, and it is possible to prevent peeling of the functional layer 102.

[0050] In addition, since the first metal film 110 (Mo) is interposed between the third layer 143 (Au) of the second metal film 140 and the functional layer 102 (AlN), diffusion of Au into the AlN is prevented, and a functional layer 102 with stable characteristics is obtained.

[0051] In particular, since the first metal film 110 wraps around the side surface 102b of the functional layer 102, even if the second metal film 140 is deformed by the annealing treatment, contact between the third layer 143 (Au) and the functional layer 102 (AlN) is prevented, and diffusion of Au into the AlN is more reliably prevented.

[0052] <Advantages of the First Embodiment> As described above, the electronic device 10 of the first embodiment has the functional layer 102 (functional portion), the device substrate 130 as a substrate supporting the functional layer 102, the first metal film 110 as an electrode deposited on the device substrate 130 side of the functional layer 102, and the second metal film 140 formed on the device substrate 130 and bonded to the first metal film 110. The first metal film 110 is deposited from the lower surface (first surface) 102a of the functional layer 102 to a part of the side surface (second surface) 102b.

[0053] In this manner, the first metal film 110 formed on the functional layer 102 and the second metal film 140 formed on the device substrate 130 are bonded to each other, so that even if the functional layer 102 is warped, the functional layer 102 can be well bonded to the device substrate 130. In particular, the first metal film 110 is formed from the lower surface 102a to a part of the side surface 102b of the functional layer 102, so that the integrity of the first metal film 110 and the functional layer 102 can be improved and peeling of the functional layer 102 can be prevented.

[0054] Furthermore, since the side 102b of the functional layer 102 has a slope such that the size of the functional layer 102 in a plane parallel to the bottom surface 102a becomes smaller the further upward (the further away from the bottom surface 102a), the first metal film 110 can act to grip the bottom surface 102a and the side surface 102b of the functional layer 102, thereby enhancing the effect of preventing peeling of the functional layer 102.

[0055] In addition, since the functional layer 102 is a piezoelectric element layer containing AlN, the electronic device 10 can be configured as a piezoelectric device. In addition, since the first metal film 110 is formed on the functional layer 102 (piezoelectric element layer), the functional layer 102 and the second metal film 140 on the device substrate 130 can be electrically connected via the first metal film 110.

[0056] Moreover, the manufacturing method of the electronic device 10 of the first embodiment includes forming a first metal film 110 from a lower surface (first surface) 102a to a part of a side surface (second surface) 102b of a functional layer (functional portion) 102 separated from a growth substrate 101 serving as a first substrate, and bonding the first metal film 110 formed on the functional layer 102 to a second metal film 140 formed on a device substrate 130 serving as a second substrate different from the growth substrate 101. Therefore, even if the functional layer 102 is warped, it is possible to manufacture an electronic device 10 in which the functional layer 102 is well bonded to the device substrate 130.

[0057] Second Embodiment The second embodiment relates to an electronic device 20 as a vertical GaN semiconductor (more specifically, a Schottky barrier diode) and a method for manufacturing the same.

[0058] Fig. 8(A) is a cross-sectional view showing a growth substrate 201 used in the manufacturing method of the electronic device 20 according to the second embodiment. The growth substrate 201 as a first substrate shown in Fig. 8(A) is, for example, a Si(111) substrate. Note that the growth substrate 201 is not limited to Si(111) and may be any substrate on which the functional section 200 described later can be grown.

[0059] Fig. 8(B) is a cross-sectional view showing a step of forming the buffer layer 202 and the functional section 200. As shown in Fig. 8(B), the buffer layer 202, which is an AlN layer, is epitaxially grown on the surface of the growth substrate 201. The buffer layer 202 is a single layer of AlN here, but is not limited thereto, and may be, for example, a laminate of an AlN layer and an AlGaN layer. The thickness of the buffer layer 202 is, for example, 200 nm to 1 µm.

[0060] An n+GaN layer 203 serving as a contact layer is epitaxially grown on the buffer layer 202. The thickness of the n+GaN layer 203 is, for example, 500 nm to 3 μm.

[0061] Furthermore, an n-GaN layer 204 serving as a drift layer is epitaxially grown on the n+GaN layer 203. The thickness of the n-GaN layer 204 is, for example, 500 nm to 20 μm.

[0062] The n+GaN layer 203 and the n-GaN layer 204 constitute a functional portion (semiconductor thin film) 200.

[0063] Fig. 8(C) is a cross-sectional view showing a process of patterning the growth substrate 201, the buffer layer 202, and the functional section 200. As shown in Fig. 8(C), the growth substrate 201, the buffer layer 202, and the functional section 200 are patterned into an element shape. The patterning is performed by forming a photoresist (not shown) on the n-GaN layer 204 and dry etching it.

[0064] Dry etching is performed until the depth (overetching amount) t from the surface of the growth substrate 201 reaches 50 to 10,000 nm. As a result, a sacrificial layer 201a having approximately the same area as the lower surface of the buffer layer 202 is formed on the surface of the growth substrate 201.

[0065] The dry etching conditions are set so that the side surface of the functional part 200 is an inclined surface, as described in the first embodiment. The inclination direction of the functional part 200 is a direction in which the size of the functional part 200 in a plane parallel to the lower surface (lower surface 203a described later) of the functional part 200 decreases toward the upper side (the further away from the lower surface). Here, a case where the side surface of the functional part 200 is an inclined surface will be described, but it is sufficient that at least the side surface 203b (described later) of the n+ GaN layer 203 (contact layer) is an inclined surface.

[0066] 9(A) is a cross-sectional view showing a process of forming a Schottky electrode 205 and a photoresist 206 on a functional section 200. As shown in FIG 9(A), a Schottky electrode 205 is formed on an upper surface of an n-GaN layer 204. The Schottky electrode 205 is made of, for example, Ni (nickel), Pd (palladium), or Mo, and is formed by sputtering or vapor deposition.

[0067] Furthermore, a photoresist 206 for patterning is formed on the Schottky electrode 205. The photoresist 206 is formed by, for example, spin coating.

[0068] Fig. 9(B) is a cross-sectional view showing a step of patterning the Schottky electrode 205. As shown in Fig. 9(B), the Schottky electrode 205 is patterned by dry etching or wet etching via the photoresist 206.

[0069] Fig. 10(A) is a cross-sectional view showing a step of etching the growth substrate 201. As shown in Fig. 10(A), the growth substrate 201 is etched in the surface direction, that is, in the (100) direction, by wet etching using KOH.

[0070] The sacrificial layer 201a of the growth substrate 201 may be partially etched as described with reference to Fig. 2(B) in the first embodiment, or may be completely removed as described with reference to Fig. 2(C), thereby making it possible to easily separate the functional section 200 from the growth substrate 201.

[0071] 10(B) is a cross-sectional view showing a process of separating buffer layer 202, functional unit 200, and Schottky electrode 205 from growth substrate 201. As shown in Fig. 10(B), a stamp 220 is attached as a holding member to the upper surface of Schottky electrode 205, and buffer layer 202, functional unit 200, and Schottky electrode 205 are separated from growth substrate 201. The configuration of stamp 220 is similar to that of stamp 120 in the first embodiment.

[0072] Here, the a-axis lattice constant L of the Si(111) substrate constituting the growth substrate 201 is 201 The a-axis lattice constant L of the AlN constituting the buffer layer 202 is 3.89 [Å]. 202 The a-axis lattice constant L of GaN constituting the functional section 200 (i.e., the n+GaN layer 203 and the n-GaN layer 204) is 3.11 [Å]. 200 is 3.19 Å. These lattice constants are L 201 >L 200 >L 202 This is in a relationship.

[0073] In addition, the thermal expansion coefficient T 201 is 2.4 × 10 -6 ~4.4×10 -6 [ / K]. The thermal expansion coefficient T 202 is 4.3 x 10 -6 ~4.8×10 -6 [ / K]. The thermal expansion coefficient T 200 is 3.72 x 10 -6 ~5.45×10 -6 [ / K]. These thermal expansion coefficients are T 200 >T 202 >T 201 This is in a relationship.

[0074] In the epitaxial growth step (FIG. 8(B)), the buffer layer 202 and the functional section 200 are epitaxially grown under a tensile stress so that their lattice constants match those of the growth substrate 201. When the buffer layer 202 and the functional section 200 are subsequently cooled to room temperature, the buffer layer 202 and the functional section 200 shrink more than the growth substrate 201 due to the difference in thermal expansion, causing the buffer layer 202 and the functional section 200 to warp. The warping of the buffer layer 202 and the functional section 200 becomes evident when they are separated from the growth substrate 201 as shown in FIG. 10(B).

[0075] Fig. 11(A) is a cross-sectional view showing a step of removing buffer layer 202. As shown in Fig. 11(B), buffer layer 202 is removed from functional section 200 by etching or polishing such as CMP (chemical mechanical polishing). This exposes lower surface 203a of n+GaN layer 203 of functional section 200. By removing buffer layer 202, the warpage of functional section 200 is alleviated, but not completely eliminated.

[0076] Fig. 11(B) is a cross-sectional view showing a step of forming first metal film 210. As shown in Fig. 11(B), first metal film 210 is formed on lower surface 203a of n+GaN layer 203 of functional section 200. First metal film 210 is an electrode for n+GaN layer 203, and is composed of a multilayer film including multiple metal layers.

[0077] First metal film 210 is formed so as to wrap around from lower surface 203a to side surface 203b of n+ GaN layer 203. The angle between lower surface 203a and side surface 203b of n+ GaN layer 203 is 45 to 90 degrees, similar to angle R (FIG. 4(B)) described in the first embodiment, and is more preferably 60 degrees or more and less than 90 degrees.

[0078] 12(A) to 12(E) are cross-sectional views of each process showing a method for forming first metal film 210. As shown in Fig. 12(A), first layer 211 made of Ti is formed by sputtering or vapor deposition on lower surface 203a of n+ GaN layer 203. First layer 211 is formed so as to wrap around from lower surface 203a of n+ GaN layer 203 to side surface 203b.

[0079] 12(B), a second layer 212 made of Al is formed by sputtering or vapor deposition on the first layer 211. The second layer 212 is formed so as to completely cover the first layer 211 and reach the side surface 203b of the n+GaN layer 203.

[0080] 12(C), a third layer 213 made of Ti is formed by sputtering or vapor deposition on the second layer 212. The third layer 213 is formed so as to completely cover the second layer 212 and reach the side surface 203b of the n+GaN layer 203.

[0081] 12(D), a fourth layer 214 made of Pt is formed by sputtering or vapor deposition on the third layer 213. The fourth layer 214 is formed so as to completely cover the third layer 213 and reach the side surface 203b of the n+GaN layer 203. The fourth layer 214 is also referred to as a barrier metal layer.

[0082] 12(E), a fifth layer 215 made of Au is formed by sputtering or vapor deposition on the fourth layer 214. The fifth layer 215 is formed so as to completely cover the fourth layer 214 and reach the side surface 203b of the n+GaN layer 203.

[0083] In this manner, the first layer 211 to the fifth layer 215 of the first metal film 210 are formed so as to completely cover the lower layers and to reach the side surface 203b of the n+GaN layer 203.

[0084] In addition, when the third layer 243 (Au) of the second metal film 240 on the device substrate 230 described later is thick, the fifth layer 215 (Au) of the first metal film 210 may be omitted, and a four-layer structure may be formed of the first layer 211 (Ti) to the fourth layer 214 (Pt).

[0085] When forming the first metal film 210 by sputtering or vapor deposition, for example, the functional part 200 is separated from the growth substrate 201 as shown in FIG. 11(A), and metal atoms for forming the first metal film 210 are deposited toward the lower surface 203a, so that the first metal film 210 is formed from the lower surface 203a to the side surface 203b.

[0086] At this time, since side surface 203b of n+GaN layer 203 is an inclined surface having an angle of 45 to 90 degrees (more preferably 60 degrees or more and less than 90 degrees) with respect to bottom surface 203a, first metal film 210 can be formed so as not to contact the side surface of n-GaN layer 204. By not contacting first metal film 210 with n-GaN layer 204, it is possible to prevent a decrease in the voltage resistance of n-GaN layer 204 (drift layer).

[0087] In addition, since the fourth layer 214 (Pt) is formed between the second layer 212 (Al) and the fifth layer 215 (Au) of the first metal film 210 so as to wrap around the side surface 203b of the n+GaN layer as shown in Figures 12(D) and (E), it is possible to prevent an increase in electrical resistance due to the eutectic of Al and Au during the annealing treatment described later.

[0088] The fourth layer 214 as a barrier metal layer may be made of Mo instead of Pt. In this case, the third layer 213 (Ti) may be omitted.

[0089] Fig. 13(A) is a cross-sectional view showing a step of transferring the functional unit 200 to a device substrate 230. As shown in Fig. 13(A), the functional unit 200 held by the stamp 220 is transferred to a device substrate 230 as a second substrate. The device substrate 230 is a substrate separate from the growth substrate 201, and is, for example, a SiC substrate. However, the device substrate 230 is not limited to SiC, and may be, for example, Si, glass, or the like.

[0090] A second metal film 240 is formed on the surface of the device substrate 230. Fig. 13(B) is an enlarged cross-sectional view showing the second metal film 240 on the surface of the device substrate 230. As shown in Fig. 13(B), the second metal film 240 has, in order from the device substrate 230 side (lower side), a first layer 241 made of Ti, a second layer 242 made of Pt, and a third layer 243 made of Au.

[0091] The first layer 241 and the second layer 242 have a thickness of, for example, 100 nm. The third layer 243 has a thickness of, for example, 100 nm to 10 μm. The first layer 241, the second layer 242, and the third layer 243 are formed by sputtering or vapor deposition, and are unlikely to warp. The second metal film 240 is not limited to the three layers of Ti, Pt, and Au, and other combinations of layers are also possible.

[0092] When transferring the functional section 200 to the device substrate 230, the first metal film 210 and the second metal film 240 are bonded together by applying a predetermined pressure. Then, the stamp 220 is peeled off from the upper surface of the Schottky electrode 205 and removed.

[0093] Fig. 14(A) is a cross-sectional view showing a process of bonding the metal films 210, 240 of the functional section 200 and the device substrate 230. As shown in Fig. 14(A), in a state where the first metal film 210 and the second metal film 240 are bonded together, an annealing treatment is performed at 500 to 800 degrees.

[0094] This bonds the first metal film 210 and the second metal film 240. Even if the functional section 200 is warped, the first metal film 210 and the second metal film 240 are bonded well without any gaps due to the pressure applied during bonding and the subsequent annealing treatment.

[0095] Moreover, the annealing process provides ohmic contact between the n+GaN layer 203 of the functional section 200 and the first layer 211 (Ti) and the second layer 212 (Au) of the first metal film 210. Also, the outermost fifth layer 215 (Au) of the first metal film 210 and the third layer 243 (Au), which is the uppermost layer of the second metal film 240, are integrated together.

[0096] Fig. 14(B) is a cross-sectional view showing a process of forming an insulating film 207 and a wiring layer 208 on the functional unit 200. As shown in Fig. 14(B), the insulating film 207 is formed so as to cover the functional unit 200 except for the Schottky electrode 205. The insulating film 207 is, for example, an oxide film such as SiO2 (silicon oxide), and is formed by sputtering or vapor deposition.

[0097] Thereafter, the wiring layer 208 is formed so as to cover the upper surface of the Schottky electrode 205. The wiring layer 208 is made of, for example, Au or Al. Alternatively, it may be a laminate of a Ti layer and an Al layer.

[0098] Wiring (not shown) is connected to the second metal film 240 (third layer 243) of the device substrate 230. This completes the electronic device 20, which is a vertical GaN semiconductor device (more specifically, a Schottky barrier diode).

[0099] Here, the Schottky electrode 205 is formed before the functional section 200 is separated from the growth substrate 201 (see FIGS. 9(A) and 9(B)), but the Schottky electrode 205 may be formed after the functional section 200 is transferred to the device substrate 230. In this case, the Schottky electrode 205 and the wiring layer 208 may be formed integrally.

[0100] In the example described here, the first metal film 210 formed on the functional section 200 is composed of a Ti layer, an Al layer, a Ti layer, a Pt layer and an Au layer (first layer 211 to fifth layer 215), and the second metal film 240 formed on the device substrate 230 is composed of an Au layer, a Pt layer and a Ti layer (first layer 241 to third layer 243).

[0101] However, the configuration of the metal films 210, 240 is not limited to the above example. As the configuration of each layer of the metal films 210, 240, for example, 26 combinations shown in Table 1 below are possible.

[0102] In Table 1, for each layer of the first metal film 210 on the functional unit 200 side, the layer on the right side is closer to the bonding surface of the metal films 210, 240. For each layer of the second metal film 240 on the device substrate 230 side, the layer on the left side is closer to the bonding surface of the metal films 210, 240. For example, in the combination of number 1, the Au layer of the first metal film 210 is closest to the bonding surface, and the Au layer of the second metal film 240 is closest to the bonding surface.

[0103] [Table 1]

[0104] The combinations shown in Table 1 are not limited to the metal films 210 and 240 of the second embodiment, but can also be applied to the first metal film and the second metal film of the third to seventh embodiments described below.

[0105] As described above, the electronic device 20 of the second embodiment includes the functional unit 200, the device substrate 230 as a substrate supporting the functional unit 200, the first metal film 210 as an electrode formed on the device substrate 230 side of the functional unit 200, and the second metal film 240 formed on the device substrate 230 and to which the first metal film 210 is bonded. The first metal film 210 is formed from the lower surface (first surface) 203a to a part of the side surface (second surface) 203b of the functional unit 200. Therefore, as in the first embodiment, even if the functional unit 200 is warped, the functional unit 200 can be well bonded to the device substrate 230, and peeling of the functional unit 200 can be prevented.

[0106] Furthermore, since functional unit 200 has n+GaN layer 203 as a contact layer and n-GaN layer 204 as a drift layer, and first metal film 210 is formed on n+GaN layer 203, functional unit 200 and second metal film 240 on device substrate 230 can be electrically connected via first metal film 210.

[0107] Moreover, a fourth layer 214 (Pt) serving as a barrier metal layer is interposed between the second layer 212 (Al) and the fifth layer 215 (Au) of the first metal film 210, and is also interposed between the third layer 213 (Al) of the first metal film 210 and the third layer 243 (Au) of the second metal film 240. This makes it possible to prevent a eutectic reaction caused by contact between Al and Au, and to prevent poor bonding.

[0108] Third Embodiment The third embodiment relates to an electronic device 30 as a vertical GaN light emitting diode (LED) and a method for manufacturing the same.

[0109] Fig. 15(A) is a cross-sectional view showing a step of forming a buffer layer 302 and a functional section 300 on a growth substrate 301 in a manufacturing method of an electronic device 30 according to the third embodiment. The growth substrate 301 as a first substrate shown in Fig. 15(A) is, for example, a Si(111) substrate. Note that the growth substrate 301 is not limited to Si(111) and may be any substrate on which the functional section 300 described below can be grown.

[0110] A buffer layer 302, which is an AlN layer, is epitaxially grown on the surface of a growth substrate 301. The buffer layer 302 is a single layer of AlN here, but is not limited to this and may be, for example, a laminate of an AlN layer and an AlGaN layer. The thickness of the buffer layer 302 is, for example, 200 nm to 1 μm.

[0111] An nGaN layer 303 serving as a contact layer is epitaxially grown on the buffer layer 302. The thickness of the nGaN layer 303 is, for example, 2 μm.

[0112] Next, an n-AlGaN layer 304 serving as a cladding layer is epitaxially grown on the n-GaN layer 303. The thickness of the n-AlGaN layer 304 is, for example, 100 to 300 nm.

[0113] Furthermore, an InGaN layer 305 serving as an active layer or a light emitting layer is epitaxially grown on the nAlnGaN layer 304. The InGaN layer 305 is a MQW (multiple quantum well) layer. The thickness of the InGaN layer 305 is, for example, 100 nm.

[0114] Next, a pAlGaN layer 306 serving as a cladding layer is epitaxially grown on the InGaN layer 305. The thickness of the pAlGaN layer 306 is, for example, 50 nm.

[0115] Furthermore, a pGaN layer 307 serving as a contact layer is epitaxially grown on the pAlGaN layer 306. The thickness of the pGaN layer 307 is, for example, 50 nm.

[0116] The nGaN layer 303 , the nAlGaN layer 304 , the InGaN layer 305 , the pAlGaN layer 306 and the pGaN layer 307 constitute a functional portion (semiconductor thin film) 300 .

[0117] Fig. 15(B) is a cross-sectional view showing a process of patterning the growth substrate 301, the buffer layer 302, and the functional section 300. As shown in Fig. 15(B), the growth substrate 301, the buffer layer 302, and the functional section 300 are patterned into an element shape. The patterning is performed by forming a photoresist (not shown) on the pGaN layer 307 and dry etching.

[0118] Dry etching is performed until the depth (overetching amount) t from the surface of the growth substrate 301 reaches 50 to 10,000 nm. As a result, a sacrificial layer 301a having approximately the same area as the lower surface of the buffer layer 302 is formed on the surface of the growth substrate 301.

[0119] The dry etching conditions are set so that the side surface of the functional part 300 is an inclined surface, as described in the first embodiment. The inclination direction of the functional part 300 is a direction in which the size of the functional part 300 in a plane parallel to the lower surface (lower surface 303a described later) of the functional part 300 decreases toward the upper side (the further away from the lower surface). Here, a case where the side surface of the functional part 300 is an inclined surface will be described, but it is sufficient that at least the side surface 303b (described later) of the nGaN layer 303 (contact layer) is an inclined surface.

[0120] Fig. 16(A) is a cross-sectional view showing a step of etching the growth substrate 301. As shown in Fig. 16(A), the growth substrate 301 is etched in the surface direction, i.e., in the (100) direction, by wet etching using KOH.

[0121] The sacrificial layer 301a of the growth substrate 301 may be partially etched as described with reference to Fig. 2(B) in the first embodiment, or may be completely removed as described with reference to Fig. 2(C), thereby making it possible to easily separate the functional section 300 from the growth substrate 301.

[0122] 16(B) is a cross-sectional view showing a step of separating the buffer layer 302 and the functional unit 300 from the growth substrate 301. As shown in Fig. 16(B), a stamp 320 is attached as a holding member to the upper surface of the functional unit 300 (the surface opposite to the growth substrate 301), and the buffer layer 302 and the functional unit 300 are separated from the growth substrate 301. The configuration of the stamp 320 is similar to that of the stamp 120 of the first embodiment.

[0123] Here, the a-axis lattice constant L of the Si(111) substrate constituting the growth substrate 301 is 301 The a-axis lattice constant L of the AlN constituting the buffer layer 302 is 3.89 [Å]. 302 The a-axis lattice constant L of the GaN constituting each layer of the functional section 300 is 3.11 [Å]. 300 is 3.19 Å. These lattice constants are L 301 >L 300 >L 302 This is in a relationship.

[0124] The thermal expansion coefficient T 301 is 2.4 × 10 -6 ~4.4×10 -6 [ / K]. The thermal expansion coefficient T 302 is 4.3 x 10 -6 ~4.8×10 -6 [ / K]. The thermal expansion coefficient T 300 is 3.72 x 10 -6 ~5.45×10 -6 [ / K]. These thermal expansion coefficients are T 300 >T 302 >T 301 This is in a relationship.

[0125] In the epitaxial growth process (FIG. 15(A)), the buffer layer 302 and the functional section 300 are epitaxially grown under a tensile stress so that their lattice constants match those of the growth substrate 301. When the buffer layer 302 and the functional section 300 are subsequently cooled to room temperature, the buffer layer 302 and the functional section 300 shrink more than the growth substrate 301 due to the difference in thermal expansion, causing the buffer layer 302 and the functional section 300 to warp. The warping of the buffer layer 302 and the functional section 300 becomes evident when they are separated from the growth substrate 301 as shown in FIG. 16(B).

[0126] Fig. 17(A) is a cross-sectional view showing a step of removing the buffer layer 302. As shown in Fig. 17(A), the buffer layer 302 is removed from the functional section 300 by etching or polishing such as CMP. This exposes the lower surface 303a of the nGaN layer 303 of the functional section 300. By removing the buffer layer 302, the warpage of the functional section 300 is alleviated, but not completely eliminated.

[0127] Fig. 17(B) is a cross-sectional view showing a step of forming the first metal film 310. As shown in Fig. 17(B), the first metal film 310 is formed on the lower surface 303a of the nGaN layer 303 of the functional section 300. The first metal film 310 is an electrode for the nGaN layer 303, and is composed of a multilayer film.

[0128] The first metal film 310 is formed so as to wrap around from the lower surface 303a to the side surface 303b of the nGaN layer 303. The angle between the lower surface 303a and the side surface 303b of the nGaN layer 303 is 45 to 90 degrees, similar to the angle R (FIG. 4(B)) described in the first embodiment, and is more preferably 60 degrees or more and less than 90 degrees.

[0129] Fig. 17(C) is an enlarged view of the portion surrounded by the symbol A in Fig. 17(B). It is an enlarged view of the first metal film 310. The first metal film 310 has, in order from the nGaN layer 303 side, a first layer 311 made of Ti, a second layer 312 made of Al, a third layer 313 made of Ti, a fourth layer 314 made of Pt, and a fifth layer 315 made of Au. The fourth layer 314 is also called a barrier metal layer. The method of forming each layer is as described with reference to Figs. 12(A) to (E) in the second embodiment.

[0130] As described in the second embodiment, when forming the first metal film 310 by sputtering or vapor deposition, for example, the functional part 300 is separated from the growth substrate 301 as shown in FIG. 17(A), and metal atoms for forming the first metal film 310 are deposited toward the lower surface 303a, so that the first metal film 310 is formed from the lower surface 303a to the side surface 303b.

[0131] At this time, since the side surface 303b of the nGaN layer 303 is an inclined surface having an angle of 45 to 90 degrees (more preferably 60 degrees or more and less than 90 degrees) with respect to the bottom surface 303a, the first metal film 310 can be formed so as not to extend beyond the nAlnGaN layer 304 and contact the side surface of the InGaN layer 305.

[0132] Therefore, the first metal film 310 comes into contact with the side surface of the InGaN layer 305, thereby preventing leakage current from flowing into the InGaN layer 305, and as a result, it is possible to prevent a decrease in the light emission efficiency of the InGaN layer 305 (MQW layer). Note that, although the first metal film 310 here covers a part of the side surface 303b of the nGaN layer 303, it may also cover a part of the side surface of the nAlnGaN layer 304.

[0133] Furthermore, since the fourth layer 314 (Pt) is formed between the second layer 312 (Al) and the fifth layer 315 (Au) of the first metal film 310 so as to wrap around the side surface 303b of the nGaN layer 303 as shown in FIG. 17(C), it is possible to prevent an increase in electrical resistance due to the eutectic of Al and Au during the annealing treatment described later.

[0134] Fig. 18(A) is a cross-sectional view showing a step of transferring the functional unit 300 to a device substrate 330. As shown in Fig. 20(A), the functional unit 300 held by the stamp 320 is transferred to a device substrate 330 as a second substrate. The device substrate 330 is a substrate separate from the growth substrate 301, and is, for example, a SiC substrate. However, the device substrate 330 is not limited to SiC, and may be, for example, Si, glass, or the like.

[0135] A second metal film 340 is formed on the surface of the device substrate 330. Fig. 18(B) is an enlarged cross-sectional view showing the second metal film 340 on the surface of the device substrate 330. As shown in Fig. 18(B), the second metal film 340 has a first layer 341, a second layer 342, and a third layer 343, in this order from the device substrate 330 side (lower side).

[0136] The first to third layers 341 to 343 of the second metal film 340 are formed in the same manner as the first to third layers 241 to 243 of the second metal film 240 of the second embodiment (FIG. 13(B)).

[0137] When transferring the functional section 300 to the device substrate 330, the first metal film 310 and the second metal film 340 are bonded together by applying a predetermined pressure, after which the stamp 320 is peeled off from the upper surface of the functional section 300 and removed.

[0138] Fig. 19(A) is a cross-sectional view showing a process of bonding the metal films 310, 340 of the functional section 300 and the device substrate 330. As shown in Fig. 19(A), in a state where the first metal film 310 and the second metal film 340 are bonded together, an annealing treatment is performed at 500 to 800 degrees.

[0139] This bonds the first metal film 310 and the second metal film 340. Even if the functional section 300 is warped, the first metal film 310 and the second metal film 340 are bonded together without any gaps due to the pressure applied during bonding and the subsequent annealing treatment.

[0140] Furthermore, annealing treatment provides ohmic contact between the nGaN layer 303 of the functional unit 300 and the first and third layers 311 and 313 (Ti) and second layer 312 (Au) of the first metal film 310 (FIG. 17(C)). Furthermore, the outermost fifth layer 315 (Au) of the first metal film 310 formed on the functional unit 300 is integrated with the third layer 343 (Au), which is the uppermost layer of the second metal film 340 on the device substrate 330.

[0141] Fig. 19(B) is a cross-sectional view showing a process of forming P electrode 351 and N electrode 352 on functional unit 300. As shown in Fig. 19(B), P electrode 351 is formed on pGaN layer 307 of functional unit 300. P electrode 351 is formed of, for example, ITO (indium tin oxide) or Ni / Au.

[0142] Moreover, an N-electrode 352 is formed on the second metal film 340 (third layer 243) of the device substrate 330. The N-electrode 352 is formed of Ti or a laminate of Ti, Pt, and Au. Note that the second metal film 340 of the device substrate 330 may be used as an electrode without forming the N-electrode 352. Through the above steps, the electronic device 30, which is a vertical GaN light-emitting diode, is completed.

[0143] As described above, the electronic device 30 of the third embodiment includes the functional unit 300, the device substrate 330 as a substrate supporting the functional unit 300, the first metal film 310 as an electrode formed on the device substrate 330 side of the functional unit 300, and the second metal film 340 formed on the device substrate 330 and to which the first metal film 310 is bonded. The first metal film 310 is formed from the lower surface (first surface) 303a to a part of the side surface (second surface) 303b of the functional unit 300. Therefore, as in the first embodiment, even if the functional unit 300 is warped, the functional unit 300 can be well bonded to the device substrate 330, and peeling of the functional unit 300 can be prevented.

[0144] Furthermore, since the functional unit 300 has an nGaN layer 303 as a contact layer and semiconductor layers (nAlGaN layer 304 to pGaN layer 307) thereon, and a first metal film 310 is formed on the nGaN layer 303, the functional unit 300 can be electrically connected to a second metal film 340 on the device substrate 330 via the first metal film 310.

[0145] Fourth Embodiment The fourth embodiment relates to an electronic device 40 as a vertical GaN field effect transistor (FET) device having a trench structure and a method for manufacturing the same.

[0146] Fig. 20(A) is a cross-sectional view showing a step of forming a buffer layer 402 and a functional section 400 on a growth substrate 401 in a manufacturing method of an electronic device 40 according to the fourth embodiment. The growth substrate 401 as a first substrate shown in Fig. 20(A) is, for example, a Si(111) substrate. Note that the growth substrate 401 is not limited to Si(111) and may be any substrate on which the functional section 400 described below can be grown.

[0147] A buffer layer 402, which is an AlN layer, is epitaxially grown on the surface of a growth substrate 401. The buffer layer 402 is a single layer of AlN here, but is not limited to this and may be, for example, a laminate of an AlN layer and an AlGaN layer. The thickness of the buffer layer 402 is, for example, 200 nm to 1 μm.

[0148] An n+ GaN layer 403 serving as a contact layer is epitaxially grown on the buffer layer 402. The thickness of the n+ GaN layer 403 is, for example, 5 μm or less. When grown on a GaN substrate, the thickness of the n+ GaN layer 403 is 100 μm or more, but by growing the n+ GaN layer 403 on a growth substrate 401 (Si) via the buffer layer 402, the thickness can be reduced to 5 μm or less.

[0149] Next, n-GaN layer 404 as a drift layer is epitaxially grown on n+GaN layer 403. The thickness of n-GaN layer 404 is, for example, 2 to 50 μm.

[0150] Furthermore, a pGaN layer 405 serving as a contact layer is epitaxially grown on the n-GaN layer 404. The thickness of the pGaN layer 405 is, for example, 10 μm or less.

[0151] Next, n+GaN layer 406 is epitaxially grown on pGaN layer 405. The thickness of n+GaN layer 406 is, for example, 1 μm or less.

[0152] The n+GaN layer 403 , the n-GaN layer 404 , the pGaN layer 405 and the n+GaN layer 406 constitute a functional portion (semiconductor thin film) 400 .

[0153] Fig. 20(B) is a cross-sectional view showing a process of patterning the growth substrate 401, the buffer layer 402, and the functional section 400. As shown in Fig. 20(B), the growth substrate 401, the buffer layer 402, and the functional section 400 are patterned into an element shape. The patterning is performed by forming a photoresist (not shown) on the functional section 400 and dry etching it.

[0154] Dry etching is performed until the depth (overetching amount) t from the surface of the growth substrate 401 reaches 50 to 10,000 nm. As a result, a sacrificial layer 401a having approximately the same area as the lower surface of the buffer layer 402 is formed on the surface of the growth substrate 401.

[0155] The dry etching conditions are set so that the side surface of the functional part 400 is an inclined surface, as described in the first embodiment. The inclination direction of the functional part 400 is a direction in which the size of a plane parallel to the lower surface (lower surface 403a described later) of the functional part 400 decreases upward (as it moves away from the lower surface). Here, a case where the side surface of the functional part 400 is an inclined surface will be described, but it is sufficient that at least the side surface 403b (described later) of the n+ GaN layer 403 (contact layer) is an inclined surface.

[0156] Fig. 21(A) is a cross-sectional view showing a step of etching the growth substrate 401. As shown in Fig. 21(A), the growth substrate 401 is etched in the surface direction, that is, in the (100) direction, by wet etching using KOH.

[0157] The sacrificial layer 401a of the growth substrate 401 may be partially etched as described with reference to Fig. 2(B) in the first embodiment, or may be completely removed as described with reference to Fig. 2(C), thereby making it possible to easily separate the functional section 400 from the growth substrate 401.

[0158] 21(B) is a cross-sectional view showing a step of separating the buffer layer 402 and the functional unit 400 from the growth substrate 401. As shown in Fig. 21(B), a stamp 420 is attached as a holding member to the upper surface of the functional unit 400 (the surface opposite to the growth substrate 401), and the buffer layer 402 and the functional unit 400 are separated from the growth substrate 401. The configuration of the stamp 420 is similar to that of the stamp 120 of the first embodiment.

[0159] Here, the a-axis lattice constant L of the Si(111) substrate constituting the growth substrate 401 is 401 The a-axis lattice constant L of the AlN constituting the buffer layer 402 is 3.89 [Å]. 402 The a-axis lattice constant L of the GaN constituting each layer of the functional section 400 is 3.11 [Å]. 400 is 3.19 Å. These lattice constants are L 401 >L 400 >L 402 This is in a relationship.

[0160] In addition, the thermal expansion coefficient T 401 is 2.4 × 10 -6 ~4.4×10 -6 [ / K]. The thermal expansion coefficient T 402 is 4.3 x 10 -6 ~4.8×10 -6 [ / K]. The thermal expansion coefficient T 400is 3.72 x 10 -6 ~5.45×10 -6 [ / K]. These thermal expansion coefficients are T 400 >T 402 >T 401 This is in a relationship.

[0161] In the epitaxial growth process (FIG. 20(A)), the buffer layer 402 and the functional section 400 are epitaxially grown under a tensile stress so that their lattice constants match those of the growth substrate 401. When the buffer layer 402 and the functional section 400 are subsequently cooled to room temperature, the buffer layer 402 and the functional section 400 shrink more than the growth substrate 401 due to the difference in thermal expansion, causing the buffer layer 402 and the functional section 400 to warp. The warping of the buffer layer 402 and the functional section 400 becomes evident when they are separated from the growth substrate 401 as shown in FIG. 21(B).

[0162] Fig. 22(A) is a cross-sectional view showing a step of removing buffer layer 402. As shown in Fig. 22(A), buffer layer 402 is removed from functional section 400 by etching or polishing such as CMP. This exposes lower surface 403a of n+GaN layer 403 of functional section 400. By removing buffer layer 402, the warpage of functional section 400 is alleviated, but not completely eliminated.

[0163] Fig. 22(B) is an enlarged view of the portion surrounded by the symbol A in Fig. 22(A). As shown in Fig. 22(B), a first metal film 410 is formed on the lower surface 403a of the n+ GaN layer 403 of the functional section 400. The first metal film 410 is an electrode for the n+ GaN layer 403, and is composed of a multilayer film.

[0164] First metal film 410 is formed so as to wrap around from lower surface 403a to side surface 403b of n+ GaN layer 403. The angle between lower surface 403a and side surface 403b of n+ GaN layer 403 is 45 to 90 degrees, similar to angle R (FIG. 4(B)) described in the first embodiment, and is more preferably 60 degrees or more and less than 90 degrees.

[0165] 22(C) is an enlarged view of first metal film 410. First metal film 410 has, in order from the n+GaN layer 403 side, first layer 411 made of Ti, second layer 412 made of Al, third layer 413 made of Ti, fourth layer 414 made of Pt, and fifth layer 415 made of Au. The method of forming each layer is as described with reference to FIGS. 12(A) to (E) in the second embodiment.

[0166] As described in the second embodiment, when forming the first metal film 410 by sputtering or vapor deposition, for example, the functional part 400 is separated from the growth substrate 401 as shown in FIG. 22(A), and metal atoms for forming the first metal film 410 are attached toward the lower surface 403a, so that the first metal film 410 is formed from the lower surface 403a to the side surface 403b.

[0167] At this time, since side surface 403b of n+GaN layer 403 is an inclined surface having an angle of 45 to 90 degrees (more preferably 60 degrees or more and less than 90 degrees) with respect to bottom surface 403a, first metal film 410 can be formed so as not to contact the side surface of n-GaN layer 404. By not contacting first metal film 410 with n-GaN layer 404, it is possible to prevent a decrease in the voltage resistance of n-GaN layer 404 (drift layer).

[0168] In addition, since the fourth layer 414 (Pt) is formed between the second layer 412 (Al) and the fifth layer 415 (Au) of the first metal film 410 so as to wrap around the side surface 403b of the n+GaN layer 403 as shown in FIG. 22(C), it is possible to prevent an increase in electrical resistance due to the eutectic of Al and Au during the annealing treatment described later.

[0169] 23(A) to (H) are cross-sectional views of each process showing another example of the method for forming first metal film 410. As shown in Fig. 23(A), a first layer 411 made of Ti is formed on lower surface 403a of n+ GaN layer 403 by sputtering or vapor deposition.

[0170] Thereafter, as shown in FIG. 23(B), an end E1 of the first layer 411 (more specifically, an end E1 closer to the side surface 403b of the n+ GaN layer 403) is removed by etching.

[0171] 23(C), a second layer 412 made of Al is formed by sputtering or vapor deposition so as to cover the first layer 411. The second layer 412 is formed so as to cover the first layer 411 and the lower surface 403a exposed by removing the end E1, but does not extend around the side surface 403b.

[0172] Thereafter, as shown in FIG. 23(D), the end E2 of the second layer 412 is removed by etching.

[0173] 23(E), a third layer 413 made of Ti is formed by sputtering or vapor deposition so as to cover the second layer 412. The third layer 413 is formed so as to cover the second layer 412 and the lower surface 403a exposed by removing the end E1, but does not extend around the side surface 403b.

[0174] Thereafter, as shown in FIG. 23(F), the end E3 of the third layer 413 is removed by etching.

[0175] 23(G), a fourth layer 414 made of Pt is formed by sputtering or vapor deposition so as to cover the third layer 413. The fourth layer 414 is formed so as to cover the third layer 413 and the lower surface 403a exposed by removing the end E1, but does not extend around the side surface 403b.

[0176] 23(H), a fifth layer 415 made of Au is formed by sputtering or vapor deposition so as to cover the fourth layer 414. The fifth layer 415 is formed so as to cover the fourth layer 414, cover the lower surface 403a exposed by removing the end E1, and further wrap around the side surface 403b.

[0177] In this manner, the first layer 411 to the fifth layer 415 of the first metal film 410 are formed so as to completely cover the layers below. Of the first layer 411 to the fifth layer 415 of the first metal film 410, only the fifth layer 415 wraps around the side surface 403b of the n+ GaN layer 403.

[0178] 23(A)-(H), the angle between the lower surface 403a and the side surface 403b of the +GaN layer 403 is 45-90 degrees, so that the first metal film 410 is not in contact with the side surface of the n-GaN layer 404, and it is possible to prevent a decrease in the withstand voltage of the n-GaN layer 404. In addition, the first metal film 410 acts to hold the lower surface 403a and the side surface 403b of the GaN layer 403, so that it is possible to prevent the functional portion 400 from peeling off.

[0179] In addition, since the fourth layer 414 (Pt) is provided between the second layer 412 (Al) and the fifth layer 415 (Au) of the first metal film 410, an increase in electrical resistance due to the eutectic of Al and Au during annealing can be prevented.

[0180] In the example shown in Figures 23(A) to (H), of the first layer 411 to the fifth layer 415 of the first metal film 410, only the fifth layer 415 wraps around to the side surface 403b of the n+GaN layer 403, but this is not limited to the example, and two or more layers including the fifth layer 415 may wrap around to the side surface 403b.

[0181] Fig. 24(A) is a cross-sectional view showing a step of transferring the functional unit 400 to a device substrate 430. As shown in Fig. 24(A), the functional unit 400 held by the stamp 420 is transferred to a device substrate 430 as a second substrate. The device substrate 430 is a substrate different from the growth substrate 401, and is, for example, a SiC substrate. However, the device substrate 430 is not limited to Si, and may be, for example, Si, glass, or the like.

[0182] A second metal film 440 is formed on the surface of the device substrate 430. Fig. 24(B) is an enlarged cross-sectional view showing the second metal film 440 on the surface of the device substrate 430. As shown in Fig. 24(B), the second metal film 440 has a first layer 441, a second layer 442, and a third layer 443 in this order from the device substrate 430 side (lower side).

[0183] The first to third layers 441 to 443 of the second metal film 440 are formed in the same manner as the first to third layers 241 to 243 of the second metal film 240 of the second embodiment (FIG. 13(B)).

[0184] When transferring the functional section 400 to the device substrate 430, the first metal film 410 and the second metal film 440 are bonded together by applying a predetermined pressure. Thereafter, the stamp 420 is peeled off from the upper surface of the functional section 400 and removed.

[0185] Fig. 25(A) is a cross-sectional view showing a process of bonding the metal films 410, 440 of the functional section 400 and the device substrate 430. As shown in Fig. 25(A), an annealing process is performed at 500 to 800 degrees in a state where the first metal film 410 formed on the functional section 400 and the second metal film 440 formed on the device substrate 430 are bonded together.

[0186] This bonds the first metal film 410 and the second metal film 440. Even if the functional section 400 is warped due to the pressure applied during bonding and the subsequent annealing process, the first metal film 410 and the second metal film 440 are bonded without any gaps.

[0187] Moreover, annealing treatment provides ohmic contact between the n+GaN layer 403 of the functional unit 400 and the first layer 411 (Ti) and the second layer 412 (Au) of the first metal film 410 (FIG. 22(C)). Also, the outermost fifth layer 415 (Au) of the first metal film 410 formed on the functional unit 400 is integrated with the third layer 443 (Au), which is the uppermost layer of the second metal film 440 on the device substrate 430.

[0188] Fig. 25(B) is a cross-sectional view showing a process of forming an insulating film 451 on the functional section 400. As shown in Fig. 25(B), the insulating film 451 is formed so as to cover the device substrate 430 and the functional section 400. The insulating film 451 is an oxide film such as SiO2, Al2O3, etc., has a thickness of about 10 nm to 1 µm, and is formed by sputtering or CVD (chemical vapor deposition).

[0189] Fig. 26(A) is a cross-sectional view showing a process of forming and patterning a photoresist 452 on an insulating film 451. As shown in Fig. 26(A), a photoresist 452 is formed by, for example, spin coating on the insulating film 451 covering the functional section 400. Furthermore, the photoresist 452 is patterned to form an opening 453 at a position where a trench, which will be described later, is to be formed.

[0190] Fig. 26(B) is a cross-sectional view showing a process of forming trenches 407 in the functional section 400. As shown in Fig. 26(B), dry etching is performed via photoresist 452 to form trenches 407 in the functional section 400, reaching the n-GaN layer 404 (drift layer).

[0191] Fig. 27(A) is a cross-sectional view showing a process of forming an insulating film 451 and a photoresist 452 in a trench 407. As shown in Fig. 27(A), an insulating film 451 is formed by, for example, CVD or ALD (atomic layer deposition) so as to cover the inner surface of the trench 407. Furthermore, a photoresist 452 is formed by, for example, spin coating so as to cover the insulating film 451 in the trench 407.

[0192] Fig. 27(B) is a cross-sectional view showing a step of forming an opening 454 in the photoresist 452. As shown in Fig. 27(B), the photoresist 452 is exposed to light and developed to form an opening 454 at a position where a source electrode 461, which will be described later, is to be formed.

[0193] 28(A) is a cross-sectional view showing a process of forming a groove 455 in the functional unit 400. As shown in FIG. 28(A), dry etching is performed via a photoresist 452 to form a groove 455 for forming a source electrode 461 in the functional unit 400. The groove 455 is formed on both sides of the trench 407 so as to reach the pGaN layer 405.

[0194] In FIG. 28B, photoresist 452 is exposed and developed to form an opening 456 that is slightly larger than groove 455 at a position that overlaps with groove 455.

[0195] 29(A) is a cross-sectional view showing a step of forming a source electrode 461 and a gate electrode 462. The source electrode 461 is formed so as to fill the groove portion 455 of the functional portion 400 and the opening 456 of the photoresist 452. The source electrode 461 is made of, for example, Ti or Al, and is formed by sputtering or vapor deposition.

[0196] Furthermore, a gate electrode 462 is formed in the trench 407 of the functional section 400. The gate electrode 462 is made of, for example, Pd or Mo, and is formed by sputtering or deposition.

[0197] Fig. 29(B) is a cross-sectional view showing a step of removing photoresist 452. As shown in Fig. 29(B), photoresist 452 covering functional section 400 is removed by peeling or dissolving in an organic solvent.

[0198] In this manner, the source electrode 461 and the gate electrode 462 are formed in the functional section 400. The third layer 443 (Au) of the second metal film 440 on the device substrate 430 serves as a drain electrode. This completes the electronic device 40, which is a vertical GaN field effect transistor with a trench structure.

[0199] Since the functional section 400 (GaN) is grown on the growth substrate 401 such as Si via the buffer layer 402 (AlN), there is no need to use an expensive GaN substrate as the growth substrate 401, and the manufacturing cost can be reduced.

[0200] In addition, by removing the buffer layer 402, a first metal film 410 serving as a drain electrode can be directly formed on the n+GaN layer 403 and joined to a second metal film 440 on the device substrate 430, thereby realizing a vertical-structure GaN field effect transistor (GaN_FET) with low electrical resistance.

[0201] In addition, since the thickness of the n+GaN layer 403, which is a contact layer, can be made sufficiently thinner than the n-GaN layer 404, which is a drift layer, an ohmic contact can be obtained between the n+GaN layer 403 and the first metal film 410, which serves as a drain electrode, thereby reducing the on-resistance between the source electrode 461 and the drain electrode and improving the operating efficiency of the electronic device 40.

[0202] Furthermore, since a SiC substrate can be used as the device substrate 430, the heat dissipation of the electronic device 40 can be improved compared to the case where a GaN substrate is used.

[0203] As described above, the electronic device 40 of the fourth embodiment includes the functional unit 400, the device substrate 430 as a substrate supporting the functional unit 400, the first metal film 410 as an electrode formed on the device substrate 430 side of the functional unit 400, and the second metal film 440 formed on the device substrate 430 and to which the first metal film 410 is bonded. The first metal film 410 is formed from the lower surface (first surface) 403a to a part of the side surface (second surface) 403b of the functional unit 400. Therefore, as in the first embodiment, even if the functional unit 400 is warped, the functional unit 400 can be well bonded to the device substrate 430, and peeling of the functional unit 400 can be prevented.

[0204] Furthermore, since the functional section 400 has an n+GaN layer 403 as a contact layer and semiconductor layers thereon (n-GaN layer 404, pGaN layer 405 and n+GaN layer 406), and a first metal film 410 is formed on the n+GaN layer 403, the semiconductor layers can be electrically connected to a second metal film 440 on the device substrate 430 via the first metal film 410.

[0205] Fifth Embodiment The structure of the electronic device of the fifth embodiment is the same as that of the electronic device 40 of the fourth embodiment. The manufacturing method of the electronic device of the fifth embodiment differs from the manufacturing method of the electronic device 40 of the fourth embodiment in that a trench 507 is formed before the functional unit 500 is transferred to the device substrate 530.

[0206] FIG. 30(A) is a cross-sectional view showing a step of forming a buffer layer 502 and a functional section 500 on a growth substrate 501 serving as a first substrate in the method for manufacturing an electronic device according to the fifth embodiment.

[0207] Growth substrate 501, buffer layer 502, n+GaN layer 503, n-GaN layer 504, pGaN layer 505, and n+GaN layer 506 shown in FIG. 30(A) are formed in the same manner as growth substrate 401, buffer layer 402, n+GaN layer 403, n-GaN layer 404, pGaN layer 405, and n+GaN layer 406, respectively, described in embodiment 4.

[0208] The n+GaN layer 503 , the n-GaN layer 504 , the pGaN layer 505 and the n+GaN layer 506 constitute the functional section 500 .

[0209] Fig. 30(B) is a cross-sectional view showing a process of patterning the growth substrate 501, the buffer layer 502, and the functional section 500. As shown in Fig. 30(B), the growth substrate 501, the buffer layer 502, and the functional section 500 are patterned into an element shape. The patterning method is as described with reference to Fig. 20(B) in the fourth embodiment.

[0210] Fig. 31(A) is a cross-sectional view showing a process of forming an insulating film 551 and a photoresist 552 on the functional section 500. As shown in Fig. 31(A), the insulating film 551 is formed so as to cover the functional section 500. The insulating film 551 is an oxide film such as SiO2 or Al2O3, has a thickness of about 10 nm to 1 µm, and is formed by sputtering or vapor deposition.

[0211] Furthermore, a photoresist 552 is formed by, for example, spin coating on the insulating film 551 that covers the functional section 500. Furthermore, the photoresist 552 is patterned to form an opening 553 at a position where a trench, which will be described later, is to be formed.

[0212] Fig. 31(B) is a cross-sectional view showing a step of forming trenches 507 in the functional unit 500. As shown in Fig. 31(B), dry etching is performed via photoresist 552 to form trenches 507 in the functional unit 500, reaching the n-GaN layer 504 (drift layer).

[0213] Fig. 32(A) is a cross-sectional view showing a step of forming an insulating film 551 and a photoresist 552 in a trench 507. As shown in Fig. 32(A), an insulating film 551 is formed by, for example, CVD or ALD so as to cover the inner surface of the trench 507. Furthermore, a photoresist 552 is formed by, for example, spin coating so as to cover the insulating film 551 in the trench 507.

[0214] Fig. 32(B) is a cross-sectional view showing a step of etching the growth substrate 501. As shown in Fig. 32(A), the growth substrate 501 is etched in the surface direction, that is, in the (100) direction, by wet etching using KOH.

[0215] The sacrificial layer 501a of the growth substrate 501 may be partially etched as described with reference to Fig. 2(B) in the first embodiment, or may be completely removed as described with reference to Fig. 2(C), thereby making it possible to easily separate the functional section 500 from the growth substrate 501.

[0216] 33(A) is a cross-sectional view showing a step of separating the buffer layer 502 and the functional unit 500 from the growth substrate 501. As shown in Fig. 33(A), a stamp 520 is attached as a holding member to the upper surface of the functional unit 500, and the buffer layer 502 and the functional unit 500 are separated from the growth substrate 501. The configuration of the stamp 520 is similar to that of the stamp 120 of the first embodiment.

[0217] When the buffer layer 502 and the functional section 500 are separated from the growth substrate 501, warping of the buffer layer 502 and the functional section 500 becomes evident as described in the fourth embodiment.

[0218] Fig. 33(B) is a cross-sectional view showing a step of removing buffer layer 502. As shown in Fig. 33(B), buffer layer 502 is removed by etching or polishing such as CMP. This exposes lower surface 503a of n+GaN layer 503 of functional section 500. By removing buffer layer 502, the warpage of functional section 500 is alleviated, but not completely eliminated.

[0219] Fig. 34(A) is a cross-sectional view showing a step of forming a first metal film 510. As shown in Fig. 34(A), a first metal film 510 is formed on a lower surface 503a of an n+ GaN layer 503 of a functional unit 500. The metal film 510 is an electrode for the n+ GaN layer 503. The configuration of the first metal film 510 is similar to that of the first metal film 410 of the fourth embodiment (Fig. 22(C)).

[0220] Fig. 34(B) is a cross-sectional view showing a step of transferring the functional unit 500 to a device substrate 530. As shown in Fig. 34(B), the functional unit 500 held by the stamp 520 is transferred to a device substrate 530 serving as a second substrate. A second metal film 540 is formed on the surface of the device substrate 530.

[0221] The device substrate 530 and the second metal film 540 are similar to the device substrate 450 and the second metal film 440 (FIG. 24(B)) of the fourth embodiment. For each layer of the metal films 510 and 540 of the fifth embodiment, the combinations shown in Table 1 of the fourth embodiment may be used.

[0222] The steps after bonding the functional section 500 to the device substrate 530 are as described with reference to Figures 25(A) to 29(B) in the fourth embodiment. In this way, an electronic device, which is a vertical GaN field effect transistor with a trench structure, is completed.

[0223] As described above, in the method for manufacturing an electronic device according to the fifth embodiment, the trenches 507 are formed before the functional unit 500 is separated from the growth substrate 501, and therefore the number of processing steps after the functional unit 500 is transferred to the device substrate 530 is reduced. As a result, stresses and the like applied to the metal films 510 and 540 can be reduced, and bonding defects can be suppressed.

[0224] Sixth Embodiment The sixth embodiment, like the fourth and fifth embodiments, relates to an electronic device 60 as a vertical GaN field effect transistor (FET) device having a trench structure and a method for manufacturing the same.

[0225] Fig. 35(A) is a cross-sectional view showing a step of forming a buffer layer 602 and a functional section 600 on a growth substrate 601 in a manufacturing method of an electronic device 60 according to the sixth embodiment. Growth substrate 601, buffer layer 602, n+GaN layer 603, n-GaN layer 604, pGaN layer 605, and n+GaN layer 606 shown in Fig. 35(A) are formed in the same manner as growth substrate 401, buffer layer 402, n+GaN layer 403, n-GaN layer 404, pGaN layer 405, and n+GaN layer 406 (Fig. 20(A)) described in the fourth embodiment, respectively.

[0226] The n+GaN layer 603 , the n-GaN layer 604 , the pGaN layer 605 and the n+GaN layer 606 constitute a functional portion (semiconductor thin film) 600 .

[0227] Fig. 35(B) is a cross-sectional view showing a first patterning step for the functional section 600. As shown in Fig. 35(B), the n-GaN layer 604, the pGaN layer 605, and the n+GaN layer 606 of the functional section 600 are patterned into a first element shape. The first patterning step is performed by forming a photoresist (mask) (not shown) on the functional section 600 and performing dry etching.

[0228] Moreover, the dry etching conditions in the first patterning step are set so that the side surfaces of the n-GaN layer 604, the pGaN layer 605, and the n+GaN layer 606 of the functional section 600 become vertical surfaces (ie, surfaces perpendicular to the surface of the growth substrate 601).

[0229] Fig. 36(A) is a cross-sectional view showing a second patterning step for the growth substrate 601, the buffer layer 602, and the functional section 600. As shown in Fig. 36(A), the growth substrate 601, the buffer layer 602, and the n+GaN layer 603 are patterned into a second element shape. The second patterning step is performed by forming a photoresist (mask) (not shown) on the functional section 600 and performing dry etching.

[0230] In the second patterning step, dry etching is performed until the depth (overetching amount) t from the surface of the growth substrate 601 reaches 50 to 10,000 nm. As a result, a sacrificial layer 601a having approximately the same area as the lower surface of the buffer layer 602 is formed on the surface of the growth substrate 601.

[0231] Moreover, the dry etching conditions in the second patterning step are set so that the side surfaces of the buffer layer 602 and the n+GaN layer 603 are inclined. It is preferable that the dry etching conditions are set so that a step portion S is formed between the n+GaN layer 603 and the n-GaN layer 604.

[0232] Through these two patterning steps, the functional section 600 has a first portion (n+GaN layer 603) whose side surfaces are inclined, and a second portion (n-GaN layer 604, pGaN layer 605, and n+GaN layer 606) whose side surfaces are vertical. Note that the side surfaces of the second portion are not limited to being vertical, and may have a different inclination from that of the first portion.

[0233] Fig. 36(B) is a cross-sectional view showing a step of etching the growth substrate 601. As shown in Fig. 36(B), the growth substrate 601 is etched in the surface direction, that is, in the (100) direction, by wet etching using KOH.

[0234] The sacrificial layer 601a of the growth substrate 601 may be partially etched as described with reference to Fig. 2(B) in the first embodiment, or may be completely removed as described with reference to Fig. 2(C), so that the functional section 600 can be easily separated from the growth substrate 601.

[0235] Fig. 37(A) is a cross-sectional view showing a step of separating the buffer layer 602 and the functional unit 600 from the growth substrate 601. As shown in Fig. 37(A), a stamp 620 is attached as a holding member to the upper surface of the functional unit 600 (the surface opposite to the growth substrate 601), and the buffer layer 602 and the functional unit 600 are separated from the growth substrate 601. The configuration of the stamp 620 is similar to that of the stamp 120 of the first embodiment.

[0236] When the buffer layer 602 and the functional section 600 are separated from the growth substrate 601, warping of the buffer layer 602 and the functional section 600 becomes evident as described in the fourth embodiment.

[0237] Fig. 37(B) is a cross-sectional view showing a step of removing buffer layer 602. As shown in Fig. 37(B), buffer layer 602 is removed by etching or polishing such as CMP. This exposes lower surface 603a of n+GaN layer 603 of functional section 600. By removing buffer layer 602, the warpage of functional section 600 is alleviated, but not completely eliminated.

[0238] Fig. 38(A) is a cross-sectional view showing a step of forming a first metal film 610. As shown in Fig. 38(A), a first metal film 610 is formed on a lower surface 603a of an n+ GaN layer 603 of a functional section 600. The first metal film 610 is an electrode for the n+ GaN layer 603, and is composed of a multilayer film.

[0239] First metal film 610 is formed so as to wrap around from lower surface 603a to side surface 603b of n+ GaN layer 603. The angle between lower surface 603a and side surface 603b of n+ GaN layer 603 is larger than angle R (FIG. 4(B)) described in the first embodiment, and is, for example, 80 to 90 degrees.

[0240] Fig. 38(B) is an enlarged view of a portion surrounded by the symbol A in Fig. 38(A). It is an enlarged view of a first metal film 610. The first metal film 610 has, in order from the n+GaN layer 603 side, a first layer 611 made of Ti, a second layer 612 made of Al, a third layer 613 made of Ti, a fourth layer 614 made of Pt, and a fifth layer 615 made of Au. The method of forming each layer is as described with reference to Figs. 12(A) to (E) in the second embodiment.

[0241] As described in the second embodiment, when forming the first metal film 610 by sputtering or vapor deposition, for example, the functional part 600 is separated from the growth substrate 601 as shown in FIG. 37(B), and metal atoms for forming the first metal film 610 are deposited toward the lower surface 603a, so that the first metal film 610 is formed from the lower surface 603a to the side surface 603b.

[0242] At this time, since the side surface 603b of the n+GaN layer 603 is an inclined surface having an angle of 45 to 90 degrees (more preferably 60 degrees or more and less than 90 degrees) with respect to the lower surface 603a, the first metal film 610 can be formed so as not to contact the side surface of the n-GaN layer 604. By not contacting the first metal film 610 with the n-GaN layer 604, it is possible to prevent a decrease in the withstand voltage of the n-GaN layer 604 (active layer).

[0243] Furthermore, in the sixth embodiment, since two-stage etching is performed (FIGS. 35(B) and 36(A)), a step portion S can be formed between n+GaN layer 603 and n-GaN layer 604. This allows the side surface of n-GaN layer 604 to be retracted toward the inside of functional section 600 relative to side surface 603b of n+GaN layer 603. This makes it difficult for first metal film 610 to come into contact with n-GaN layer 604, thereby enhancing the effect of preventing a decrease in the breakdown voltage of n-GaN layer 604.

[0244] Furthermore, since the fourth layer 614 (Pt) is formed between the second layer 612 (Al) and the fifth layer 615 (Au) of the first metal film 610 so as to wrap around the side surface 603b of the n+GaN layer 603 as shown in FIG. 38(B), it is possible to prevent an increase in electrical resistance due to the eutectic of Al and Au during the annealing treatment described later.

[0245] Fig. 39(A) is a cross-sectional view showing a step of transferring the functional unit 600 to a device substrate 630. As shown in Fig. 39(A), the functional unit 600 held by the stamp 620 is transferred to a device substrate 630 serving as a second substrate. The device substrate 630 is similar to the device substrate 430 described in the fourth embodiment.

[0246] A second metal film 640 is formed on the surface of the device substrate 630. Fig. 39(B) is an enlarged cross-sectional view showing the second metal film 640 on the surface of the device substrate 630. As shown in Fig. 39(B), the second metal film 640 has a first layer 641, a second layer 642, and a third layer 643, in this order from the device substrate 630 side (lower side).

[0247] The first layer 641 to the third layer 643 of the second metal film 640 are formed in the same manner as the first layer 441 to the third layer 443 of the second metal film 440 described in the embodiment 4. For each layer of the metal films 610 and 640, the combinations shown in Table 1 of the embodiment 2 may be used.

[0248] When transferring the functional section 600 to the device substrate 630, the first metal film 610 and the second metal film 640 are bonded together by applying a predetermined pressure, after which the stamp 620 is peeled off from the upper surface of the functional section 600 and removed.

[0249] Fig. 40(A) is a cross-sectional view showing a process of bonding the metal films 610, 640 of the functional section 600 and the device substrate 630. As shown in Fig. 40(A), in a state where the first metal film 610 and the second metal film 640 are bonded together, an annealing treatment is performed at 500 to 800 degrees.

[0250] This bonds the first metal film 610 and the second metal film 640. Even if the functional section 600 is warped due to the pressure applied during bonding and the subsequent annealing treatment, the first metal film 610 and the second metal film 640 are bonded without any gaps.

[0251] Furthermore, the annealing process provides ohmic contact between the n+GaN layer 603 of the functional unit 600 and the first layer 611 (Ti) and the second layer 612 (Au) of the first metal film 610. Furthermore, the outermost fifth layer 615 (Au) of the first metal film 610 formed on the functional unit 600 and the third layer 643 (Au), which is the uppermost layer of the second metal film 640 on the device substrate 630, are integrated together.

[0252] Fig. 40(B) is a cross-sectional view showing a process of forming an insulating film 651 on the functional section 600. As shown in Fig. 40(B), the insulating film 651 is formed so as to cover the device substrate 630 and the functional section 600. The insulating film 651 is an oxide film such as SiO2, Al2O3, etc., has a thickness of about 10 nm to 1 µm, and is formed by sputtering or deposition.

[0253] Fig. 41(A) is a cross-sectional view showing a process of forming and patterning a photoresist 652 on an insulating film 651. As shown in Fig. 41(A), a photoresist 652 is formed by, for example, spin coating on the insulating film 651 covering the functional section 600. Furthermore, the photoresist 652 is patterned to form an opening 653 at a position where a trench, which will be described later, is to be formed.

[0254] Fig. 41(B) is a cross-sectional view showing a step of forming a trench 607 in the functional unit 600. As shown in Fig. 41(B), dry etching is performed via a photoresist 652 to form a trench 607 in the functional unit 600, the trench reaching the n-GaN layer 604 (drift layer).

[0255] Fig. 42(A) is a cross-sectional view showing a step of forming an insulating film 651 and a photoresist 652 in a trench 607. As shown in Fig. 42(A), an insulating film 651 is formed by, for example, CVD or ALD so as to cover the inner surface of the trench 607. Furthermore, a photoresist 652 is formed by, for example, spin coating so as to cover the insulating film 651 in the trench 607.

[0256] Fig. 42(B) is a cross-sectional view showing a step of forming an opening 654 in the photoresist 652. As shown in Fig. 42(B), the photoresist 652 is exposed to light and developed to form an opening 654 at a position where a source electrode 661 (described later) is to be formed.

[0257] 43(A) is a cross-sectional view showing a step of forming a groove 655 in the functional unit 600. As shown in FIG. 43(A), dry etching is performed via a photoresist 652 to form a groove 655 for forming a source electrode 661 in the functional unit 600. The groove 655 is formed so as to reach the pGaN layer 605.

[0258] 43B, the photoresist 652 is exposed and developed to form an opening 656 that is slightly larger than the groove 655 at a position that overlaps the groove 655. The photoresist 652 in the trench 607 is then removed.

[0259] 44(A) is a cross-sectional view showing a step of forming a source electrode 661 and a gate electrode 662. The source electrode 661 is formed so as to fill the groove 655 of the functional portion 600 and the opening 656 of the photoresist 652. The source electrode 661 is made of, for example, Ti or Al, and is formed by sputtering or vapor deposition.

[0260] Furthermore, a gate electrode 662 is formed in the trench 607 of the functional section 600. The gate electrode 662 is made of, for example, Pd or Mo, and is formed by sputtering or vapor deposition.

[0261] Fig. 44(B) is a cross-sectional view showing a step of removing the photoresist 652. As shown in Fig. 49(B), the photoresist 652 covering the functional section 600 is removed by peeling or dissolving in an organic solvent.

[0262] In this manner, the source electrode 661 and the gate electrode 662 are formed in the functional section 600, and the third layer 643 (Au) of the second metal film 640 on the device substrate 630 serves as a drain electrode. This completes the electronic device 60, which is a vertical GaN field effect transistor with a trench structure.

[0263] As described above, the electronic device 60 of the sixth embodiment includes the functional unit 600, the device substrate 630 as a substrate supporting the functional unit 600, the first metal film 610 as an electrode formed on the device substrate 630 side of the functional unit 600, and the second metal film 640 formed on the device substrate 630 and to which the first metal film 610 is bonded. The first metal film 610 is formed from the lower surface (first surface) 603a to a part of the side surface (second surface) 603b of the functional unit 600. Therefore, as in the first embodiment, even if the functional unit 600 is warped, the functional unit 600 can be well bonded to the device substrate 630, and peeling of the functional unit 600 can be prevented.

[0264] Furthermore, while the side surfaces of the first portion (n+GaN layer 603) of functional unit 600 are inclined, the side surfaces of the second portion (i.e., n-GaN layer 604, pGaN layer 605, and n+GaN layer 606) are not inclined, so that functional unit 600 can be formed larger than functional units 400 and 500 of embodiments 4 and 5.

[0265] Furthermore, in the direction parallel to the surface of the device substrate 630, the n-GaN layer 604 of the functional section 600 can be formed at a position retreated from the n+GaN layer 603, so that the first metal film 610 or the second metal film 640 is not brought into contact with the n-GaN layer 604, thereby preventing a decrease in the voltage resistance of the n-GaN layer 604.

[0266] Seventh Embodiment The seventh embodiment relates to an electronic device 70 as a planar vertical GaN field effect transistor (FET) device and a method for manufacturing the same.

[0267] Fig. 45(A) is a cross-sectional view showing a step of forming a buffer layer 702 and a functional section 700 on a growth substrate 701 in a manufacturing method of an electronic device 70 according to the seventh embodiment. The growth substrate 701 shown in Fig. 45(A) is, for example, a Si(111) substrate. Note that the growth substrate 701 is not limited to Si(111) and may be any substrate on which the functional section 700 described below can be grown.

[0268] A buffer layer 702, which is an AlN layer, is epitaxially grown on the surface of a growth substrate 701. The buffer layer 702 is a single layer of AlN here, but is not limited to this and may be, for example, a laminate of an AlN layer and an AlGaN layer. The thickness of the buffer layer 702 is, for example, 200 nm to 1 μm.

[0269] An n+GaN layer 703 serving as a contact layer is epitaxially grown on the buffer layer 702. The thickness of the n+GaN layer 703 is, for example, 5 μm or less.

[0270] Next, an n-GaN layer 704 serving as a drift layer is epitaxially grown on n+GaN layer 703. The thickness of n-GaN layer 704 is, for example, 2 to 50 μm.

[0271] Furthermore, a pGaN layer 705 is epitaxially grown on the n-GaN layer 704. The thickness of the pGaN layer 705 is, for example, 10 μm or less.

[0272] The n+GaN layer 703 , the n-GaN layer 704 and the pGaN layer 705 constitute the functional section 700 .

[0273] Fig. 45(B) is a cross-sectional view showing a process of patterning the growth substrate 701, the buffer layer 702, and the functional section 700. As shown in Fig. 45(B), the growth substrate 701, the buffer layer 702, and the functional section 700 are patterned into an element shape. The patterning is performed by forming a photoresist (mask) (not shown) on the functional section 700 and dry etching.

[0274] Dry etching is performed until the depth (overetching amount) t from the surface of the growth substrate 701 reaches 50 to 10,000 nm. As a result, a sacrificial layer 701a having approximately the same area as the lower surface of the buffer layer 702 is formed on the surface of the growth substrate 701.

[0275] The dry etching conditions are set so that the side surface of the functional section 700 is an inclined surface, as described in the first embodiment. The inclination direction of the functional section 700 is a direction in which the size of the surface parallel to the seventh surface (lower surface 703a described later) of the functional section 400 decreases upward (as it moves away from the lower surface). Here, a case where the side surface of the functional section 700 is an inclined surface will be described, but it is sufficient that at least the side surface 703b described later of the n+GaN layer 703 (contact layer) is an inclined surface.

[0276] Fig. 46(A) is a cross-sectional view showing a process of forming an insulating film 751 on the functional section 700. As shown in Fig. 46(A), the insulating film 751 is formed so as to cover the functional section 700. The insulating film 751 is an oxide film such as SiO2, Al2O3, etc., has a thickness of about 10 nm to 1 µm, and is formed by sputtering or deposition.

[0277] Furthermore, the insulating film 751 is patterned via a photoresist (not shown) on the insulating film 751, and an opening 752 is formed above a position where a groove 753 (FIG. 46(B)) to be described later is to be formed.

[0278] Fig. 46(B) is a cross-sectional view showing a step of forming grooves 753 in functional section 700. As shown in Fig. 46(B), grooves 753 reaching n-GaN layer 704 (drift layer) are formed in functional section 700 by dry etching.

[0279] 47(A) is a cross-sectional view showing a step of epitaxially growing n-GaN layer 704 in groove 753. As shown in FIG 47(A), n-GaN layer 704 is epitaxially grown so as to fill groove 753 of functional section 700.

[0280] Fig. 47(B) is a cross-sectional view showing a step of forming openings 754 in insulating film 751. As shown in Fig. 47(B), insulating film 751 is patterned via a photoresist (not shown) to remove a portion located on pGaN layer 705 to form openings 754. Openings 754 are formed on both sides of n-GaN layer 704 filled in grooves 753 (Fig. 46(B)).

[0281] 48(A) is a cross-sectional view showing a process of forming n+GaN layers 755, 756 by ion implantation into pGaN layer 705. As shown in FIG 48(A), Si ions are implanted into pGaN layer 705 through opening 754 in insulating film 751, to form n+GaN layers 755, 756.

[0282] Fig. 48(B) is a cross-sectional view showing a step of re-forming insulating film 751. As shown in Fig. 48(B), insulating film 751 is formed so as to cover n-GaN layer 704 and n+GaN layers 755 and 756 in groove portion 753.

[0283] Fig. 49(A) is a cross-sectional view showing a step of etching the growth substrate 701. As shown in Fig. 48(A), the growth substrate 701 is etched in the surface direction, that is, in the (100) direction, by wet etching using KOH.

[0284] The sacrificial layer 701a of the growth substrate 701 may be partially etched as described with reference to Fig. 2(B) in the first embodiment, or may be completely removed as described with reference to Fig. 2(C), so that the functional section 700 can be easily separated from the growth substrate 701.

[0285] Fig. 49(B) is a cross-sectional view showing a step of separating the buffer layer 702 and the functional unit 700 from the growth substrate 701. As shown in Fig. 49(A), a stamp 720 is attached as a holding member to the upper surface of the functional unit 700 (the surface opposite to the growth substrate 701), and the buffer layer 702 and the functional unit 700 are separated from the growth substrate 701. The configuration of the stamp 720 is similar to that of the stamp 120 of the first embodiment.

[0286] When the buffer layer 702 and the functional section 700 are separated from the growth substrate 701, warping of the buffer layer 702 and the functional section 700 becomes evident as described in the fourth embodiment.

[0287] Fig. 50(A) is a cross-sectional view showing a step of removing buffer layer 702 from functional section 700. As shown in Fig. 50(A), buffer layer 702 is removed by etching or polishing such as CMP. This exposes bottom surface 703a of n+GaN layer 703 of functional section 700. By removing buffer layer 702, the warpage of functional section 700 is alleviated, but not completely eliminated.

[0288] Fig. 50(B) is a cross-sectional view showing a step of forming a first metal film 710. As shown in Fig. 50(B), a first metal film 710 is formed on a lower surface 703a of an n+ GaN layer 703 of a functional section 700. The first metal film 710 is an electrode for the n+ GaN layer 703, and is composed of a multilayer film.

[0289] First metal film 710 is formed so as to wrap around from bottom surface 703a to side surface 703b of n+ GaN layer 703. The angle between bottom surface 703a and side surface 703b of n+ GaN layer 703 is 45 to 90 degrees, similar to angle R (FIG. 4(B)) described in the first embodiment, and is more preferably 60 degrees or more and less than 90 degrees.

[0290] As described in the second embodiment, when forming the first metal film 710 by sputtering or vapor deposition, for example, the functional part 700 is separated from the growth substrate 701 as shown in FIG. 50(A), and metal atoms for forming the first metal film 710 are deposited toward the lower surface 703a, so that the first metal film 710 is formed from the lower surface 703a to the side surface 703b.

[0291] At this time, since the side surface 703b of the n+GaN layer 703 is an inclined surface having an angle of 45 to 90 degrees (more preferably 60 degrees or more and less than 90 degrees) with respect to the bottom surface 703a, the first metal film 710 can be formed so as not to contact the side surface of the n-GaN layer 704. By not contacting the first metal film 710 with the n-GaN layer 704, it is possible to prevent a decrease in the voltage resistance of the n-GaN layer 704 (drift layer).

[0292] Furthermore, since the fourth layer 714 (Pt) is formed between the second layer 712 (Al) and the fifth layer 715 (Au) of the first metal film 710 so as to wrap around the side surface 703b of the n+GaN layer 703 as shown in FIG. 50(C), it is possible to prevent an increase in electrical resistance due to the eutectic of Al and Au during the annealing treatment described later.

[0293] Fig. 50(C) is an enlarged view of the portion surrounded by the symbol A in Fig. 50(B). The first metal film 710 has a first layer 711 made of Ti, a second layer 712 made of Al, a third layer 713 made of Ti, a fourth layer 714 made of Pt, and a fifth layer 715 made of Au. The method of forming each layer is as described with reference to Figs. 12(A) to (E) in the second embodiment.

[0294] Fig. 51(A) is a cross-sectional view showing a step of transferring the functional unit 700 to a device substrate 770. As shown in Fig. 51(A), the functional unit 700 held by the stamp 720 is transferred to a device substrate 730 serving as a second substrate. The device substrate 730 is similar to the device substrate 430 described in the fourth embodiment.

[0295] A second metal film 740 is formed on the surface of the device substrate 730. Fig. 51(B) is an enlarged cross-sectional view showing the second metal film 740 on the surface of the device substrate 730. As shown in Fig. 51(B), the second metal film 740 has, in order from the device substrate 730 side, a first layer 741 made of Ti, a second layer 742 made of Pt, and a third layer 743 made of Au.

[0296] The first to third layers 741 to 743 are formed in the same manner as the first to third layers 441 to 443 of the second metal film 440 described in the embodiment 4. For each layer of the metal films 710 and 740 in the embodiment 7, the combinations shown in Table 1 in the embodiment 4 may be used.

[0297] When transferring the functional section 700 to the device substrate 730, the first metal film 710 and the second metal film 740 are bonded together by applying a predetermined pressure, after which the stamp 720 is peeled off from the upper surface of the functional section 700 and removed.

[0298] Fig. 52(A) is a cross-sectional view showing a process of bonding the metal films 710, 740 of the functional section 700 and the device substrate 730. As shown in Fig. 52(A), in a state where the first metal film 710 and the second metal film 740 are bonded together, an annealing treatment is performed at 500 to 800 degrees.

[0299] This bonds the first metal film 710 and the second metal film 740. Even if the functional section 700 is warped due to the pressure applied during bonding and the subsequent annealing treatment, the first metal film 710 and the second metal film 740 are bonded without any gaps.

[0300] Furthermore, the annealing process provides ohmic contact between the n+GaN layer 703 of the functional unit 700 and the first layer 711 (Ti) and the second layer 712 (Au) of the first metal film 710. Furthermore, the outermost fifth layer 715 (Au) of the first metal film 710 formed on the functional unit 700 and the third layer 743 (Au), which is the uppermost layer of the second metal film 740 on the device substrate 730, are integrated together.

[0301] Fig. 52(B) is a cross-sectional view showing a step of patterning the insulating film 751. As shown in Fig. 58(A), the insulating film 751 on the functional section 700 is patterned and removed except for a portion where a gate electrode 763 (Fig. 53) to be described later is to be formed.

[0302] Fig. 53 is a cross-sectional view showing a process of forming source electrodes 761, 762 and gate electrode 763. As shown in Fig. 53, source electrode 761 is formed so as to straddle n+GaN layer 755 and pGaN layer 705 on one side, and source electrode 762 is formed so as to straddle n+GaN layer 756 and pGaN layer 705 on the other side. Source electrodes 761, 762 are made of, for example, Ti or Al, and are formed by sputtering or deposition.

[0303] Furthermore, a gate electrode 763 is formed on the insulating film 751 that spans the two n+GaN layers 755 and 756. The gate electrode 763 is made of, for example, Pd or Mo, and is formed by sputtering or vapor deposition.

[0304] In this manner, the source electrodes 761, 762 and the gate electrode 763 are formed in the functional section 700, and the third layer 743 (Au) of the second metal film 740 on the device substrate 730 serves as a drain electrode. This completes the electronic device 70, which is a planar-type vertical GaN field effect transistor.

[0305] As described above, the electronic device 70 of the seventh embodiment includes the functional unit 700, the device substrate 630 as a substrate supporting the functional unit 700, the first metal film 710 as an electrode formed on the device substrate 630 side of the functional unit 700, and the second metal film 740 formed on the device substrate 730 and to which the first metal film 710 is bonded. The first metal film 410 is formed from the lower surface (first surface) 703a to a part of the side surface (second surface) 703b of the functional unit 700. Therefore, as in the first embodiment, even if the functional unit 700 is warped, the functional unit 700 can be well bonded to the device substrate 630 and peeling of the functional unit 700 can be prevented.

[0306] The above-mentioned first to seventh embodiments can be combined as appropriate.

[0307] The functional layer 102 (functional portion) of the first embodiment is made of AlN, and the functional portions 200, 300, 400, 500, 600, and 700 of the second to seventh embodiments are made of GaN. However, the functional portion in the present disclosure is not limited to AlN and GaN, and may be any epitaxial layer containing a nitride. In addition to the epitaxial layer containing a nitride, the functional portion may be, for example, a GaAs-based semiconductor layer, or a piezoelectric element layer such as PZT, LN, or LT.

[0308] In addition, in the first to seventh embodiments, the functional layer (AlN layer, GaN layer) formed on the growth substrate is patterned for each element (each electronic device) and then transferred to the device substrate, but the present invention is not limited to such an example. For example, a functional layer (AlN layer, GaN layer) including multiple elements may be formed on the growth substrate, transferred to the device substrate, and then patterned for each element.

[0309] In the first to seventh embodiments, the functional units are formed on the growth substrate in electronic device units and then transferred to the transfer substrate, but N (e.g., four) functional units may be formed in a matrix (e.g., two rows and two columns) on the growth substrate. In this case, a first metal film may be formed on each of the N functional units, and a second metal film bondable to the N functional units may be formed on the device substrate, and the N functional units may be transferred thereto.

[0310] Although the preferred embodiments have been specifically described above, the present disclosure is not limited to the above-described embodiments, and various improvements and modifications can be made.

[0311] The present disclosure can be applied to electronic devices such as piezoelectric devices, photoelectric conversion devices (eg, LED devices), and semiconductor devices (eg, Schottky barrier diodes, field effect transistors), and methods for manufacturing the same.

[0312] Various aspects of the present disclosure are summarized below as appendices. (Appendix 1) A functional part; A substrate supporting the functional unit; a first metal film as an electrode formed on the substrate side of the functional unit; a second metal film formed on the substrate and to which the first metal film is bonded; having The functional unit includes: a first surface facing the substrate via the first metal film; a second surface extending from the first surface in a direction different from the extending direction of the first surface; having The first metal film is formed from the first surface to a part of the second surface in the functional portion. 1. An electronic device comprising: (Appendix 2) the functional portion has an inclined surface that is inclined such that a size in a plane parallel to the first surface decreases with increasing distance from the first surface, The second surface is the inclined surface. 2. The electronic device according to claim 1 . (Appendix 3) The functional unit includes: a contact layer having the first surface and the second surface; At least one semiconductor layer formed on the contact layer; 3. The electronic device according to claim 1 or 2, comprising: (Appendix 4) the first metal film has a plurality of metal layers; Each of the plurality of metal layers is formed so as to cover the layer closer to the functional section. 4. An electronic device according to claim 1, (Appendix 5) the functional portion has, from a side closer to the substrate, a first portion and a second portion, The side surface of the first portion and the side surface of the second portion have different inclination angles. 5. An electronic device according to any one of claims 1 to 4. (Appendix 6) the first metal film has an Al layer and an Au layer; A metal barrier layer containing at least one of Ti, Pt, and Mo is formed between the Al layer and the Au layer. 6. An electronic device according to any one of claims 1 to 5, (Appendix 7) The second metal film has a plurality of metal layers. 7. An electronic device according to any one of claims 1 to 6, (Appendix 8) The functional portion is an epitaxial layer including a nitride. 8. An electronic device according to any one of claims 1 to 7, (Appendix 9) a first metal film is formed on a first surface and a second surface extending from the first surface in a direction different from an extending direction of the first surface in a functional portion and over a part of the second surface; The first metal film formed on the functional portion is bonded to a second metal film formed on a substrate. 2. A method for producing an electronic device comprising the steps of: (Appendix 10) The functional unit is a functional unit separated from a first substrate different from a second substrate as the substrate, The first surface is a surface of the functional unit on a side separated from the first substrate. 10. A method for producing an electronic device according to claim 9, (Appendix 11) Before forming the first metal film, the functional section and the buffer layer epitaxially grown on the first substrate via a buffer layer are separated from the first substrate; removing the buffer layer from the functional portion; The first metal film is formed on the first surface of the functional section from which the buffer layer has been removed. 11. A method for producing an electronic device according to claim 10, [Explanation of symbols]

[0313] 10,20,30,40,60,70 Electronic device; 101,201,301,401,501,601,701 Growth substrate (first substrate); 101a,201a,301a,401a,501a,601a,701a Sacrificial layer; 102 Functional layer (functional portion); 102a,203a,303a,403a,503a,603a,703a Lower surface (first surface); 102b,203b,303b,403b,503b,603b,703b Side surface (second surface); 110,210,310,410,510,610,710 First metal film; 120,220,320,420,520,620,720 stamp (holding member), 130,230,330,430,530,630,730 device substrate (second substrate, substrate), 140,240,340,440,540,640,740 second metal film, 200,300,400,500,600,700 functional part, 202,302,402,502,602,702 buffer layer, 203 n+GaN layer (contact layer), 204 n-GaN layer (drift layer), 230 device substrate, 303 nGaN layer (contact layer), 304 nAlGaN layer (cladding layer), 305 InGaN layer (active layer), 306 pAlGaN layer (cladding layer), 307 pGaN layer (contact layer), 403,503,603,703 n+GaN layer (contact layer), 404,504,604,704, n-GaN layer (drift layer), 405,505,605,705 pGaN layer (contact layer), 406,506,606 n+GaN layer, 407,507,607 Trench.

Claims

1. A functional part; A substrate supporting the functional unit; a first metal film as an electrode formed on the substrate side of the functional unit; a second metal film formed on the substrate and to which the first metal film is bonded; having The functional unit includes: a first surface facing the substrate via the first metal film; a second surface extending from the first surface in a direction different from the extending direction of the first surface; having The first metal film is formed from the first surface to a part of the second surface in the functional portion.

1. An electronic device comprising:

2. the functional portion has an inclined surface that is inclined such that a size in a plane parallel to the first surface decreases with increasing distance from the first surface, The second surface is the inclined surface.

2. The electronic device according to claim 1 .

3. The functional unit includes: a contact layer having the first surface and the second surface; At least one semiconductor layer formed on the contact layer; 3. The electronic device according to claim 1, further comprising:

4. the first metal film has a plurality of metal layers; Each of the plurality of metal layers is formed so as to cover the layer closer to the functional section.

3. The electronic device according to claim 1 or 2.

5. The functional portion has a first portion and a second portion from a side closer to the substrate, The side surface of the first portion and the side surface of the second portion have different inclination angles.

3. The electronic device according to claim 1 or 2.

6. the first metal film has an Al layer and an Au layer; A metal barrier layer containing at least one of Ti, Pt, and Mo is formed between the Al layer and the Au layer.

3. The electronic device according to claim 1 or 2.

7. The second metal film has a plurality of metal layers.

3. The electronic device according to claim 1 or 2.

8. The functional portion is an epitaxial layer including a nitride.

3. The electronic device according to claim 1 or 2.

9. a first metal film is formed on a first surface and a second surface extending from the first surface in a direction different from an extending direction of the first surface in a functional portion and over a part of the second surface; The first metal film formed on the functional portion is bonded to a second metal film formed on a substrate.

2. A method for producing an electronic device comprising the steps of:

10. The functional unit is a functional unit separated from a first substrate different from a second substrate as the substrate, The first surface is a surface of the functional portion on a side separated from the first substrate. The method for manufacturing an electronic device according to claim 9 .

11. Before forming the first metal film, the functional section and the buffer layer epitaxially grown on the first substrate via a buffer layer are separated from the first substrate; removing the buffer layer from the functional portion; The first metal film is formed on the first surface of the functional portion from which the buffer layer has been removed. The method for manufacturing an electronic device according to claim 10 .

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