A / d conversion device and battery monitoring integrated circuit device

Abstract

To provide an A / D conversion device and a battery monitoring integrated circuit device, which have two or more operating modes and in which a reference voltage applied to a quantizer can be set for each mode.SOLUTION: An A / D conversion device 101 includes: an integrator 11 into which an input signal and the output of a DAC 13 are input; a quantizer 12 to which a reference potential is applied and into which the output of the integrator 11 is input; the DAC 13 for performing DA conversion of the output of the quantizer 12; a control circuit 10 for performing switching operation between two or more operating modes including a second-order ΔΣ mode and a cyclic mode; and a potential generating circuit 14 capable of switching the reference potential to be applied to the quantizer 12 in accordance with the operating mode.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to an A / D conversion device and a battery monitoring integrated circuit device. [Background technology]

[0002] The applicant of the present application has proposed a technology for performing AD conversion processing using a hybrid mode that combines the ΔΣ method and the cyclic method, and has further proposed an A / D conversion device that operates in at least two modes: the ΔΣ mode of the ΔΣ method, the hybrid mode that combines the ΔΣ method and the cyclic method, and the cyclic mode of the cyclic method (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2021-044632 Summary of the Invention [Problem to be solved by the invention]

[0004] For example, in the case of a battery monitoring integrated circuit device that has a low-speed, high-precision battery status detection function and a high-speed, low-precision fault diagnosis function, implementing two A / D conversion devices to accommodate two different specifications would result in an increase in the circuit implementation area and power consumption.

[0005] Furthermore, if one A / D conversion device is implemented so that it can switch between multiple operating modes, the reference potential becomes fixed, causing the integrator operation in the A / D conversion device to become saturated and unstable, resulting in a deterioration in accuracy. Furthermore, providing a quantizer and a reference voltage generation circuit for each operating mode increases the overall power consumption of the quantizer and also increases the circuit implementation area.

[0006] The present invention has been made in consideration of the above circumstances, and has an object to provide an A / D conversion device and a battery monitoring integrated circuit device in which the reference potential to be applied to the quantizer can be set for each operating mode. [Means for solving the problem]

[0007] The invention described in claim 1 comprises an integrator to which an input signal and the output of a DAC are input, a quantizer to which a reference potential is applied and to which the output of the integrator is input, the DAC that performs digital-to-analog conversion of the output of the quantizer, a control circuit that switches between two or more operating modes including a second-order ΔΣ mode and a cyclic mode, and a potential generating circuit that can switch the reference potential applied to the quantizer depending on the operating mode.

[0008] According to the invention of claim 1, the reference potential applied by the potential generating circuit to the quantizer can be switched in accordance with two or more operation modes, and the reference potential to be applied to the quantizer can be set for each operation mode. [Brief description of the drawings]

[0009] [Figure 1] FIG. 1 is a block diagram showing an electrical configuration of an A / D conversion device according to a first embodiment. [Diagram 2] Electrical configuration block diagram of a battery monitoring integrated circuit device according to a first embodiment [Diagram 3] FIG. 1 is a block diagram showing an electrical configuration of a specific example of an A / D conversion device according to a first embodiment. [Figure 4] FIG. 1 is a detailed circuit diagram of a specific example of an A / D conversion device according to the first embodiment (basic switch states in ΔΣ mode); [Diagram 5] FIG. 1 is a detailed circuit diagram of a specific example of an A / D conversion device according to a first embodiment (basic switch states in cyclic mode and hybrid mode); [Figure 6] Electrical configuration diagram 1 showing a part of the DAC in the first embodiment [Figure 7] Electrical configuration diagram showing part of the DAC in the first embodiment, part 2 [Figure 8]Electrical configuration diagram 3 showing a part of the DAC in the first embodiment [Figure 9] Electrical configuration diagram showing part of the DAC in the first embodiment, part 4 [Figure 10] FIG. 1 is a diagram for explaining signal transmission paths in a cyclic mode and a hybrid mode in the first embodiment. [Figure 11] Electrical configuration diagram of a telescopic amplifier in the second embodiment [Figure 12] Electrical configuration diagram of a potential generating circuit in the third embodiment [Figure 13] Electrical configuration diagram of a potential generating circuit in the fourth embodiment [Figure 14] Electrical configuration diagram of the switch in the fourth embodiment DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Hereinafter, several embodiments of the A / D conversion device will be described. In each embodiment described below, components that perform the same or similar operations are denoted by the same or similar reference numerals, and descriptions thereof will be omitted as necessary.

[0011] (First embodiment) First, in order to explain the technical essence, the configuration of an A / D conversion device 101 will be described with reference to Fig. 1. The A / D conversion device 101 shown in Fig. 1 performs AD conversion processing on an analog input signal Vin to obtain a high-resolution digital output, and is configured using a ΔΣ modulator equipped with an integrator 11, a DAC 13, a quantizer 12, a potential generating circuit 14, an adder / subtractor 15, and a control circuit 10. ΔΣ modulation is a type of pulse modulation method.

[0012] The integrator 11 receives the analog input signal Vin and the output of the DAC 13. Specifically, the integrator 11 receives and integrates the result of adding the output of the DAC 13 to the analog input signal Vin by the adder-subtractor 15, or subtracting the output of the DAC 13 from the analog input signal Vin.

[0013] The quantizer 12 is composed of, for example, a comparator, to which a reference potential Vref is applied from the potential generating circuit 14 and to which the output of the integrator 11 is input, and which outputs the result of comparing the output of the integrator 11 with the reference potential Vref.

[0014] The quantizer 12 is configured as a continuous time amplifier type or a dynamic type. The potential generating circuit 14 includes a reference potential changeover switch 14a, and switches a reference potential Vref by the reference potential changeover switch 14a so that the output of the integrator 11 can be quantized by the quantizer 12, and outputs the reference potential Vref to the quantizer 12. The DAC 13 converts the output of the quantizer 12 and outputs it to the adder / subtracter 15. The output of the quantizer 12 is used as the output of the A / D conversion device 101.

[0015] The potential generating circuit 14 makes it possible to switch the reference potential Vref applied to the quantizer 12 according to the operation mode. For example, if the quantization bit of the quantizer 12 has three levels, the reference potential Vref having two levels, which is one level less than the three levels, is switched for each operation mode and output to the quantizer 12. The quantizer 12 quantizes the input signal by comparing it with the two-level reference potential Vref.

[0016] The control circuit 10 switches between two or more operation modes including at least a second-order ΔΣ mode and a cyclic mode. The ΔΣ mode refers to a mode in which the analog input signal Vin is AD converted by the ΔΣ method, and among them, the second-order ΔΣ mode refers to a mode in which the analog input signal Vin is processed by the ΔΣ method using integrators 11 (a first-order integrator 11a and a second-order integrator 11b described later) connected in cascade in two stages.

[0017] The cyclic mode refers to a mode in which the analog input signal Vin is AD converted in a cyclic manner. In addition, the operation modes that can be set by the control circuit 10 may include a hybrid mode in which the analog residue is AD converted in a cyclic manner after AD conversion in a ΔΣ manner, and may be configured to switch between three or more operation modes.

[0018] The hybrid mode refers to a mode in which the analog input signal Vin is AD converted using the primary ΔΣ method for the most significant bits, and then the analog residual is AD converted using the cyclic method. In the hybrid mode, the primary ΔΣ operation is performed at the start of AD conversion of the analog input signal Vin, and the on / off state of the switch is switched during the AD conversion to perform a cyclic operation, and the AD conversion result of the primary ΔΣ operation and the AD conversion result of the cyclic operation are combined and output as the AD conversion result of the hybrid mode.

[0019] The first-order ΔΣ mode indicates a mode in which processing is performed by first-order ΔΣ operation using a single-stage integrator 11. The control circuit 10 switches between these operation modes and controls in accordance with the operation mode.

[0020] When the control circuit 10 operates the A / D conversion device 101 in the ΔΣ mode, it switches the switch SW to connect the digital filter 16 to the rear stage of the A / D conversion device 101, thereby using the output of the digital filter 16 as output data. When the control circuit 10 operates the A / D conversion device 101 in the cyclic mode or hybrid mode, it uses the output of the A / D conversion device 101 as it is as output data.

[0021] In addition, in the hybrid mode, the A / D conversion device 101 combines and combines the AD conversion result of the primary ΔΣ operation and the AD conversion result of the cyclic operation using a circuit in which a shift register and a digital accumulator circuit are cascade-connected (not shown). In the hybrid mode, the A / D conversion device 101 combines the AD conversion result of the primary ΔΣ operation as the upper bits and the AD conversion result of the cyclic operation as the lower bits.

[0022] ​Next, a method of applying the A / D conversion device 101 shown in Fig. 1 will be described. As shown in Fig. 2, the A / D conversion device 101 can be incorporated into a battery monitoring integrated circuit device 1. The battery monitoring integrated circuit device 1 monitors a battery 3, a battery pack 4, and the like mounted on a vehicle, and is configured as, for example, an ASIC. The battery 3 is a lead battery that serves as a battery auxiliary, and its positive terminal is connected to a vehicle load (not shown) via a transistor Q1, a shunt resistor Rs1, and a transistor Q2. The negative terminal of the battery 3 is connected to a ground line Lg. The ground line Lg is connected to the ground GND of the battery monitoring integrated circuit device 1.

[0023] The battery pack 4 is configured with multiple battery cells 4a, 4b...4c, which are secondary batteries such as lithium ion batteries, connected in series in multiple stages. A common mode voltage is superimposed on the multiple battery cells 4a, 4b...4c. The common mode voltage is higher for battery cells connected to the upper stage of the battery pack 4, i.e., the higher potential side. Note that in FIG. 1 and other figures, two battery cells 4a-4b of the multiple battery cells 4a, 4b...4c and their corresponding configurations are illustrated, along with the bottommost battery cell 4c.

[0024] The positive terminal of the battery cell 4a located in the uppermost stage of the battery pack 4, i.e., on the highest potential side, is connected to the vehicle load via transistor Q3, shunt resistor Rs2, and transistor Q4. The negative terminal of the battery cell 4c located in the lowermost stage of the battery pack 4, i.e., on the lowest potential side, is connected to the ground line Lg.

[0025] The power supply path of the battery 3 to the vehicle load can be opened and closed by transistor Q1. In addition, the power supply path of the battery cell 4a to the vehicle load can be opened and closed by transistors Q3 and Q4. The battery monitoring integrated circuit device 1 has functions such as detecting the current flowing through the battery 3 by shunt resistor Rs1, detecting the current flowing through the battery pack 4, i.e., battery cells 4a-4c, by shunt resistor Rs2, and detecting the voltages of the battery cells 4a, 4b.

[0026] The battery monitoring integrated circuit device 1 has terminals P1 and P2 corresponding to the respective terminals of the shunt resistor Rs1 and terminals P3 and P4 corresponding to the respective terminals of the shunt resistor Rs2. Each terminal of the shunt resistor Rs1 is connected to the terminals P1 and P2 via a filter 5 for removing noise. The filter 5 is an RC filter including a resistor R1 connected between the high potential terminal of the shunt resistor Rs1 and the terminal P1, a resistor R2 connected between the low potential terminal of the shunt resistor Rs1 and the terminal P2, and a capacitor C1 connected between the terminals P1 and P2.

[0027] Each terminal of the shunt resistor Rs2 is connected to terminals P3, P4 via a filter 6. The filter 6 is an RC filter configured similarly to the filter 5, and includes resistors R3, R4 and a capacitor C2. The battery monitoring integrated circuit device 1 includes terminals P5, P6 corresponding to each terminal of the battery cell 4a, terminals P7, P8 corresponding to each terminal of the battery cell 4b, and a terminal P9 for supplying a ground potential (0V).

[0028] Each terminal of the battery cell 4a is connected to terminals P5, P6 via a filter 7. Filter 7 is an RC filter configured similarly to filter 5, etc., and includes resistors R5, R6 and a capacitor C3. Each terminal of the battery cell 4b is connected to terminals P7, P8 via a filter 8. Filter 8 is an RC filter configured similarly to filter 5, etc., and includes resistors R7, R8 and a capacitor C4. The negative terminal of the battery cell 4c, i.e., the ground line Lg, is connected to terminal P9.

[0029] The battery monitoring integrated circuit device 1 includes a multiplexer 9 and an A / D conversion device 101. The multiplexer 9 includes switches S1 to S8, and one terminal of the switches S1 to S8 is connected to terminals P1 to P8, respectively. The other terminals of the switches S1, S3, S5, and S7 are commonly connected to a first output line Lo1. The other terminals of the switches S2, S4, S6, and S8 are commonly connected to a second output line Lo2. The control circuit 10 switches the switches S1 to S8 of the multiplexer 9, thereby enabling the voltage of the battery cells 4a, 4b...4c to be detected using the A / D conversion device 101, and further enabling the current flowing through the battery 3 or the assembled battery 4 to be detected.

[0030] Also, a chop switch 17 is provided between the output of the multiplexer 9 and the input of the A / D conversion device 101. The chop switch 17 is configured by combining switches S11 to S14 as shown in the figure. The control circuit 10 turns on the switches S11 and S13 and turns off the switches S12 and S14, so that the voltage of the output line can be input directly to the A / D conversion device 101. The control circuit 10 turns off the switches S11 and S13 and turns on the switches S12 and S14, so that the voltage of the output line can be inverted and input to the A / D conversion device 101. This makes it possible to switch the polarity of the analog input signal Vin of the A / D conversion device 101.

[0031] Hereinafter, a specific configuration example of the A / D conversion device 101 shown in Fig. 1 will be described with reference to Fig. 3 to Fig. 10. As shown in Fig. 3, the integrator 11 includes a first-order integrator 11a, a second-order integrator 11b, and an integrator output changeover switch 11c.

[0032] ​The primary integrator 11a receives the analog input signal Vin and the output of the DAC 13 through the adder-subtractor 15a. The secondary integrator 11b receives the output of the primary integrator 11a and the output of the DAC 13 through the adder-subtractor 15b. The integrator output changeover switch 11c can change over whether the input to the quantizer 12 is the output of the primary integrator 11a or the output of the secondary integrator 11b, and the control circuit 10 controls the changeover of the integrator output changeover switch 11c to change over whether the input to the quantizer 12 is the output of the primary integrator 11a or the output of the secondary integrator 11b. This makes it possible to switch between the primary ΔΣ mode of the primary ΔΣ method and the secondary ΔΣ mode of the secondary ΔΣ method described above.

[0033] Below, a specific configuration of the main parts of the A / D conversion device 101 will be described with reference to Figures 4 and 5, and the operations in the second-order ΔΣ mode, cyclic mode, and hybrid mode will be described. Figure 4 shows the basic switch states in the second-order ΔΣ mode, and Figure 5 shows the basic switch states in the cyclic mode and hybrid mode.

[0034] 4 and 5 includes a primary integrator 11a, a secondary integrator 11b, an integrator output changeover switch 11c, a quantizer 12, a DAC 13, and a potential generating circuit 14. An analog input signal Vin is input to an input terminal Tis of the primary integrator 11a.

[0035] The primary integrator 11a includes capacitor switching circuits 20p-23p and 20m-23m, and a fully differential operational amplifier 24. Capacitor switching circuits 20p-22p and 20m-22m are symmetrically connected to differential input terminals of the fully differential operational amplifier 24. In addition, a capacitor switching circuit 23p is connected between the non-inverting input terminal and the inverting output terminal of the fully differential operational amplifier 24, and a capacitor switching circuit 23m is connected between the inverting input terminal and the non-inverting output terminal.

[0036] ​The differential input terminals of the operational amplifier 24 are connected to the common output nodes of the capacitor switching circuits 20p-22p, 20m-22m, respectively. The differential output of the operational amplifier 24 is input to the input node of the secondary integrator 11b. In addition, in Fig. 4 and Fig. 5, the reference characters of the components on each side of the differential configuration are suffixed with "p, m", respectively. Since the configuration is symmetrical, in the following explanation, only the configuration on the side with the reference character suffixed with p will be explained, and the explanation of the configuration on the side with the reference character suffixed with m will be omitted.

[0037] The capacitor switching circuit 20p includes a capacitor Cs1p, switches SS11p to SS14p, SSD11p, and a D / A converter 25p shown in FIG. 6. The capacitor Cs1 is used as a sampling capacitance for sampling an analog input signal Vin input from an input terminal Tis. The capacitor Cs1p charges and discharges electric charge in response to the control circuit 10 switching the switches SS11p to SS14p on or off. One terminal of the capacitor Cs1p is connected to the input terminal Tis via the switch SS11p, and is connected to a common potential Vcm via the switch SS14p. The other terminal of the capacitor Cs1p is connected to an input node of the operational amplifier 24 via the switch SS13p, and is connected to a common potential Vcm via the switch SS12p.

[0038] Fig. 6 shows a partial equivalent circuit of the capacitor switching circuit 20p shown in Fig. 4. As shown in Fig. 4 and Fig. 6, the D / A converter 25p includes a switch SDD1*p and a capacitor Csd1p. As shown in Fig. 6, the switch SDD1*p shown in Fig. 4 is composed of a plurality of switches SDD1Tp, SDD1Mp, and SDD1Bp.

[0039] The capacitor Csd1p is used as a DAC capacitance of the D / A converter 25p. As shown in Fig. 4, a switch SSD11p is connected between the input terminal Tis and the other terminal of the capacitor Csd1p. The switch SSD11p is a switch that is controlled when the capacitor Csd1p is used as a sampling capacitance, and is configured to be on / off controllable by the control circuit 10. The capacitor Csd1p may also function as a sampling capacitance for sampling the analog input signal Vin input from the input terminal Tis through the switch SSD11p.

[0040] The control circuit 10 selectively turns on the switches SDD1Tp, SDD1Mp, and SDD1Bp to apply one of the D / A converter reference potentials Vrefp, Vcm, and Vrefm to the other terminal of the capacitor Csd1p. The D / A converter reference potentials Vrefp, Vcm, and Vrefm correspond to analog voltages obtained by D / A converting the quantized output of the quantizer 12, and have a relationship of, for example, Vrefp>Vcm>Vrefm, where Vcm is a common potential. In the following, the D / A converter output selected from the D / A converter reference potentials Vrefp, Vcm, and Vrefm is referred to as VR. The D / A converter reference potentials Vrefp, Vcm, and Vrefm are voltages that depend on the result of the quantizer 12 comparing the input signal with the reference potential Vref of the potential generating circuit 14.

[0041] The capacitor switching circuit 21p shown in Fig. 4 includes a capacitor Ccc1p, switches SC11p, SC14p, SCD11p to SCD13p, and a D / A converter 26p shown in Fig. 7. The capacitor Ccc1p is configured to charge and discharge electric charge in response to the control circuit 10 switching on or off the switches SC11p, SC14p, SCD12p, and SCD13p. One terminal of the capacitor Ccc1p is connected to the input node of the operational amplifier 24 via the switch SCD13p, and is connected to the node of the common potential Vcm via the switch SCD12p. The other terminal of the capacitor Ccc1p is connected to the output node of the primary integrator 11a via the switch SC11p, and is connected to the node of the common potential Vcm via the switch SC14p.

[0042] Fig. 7 shows a partial equivalent circuit of the capacitor switching circuit 21p shown in Fig. 4. As shown in Fig. 4 and Fig. 7, the D / A converter 26p includes a switch SCD1*p and a capacitor Ccd1p. The capacitor Ccd1p is used as a DAC capacitance of the D / A converter 26p. As shown in Fig. 7, the switch SCD1*p shown in Fig. 4 is composed of a plurality of switches SCD1Tp, SCD1Mp, and SCD1Bp.

[0043] The D / A converter 26p includes a plurality of switches SCD1Tp, SCD1Mp, SCD1Bp, and a capacitor Ccd1p. The control circuit 10 selectively switches on the switches SCD1Tp, SCD1Mp, SCD1Bp to apply one of the D / A converter reference potentials Vrefp, Vcm, and Vrefm to the other terminal of the capacitor Ccd1p as the D / A converter output VR. A switch SCD11p is connected between the output node of the primary integrator 11a and the other terminal of the capacitor Ccd1p. The switches SC11p and SCD11p are used when sampling the voltage of the output node of the primary integrator 11a to the capacitors Ccc1p and Ccd1p in a cyclic manner, and are configured to be on / off controllable by the control circuit 10.

[0044] The capacitor switching circuit 22p shown in Fig. 4 includes a capacitor Ccc2p, switches SC21p, SC24p, SCD21p to SCD23p, and a D / A converter 27p shown in Fig. 8. The capacitor Ccc2p is configured to charge and discharge electric charge in response to the control circuit 10 switching on or off the switches SC21p, SC24p, SCD22p, and SCD23p. One terminal of the capacitor Ccc2p is connected to the input node of the operational amplifier 24 via the switch SCD23p, and is connected to the node of the common potential Vcm via the switch SCD22p. The other terminal of the capacitor Ccc2p is connected to the output node of the primary integrator 11a via the switch SC21p, and is connected to the node of the common potential Vcm via the switch SC24p.

[0045] Fig. 8 shows a partial equivalent circuit of the capacitor switching circuit 21p shown in Fig. 4. As shown in Fig. 4 and Fig. 8, the D / A converter 27p includes a switch SCD2*p and a capacitor Ccd2p. The capacitor Ccd2p is used as a DAC capacitance of the D / A converter 27p. As shown in Fig. 8, the switch SCD2*p shown in Fig. 4 is composed of a plurality of switches SCD2Tp, SCD2Mp, and SCD2Bp.

[0046] The D / A converter 27p includes a plurality of switches SCD2Tp, SCD2Mp, SCD2Bp and a capacitor Ccd2p. The control circuit 10 selectively switches on the switches SCD2Tp, SCD2Mp, SCD2Bp to apply one of the D / A converter reference potentials Vrefp, Vcm, Vrefm as the D / A converter output VR to the other terminal of the capacitor Ccd2p. A switch SCD21p is connected between the output node of the primary integrator 11a and the other terminal of the capacitor Ccd2p. The switches SC21p, SCD21p are used when sampling the voltage of the output node of the primary integrator 11a to the capacitors Ccc2p, Ccd2p in a cyclic manner, and are configured to be on / off controllable by the control circuit 10.

[0047] The capacitor switching circuit 23p shown in Fig. 4 includes switches SF11p, SF14p, SA12p, and a capacitor Cf11. The capacitor Cf11 is configured as a feedback capacitor between the input node of the operational amplifier 24 and the output node of the primary integrator 11a. One terminal of the capacitor Cf11 is connected to the input node of the operational amplifier 24 and is connected to the node of the common potential Vcm via the switch SA12p. The other terminal of the capacitor Cf11p is connected to the output node of the primary integrator 11a via the switch SF11p and is connected to the node of the common potential Vcm via the switch SF14. As described above, the description of the connections on the side with the subscript m will be omitted.

[0048] The switches in the capacitor switching circuits 20p to 23p, 20m to 23m are listed as follows: primary integrator 11a includes switches SS11p to SS14p, SS11m to SS14m, SC11p, SC14p, SC11m, SC14m, SCD11p to SCD13p, SCD11m to SCD13m, SC21p, SC24p, SCD21p to SCD23p, SCD21m to SCD23m, SDD1*p, SCD1*p, SCD2*p, SF11p, SA12p, SF14p, SF11m, SA12m, and SF14m.

[0049] Furthermore, the input capacitors Cs1p, Csd1p, Cs1m and Csd1m and the capacitors Csd1p, Ccd1p, Ccd2p, Csd1m, Ccd1m and Ccd2m of the D / A converters 25p to 27p and 25m to 27m constituting the DAC 12 are configured to have the same capacitance value.

[0050] The control circuit 10 switches on and off the switches SS11p to SS14p, SS11m to SS14m, SC11p, SC14p, SC11m, SC14m, SCD11p to SCD13p, SCD11m to SCD13m, SC21p, SC24p, SCD21p to SCD23p, SCD21m to SCD23m, SDD1*p, SCD1*p, SCD2*p, SF11p, SA12p, SF14p, SF11m, SA12m, and SF14m, thereby The gain of a switched capacitor amplifier that combines SF11p, SA12p, SF14p, SF11m, SA12m, SF14m and capacitors Cs1p, Csd1p, Cs1m, Csd1m, Csd1p, Ccd1p, Ccd2p, Csd1m, Ccd1m, Ccd2m, Cf11p and Cf11m can be switched.

[0051] The capacitors Cs1p, Csd1p, Cs1m, Csd1m and the capacitors Csd1p, Ccd1p, Ccd2p, Csd1m, Ccd1m, Ccd2m may be configured by combining unit capacitors having the same area and unit capacitance in an array. This can prevent mismatching of the capacitance values ​​of these capacitors as much as possible. In addition, the gain error of the switched capacitor amplifier can be reduced, the input / output characteristics of the A / D conversion device 101 can be made highly linear, and low gain error can be achieved. Moreover, extra capacitors can be eliminated, allowing for minimization. Here, the capacitors Cs1p, Csd1p, Cs1m, Csd1m and the capacitors Csd1p, Ccd1p, Ccd2p, Csd1m, Ccd1m, Ccd2m constituting the primary integrator 11a have been described, but the capacitors (see below) constituting the secondary integrator 11b may also be configured to have the same capacitance value. Conversely, the capacitors may be configured to have different capacitance values.

[0052] A secondary integrator 11b is connected in cascade to the rear stage of the primary integrator 11a. The secondary integrator 11b includes capacitor switching circuits 20bp, 20bm, 23bp, and 23bm, and a fully differential operational amplifier 24b. The capacitor switching circuits 20bp and 20bm are symmetrically connected to the differential input terminals of the fully differential operational amplifier 24b.

[0053] A capacitor switching circuit 23bp is connected between the non-inverting input terminal and the inverting output terminal of the fully differential operational amplifier 24, and a capacitor switching circuit 23bm is connected between the inverting input terminal and the non-inverting output terminal. In the following explanation, as in the above, only the configuration on the side with the subscript p will be explained, and the explanation of the configuration on the side with the subscript m will be omitted.

[0054] The capacitor switching circuit 20bp includes a capacitor Cs2p, switches SS21p to SS24p, and a D / A converter 25bp shown in FIG. 8. The capacitor Cs2p is used as a sampling capacitance for sampling the output voltage input from the output node of the primary integrator 11a through the switch SS21p. The capacitor Cs2p charges and discharges electric charge in response to the switches SS21p to SS24p being switched on or off by the control circuit 10. The differential input terminals of the operational amplifier 24 are connected to the output nodes of the capacitor switching circuits 20bp and 20bm.

[0055] One terminal of the capacitor Cs2p is connected to the output node of the primary integrator 11a via a switch SS21p, and is connected to the node of the common potential Vcm via a switch SS24p. The other terminal of the capacitor Cs2p is connected to the input node of the operational amplifier 24b via a switch SS23p, and is connected to the node of the common potential Vcm via a switch SS22p.

[0056] Fig. 9 shows a partial equivalent circuit of the capacitor switching circuit 20bp shown in Fig. 4. As shown in Fig. 4 and Fig. 9, the D / A converter 25bp includes a switch SSD2*p and a capacitor Csd2p. As shown in Fig. 9, the switch SSD2*p shown in Fig. 4 is composed of a plurality of switches SCD2Tp, SCD2Mp, and SCD2Bp.

[0057] The D / A converter 25bp includes a plurality of switches SDD2Tp, SDD2Mp, SDD2Bp, and a capacitor Csd2. The control circuit 10 selectively switches on the switches SDD2Tp, SDD2Mp, SDD2Bp to apply one of the D / A converter reference potentials Vrefp, Vcm, Vrefm as the D / A converter output VR to the other terminal of the capacitor Csd2.

[0058] The capacitor switching circuit 23bp includes switches SF21p, SF24p, SA21p, and a capacitor Cf21p. The capacitor Cf21p is configured as a feedback capacitor between the input node and the output node of the operational amplifier 24b. One terminal of the capacitor Cf21p is connected to the output node of the operational amplifier 24b, and is also connected to the node of the common potential Vcm via the switch SA22p. The other terminal of the capacitor Cf21p is connected to the output node of the secondary integrator 11b via the switch SF21p, and is also connected to the node of the common potential Vcm via the switch SF24p. As described above, the configuration description of the side with the subscript m will be omitted.

[0059] <Integrator output changeover switch 11c and reference potential changeover switch 14a> The integrator output changeover switch 11c shown in Fig. 3 includes switches SCMP1p, SCMP2p, SCMP1m, and SCMP2m shown in Fig. 4. As shown in Fig. 4, the switches SCMP1p and SCMP1m are connected between the output node of the primary integrator 11a and the input node of the quantizer 12. In addition, the switches SCMP2p and SCMP2m are connected between the output node of the secondary integrator 11b and the input node of the quantizer 12.

[0060] The control circuit 10 can selectively input the output of the primary integrator 11a or the output of the secondary integrator 11b to the quantizer 12 by switching between turning on the switches SCMP1p and SCMP1m and turning off the switches SCMP2p and SCMP2m, or turning off the switches SCMP1p and SCMP1m and turning on the switches SCMP2p and SCMP2m.

[0061] On the other hand, the potential generating circuit 14 shown in FIG. 3 generates the reference potentials VREF1P, VREF2P, VREF1M, and VREF2M shown in FIG. 4 or FIG.

[0062] The reference potential changeover switch 14a of the potential generating circuit 14 is composed of switches SCP1p, SCP2p, SCP1m, and SCP2m, and outputs a plurality of reference potentials Vref to the quantizer 12. Specific configuration examples of the potential generating circuit 14 will be described in the third and fourth embodiments described later.

[0063] The control circuit 10 can input a reference potential Vref appropriate for the operating mode to the quantizer 12 by switching between turning on the switches SCP1p and SCP1m and turning off the switches SCP2p and SCP2m, or turning off the switches SCP1p and SCP1m and turning on the switches SCP2p and SCP2m.

[0064] 4 shows the basic states of the integrator output changeover switch 11c and the reference potential changeover switch 14a in the second-order ΔΣ mode. In the second-order ΔΣ mode, the control circuit 10 turns off the switches SCMP1p and SCMP1m and turns on the switches SCMP2p and SCMP2m to selectively input the output of the second-order integrator 11b to the quantizer 12. The control circuit 10 also turns on the switches SCP1p and SCP1m and turns off the switches SCP2p and SCP2m to selectively input the reference potential Vref suitable for the second-order ΔΣ mode to the quantizer 12.

[0065] 5 shows the basic states of the integrator output changeover switch 11c and the reference potential changeover switch 14a in the cyclic mode and the hybrid mode. In the cyclic mode and the hybrid mode, the control circuit 10 turns on the switches SCMP1p and SCMP1m and turns off the switches SCMP2p and SCMP2m to selectively input the output of the secondary integrator 11b to the quantizer 12. The control circuit 10 turns off the switches SCP1p and SCP1m and turns on the switches SCP2p and SCP2m to selectively input the reference potential Vref suitable for the cyclic mode or the hybrid mode to the quantizer 12.

[0066] In this way, it is desirable for the control circuit 10 to switch the integrator output changeover switch 11c and the reference potential changeover switch 14a in synchronization with the switching of the AD conversion operation mode, i.e., the switching between the quadratic ΔΣ mode, the cyclic mode, and the hybrid mode. Then, the reference potential Vref suitable for each operation mode can be provided to the quantizer 12.

[0067] The quantizer 12 compares the integrator output with a reference potential Vref, generates a three-level (1.5-bit) quantized output, and feeds it back to the DAC 13. Which of the above-mentioned D / A converter reference potentials Vrefp, Vcm, and Vrefm is output as the D / A converter output VR depends on the magnitude relationship of the input signal compared by the quantizer 12 with the reference potential Vref of the potential generating circuit 14. Therefore, even if the stable operation range and saturation level of the integrator output differ for each operation mode, the potential generating circuit 14 can select an appropriate reference from the D / A converter reference potentials Vrefp, Vcm, and Vrefm and output it as the D / A converter output VR by switching the reference potential Vref. This allows the integrator output to be controlled within the stable operation range, and A / D conversion to be performed with high accuracy.

[0068] <Explanation of each operation mode> The following is a brief description of the operation of the primary integrator 11a and the secondary integrator 11b in each of the secondary ΔΣ mode, cyclic mode, and hybrid mode. In the following description of the operation, the switches that the control circuit 10 controls to be on in each operation mode are described, and the switches that it controls to be off are omitted. In addition, since the configuration is differential and symmetrical as described above, the following description will be given without adding the subscripts "p, m" to the components that are symmetrical to the subscripts "p, m".

[0069] (1) Second-order ΔΣ mode In the second-order ΔΣ mode, the A / D conversion device 101 executes so-called oversampling type AD conversion processing. At this time, the potential generating circuit 14 generates a reference potential Vref suited to the second-order ΔΣ mode based on the control of the control circuit 10 and outputs it to the quantizer 12, thereby adjusting the output of the quantizer 12. The reference potential Vref output by the potential generating circuit 14 to the quantizer 12 in the second-order ΔΣ mode is set to be smaller than the reference potential Vref output in the cyclic mode and hybrid mode described later. In the second-order ΔΣ mode, the first-order integrator 11a and the second-order integrator 11b are used for operation, but the operational stability of the integrator 11 can be ensured, and the quantizer 12 can perform appropriate quantization.

[0070] Both the primary integrator 11a and the secondary integrator 11b perform a reset operation, a ΔΣ sample operation, and a ΔΣ hold operation simultaneously in parallel, and then repeatedly perform the ΔΣ sample operation and the ΔΣ hold operation. At this time, the A / D conversion device 101 performs AD conversion processing by oversampling these operations a predetermined number of times, while the quantizer 12 continues to quantize and output, and the output of the quantizer 12 is low-pass filtered by the digital filter 16 to obtain output data.

[0071] <Reset operation> First, the control circuit 10 turns on the switches SS14, SS12, SDD1M, SC14, SCD12, SCD1M, SC24, SCD22, SCD2M, SA12, and SF14 to discharge the accumulated charges of the capacitors Cs1, Csd1, Ccc1, Ccd1, Ccc2, Ccd2, and Cf11 to the node of the common potential Vcm, thereby resetting the primary integrator 11a. The control circuit 10 turns on the switches SS22, SS24, SDD2M, SA22, and SF24 to discharge the accumulated charges of the capacitors Cs2, Csd2, and Cf21 to the node of the common potential Vcm, thereby resetting the secondary integrator 11b. The control circuit 10 resets the digital filter 16 before switching to the ΔΣ mode.

[0072] During the ΔΣ mode described below, the control circuit 10 keeps the switches SCD12, SCD1M, SC14, SCD22, SCD2M, and SC24 of the primary integrator 11a on, so that the voltages across the capacitors Ccc1, Ccd1, Ccc2, and Ccd2 are kept at zero.

[0073] <ΔΣ sampling operation in ΔΣ mode> The control circuit 10 turns on the switches SSD11, SS12, SS14, SCD1M, SCD12, SC14, SCD2M, SCD22, SC24, and SF11 of the primary integrator 11a. At this time, the control circuit 10 turns on the switches SSD11, SS12, and SS14 of the primary integrator 11a to cause the capacitor Csd1 to sample the analog input signal Vin. In addition, the control circuit 10 turns on the switch SF11, so that the capacitor Cf11 is connected between the inverting input terminal and the output terminal of the operational amplifier 24.

[0074] In addition, the control circuit 10 turns on the switches SS21, SS22, and SSD2M of the second-order integrator 11b to input the output of the first-order integrator 11a to the other terminal of the capacitor Cs1. At this time, the capacitor Cs2 samples the output of the first-order integrator 11a.

[0075] At the same time, the control circuit 10 turns on the switch SF21, so that the capacitor Cf21 is connected between the input node and the output node of the operational amplifier 24b. This allows the second-order integrator 11b to output a voltage according to the charge stored in the capacitor Cf21. As described above, the control circuit 10 turns on the switch SCMP2, so that the output of the second-order integrator 11b is connected to the quantizer 12. This causes the quantizer 12 to output a quantizer output Qout (Quantizer out) that is a quantized version of the output of the second-order integrator 11b. The control circuit 10 selects one of the D / A conversion reference potentials Vrefp, Vcm, and Vrefm to be output for D / A conversion based on the quantizer output Qout.

[0076] <ΔΣ hold operation in ΔΣ mode> Next, the control circuit 10 controls the switches SS14, SS13, SCD1M, SCD12, SC14, SCD2M, SCD22, SC24, and SF11 of the primary integrator 11a to be on. At this time, the control circuit 10 turns on the switch SS13, so that one ends of the capacitors Cs1 and Csd1 can be connected to the input terminal of the operational amplifier 24. In addition, the control circuit 10 turns on the switch SF11, so that the capacitor Cf11 can be connected to the input / output terminal of the operational amplifier 24.

[0077] Furthermore, the control circuit 10 outputs the D / A converter output VR by turning on a switch (here, SDD1T) that constitutes the D / A converter. During the above-mentioned <ΔΣ sample operation>, charge is accumulated in the capacitor Csd1, but during the <ΔΣ hold operation>, a charge corresponding to the D / A converter output VR is subtracted from the accumulated charge in this capacitor Csd1, and the residual charge that is fed back is moved to the capacitor Cf11. As a result, the residual charge is accumulated in the capacitor Cf11, and the primary integrator 11a outputs an integral voltage corresponding to the accumulated charge in the capacitor Cf11 from its output node.

[0078] On the other hand, the control circuit 10 outputs the D / A converter output VR by turning on the switches SS23, SS24, SF21 in the second-order integrator 11b and the switch (here, SDD2T) of the D / A converter 25b. During the above-mentioned <ΔΣ sample operation>, charge is stored in the capacitor Cs2, but during the <ΔΣ hold operation>, a charge corresponding to the D / A converter output VR is subtracted from the stored charge in the capacitor Cs2, and the residual charge fed back is moved to the capacitor Cf21. As a result, the residual charge is stored in the capacitor Cf21, and the operational amplifier 24b outputs the integrated voltage by the second-order integrator 11b corresponding to the stored charge in the capacitor Cf21 to the output node.

[0079] The primary integrator 11a and the secondary integrator 11b simultaneously and alternately execute the above-mentioned <ΔΣ sample operation> and <ΔΣ hold operation> a predetermined number of times. In this ΔΣ mode, the primary integrator 11a and the secondary integrator 11b are in the same operating state at the same timing. The control circuit 10 of the A / D conversion device 101 oversamples these operations while the quantizer 12 continues to output values, and the output value of the quantizer 12 is low-pass filtered by the digital filter 16 to produce output data.

[0080] In this way, in the ΔΣ mode, the operational amplifier 24 of the primary integrator 11a and the operational amplifier 24b of the secondary integrator 11b are used, and AD conversion processing is performed by the ΔΣ method while the output of the secondary integrator 11b is quantized by the quantizer 12. The ΔΣ mode has secondary modulation characteristics and a large noise shaping effect, enabling highly accurate A / D conversion.

[0081] (2) Hybrid mode In the hybrid mode, the A / D conversion device 101 performs AD conversion processing of the analog input signal Vin by the ΔΣ method using the primary integrator 11a without using the operational amplifier 24b of the secondary integrator 11b, and then performs AD conversion processing of the residual by the cyclic method. At this time, the potential generating circuit 14 generates a reference potential Vref suited to the hybrid mode based on the control of the control circuit 10 and outputs it to the quantizer 12, thereby adjusting the quantized output of the quantizer 12.

[0082] In the hybrid mode, the A / D conversion device 101 may perform amplification processing by connecting a capacitor and a switch (neither of which is shown) in parallel with the capacitor Cf11 before performing AD conversion processing by the cyclic method after performing AD conversion processing by the ΔΣ method, as described in Patent Document 1. The following description will be given of a form in which amplification processing is not performed.

[0083] <Hybrid mode reset operation> First, the control circuit 10 resets the primary integrator 11a and the secondary integrator 11b simultaneously. The processing operation at this time is the same as the reset operation in the ΔΣ mode, so a description thereof will be omitted. After that, the A / D conversion device 101 performs oversampling processing by alternately repeating the ΔΣ sampling operation and the ΔΣ hold operation of the ΔΣ method a predetermined number of times (for example, several tens of times) using only the primary integrator 11a.

[0084] <Delta-Sigma sampling operation in hybrid mode> The control circuit 10 turns on the switches SDD1M, SS11, and SS12 of the primary integrator 11a to cause the capacitor Cs1 to sample the analog input signal Vin. At the same time, the control circuit 10 turns on the switch SF11 to connect the capacitor Cf11 between the input terminal and the output terminal of the operational amplifier 24.

[0085] Moreover, the control circuit 10 turns on the switch SCMP1 to connect the output of the primary integrator 11a to the quantizer 12. As a result, the quantizer 12 quantizes the output of the primary integrator 11a and outputs the digital value to the control circuit 10, and the control circuit 10 selects the D / A converter output VR to be used in the subsequent ΔΣ hold operation.

[0086] On the other hand, the control circuit 10 turns on the switches SS22, SS24, SDD2M, and SF21 of the second-order integrator 11b to set the potentials across the capacitors Cs2 and Csd2 to the common potential Vcm and puts the operational amplifier 24 in a feedback state, so that the second-order integrator 11b can be put into a non-operating state as shown by the thick line in Figure 10.

[0087] <ΔΣ hold operation in hybrid mode> The control circuit 10 outputs the D / A converter output VR by turning on the switches SS14 and SS13 of the primary integrator 11a and the switch (here, SDD1T) of the D / A converter 25, and connects one end of the capacitors Cs1 and Csd1 to the inverting input terminal of the operational amplifier 24. During the above-mentioned ΔΣ sample operation, charge is accumulated in the capacitor Cs1, but during the ΔΣ hold operation, a charge corresponding to the D / A converter output VR is subtracted from the accumulated charge of the capacitor Cs1, and the residual charge fed back is moved to the capacitor Cf11. As a result, the residual charge is accumulated in the capacitor Cf11, and the operational amplifier 24 outputs an integrated voltage by the primary integrator 11a corresponding to the accumulated charge of the capacitor Cf11 from the output node.

[0088] In this manner, the A / D conversion device 101 performs AD conversion processing using the ΔΣ method by repeatedly executing the <ΔΣ sample operation in hybrid mode> and the <ΔΣ hold operation in hybrid mode> a predetermined number of times.

[0089] <Hybrid mode patrol operation part 1> Thereafter, the A / D conversion device 101 performs AD conversion processing in a cyclic manner. The control circuit 10 turns on the switches SC24, SCD22, and SCD2M to charge and discharge the accumulated charges in the capacitors Ccc2 and Ccd2 to the common potential Vcm and reset them. The control circuit 10 also turns on the switch SF11 to connect the capacitor Cf11 between the input and output terminals of the operational amplifier 24.

[0090] Moreover, the control circuit 10 turns on the switches SC11, SCD11, and SCD12 to connect the output node of the primary integrator 11a to one end of the capacitors Ccc1 and Ccd1, and samples the output voltage of the primary integrator 11a to the capacitors Ccc1 and Ccd1.

[0091] <Hybrid mode patrol operation part 2> Next, the control circuit 10 turns on the switches SC14, SCD13, and a switch (here, SCD1T) of the D / A converter 26 to output the D / A converter output VR and connect one end of the capacitors Ccc1 and Ccd1 to the input node of the operational amplifier 24. In the above-mentioned cyclic operation 1, the output of the primary integrator 11a is sampled by the capacitors Ccc1 and Ccd1, but in cyclic operation 2, the residual charge that is fed back by subtracting the charge corresponding to the D / A converter output VR from the accumulated charge of the capacitors Ccc1 and Ccd1 is moved to the capacitor Cf11. As a result, the residual charge is accumulated in the capacitor Cf11.

[0092] At the same time, the control circuit 10 turns on the switches SC21, SCD21, and SCD22 to connect the output node of the primary integrator 11a to one end of the capacitors Ccc2 and Ccd2, and samples the output of the primary integrator 11a to the capacitors Ccc2 and Ccd2. This allows the primary integrator 11a to perform a cyclic sample operation using the capacitor switching circuit 22 while performing a cyclic hold operation using the capacitor switching circuit 21, and therefore the cyclic sample operation and the cyclic hold operation can be performed simultaneously.

[0093] <Hybrid mode patrol operation part 3> Next, the control circuit 10 outputs the D / A converter output VR by turning on the switches SC24, SCD23, and the switch (here, SCD2T) of the D / A converter 27, and connects one end of the capacitors Ccc2 and Ccd2 to the inverting input terminal of the operational amplifier 24. In the above-mentioned cyclic operation part 2, the output voltage of the primary integrator 11a is sampled by the capacitors Ccc2 and Ccd2, but in the cyclic operation part 3, the residual charge that is fed back by subtracting the charge corresponding to the D / A converter output VR from the accumulated charge of the capacitors Ccc2 and Ccd2 is moved to the capacitor Cf11. As a result, the residual charge is accumulated in the capacitor Cf11.

[0094] At the same time, the control circuit 10 turns on the switches SC11, SCD11, and SCD12 to connect the output node of the primary integrator 11a to one end of the capacitors Ccc1 and Ccd1, and samples the output of the primary integrator 11a to the capacitors Ccc1 and Ccd1. This allows the primary integrator 11a to perform a cyclic sample operation using the capacitor switching circuit 21 while performing a cyclic hold operation using the capacitor switching circuit 22, and therefore the cyclic sample operation and the cyclic hold operation can be performed simultaneously.

[0095] After that, the primary integrator 11a repeats these cyclic operations 2 and 3. Therefore, the control circuit 10 adds the quantized value obtained by the cyclic AD conversion process to the value of the most significant bits generated by the ΔΣ method as the least significant bits while shifting the digits using a shift register or a data accumulation circuit, and outputs the sum as output data. In this way, the final A / D conversion result is obtained.

[0096] (3) Cyclic mode In the cyclic mode, the A / D conversion device 101 performs AD conversion processing of the analog input signal Vin in a cyclic manner using the configuration of the first integrator 11a without using the second integrator 11b. To reduce power consumption, the operating current of the unused second integrator 11b is cut in this cyclic mode. At this time, the control circuit 10 may cut the operating current of the second integrator 11b by cutting off the power supply voltage VDD of the operational amplifier 24b constituting the second integrator 11b. This can suppress current consumption. In addition, the potential generating circuit 14 generates a reference potential Vref suited to the cyclic mode based on the control of the control circuit 10 and outputs it to the quantizer 12 to adjust the output of the quantizer 12.

[0097] <Reset operation of patrol mode> First, the control circuit 10 resets the primary integrator 11a and the secondary integrator 11b simultaneously. The processing operation at this time is the same as the reset operation in the ΔΣ mode, so a description thereof will be omitted. After that, the A / D conversion device 101 alternately repeats the cyclic sampling operation and the cyclic hold operation of the cyclic method a predetermined number of times (for example, a dozen or so times) using only the primary integrator 11a.

[0098] <Cycling sample operation in cycling mode> The control circuit 10 turns on the switches SDD1M, SS11, and SS12 of the primary integrator 11a, causing the capacitor Cs1 to sample the analog input signal Vin. At the same time, the control circuit 10 turns on the switch SF11, so that the capacitor Cf11 is connected between the input and output terminals of the operational amplifier 24. In addition, the control circuit 10 turns on the switch SCMP1, causing the output of the primary integrator 11a to be input to the quantizer 12.

[0099] Next, the control circuit 10 moves the charge stored in the capacitor Cs1 to the capacitor Cf11 by turning on the switches SS13 and SS14. At the same time, the control circuit 10 turns on the switches SC11, SCD11, and SCD12 to connect the output node of the primary integrator 11a to one end of the capacitors Ccc1 and Ccd1, and samples the output of the primary integrator 11a to the capacitors Ccc1 and Ccd1. This allows the primary integrator 11a to perform cyclic sampling operation using the capacitor switching circuit 21.

[0100] After that, the primary integrator 11a repeats the same operations as <Cyclic Operation in Hybrid Mode Part 2> and <Cyclic Operation in Hybrid Mode Part 3>. This is the same as described above, so the explanation is omitted. As a result, AD conversion processing can be performed in a cyclic manner using the primary integrator 11a without using the secondary integrator 11b.

[0101] <Summary of this embodiment> According to this embodiment, the A / D conversion device 101 can be configured by sharing the quantizer 12 and the potential generating circuit 14 in the second-order ΔΣ mode, the cyclic mode, and the hybrid mode. This allows for miniaturization. When implemented in the same configuration area as before, the power used for other circuits can be increased accordingly, and the configuration area can be increased, resulting in higher speed and higher accuracy. In addition, by using the above-mentioned integrator 11, the second-order ΔΣ mode and other operation modes can be switched to configure the device.

[0102] The A / D conversion device 101 performs AD conversion processing using the primary integrator 11a and the secondary integrator 11b in the secondary ΔΣ mode, and performs AD conversion processing using only the primary integrator 11a in the hybrid mode and cyclic mode. As a result, in modes other than the secondary ΔΣ mode, i.e., in the hybrid mode and cyclic mode, the A / D conversion device 101 does not need to operate the secondary integrator 11b.

[0103] The A / D conversion device 101 can be realized with low power consumption because the power consumption of the second-order integrator 11b can be suppressed in the cyclic mode and the hybrid mode. Since the second-order integrator 11b is not used in the hybrid mode and the cyclic mode, an operational amplifier with a lower gain error than the operational amplifier 24 of the first-order integrator 11a can be used as the operational amplifier 24b of the second-order integrator 11b.

[0104] In this embodiment, the A / D conversion device 101 uses the capacitor Csd1 as a sampling capacitance in the ΔΣ mode, and uses the capacitor Cs1 as a sampling capacitance in the hybrid mode and the cyclic mode. For example, if the capacitance values ​​of the capacitors Cs1 and Csd1 are set to the same capacitance value, the gain of the input sampling capacitance value can be made the same between the ΔΣ mode and other modes. Conversely, if the capacitance values ​​of the capacitors Cs1 and Csd1 are set to different capacitance values, the gain of the input sampling capacitance value can be switched between the ΔΣ mode and other modes.

[0105] Generally, when ΔΣ mode is used, the A / D conversion accuracy is higher than in cyclic mode due to the effect of oversampling, but when ΔΣ mode is used, the A / D conversion accuracy can be maintained even if the capacitance value of the sampling capacitor Csd1 is reduced. In this case, the configuration area of ​​the sampling capacitor Csd1 can be minimized. Conversely, the A / D conversion accuracy in ΔΣ mode can be further improved by setting the capacitance value of the sampling capacitor Csd1 to a large value.

[0106] Also, the integrator output changeover switch 11c can change over whether the input to the quantizer 12 is the output of the primary integrator 11a or the output of the secondary integrator 11b. For this reason, when the primary integrator 11a and the secondary integrator 11b are arranged in a predetermined direction (for example, horizontal direction) along the surface of the semiconductor substrate in terms of the layout of the battery monitoring integrated circuit device 1, it is preferable to arrange the quantizer 12 in a crossing direction (upward or downward). By configuring in this way, it is possible to shorten the wiring connecting the primary integrator 11a shown by the thick line in FIG. 10 to the quantizer 12 via the integrator output changeover switch 11c. As a result, it is possible to reduce interference between circuits and speed up the circuit operation.

[0107] The reference potential Vref that the potential generating circuit 14 outputs to the quantizer 12 in the second-order ΔΣ mode is set to be smaller than the reference potential Vref that it outputs in the cyclic mode and the hybrid mode. Therefore, in the second-order ΔΣ mode, the operational stability of the integrator 11 can be ensured, and the quantizer 12 can perform appropriate quantization.

[0108] The capacitors Cs1p, Csd1p, Cs1m, Csd1m and the capacitors Csd1p, Ccd1p, Ccd2p, Csd1m, Ccd1m, Ccd2m may be configured by combining unit capacitors having the same area and unit capacitance in an array. This makes it easier to obtain matching and reduces mismatching. This reduces the gain error of the switched capacitor amplifier that constitutes the primary integrator 11a, achieving high linearity and low gain error.

[0109] Since the control circuit 10 switches the operation mode by switching the integrator output changeover switch 11c, there is no need to use an extra capacitor, and therefore the A / D conversion device 101 that realizes multiple operation modes can be configured while being as compact as possible.

[0110] According to this embodiment, the low-speed, high-precision second-order ΔΣ mode, the high-speed, low-precision cyclic mode, and the medium-speed, medium-precision hybrid mode can be realized using the same hardware. These operating modes can be configured at a lower cost than when implemented separately. Since the hybrid mode is a combination of the first-order ΔΣ mode and the cyclic mode, there is no need to prepare hardware for each operating mode, and it can be realized at a low cost.

[0111] Furthermore, when a high voltage of about 100V is input as the analog input signal Vin as in the battery monitoring integrated circuit device 1 described in this embodiment, capacitors Cs1p, Cs1m, Csd1p, and Csd1m serving as sampling capacitances are prepared that have high voltage resistance. In this case, by configuring the A / D conversion device 101 of this embodiment, it is possible to achieve a configuration that can withstand high voltage input, and it is also possible to switch the accuracy and speed by switching the operation mode, so that it is possible to realize an A / D conversion device 101 that meets requirements.

[0112] For example, if the required accuracy and speed differ significantly between monitoring multiple battery cells 4a, 4b...4c and detecting the cell voltage of each battery cell 4a, 4b...4c with high accuracy and quickly scanning and diagnosing all of the multiple battery cells 4a...4c, a single A / D conversion device 101 can meet these requirements by switching operating modes.

[0113] Second embodiment The second embodiment will be described with reference to Fig. 11. For the operational amplifiers 24, 24b constituting the switched capacitor amplifier, it is desirable to use a telescopic amplifier 224 with a gain boost amplifier as shown in Fig. 11.

[0114] The telescopic amplifier 224 is configured by combining an input MOS transistor pair M1p-M1m that receives a differential input signal AINP-AINM, MOS transistor pairs M2p-M2m, M3p-M3m, and M4p-M4m that are telescopically cascode-connected to the input MOS transistor pair M1p-M1m, fully differential operational amplifiers A1 and A2, and a MOS transistor Mb that serves as a current source. Although omitted in Fig. 11, the MOS transistor Mb configures a current mirror circuit and is configured to pass a constant current Iss.

[0115] The MOS transistor pairs M1p-M1m and M2p-M2m are each composed of an n-channel MOSFET, and the MOS transistor pairs M3p-M3m and M4p-M4m are each composed of a p-channel MOSFET.

[0116] The fully differential operational amplifier A1 is provided for gain boost, and its differential input terminals are connected to a common connection point between the drains of the MOS transistors M1p and M2p, and a common connection point between the drains of the MOS transistors M1m and M2m, and its differential output terminals are connected to the gates of the MOS transistors M2p and M2m.

[0117] The fully differential operational amplifier A2 is provided for gain boost, and its differential input terminals are connected to a common connection point between the drain of the MOS transistor M4p and the source of the MOS transistor M3p, and a common connection point between the drain of the MOS transistor M4m and the source of the MOS transistor M3m. The differential output terminals of the fully differential operational amplifier A2 are connected to the gate of the MOS transistor M3p and the gate of the MOS transistor M3m. The MOS transistors M2p and M3p, and M2m and M3m are connected in common, and serve as output terminals that output differential output signals AOUTM-AOUTP.

[0118] The A / D conversion device 101 uses the operational amplifiers 24, 24b for a switched capacitor amplifier. A switched capacitor amplifier has no current load because it is configured by combining a switch and a capacitor (symbol omitted). Therefore, by configuring the operational amplifiers 24, 24b using the telescopic amplifier 224 with a gain boost amplifier shown in Fig. 11, the switched capacitor amplifier can be configured with low power and high accuracy.

[0119] However, if it is simply configured as a single-stage amplifier, it is likely to generate nonlinear errors due to the current load. If it is configured as a two-stage amplifier to increase the gain, the current consumption increases. By adding fully differential operational amplifiers A1 and A2 for gain boost while using a single-stage amplifier like the telescopic amplifier 224, it can be configured with low power consumption and high accuracy.

[0120] In addition, the telescopic amplifier 224 tends to narrow the input / output common voltage range (common range). However, as described in the first embodiment, the potential generating circuit 14 changes and applies the reference potential Vref, which is the quantization threshold value, to the quantizer 12. Therefore, even if the input range of the quantizer 12 is limited, the reference potential Vref can be adjusted to match the input range. This improves the degree of freedom of the input / output voltage range of the operational amplifier 24b, and the quantizer 12 can accurately quantize to an appropriate level even if the telescopic amplifier 224 is used for the operational amplifier 24b.

[0121] Third embodiment The third embodiment will be described with reference to Fig. 12. In the third embodiment, a configuration example of the potential generating circuit 14 described in the first embodiment will be described as a potential generating circuit 314. The potential generating circuit 314 shown in Fig. 12 includes switches SCP1p, SCP2p, SCP1m, and SCP2m as a reference potential changeover switch 314a, and generates a plurality of reference potentials Vref to be compared by the quantizer 12. In Fig. 12, the plurality of reference potentials Vref are shown divided into a reference potential REFINP of a relatively high potential and a reference potential REFINM of a relatively low potential.

[0122] The potential generating circuit 314 is configured by combining a resistor ladder Rr1, MOSFETs M5p, M6p, M5m, and M6m, as shown in FIG. 12. The MOSFETs M5p, M6p, M5m, and M6m are all configured as n-channel types. The resistor ladder Rr1 is configured by connecting a plurality of voltage dividing resistors between an application node of the highest reference potential VREFP and an application node of the lowest reference potential VREFM, and generates reference potentials VREF2P, VREF1P, VREF1M, and VREF2M by the divided voltages of the plurality of voltage dividing resistors. Note that there is a relationship of VREF2P>VREF1P>VREF1M>VREF2M.

[0123] The switch SCP2p is composed of a MOSFET_M6p. The MOSFET_M6p inputs the divided voltage VREF2P of the resistor ladder Rr1 to one of its drain and source, and connects the other of its drain and source to the input terminal of the reference potential REFINP of the quantizer 12. The switch SCP1p is composed of a MOSFET_M5p. The MOSFET_M5p inputs the divided voltage VREF1P of the resistor ladder Rr1 to one of its drain and source, and connects the other of its drain and source to the input terminal of the reference potential REFINP of the quantizer 12.

[0124] The control circuit 10 can input one of the reference potentials VREF2P and VREF1P to the quantizer 12 as the reference potential REFINP by turning on one of the MOSFETs_M5p and M6p.

[0125] The switch SCP1m is composed of a MOSFET_M5m. The MOSFET_M5m inputs the divided voltage VREF1M of the resistor ladder Rr1 to one of its drain and source, and connects the other of its drain and source to the input terminal of the reference potential REFINM of the quantizer 12. The switch SCP2m is composed of a MOSFET_M6m. The MOSFET_M6m inputs the divided voltage VREF2M of the resistor ladder Rr1 to one of its drain and source, and connects the other of its drain and source to the input terminal of the reference potential REFINM of the quantizer 12.

[0126] The control circuit 10 can input one of the reference potentials VREF1M and VREF2M as the reference potential REFINM to the quantizer 12 by turning on one of the MOSFETs_M5m and M6m. This allows the potential generating circuit 14 to input the reference potential Vref that satisfies the relationship REFINP>REFINM to the quantizer 12.

[0127] According to this embodiment, multiple reference potentials Vref (REFINP, REPINM) can be configured with low power and small size by configuring only one resistor ladder Rr1. The larger the area of ​​the resistor ladder Rr1, the smaller the mismatch between each voltage dividing resistor can be. Therefore, by adopting the resistor ladder Rr1 and making it smaller, the mounting area of ​​each resistor of the resistor ladder Rr1 can be increased to reduce the effect of mismatch.

[0128] When the control circuit 10 switches the output of the voltage dividing resistors by switching the MOS transistors M5p, M6p, M5m, and M6m on and off, the reference potential Vref fluctuates during switching. For this reason, it is desirable to temporarily stop the AD conversion process when switching the operation mode of the A / D conversion device 101, and to switch the reference potential Vref during this stop. By switching the reference potential Vref while the AD conversion process is temporarily stopped, the AD conversion accuracy is not adversely affected.

[0129] (Fourth embodiment) The fourth embodiment will be described with reference to Fig. 13 and Fig. 14. In the fourth embodiment, a configuration example of the potential generating circuit 14 in the first embodiment will be described as a potential generating circuit 414, but the same components as in the third embodiment will be given the same reference numerals and will not be described. In the present embodiment, a configuration example of the integrator output changeover switch 11c will be described as an integrator output changeover switch 411c.

[0130] The potential generating circuit 414 includes a resistor ladder Rr2 in addition to the resistor ladder Rr1, and also includes switches SCP1p, SCP2p, SCP1m, and SCP2m as a reference potential changeover switch 414a, and generates a plurality of reference potentials Vref to be compared by the quantizer 12. In Fig. 13, the plurality of reference potentials Vref are shown divided into a reference potential REFINP of a relatively high potential and a reference potential REFINM of a relatively low potential.

[0131] The resistor ladder Rr2 is configured by connecting a plurality of voltage dividing resistors between an application node of the power supply voltage VDD and an application node of the lowest reference potential VREFM, and generates a common potential VCM0 by the divided voltages of the plurality of voltage dividing resistors.

[0132] The switch SCP1p of the reference potential changeover switch 414a includes a MOSFET_M7p in addition to a MOSFET_M5p. The switch SCP1p is configured with two drains / sources of MOSFET_M5p and M7p connected in series. When the switch SCP1p is on, the control circuit 10 controls the MOSFET_M5p and M7p to be on and controls the MOSFET_M9p to be off. When the switch SCP1p is off, the control circuit 10 controls the MOSFET_M5p and M7p to be off and controls the MOSFET_M9p to be on, thereby connecting the intermediate potential to the common potential VCM0 via the MOSFET_M9p.

[0133] The switch SCP2p of the reference potential changeover switch 414a includes a MOSFET_M8p in addition to a MOSFET_M6p. The switch SCP2p is configured with two drains / sources of MOSFET_M6p and M8p connected in series. When the switch SCP2p is controlled to be on, the control circuit 10 controls the MOSFET_M6p and M8p on and controls the MOSFET_M10p off. When the switch SCP2p is controlled to be off, the control circuit 10 controls the MOSFET_M6p and M8p off and controls the MOSFET_M10p on, thereby connecting the intermediate potential to the common potential VCM0 via the MOSFET_M10p.

[0134] The switch SCP1m of the reference potential changeover switch 414a includes a MOSFET_M7m in addition to a MOSFET_M5m. The switch SCP1m is configured with two drains / sources of MOSFET_M5m and M7m connected in series. When the switch SCP1m is controlled to be on, the control circuit 10 controls the MOSFET_M5m and M7m to be on and controls the MOSFET_M9m to be off. When the switch SCP1m is controlled to be off, the control circuit 10 controls the MOSFET_M5m and M7m to be off and controls the MOSFET_M9m to be on, thereby connecting the intermediate potential to the common potential VCM0 via the MOSFET_M9m.

[0135] The switch SCP2m of the reference potential changeover switch 414a includes a MOSFET_M8m in addition to a MOSFET_M6m. The switch SCP2m is configured with two drains / sources of MOSFET_M6m and M8m connected in series. When the switch SCP2m is controlled to be on, the control circuit 10 controls the MOSFET_M6m and M8m on and controls the MOSFET_M10m off. When the switch SCP2m is controlled to be off, the control circuit 10 controls the MOSFET_M6m and M8m off and controls the MOSFET_M10m on, thereby connecting the intermediate potential to the common potential VCM0 via the MOSFET_M10m.

[0136] 14, each of the switches SCMP1p, SCMP2p, SCMP1m, and SCMP2m of the integrator output changeover switch 411c may be configured by combining MOSFETs M11, M12, and M13, respectively. The switches SCMP1p, SCMP2p, SCMP1m, and SCMP2m of the integrator output changeover switch 411c are configured by connecting two drains / sources of MOSFETs M11 and M12 in series.

[0137] When controlling the switches SCMP1p, SCMP2p, SCMP1m, and SCMP2m to be on, the control circuit 10 controls the MOSFETs_M11 and M12 to be on and controls the MOSFET_M13 to be off. When controlling the switches SCMP1p, SCMP2p, SCMP1m, and SCMP2m to be off, the control circuit 10 controls the MOSFETs_M11 and M12 to be off and controls the MOSFET_M13 to be on, thereby connecting the intermediate potential to the common potential VCM0 via the MOSFET_M13.

[0138] When the reference potentials VREP1P, VREP2P, VREP1M, and VREP2M or the output of the operational amplifier 24b are close to the power supply potential VDD or the lowest reference potential VREFM (e.g., ground potential), current may leak from the reference potential changeover switches SCP1p, SCP2p, SCP1m, and SCP2m and the integrator output changeover switches SCMP1p, SCMP2p, SCMP1m, and SCMP2m, resulting in large AD conversion errors.

[0139] As shown in FIG. 13, by configuring the potential generating circuit 414, an intermediate potential is set between each of the MOSFETs M5p-M7p, M5m-M7m, M6p-M8p, and M6m-M8m, and in particular, the gate-to-source voltage Vgs of the MOSFETs M5p or M6p, M5m or M6m can be made negative, thereby achieving a substrate bias effect to reduce leakage, reduce AD ​​conversion errors, and improve accuracy.

[0140] As shown in FIG. 14, by configuring the integrator output changeover switch 411c, an intermediate potential is provided between the MOSFETs M11 and M12, and in particular, the gate-source voltage Vgs of the MOSFET M11 can be made negative, thereby producing a substrate bias effect to reduce leakage and AD conversion errors, thereby improving accuracy.

[0141] (Other embodiments) The present invention is not limited to the above-described embodiment, but can be implemented in various modifications and can be applied to various embodiments without departing from the spirit of the present invention. For example, the following modifications or extensions are possible. Each component is conceptual, and is not limited to the above-described embodiment.

[0142] The D / A converter output VR is not limited to three levels, and may be set appropriately according to the number of levels of the quantized value in the quantizer 12. The number of reference potentials Vref of the potential generating circuit 14 may also be set according to the number of levels of the quantized value in the quantizer 12. Also, the number of levels of the D / A converter outputs VR of the DACs 25, 26, and 27 of the capacitor switching circuits 20, 21, and 22 may also be changed according to the number of levels of the quantized value.

[0143] The capacitance values ​​of capacitors Cs1p, Csd1p, Cs2p, Csd2p, Ccc1p, Ccc1p, Ccc2p, Ccd2p, Cf11p, Cf21p, Cs1m, Csd1m, Cs2m, Csd2m, Ccc1m, Ccc1m, Ccc2m, Ccd2m, Cf11m, and Cf21m may be scaled appropriately to correspond to the input / output range of each operational amplifier 24, 24b.

[0144] The present disclosure includes the following aspects and modes in addition to the invention described in the claims. [1] an integrator (11, 11a, 11b, 11c) to which an input signal and a DAC output are input; a quantizer (12) to which a reference potential is applied and to which the output of the integrator is input; The DAC (13, 25p, 25m, 26p, 26m, 27p, 27m, 25bp, 25bm) that performs digital-to-analog conversion of the output of the quantizer; A control circuit (10) for switching between two or more operation modes including a second-order ΔΣ mode and a cyclic mode; a potential generating circuit (14; 314; 414) capable of switching the reference potential to be applied to the quantizer in accordance with the operation mode; An A / D conversion device comprising:

[0145] [2] The integrator is a first-order integrator (11a) to which the input signal and the output of the DAC are input; a second-order integrator (11b) to which the output of the first-order integrator and the output of the DAC are input; and an integrator output changeover switch (11c; 411c) that enables switching between the output of the first-order integrator and the output of the second-order integrator as the input to the quantizer.

[0146] [3] In the cyclic mode, the A / D conversion device according to [2] operates using the first integrator to cut an operating current of the second integrator.

[0147] [4] the DAC comprises a DAC capacitance; The A / D conversion device according to any one of [1] to [3], wherein the integrator is configured with a switch and a switched capacitor amplifier configured by combining a sampling capacitance that inputs the input signal and a DAC capacitance of the DAC with the same capacitance value, and the gain of the switched capacitor amplifier is switched by switching the switch.

[0148] [5] The A / D conversion device according to any one of [1] to [4], wherein a telescopic amplifier (224) with a gain boost amplifier is used as the switched capacitor amplifier.

[0149] [6] The control circuit is an A / D conversion device described in any of [1] to [4], which switches between three or more modes including a second-order ΔΣ type mode that is switched by the integrator output switching switch and uses the output of the second-order integrator, a cyclic mode that performs cyclic operation, and a hybrid mode that is switched by the integrator output switching switch and switches between first-order ΔΣ operation that uses the output of the first-order integrator and the cyclic operation midway through conversion to perform AD conversion.

[0150] [7] An A / D conversion device described in any of [1] to [6], wherein in the hybrid mode, the primary ΔΣ operation is performed at the start of the AD conversion, a cyclic operation is performed by switching the on / off state of a switch during the AD conversion, and the AD conversion result of the primary ΔΣ operation and the AD conversion result of the cyclic operation are combined and output as the AD conversion result in the hybrid mode.

[0151] [8] The A / D conversion device according to any one of [1] to [7], wherein the potential generating circuit is configured by combining a resistor ladder (Rr1) and a reference potential switching switch (SCP1p, SCP2p, SCP1m, SCP2m), and makes the reference potential changeable.

[0152] [9] The A / D conversion device according to any one of [1] to [8], wherein the control circuit switches the reference potential changeover switch in synchronization with switching of the operation mode of the AD conversion.

[0153]

[10] the reference potential changeover switch is configured to have a first MOSFET and a second MOSFET connected in series; The A / D conversion device according to any one of [1] to [9], wherein when the reference potential changeover switch is turned off, the intermediate potential is connected to a common potential (VCM0) via a third MOSFET.

[0154]

[11] an integrator (11) to which an input signal and a DAC output are input; a quantizer (12) to which a reference potential is applied and to which the output of the integrator is input; The DAC (13) has a DAC capacitance and performs digital-to-analog conversion of the output of the quantizer; A control circuit (20) for switching between two or more operation modes including a second-order ΔΣ mode and a cyclic mode; a potential generating circuit (14) capable of switching the reference potential applied to the quantizer in accordance with the operation mode; A battery monitoring integrated circuit device comprising:

[0155] The techniques described in the present disclosure may be implemented by a special purpose computer provided by configuring a processor and memory programmed to perform one or more functions embodied in a computer program. Alternatively, the techniques described in the present disclosure may be implemented by a special purpose computer provided by configuring a processor with one or more dedicated hardware logic circuits. Alternatively, the techniques described in the present disclosure may be implemented by one or more special purpose computers configured by a combination of a processor and memory programmed to perform one or more functions and a processor configured with one or more hardware logic circuits. Also, the computer program may be stored in a computer-readable non-transitory tangible recording medium as instructions executed by the computer.

[0156] Although the present disclosure has been described based on the above-mentioned embodiment, it is understood that the present disclosure is not limited to the embodiment or the structure described in the embodiment. The present disclosure also includes various modifications and modifications within the equivalent range. In addition, various combinations and forms, and other combinations and forms including only one element, more than one element, or less than one element, are also within the scope and concept of the present disclosure. [Explanation of symbols]

[0157] In the drawings, 1 indicates a battery monitoring integrated circuit device, 10 indicates a control circuit, 11 indicates an integrator, 12 indicates a quantizer, 13 indicates a DAC, 14, 314, and 414 indicate potential generating circuits, 25p, 25m, 26p, 26m, 27p, 27m, 25bp, and 25bm indicate D / A converters (DACs), and 101 indicates an A / D conversion device.

Claims

1. an integrator (11, 11a, 11b, 11c) to which an input signal and an output of a DAC are input; a quantizer (12) to which a reference potential is applied and to which the output of the integrator is input; the DAC (13, 25p, 25m, 26p, 26m, 27p, 27m, 25bp, 25bm) for digital-to-analog converting the output of the quantizer; A control circuit (10) for switching between two or more operation modes including a quadratic ΔΣ mode and a cyclic mode; a potential generating circuit (14; 314; 414) capable of switching the reference potential to be applied to the quantizer in accordance with the operation mode; An A / D conversion device comprising:

2. The integrator is a first-order integrator (11a) receiving the input signal and the output of the DAC; a second-order integrator (11b) receiving the output of the first-order integrator and the output of the DAC; 2. The A / D conversion device according to claim 1, further comprising an integrator output changeover switch (11c; 411c) that makes it possible to change over whether the input to the quantizer is the output of the first-order integrator or the output of the second-order integrator.

3. 3. The A / D conversion device according to claim 2, wherein in the cyclic mode, the first-order integrator is used for operation, and an operating current of the second-order integrator is cut.

4. The DAC comprises a DAC capacitance; 4. The A / D conversion device according to claim 3, wherein the integrator is configured to include a switch and a switched capacitor amplifier configured by combining a sampling capacitance for inputting the input signal and a DAC capacitance of the DAC with the same capacitance value, and the gain of the switched capacitor amplifier is switched by switching the switch.

5. 5. The A / D conversion device according to claim 4, wherein a telescopic amplifier with a gain boost amplifier is used as the switched capacitor amplifier.

6. The A / D conversion device of claim 4 or 5, wherein the control circuit switches between three or more modes including a second-order ΔΣ mode in which the output of the second-order integrator is used by switching between the output switching switch, a cyclic mode in which a cyclic operation is performed, and a hybrid mode in which the output switching switch switches between a first-order ΔΣ operation in which the output of the first-order integrator is used and a cyclic operation in which an AD conversion is performed by switching between the first-order ΔΣ operation and the cyclic operation during the conversion.

7. An A / D conversion device as described in claim 6, wherein, in the hybrid mode, the primary ΔΣ operation is performed at the start of the AD conversion, a cyclic operation is performed by switching the on / off state of a switch in the middle of the AD conversion, and the AD conversion result of the primary ΔΣ operation and the AD conversion result of the cyclic operation are combined and output as the AD conversion result in the hybrid mode.

8. 5. The A / D conversion device according to claim 4, wherein the potential generating circuit is configured by combining a resistor ladder (Rr1) and reference potential changeover switches (SCP1p, SCP2p, SCP1m, SCP2m) to make the reference potential variable.

9. 9. The A / D conversion device according to claim 8, wherein the control circuit switches the reference potential changeover switch in synchronization with switching of the operation mode of the A / D conversion.

10. The reference potential changeover switch is configured by connecting a first MOSFET and a second MOSFET in series, 10. The A / D conversion device according to claim 9, wherein when the reference potential changeover switch is turned off, an intermediate potential between the first MOSFET and the second MOSFET is connected to a common potential (VCM0) via a third MOSFET.

11. An integrator (11) to which an input signal and an output of a DAC are input; a quantizer (12) to which a reference potential is applied and to which the output of the integrator is input; The DAC (13) has a DAC capacitance and performs DA conversion of the output of the quantizer; A control circuit (20) for switching between two or more operation modes including a quadratic ΔΣ mode and a cyclic mode; a potential generating circuit (14) capable of switching the reference potential to be applied to the quantizer in accordance with the operation mode; A battery monitoring integrated circuit device comprising:

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