Power semiconductor module and method for forming power semiconductor module

Abstract

To provide a power semiconductor module and a method for forming a power semiconductor module that can prevent damage to a power semiconductor device.SOLUTION: A power semiconductor module 201 includes a first substrate 210, a second substrate 220 formed on the first substrate, a support 230 which is a conductive member disposed between the first substrate and the second substrate, a first power semiconductor device 240 disposed between the first substrate and the conductive member, a second power semiconductor device 250 disposed between the conductive member and the second substrate, and a spacer 260 which is disposed on the first power semiconductor device and is made of a metal having excellent electrical conductivity. The conductive member is electrically connected to the first power semiconductor device and the second power semiconductor device.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] SUMMARY OF THE DISCLOSURE Embodiments relate to power semiconductor modules and methods of forming power semiconductor modules. [Background technology]

[0002] Unlike system semiconductors and memory that process and store information and signals, power semiconductors are core components that convert, store, distribute and control the power applied to electronic devices, and are widely used in most electronic products.

[0003] Recently, in line with the global trend of strengthening environmental protection, electric and hydrogen-based eco-cars have been widely attracting attention as an alternative to existing fossil fuel-based cars. Many power semiconductor devices are used in such eco-cars. Here, eco-cars include hybrid electric vehicles (HEVs), plug-in hybrid electric vehicles (PHEVs), electric vehicles (EVs), fuel cell electric vehicles (PCEVs), etc.

[0004] Conventionally, Si power semiconductor devices have been widely used, but there is a strong demand for the development of new power semiconductors due to their low power, low dielectric breakdown characteristics, low thermal conductivity, etc. As a result, active research is being conducted on power semiconductors based on semiconductor compounds such as SiC, GaN, and Ga2O3, which have an energy band gap three times larger than that of conventional Si power semiconductors. These power semiconductors based on semiconductor compounds have high power, high dielectric breakdown characteristics, high thermal conductivity, etc.

[0005] 2. Description of the Related Art Recently, power semiconductor modules in which a plurality of power semiconductor devices are packaged have been widely studied, and power conversion apparatuses including such power semiconductor modules are being applied to various technical fields.

[0006] A plurality of power semiconductor devices included in a power semiconductor module may be connected in series or parallel. In this case, when each of the power semiconductor devices is turned off, a stray inductance is formed in the corresponding power semiconductor device. The stray inductance is significantly affected by the electrical connection path of the power semiconductor devices. That is, the larger the electrical connection path between the power semiconductor devices, the larger the stray inductance. That is, the larger the electrical connection path between the power semiconductor devices, the larger the current path, and the larger the current path, the larger the stray inductance.

[0007] Stray inductance impedes current flow and thus impedes high power output, and therefore must be minimized or eliminated. In particular, when stray inductance becomes large, instantaneous voltage overshoot occurs. If such an overshoot voltage exceeds the withstand voltage of the power semiconductor device, the power semiconductor device may be damaged or switching loss may occur in the power semiconductor device. Therefore, there is a strong demand for a technical solution that can minimize or eliminate stray inductance.

[0008] Meanwhile, there is a demand for higher high-power output of power semiconductor devices, and the size of the power semiconductor devices is also increasing as the high-power output increases. However, there is a strong demand for reducing the size of products in which multiple power semiconductor devices are adopted. Therefore, there is an urgent need to develop a power semiconductor module that can reduce the product size while increasing the high-power output of power semiconductor devices per unit area. Summary of the Invention [Problem to be solved by the invention]

[0009] SUMMARY OF THE DISCLOSURE The embodiments are directed to solving the above-referenced problems and other problems.

[0010] Another object of the embodiments is to provide a power semiconductor module and a method for forming a power semiconductor module that can prevent damage to the power semiconductor devices.

[0011] Yet another object of the embodiments is to provide a power semiconductor module and a method for forming the power semiconductor module that can reduce switching losses in power semiconductor devices.

[0012] Yet another object of the embodiments is to provide a power semiconductor module and a method for forming the power semiconductor module that can increase high power output per unit area.

[0013] Yet another object of the embodiments is to provide a power semiconductor module and a method for forming a power semiconductor module that can be reduced in size.

[0014] The technical problems of the embodiments are not limited to those described in this section, but include those that can be understood from the description of the invention. [Means for solving the problem]

[0015] A power semiconductor module according to an embodiment includes a first substrate, a second substrate formed on the first substrate, a conductive member disposed between the first substrate and the second substrate, a first power semiconductor device disposed between the first substrate and the conductive member, and a second power semiconductor device disposed between the conductive member and the second substrate, the conductive member being electrically connected to the first power semiconductor device and the second power semiconductor device.

[0016] The first power semiconductor device and the second power semiconductor device may at least partially overlap.

[0017] The first power semiconductor device and the second power semiconductor device may be electrically connected in series.

[0018] The conductive member includes a second region and a coupling portion coupled to the second region, and the second power semiconductor device is disposed on a surface of the second region.

[0019] The conductive member includes a first region located lower than the second region and connected to the connecting portion, the conductive member includes a recess formed by the first region, the connecting portion and the second region, and the first power semiconductor device is disposed within the recess.

[0020] The semiconductor device may further include a spacer disposed between the first power semiconductor device and the conductive member.

[0021] The first power semiconductor device may include a first gate electrode, a first source electrode, and a first drain electrode, the first gate electrode being electrically connected to the first substrate using a wire, the first source electrode being electrically connected to the conductive member, and the first drain electrode being electrically connected to the first substrate, and an upper surface of the spacer may be positioned higher than an uppermost position of the wire.

[0022] The semiconductor device may include a plurality of first power semiconductor devices including the first power semiconductor device, the plurality of first power semiconductor devices being coupled in parallel between the first substrate and the conductive member.

[0023] The first substrate, the first power semiconductor device, the conductive member, the second power semiconductor device, and the second substrate are configured in this order such that a current path is formed through the first substrate, the first power semiconductor device, the conductive member, the second power semiconductor device, and the second substrate.

[0024] A method for forming a power semiconductor module according to an embodiment includes the steps of forming a first substrate, forming a first power semiconductor device on the first substrate, forming a conductive member on the first power semiconductor device such that the first power semiconductor device is disposed between the first substrate and a conductive member, forming a second power semiconductor device on the conductive member, and forming the second substrate on the second semiconductor member such that the second power semiconductor device is disposed between the conductive member and the second substrate, the conductive member being disposed between the first substrate and the second substrate. Effect of the Invention

[0025] The effects of the power semiconductor module and the method for forming the power semiconductor module according to the embodiment will be described below.

[0026] At least one of the embodiments has an advantage in that it is possible to suppress switching losses in a power semiconductor device and to perform highly precise switching control.

[0027] Since the first and / or second power semiconductor devices are connected to the plate-shaped conductive support in a surface contact manner, contact resistance between the first and / or second power semiconductor devices and the conductive support is minimized, thereby minimizing current loss, and therefore, no switching loss occurs in the first and / or second power semiconductor devices, making it possible to achieve a preset high power output and highly precise switching control.

[0028] At least one of the embodiments has an advantage that damage to the power semiconductor device can be prevented.

[0029] In the power semiconductor module according to the embodiment, the first and second power semiconductor devices can be vertically stacked between the first and second substrates with the support in between. Since the first and second power semiconductor devices are spaced apart by the thickness of the support, the spacing between the first and second power semiconductor devices is minimized.

[0030] The electrical connection path between the first power semiconductor device and the second power semiconductor device has a large effect on the stray inductance. However, in the power semiconductor module according to the embodiment, the distance between the first power semiconductor device and the second power semiconductor device is minimized, so that the stray inductance can be eliminated or minimized. As a result, even when the first power semiconductor device or the second power semiconductor device is turned off, no stray inductance is generated, so no overshoot voltage occurs. This prevents damage to the first power semiconductor device or the second power semiconductor device due to the overshoot voltage.

[0031] At least one of the embodiments has an advantage that switching loss can be reduced.

[0032] The stray inductance affects the switching loss of the first power semiconductor device or the second power semiconductor device. However, in the power semiconductor module according to the embodiment, the distance between the first power semiconductor device and the second power semiconductor device is minimized, and thus the stray inductance is eliminated or minimized, so that a preset high power output is possible without affecting the switching loss of the first power semiconductor device or the second power semiconductor device.

[0033] At least one of the embodiments has the advantage of being able to increase high power output per unit area and reduce size.

[0034] In the power semiconductor module according to the embodiment, the first power semiconductor device and the second power semiconductor device are vertically stacked with the support in between, minimizing the layout area of ​​the first power semiconductor device and the second power semiconductor device, thereby minimizing the size of the power semiconductor module or the power conversion device. This allows more first power semiconductor devices and second power semiconductor devices to be mounted per unit area, enabling higher power output.

[0035] At least one of the embodiments has an advantage that short circuits of wires can be prevented.

[0036] In the power semiconductor module according to the embodiment, a first power semiconductor device and a second power semiconductor device may be vertically stacked with a support in between. One side of the first power semiconductor device and a first substrate are electrically connected via a wire. A spacer is disposed between the first power semiconductor device and the support. The spacer may prevent the wire from being electrically shorted to the support. For example, a top surface of the spacer may be positioned higher than a top side of the wire.

[0037] At least one of the embodiments has the advantage that high power output can be enhanced.

[0038] In the power semiconductor module according to the embodiment, the first power semiconductor device and the second power semiconductor device can be stacked vertically with a support in between. By providing a plurality of first power semiconductor devices connected in parallel with each other and a plurality of second power semiconductor devices connected in parallel with each other, the current characteristics are improved and high power output is possible.

[0039] Further scope of applicability of the embodiments will become apparent from the following detailed description. However, it should be understood that the detailed description and specific embodiments, such as the preferred embodiments, are merely illustrative, since various changes and modifications within the spirit and scope of the embodiments will be apparent to those skilled in the art. [Brief description of the drawings]

[0040] [Figure 1] FIG. 1 is a circuit diagram showing an inverter for an automobile according to a first embodiment. [Diagram 2] FIG. 2 is a plan view illustrating the power semiconductor module according to the first embodiment. [Diagram 3] FIG. 3 is a cross-sectional view illustrating a power semiconductor module according to a first embodiment. [Figure 4] FIG. 4 is a cross-sectional view illustrating in detail the power semiconductor module according to the first embodiment. [Diagram 5] FIG. 5 is a cross-sectional view illustrating a power semiconductor device according to an embodiment. [Figure 6a] FIG. 6a shows the current paths in a power semiconductor module according to the applicant's internal technology. [Figure 6b] FIG. 6b shows the current paths of the power semiconductor module according to the first embodiment. [Figure 7a] FIG. 7a illustrates a manufacturing process for a power semiconductor module according to an embodiment. [Figure 7b] FIG. 7b illustrates a manufacturing process for a power semiconductor module according to an embodiment. [Figure 7c] FIG. 7c illustrates a manufacturing process of a power semiconductor module according to an embodiment. [Figure 7d] FIG. 7d illustrates a manufacturing process for a power semiconductor module according to an embodiment. [Figure 7e] FIG. 7e illustrates a manufacturing process for a power semiconductor module according to an embodiment. [Figure 8] FIG. 8 is a plan view illustrating a power semiconductor module according to the second embodiment. [Figure 9] FIG. 9 is a cross-sectional view illustrating a power semiconductor module according to a third embodiment. [Figure 10] FIG. 10 is a cross-sectional view illustrating a power semiconductor module according to a fourth embodiment. [Figure 11] FIG. 11 is a circuit diagram showing an inverter for an automobile according to the second embodiment. [Figure 12]FIG. 12 is a plan view illustrating a power semiconductor module according to the fifth embodiment. [Figure 13] FIG. 13 is a cross-sectional view illustrating a power semiconductor module according to a fifth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0041] Hereinafter, the embodiments disclosed herein will be described in detail with reference to the accompanying drawings. The same or similar components will be given the same reference numbers regardless of the drawing numbers, and redundant description thereof will be omitted. The suffixes "module" and "part" for components used in the following description are given or mixed to facilitate the preparation of the specification, and do not have a meaning or role that is different from each other by themselves. In addition, the accompanying drawings are provided to facilitate understanding of the embodiments disclosed in the present specification, and the technical ideas disclosed in the present specification are not limited by the accompanying drawings. In addition, when an element such as a layer, region, or substrate is referred to as being "on" another element, this includes elements that are directly on the other element or that may have other intermediate elements therebetween. Although terms including ordinal numbers such as first, second, etc. can be used to describe various elements, the elements are not limited by the terms. The terms are used only for the purpose of distinguishing one element from another element. A singular expression includes a plural expression unless otherwise clearly indicated in the context.

[0042] In this application, the terms "including," "having," or "comprising" are intended to specify the presence of any feature, number, step, operation, component, part, or combination thereof set forth in the specification, but are not to be understood as precluding the presence or additional possibility of one or more other features, number, steps, operations, components, parts, or combinations thereof.

[0043] In some embodiments, the power converter may be used as an inverter or converter in computers, home appliances, automobiles, solar panels, smart grids, etc. In some embodiments, the power converter may include one or more power semiconductor modules, and the power semiconductor module may include multiple power semiconductor devices.

[0044] In the following embodiments (FIGS. 1 and 11), an inverter for an automobile for driving a motor is described as a power conversion device, but the power conversion device of the embodiments can be applied to inverters, converters, etc. in the various technical fields mentioned above. Here, automobiles refer to eco-cars and include hybrid electric vehicles (HEVs), plug-in hybrid electric vehicles (PHEVs), electric vehicles (EVs), fuel cell electric vehicles (PCEVs), etc.

[0045] In the following embodiments (FIGS. 1 and 11), the switching element and the power semiconductor device may be mixed. In the following embodiments (FIGS. 1 and 11), the leg and the power semiconductor module may be mixed. In the embodiments, the power semiconductor module may refer to a module in which at least one power semiconductor device is packaged for converting, distributing and / or controlling power input to at least one electronic device. The power semiconductor device may refer to at least one semiconductor device for converting, distributing and / or controlling power input to at least one electronic device.

[0046] FIG. 1 is a circuit diagram showing an inverter for an automobile according to a first embodiment.

[0047] Referring to FIG. 1, an inverter 1000 for an automobile according to the first embodiment can convert DC power into AC power and supply the converted AC power to a load 1200 to drive the load 1200. In the inverter 1000 for an automobile according to the first embodiment, a battery is connected to an input terminal, and DC power of the battery is converted into AC power. Although not shown, a converter is connected to an input terminal of the battery, and an input terminal of the converter is connected to a charger of a charging station. In this case, AC power supplied through the charger is converted into DC power by the converter, and the converted DC power is charged to the battery to charge the battery. In addition, the DC power charged to the battery is converted into AC power by the inverter 1000 for an automobile according to the first embodiment and used to drive the load. The circuit configuration of the converter may be similar to or the same as the circuit configuration of the inverter. The load 1200 may be a motor, but is not limited thereto.

[0048] The inverter 1000 for automobiles according to the first embodiment may include a three-phase inverter, but is not limited thereto. At this time, there may be a phase difference of 120 degrees between the first phase, the second phase, and the third phase. The inverter 1000 for automobiles according to the first embodiment may include a plurality of legs 100A, 100B, and 100C. For example, the first leg 100A, the second leg 100B, and the third leg 100C may be connected in parallel to the load 1200, i.e., the motor, via the first node N1, the second node N2, and the third node N3, respectively. The first leg 100A may include a first arm 100a and a second arm 100b connected in series to each other, the second leg 100B may include a third arm 100c and a fourth arm 100d connected in series to each other, and the third leg 100C may include a fifth arm 100e and a sixth arm 100f connected in series to each other. Here, the first arm 100a, the third arm 100c, and the fifth arm 100e can be referred to as upper arms, and the second arm 100b, the fourth arm 100d, and the sixth arm 100f can be referred to as lower arms. Each of the first arm 100a to the sixth arm 100f can be referred to as a switching module, a sub-module, or the like.

[0049] The first arm 100a to the sixth arm 100f may include switching elements 100a-1, 100b-1, 100c-1, 100d-1, 100e-1, and 100f-1 and diodes 100a-2, 100b-2, 100c-2, 100d-2, 100e-2, and 100f-2, respectively. The switching elements 100a-1, 100b-1, 100c-1, 100d-1, 100e-1, and 100f-1 and the diodes 100a-2, 100b-2, 100c-2, 100d-2, 100e-2, and 100f-2 may be formed simultaneously using the same semiconductor process. The switching elements 100a-1, 100b-1, 100c-1, 100d-1, 100e-1, and 100f-1 may include power semiconductor devices.

[0050] In order for DC power to be converted into AC power by the inverter according to the first embodiment, the switching elements 100a-1, 100b-1, 100c-1, 100d-1, 100e-1, and 100f-1 of the first arm 100a to the sixth arm 100f are on / off controlled.

[0051] For example, when the first switching element 100a-1 of the first arm 100a of the first leg 100A is in an ON state, the fourth switching element 100d-1 of the fourth arm 100d of the second leg 100B and / or the sixth switching element 100f-1 of the sixth arm 100f of the third leg 100C can be in an ON state, thereby supplying DC power to the first phase inductor of the motor.

[0052] For example, when the second switching element 100b-1 of the second arm 100b of the second leg 100B is in an ON state, the sixth switching element 100f-1 of the sixth arm 100f of the third leg 100C and / or the second switching element 100b-1 of the second arm 100b of the first leg 100A can be in an ON state. This allows DC power to be supplied to the second phase inductor of the motor. The second phase is delayed by 120 degrees from the first phase.

[0053] For example, when the third switching element 100c-1 of the third arm 100c of the third leg 100C is in an ON state, the second switching element 100b-1 of the second arm 100b of the first leg 100A and / or the fourth switching element 100d-1 of the fourth arm 100d of the second leg 100B can be in an ON state. This allows DC power to be supplied to the third phase inductor of the motor. The third phase is delayed by 120 degrees from the second phase.

[0054] Thereby, AC power is generated by DC power supplied to each of the first phase inductor, the second phase inductor, and the third phase inductor.

[0055] Meanwhile, although not shown, in order to improve the withstand voltage characteristics, each of the switching elements of the first arm 100a to the sixth arm 100f, i.e., the power semiconductor devices 100a-1, 100b-1, 100c-1, 100d-1, 100e-1, and 100f-1, may be provided with a plurality of elements connected in series with each other.

[0056] Although not shown, in order to improve current characteristics, each of the switching elements of the first arm 100a to the sixth arm 100f, i.e., the power semiconductor devices 100a-1, 100b-1, 100c-1, 100d-1, 100e-1, and 100f-1, may be provided in plurality and connected in parallel with each other.

[0057] Meanwhile, the switching elements 100a-1, 100b-1, 100c-1, 100d-1, 100e-1, and 100f-1 and the diodes 100a-2, 100b-2, 100c-2, 100d-2, 100e-2, and 100f-2 constituting the first arm 100a to the sixth arm 100f can be packaged to form a power semiconductor module.

[0058] As an example, the first leg 100A, the second leg 100B, and the third leg 100C may each be configured as a power semiconductor module. That is, the first arm 100a and the second arm 100b of the first leg 100A may be packaged and configured as a first power semiconductor module. The third arm 100c and the fourth arm 100d of the second leg 100B may be packaged and configured as a second power semiconductor module. The fifth arm 100e and the sixth arm 100f of the third leg 100C may be packaged and configured as a third power semiconductor module. As another example, the first leg 100A, the second leg 100B, and the third leg 100C may be configured as a single power semiconductor module. That is, the first arm 100a and the second arm 100b of the first leg 100A, the third arm 100c and the fourth arm 100d of the second leg 100B, and the fifth arm 100e and the sixth arm 100f of the third leg 100C can be packaged and configured as a single power semiconductor module.

[0059] Fig. 2 is a plan view illustrating the power semiconductor module according to the first embodiment, and Fig. 3 is a cross-sectional view illustrating the power semiconductor module according to the first embodiment.

[0060] The power semiconductor module 201 according to the first embodiment may be one of the first leg 100A, the second leg 100B, and the third leg 100C illustrated in Fig. 1. Although not illustrated, the power semiconductor module 201 according to the first embodiment may include all of the first leg 100A, the second leg 100B, and the third leg 100C.

[0061] 2 and 3, a power semiconductor module 201 according to the first embodiment may include a first substrate 210, a second substrate 220, a support 230, a first power semiconductor device 240 and a second power semiconductor device 250.

[0062] The second substrate 220 is disposed on the first substrate 210, and the support 230 is disposed between the first substrate 210 and the second substrate 220. In such a case, the first power semiconductor device 240 is disposed between the first substrate 210 and the support 230, and the second power semiconductor device 250 is disposed between the support 230 and the second substrate 220.

[0063] The first power semiconductor device 240 and the second power semiconductor device 250 may be vertically overlapped. The first power semiconductor device 240 and the second power semiconductor device 250 may be vertically overlapped between the first substrate 210 and the second substrate 220. The first power semiconductor device 240 and the second power semiconductor device 250 may be vertically overlapped with the support 230 in between. For example, the first power semiconductor device 240 is disposed on the lower surface of the specific region of the support 230, and the second power semiconductor device 250 is disposed on the upper surface of the specific region of the support 230. Thus, the first power semiconductor device 240 and the second power semiconductor device 250 may be vertically overlapped in the specific region of the support 230. The first power semiconductor device 240 and the second power semiconductor device 250 that are vertically overlapped with each other may be connected in series.

[0064] As described above, the power semiconductor module 201 according to the first embodiment may be composed of each of the first leg 100A, the second leg 100B, and the third leg 100C shown in Fig. 1 or may be composed entirely of them. In such a case, the first power semiconductor device 240 may be one of the first switching element 100a-1 of the first arm 100a, the third switching element 100c-1 of the third arm 100c, and the fifth switching element 100e-1 of the fifth arm 100e, and the second power semiconductor device 250 may be one of the second switching element 100b-1 of the second arm 100b, the fourth switching element 100d-1 of the fourth arm 100d, and the sixth switching element 100f-1 of the sixth arm 100f. The first power semiconductor device 240 and the second power semiconductor device 250 may be N-type MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), but may also be P-type MOSFETs.

[0065] 5 is a cross-sectional view illustrating a power semiconductor device according to an embodiment. The power semiconductor device 101 according to the embodiment may be the first power semiconductor device 240 or the second power semiconductor device 250 illustrated in FIG.

[0066] 5, a power semiconductor device 101 according to an embodiment may include a substrate 110, a first conductive type epitaxial layer 120, a second conductive type well 130, a first conductive type source region 140, a gate insulating layer 150, a gate electrode 160, and a drain electrode 105. The first conductive type may be N-type, and the second conductive type may be P-type, but is not limited thereto.

[0067] For example, the power semiconductor device 101 may include a first conductive type epitaxial layer 120 formed on a given substrate 110, a second conductive type well 130 formed in the first conductive type epitaxial layer 120, a first conductive type source region 140 formed in the second conductive type well 130, a gate insulating layer 150 and a gate electrode 160 formed on the first conductive type source region 140, and a drain electrode 105 disposed under the substrate 110.

[0068] The substrate 110 and the first conductive type epitaxial layer 120 may include a semiconductor compound such as SiC, GaN, or Ga2O3.

[0069] 2 and 3, the first substrate 210 is disposed below the first power semiconductor device 240, and the second substrate 220 is disposed above the second power semiconductor device 250. The support 230 is disposed between the first power semiconductor device 240 and the second power semiconductor device 250.

[0070] The first substrate 210 and the second substrate 220 may be heat dissipation substrates having excellent heat dissipation characteristics, and the first substrate 210 and the second substrate 220 may be electrode substrates having excellent electrical conductivity.

[0071] The first power semiconductor device 240 is electrically connected to the first substrate 210. Heat generated in the first power semiconductor device 240 is dissipated to the outside through the first substrate 210. The second power semiconductor device 250 is electrically connected to the second substrate 220. Heat generated in the second power semiconductor device 250 is dissipated to the outside through the second substrate 220.

[0072] The support 230 can stably support the second power semiconductor device 250. The support 230 can be called a supporter, a seat, a clip, etc. The support 230 can be a conductive support or a conductive member. That is, the support 230 can be made of metal. The support 230 can have a plate shape. The size of the support 230 can be larger than the size of the first power semiconductor device 240 and / or the second power semiconductor device 250. In this case, the first power semiconductor device 240 is disposed under the conductive support 230, and an upper surface of the first power semiconductor device 240 is connected to the conductive support 230 in surface contact. Also, the second power semiconductor device 250 is disposed on the conductive support 230, and a lower surface of the second power semiconductor device 250 is connected to the conductive support 230 in surface contact. In this manner, since the first power semiconductor device 240 and / or the second power semiconductor device 250 are connected to the plate-shaped conductive support 230 in surface contact, contact resistance between the first power semiconductor device 240 and / or the second power semiconductor 250 and the conductive support 230 is minimized, thereby minimizing current loss. As a result, no switching loss occurs in the first power semiconductor device 240 or the second power semiconductor 250, making it possible to output a preset high power and perform highly precise switching control.

[0073] The support 230 may include a first region 231, a second region 232, and a connecting portion 233. The second region 232 may be located higher than the first region 231. A second power semiconductor device 250 is disposed on the second region 232. The second region 232 is located at the center, and the first region 231 is located on at least one side of the second region 232. The connecting portion 233 may connect the first region 231 and the second region 232. The first region 231, the second region 232, and the connecting portion 233 may be integrally formed. In the drawings, the connecting portion 233 has an inclined shape, but it may have a vertical shape or other shapes relative to the ground.

[0074] The support 230 may have a recess 235. The recess 235 is formed by the first region 231, the connecting portion 233, and the second region 232. The recess 235 is formed under the support 230. This is because the second region 232 is positioned higher than the first region 231. That is, the recess 235 is formed by a step between the first region 231 and the second region 232 and the connecting portion 233 connecting the first region 231 and the second region 232. The first power semiconductor device 240 is accommodated in the recess 235. As shown in FIG. 2, the size of the support 230 may be larger than the size of the first power semiconductor device 240 or the second power semiconductor device 250.

[0075] Meanwhile, in order to strengthen the fixation of the support 230, the first region 231 is fixed to the first substrate 210. The support 230 is electrically connected to the first substrate 210. For example, the first region 231 of the support 230 is electrically connected to the first substrate 210. The support 230 may be one of the first node N1, the second node N2, and the third node N3 illustrated in FIG. 1. Thus, the input side power is output to the load 1200 by turning on the first power semiconductor device 240 or the second power semiconductor device 250. Thus, the support 230 may be an output side terminal.

[0076] Meanwhile, the power semiconductor module 201 according to the first embodiment may include a spacer 260. The spacer 260 is disposed between the first power semiconductor device 240 and the support 230. The spacer 260 is disposed on the first power semiconductor device 240. The spacer 260 may be made of a metal having excellent electrical conductivity. Therefore, the first power semiconductor device 240 is electrically connected to the support 230 via the spacer 260.

[0077] An upper portion of the first power semiconductor device 240, i.e., the gate electrode, is electrically connected to the first substrate 210 using a wire 290. In this case, a space must be secured between the first power semiconductor device 240 and the support 230 to prevent an electrical short between the wire 290 and the support 230. To this end, a spacer 260 is disposed between the first power semiconductor device 240 and the support 230. For example, the thickness of the spacer 260 is secured so that the top surface of the spacer 260 is higher than the top side of the wire 290.

[0078] Since the wire 290 is connected onto a portion of the upper side of the first power semiconductor device 240, the uppermost side of the wire 290 may be higher than the uppermost side of the first power semiconductor device 240. Without the spacer 260, the wire 290 and the support 230 will be electrically shorted. Thus, by disposing the spacer 260 on the first power semiconductor device 240, which has a thickness that is sufficiently large so that the upper surface of the spacer 260 is higher than the uppermost side of the wire 290, an electrical short between the wire 290 and the support 230 can be prevented.

[0079] 2 and 3, the size of the second region 232 of the support 230 may be larger than the size of the spacer 260. The size of the second region 232 of the support 230 may be larger than the size of the second power semiconductor device 250.

[0080] Meanwhile, Fig. 6a shows a current path of a power semiconductor module according to the applicant's internal technology, and Fig. 6b shows a current path of a power semiconductor module according to a first embodiment.

[0081] As shown in FIG. 6a, the power semiconductor module according to the applicant's internal technology has a first power semiconductor device 3 and a second power semiconductor device 4 disposed between a first substrate 1 and a second substrate 2. The first power semiconductor device 3 and the second power semiconductor device 4 may be connected in series via the second substrate 2. In such a case, a current path is formed via a first signal pattern (not shown) of the first substrate 1, the first power semiconductor device 3, the second substrate 2, the second power semiconductor device 4, and a second signal pattern (not shown) of the first substrate 1. Although not shown, the first power semiconductor device 3 and the second power semiconductor device 4 may be connected in series via the first substrate 1. In such a case, a current path is formed via a first signal pattern (not shown) of the second substrate 2, the first power semiconductor device 3, the first substrate 1, the second power semiconductor device 4, and a second signal pattern (not shown) of the second substrate 2.

[0082] Between the first substrate 1 and the second substrate 2, the first power semiconductor device 3 and the second power semiconductor device 4 are spaced apart by a certain distance to prevent electrical shorts. Therefore, as the distance between the first power semiconductor device 3 and the second power semiconductor device 4 increases, the current path between the first power semiconductor device 3 and the second power semiconductor device 4 (see arrows) increases. When the first power semiconductor device 3 or the second power semiconductor device 4 is turned off, the increase in the current path increases the stray inductance. The increase in stray inductance makes it difficult to output high power. In addition, if the voltage overshoots due to the increase in stray inductance exceeds the withstand voltage of the first power semiconductor device 3 or the second power semiconductor device 4, there is a problem that the first power semiconductor device 3 or the second power semiconductor device 4 may be damaged or a switching loss may occur in the first power semiconductor device 3 or the second power semiconductor device 4.

[0083] 6b, in the power semiconductor module 201 according to the first embodiment, the first power semiconductor device 240 and the second power semiconductor device 250 may be connected in series via the support 230 between the first substrate 210 and the second substrate 220. In this case, a current path is formed through the first substrate 210 (or its first signal pattern), the first power semiconductor device 240, the support 230, the second power semiconductor device 250, and the second substrate (or its second signal pattern).

[0084] At this time, the first power semiconductor device 240 and the second power semiconductor device 250 are spaced apart by only the thickness of the support 230, so that the distance between the first power semiconductor device 240 and the second power semiconductor device 250 is minimized. As a result, the current path between the first power semiconductor device 240 and the second power semiconductor device 250 is minimized, so that when the first power semiconductor device 240 or the second power semiconductor device 250 is turned off, stray inductance is minimized or not generated. As a result, not only is there no overshoot voltage or it is not minimized, but the overshoot voltage does not exceed the withstand voltage of the first power semiconductor device 240 or the second power semiconductor device 250, so that the first power semiconductor device 240 or the second power semiconductor device 250 is not damaged. In addition, since no switching loss occurs in the first power semiconductor device 240 or the second power semiconductor device 250, a preset high power output is possible.

[0085] In addition, in the power semiconductor module 201 according to the first embodiment, the first power semiconductor device 240 and the second power semiconductor device 250 are vertically stacked with the support in between, minimizing the layout area of ​​the first power semiconductor device 240 and the second power semiconductor device 250, thereby minimizing the size of the power semiconductor module 201 or the power conversion device. As a result, more first power semiconductor devices 240 and second power semiconductor devices 250 can be mounted per unit area in the power semiconductor module 201 or the power conversion device, enabling a higher power output.

[0086] Meanwhile, the power semiconductor module 201 according to the first embodiment may include a plurality of first terminals 270 and a plurality of second terminals 280. The first terminals 270 may be input terminals, and the second terminals 280 may be output terminals. Instead of the term "terminals," they may be called terminals, pins, lead frames, or the like.

[0087] The plurality of first terminals 270 are electrically connected to the first substrate 210 and / or the second substrate 220. The plurality of second terminals 280 are electrically connected to the first substrate 210 and / or the second substrate 220. The plurality of first terminals 270 may be members for receiving various signals, such as gate signals, high potential voltages, low potential voltages, ground voltages, etc. The plurality of second terminals 280 may be members for outputting various signals, such as output voltages, ground voltages, etc. In the drawings, the plurality of first terminals 270 and the plurality of second terminals 280 are provided in four each, but more than four each may be provided.

[0088] Meanwhile, the power semiconductor module 201 according to the first embodiment may include a mold 295. The mold 295 is disposed between the first substrate 210 and the second substrate 220. The mold 295 may surround an outer surface of the first power semiconductor device 240 between the first substrate 210 and the second substrate 220. The mold 295 may surround each of the plurality of first terminals 270 and the plurality of second terminals 280 between the first substrate 210 and the second substrate 220.

[0089] The mold 295 is disposed on the outer side of the first substrate 210 and the outer side of the second substrate 220. The mold 295 may surround each of the first terminals 270 on the outer side of the first substrate 210. The mold 295 may surround each of the second terminals 280 on the outer side of the second substrate 220.

[0090] The mold 295 can use EMC (Epoxy Molding Compound) as a semiconductor encapsulant, which is a material for sealing semiconductor devices such as silicone chips, gold wires 290, and lead frames to protect them from heat, moisture, and impact. EMC is a composite material made of more than 10 raw materials such as silica, epoxy resin, phenolic resin, carbon black, and flame retardant, and is used as an encapsulant for the first power semiconductor device 240, the second power semiconductor device 250, the first terminals 270, and the second terminals 280. The mold 295 is formed between the first substrate 210 and the second substrate 220, on the outside of the first substrate 210, on the outside of the second substrate 220, and the like, by using an EMC compounding process.

[0091] Meanwhile, the first power semiconductor device 240 may be bonded to the first substrate 210 and the support 230 using an adhesive member (not shown). For example, the first power semiconductor device 240 may be bonded to the first substrate 210 and the support 230 using an adhesive process such as soldering, sintering, or eutectic bonding. The second power semiconductor device 250 may be bonded to the second substrate 220 and the support 230 using an adhesive member. For example, the second power semiconductor device 250 may be bonded to the second substrate 220 and the support 230 using an adhesive process such as soldering, sintering, or eutectic bonding. The adhesive member may be made of a metal or metal alloy having excellent electrical conductivity and / or adhesive performance, but is not limited thereto. Pb, etc. may be used as an adhesive member during the soldering process. An Fe-Cu-C based material and an additive such as Ni, Mo, MnS, Pb, etc. may be used as an adhesive member during the sintering process. The adhesive material used in the eutectic bonding process may be Sn-Pb, Cu-Sn, Au-Sn, AU-Si, etc. Therefore, the first power semiconductor device 240 is physically fixed to and electrically connected to the first substrate 210 and the support 230 by the adhesive material. Also, the second power semiconductor device 250 is physically fixed to and electrically connected to the second substrate 220 and the support 230 by the adhesive material.

[0092] FIG. 4 is a cross-sectional view illustrating in detail the power semiconductor module according to the first embodiment.

[0093] 4, the first power semiconductor device 240 may include a first gate electrode 241, a first source electrode 242, and a first drain electrode 243 on its outer side. When the first power semiconductor device 240 is turned on in response to a gate signal applied to the first gate electrode 241, a current may flow from the first drain electrode 243 to the first source electrode 242.

[0094] The first drain electrode 243 is disposed on the lower side, and the first gate electrode 241 and the first source electrode 242 are disposed on the upper side. In this case, the first drain electrode 243 is physically fixed to and electrically connected to the upper side of the first substrate 210 through surface contact. The first source electrode 242 is physically fixed to and electrically connected to the lower side of the spacer 260 through surface contact. The first gate electrode 241 is electrically connected to the first substrate 210 via a wire 290.

[0095] The second power semiconductor device 250 may include a second gate electrode 251, a second source electrode 252, and a second drain electrode 253 on its outer side. When the second power semiconductor device 250 is turned on in response to a gate signal applied to the second gate electrode 251, a current may flow from the second drain electrode 253 to the first source electrode 242. The second drain electrode 253 is disposed on the lower side, and the second gate electrode 251 and the second source electrode 252 are disposed on the upper side. In this case, the second drain electrode 253 is physically fixed and electrically connected to the upper side of the support 230 through surface contact. The second source electrode 252 is physically and electrically connected to the lower side of the second substrate 220 through surface contact. The second gate electrode 251 is physically and electrically connected to the lower side of the second substrate 220 through surface contact. The structures of the first power semiconductor device 240 and the second power semiconductor device 250 may be the same as the structures of the power semiconductor devices illustrated in FIG. 5, but are not limited thereto.

[0096] Meanwhile, the first substrate 210 may include multiple layers. For example, the first substrate 210 may include a first metal layer 211, a first insulating layer 212, and a second metal layer 213.

[0097] The first metal layer 211 may be made of a material having excellent electrical conductivity. The first metal layer 211 may include a plurality of first signal patterns 211a to 211e. The first signal patterns 211a to 211e are electrically connected to the plurality of first terminals 270, the first power semiconductor device 240, the support 230, and the plurality of second terminals 280.

[0098] For example, the plurality of 1-1 signal patterns 211a are physically fixed to and electrically connected to the plurality of first terminals 270 using an adhesive member, respectively. For example, the plurality of 1-2 signal patterns 211b are physically fixed to and electrically connected to the plurality of second terminals 280 using an adhesive member, respectively. For example, the 1-3 signal pattern 211c is physically fixed to and electrically connected to the first region 231 of the support 230 using an adhesive member. The 1-3 signal pattern 211c is electrically connected to the latter one of the plurality of second terminals 280, and can supply a positive voltage or a negative voltage to the outside in response to turning on the first power semiconductor device 240 or the second power semiconductor device 250.

[0099] For example, the 1-4th signal pattern 211d is physically fixed and electrically connected to the first drain electrode 243 of the first power semiconductor device 240 using an adhesive member. The 1-4th signal pattern 211d is electrically connected to the latter one of the plurality of first terminals 270, and a high potential voltage (or a positive voltage) is supplied from the outside. For example, the 1-5th signal pattern 211e is electrically connected to the first gate electrode 241 of the first power semiconductor device 240 via a wire 290. The 1-5th signal pattern 211e is electrically connected to the latter one of the plurality of first terminals 270, and a gate signal is supplied from the outside.

[0100] The first insulating layer 212 can electrically insulate the first metal layer 211 and the second metal layer 213. The first insulating layer 212 can be made of a ceramic material having high thermal conductivity, such as Al2O3. The second metal layer 213 can be made of a material having excellent heat dissipation properties. One side of the second metal layer 213 is in contact with the first insulating layer 212 and can dissipate heat to the other side. Although not shown, a heat dissipation means including a cooling medium may be disposed on the other side of the second metal layer 213.

[0101] Meanwhile, the second substrate 220 may include a plurality of layers. For example, the second substrate 220 may include a third metal layer 221, a second insulating layer 222, and a fourth metal layer 223.

[0102] The third metal layer 221 may be made of a material having excellent electrical conductivity. The third metal layer 221 may include a plurality of second signal patterns 221a to 221d. The plurality of second signal patterns 221a to 221d are electrically connected to the plurality of first terminals 270, the second power semiconductor device 250, and the plurality of second terminals 280.

[0103] For example, the plurality of 2-1 signal patterns 221a are input signal patterns, and are physically fixed and electrically connected to the plurality of first terminals 270 using an adhesive member. For example, the plurality of 2-2 signal patterns 221b are output signal patterns, and are physically fixed and electrically connected to the plurality of second terminals 280 using an adhesive member. For example, the 2-3 signal pattern 221c is physically fixed and electrically connected to the second gate electrode 251 of the second power semiconductor device 250 using an adhesive member. The 2-3 signal pattern 221c is electrically connected to the latter one of the plurality of second terminals 280, and a gate signal is supplied from the outside. For example, the 2-4 signal pattern 221d is physically fixed and electrically connected to the second source electrode 252 of the second power semiconductor device 250 using an adhesive member. For example, the second-fourth signal pattern 221d is electrically connected to one of the second terminals 280 and receives a low potential voltage (or a negative voltage) from the outside.

[0104] The second insulating layer 222 can electrically insulate the third metal layer 221 and the fourth metal layer 223. The second insulating layer 222 can be made of a ceramic material having high thermal conductivity, such as Al2O3. The fourth metal layer 223 can be made of a material having excellent heat dissipation properties. One side of the fourth metal layer 223 is in contact with the second insulating layer 222 and can dissipate heat to the other side. Although not shown, a heat dissipation means including a cooling medium may be disposed on the other side of the fourth metal layer 223.

[0105] Referring back to FIG. 4 , each of the plurality of first terminals 270 may include a first-1 terminal 271 , a first insulating layer 272 and a first-2 terminal 273 .

[0106] The first insulating layer 272 can electrically insulate the 1-1 terminal 271 and the 1-2 terminal 273. The 1-1 terminal 271 is physically fixed to and electrically connected to the 1-1 signal pattern 211a of the first substrate 210. The 1-2 terminal 273 is physically fixed to and electrically connected to the 2-1 signal pattern 221a of the second substrate 220. Each of the plurality of second terminals 280 can include a 2-1 terminal 281, a second insulating layer 282, and a 2-2 terminal 283. The second insulating layer 282 can electrically insulate the 2-1 terminal 281 and the 2-2 terminal 283. The 2-1 terminal 281 is physically fixed to and electrically connected to the 1-2 signal pattern 211b of the first substrate 210. The 2-2 terminal 283 is physically fixed to and electrically connected to the 2-2 signal pattern 221 b of the second substrate 220 .

[0107] As described above, the first power semiconductor device 240 and the second power semiconductor device 250 may be vertically stacked. In this case, the first power semiconductor device 240 and the second power semiconductor device 250 may be connected in series with the support 230 and the spacer 260 interposed therebetween. That is, the spacer 260 and the support 230 are electrically connected, the first source electrode 242 of the first power semiconductor device 240 is electrically connected to the spacer 260, and the second drain electrode 253 of the second power semiconductor device 250 is electrically connected to the support 230, so that the first power semiconductor device 240 and the second power semiconductor device 250 may be connected in series.

[0108] In this case, as shown in FIG. 6a, according to the applicant's internal technology, when the first power semiconductor device 3 and the second power semiconductor device 4 are connected in series horizontally through the second substrate 2, the current path between the first power semiconductor device 3 and the second power semiconductor device 4 increases due to the distance between the first power semiconductor device 3 and the second power semiconductor device 4, and the floating inductance increases. The first power semiconductor device 3 or the fourth power semiconductor device 4 is damaged due to the increase in floating inductance. In addition, the switching loss of the first power semiconductor device 3 or the fourth power semiconductor device 4 increases due to the increase in floating inductance, and it is difficult to obtain a preset high power output due to the switching loss. In addition, the size increases because the first substrate 1 and the second substrate 2 are arranged to be separated by a certain distance in the horizontal direction, and a larger size is required to increase the high power output.

[0109] However, as shown in Fig. 6b, in the power semiconductor module 201 according to the first embodiment, the first power semiconductor device 240 and the second power semiconductor device 250 are connected vertically in series via the support 230, so that the current path is significantly reduced and stray inductance is not generated and is therefore minimized. As a result, damage to the first power semiconductor device 240 or the second power semiconductor device 250 is prevented, and switching loss is not generated, so that a preset high power output is possible. In addition, the vertical arrangement of the first power semiconductor device 240 and the second power semiconductor device 250 reduces the size, improves the output characteristics per unit area, and significantly reduces the product size and weight, improving the fuel efficiency of the automobile.

[0110] 7a to 7e illustrate a manufacturing process of a power semiconductor module according to an embodiment.

[0111] As shown in Figure 7a, a support 230 is provided. The support 230 may be made of metal.

[0112] The support 230 may include a first region 231, a second region 232, and a connecting portion 233. The second region 232 may be located higher than the first region 231. The connecting portion 233 may connect the first region 231 and the second region 232. A recess 235 is formed by the first region 231, the connecting portion 233, and the second region 232. The recess 235 is formed below the second region 232. The first region 231, the connecting portion 233, and the second region 232 may be integrally formed, but the embodiment is not limited thereto.

[0113] The second power semiconductor device 250 is formed on the support 230. The second power semiconductor device 250 is formed on the second region 232 of the support 230. The second power semiconductor device 250 may be adhered to the support 230 using an adhesive member. For example, after an adhesive member is formed on the underside of the second power semiconductor device 250 or on the second region 232 of the support 230, the second power semiconductor device 250 may be adhered to the second region 232 of the support 230 through an adhesive process.

[0114] As shown in Fig. 7b, a first substrate 210 is prepared. The first substrate 210 may be made of a material having excellent electrical conductivity and / or heat dissipation properties. A first power semiconductor device 240 is formed on the first substrate 210. The first power semiconductor device 240 may be adhered onto the first substrate 210 using an adhesive member. The first power semiconductor device 240 is electrically connected to the first substrate 210 via the adhesive member.

[0115] A spacer 260 is formed on the first power semiconductor device 240. The spacer 260 may be adhered onto the first power semiconductor device 240 using an adhesive member. The spacer 260 is electrically coupled to the first power semiconductor device 240 via the adhesive member. Meanwhile, the first power semiconductor device 240 is electrically coupled to the first substrate 210 via a wire 290.

[0116] Referring to FIG. 4, a first power semiconductor device 240 has a first drain electrode 243 disposed on a lower side, and a first source electrode 242 and a first gate electrode 241 disposed on an upper side.

[0117] The first drain electrode 243 of the first power semiconductor device 240 is electrically connected to the 1-4 signal pattern 211d of the first substrate 210 via an adhesive member, the first source electrode 242 of the first power semiconductor device 240 is electrically connected to the spacer 260 via an adhesive member, and the first gate electrode 241 of the first power semiconductor device 240 is electrically connected to the 1-5 signal pattern 211e of the first substrate 210 via a wire 290.

[0118] As shown in Fig. 7c, one side of the support 230 is fixed to the first substrate 210. The first region 231 of the support 230 may be attached to the first substrate 210 via an adhesive member. Referring to Fig. 4, the first region 231 of the support 230 is electrically connected to the 1-3 signal pattern 211c of the first substrate 210 via the adhesive member.

[0119] The recess 235 is made large enough so that the second region 232 of the support 230 is positioned higher than the top of the wire 290, thereby preventing an electrical short between the wire 290 and the support 230.

[0120] Meanwhile, the spacer 260 may allow the second region 232 of the support 230 to be maintained at a constant height without sagging downward. Therefore, the spacer 260 prevents the second region 232 of the support 230 from sagging downward and maintains a constant height, thereby preventing an electrical short between the support 230 and the wire 290. In addition, the spacer 260 may serve as a medium for electrical connection between the first power semiconductor device 240 and the support 230.

[0121] As shown in FIG. 7d, after positioning a plurality of first terminals 270 and a plurality of second terminals 280 on both sides of a first substrate 210, a second substrate 220 can be positioned on top of the first substrate 210, the plurality of first terminals 270, and the plurality of second terminals 280.

[0122] Thereafter, the first substrate 210 and / or the second substrate 220 are pressurized and heated, so that the first terminals 270 and the second terminals 280 are bonded to the first substrate 210, and the first terminals 270, the second terminals 280, and the second power semiconductor devices 250 are bonded to the second substrate 220. An adhesive member may be formed in advance on the lower side of the second substrate 220 or on the upper sides of the first terminals 270, the second terminals 280, and the second power semiconductor devices 250. As a result, the first terminals 270 and the second terminals 280 are bonded to the first substrate 210, and the first terminals 270, the second terminals 280, and the second power semiconductor devices 250 are bonded to the second substrate 220 via the adhesive member.

[0123] 4, the plurality of 1-1 terminals 271 are physically fixed to and electrically connected to the plurality of 1-1 signal patterns 211a of the first substrate 210 via an adhesive member. The plurality of 1-2 terminals 273 are physically fixed to and electrically connected to the plurality of 2-1 signal patterns 221a of the second substrate 220 via an adhesive member. The plurality of 2-1 terminals 281 are physically fixed to and electrically connected to the plurality of 1-2 signal patterns 211b of the first substrate 210 via an adhesive member. The plurality of 2-2 terminals 283 are physically fixed to and electrically connected to the plurality of 2-2 signal patterns 221b of the second substrate 220 via an adhesive member. The second power semiconductor device 250 has a second gate electrode 251 and a second source electrode 252 disposed on the upper side. The second source electrode 252 of the second power semiconductor device 250 is physically fixed to and electrically connected to the 2-3 signal pattern 221c of the second substrate 220 via an adhesive member. The second gate electrode 251 of the second power semiconductor device 250 is physically fixed to and electrically connected to the 2-4 signal pattern 221d of the second substrate 220 via an adhesive member.

[0124] As shown in Fig. 7e, a mold 295 is formed between the first substrate 210 and the second substrate 220, on the outside of the first substrate 210, on the outside of the second substrate 220, etc., using an EMC compounding process. In this way, the power semiconductor module (201 in Figs. 2 and 3) according to the first embodiment is manufactured.

[0125] FIG. 8 is a plan view illustrating a power semiconductor module according to the second embodiment.

[0126] The second embodiment is the same as the first embodiment except for the opening 236. In the second embodiment, components having the same shape, structure and / or function as those in the first embodiment are given the same reference numerals and detailed description thereof will be omitted.

[0127] 4 and 8, the power semiconductor module 202 according to the second embodiment may include a first substrate 210, a second substrate 220, a support 230, a first power semiconductor device 240, and a second power semiconductor device 250. The power semiconductor module 202 according to the second embodiment may include a spacer 260, a plurality of first terminals 270, a plurality of second terminals 280, and a mold 295.

[0128] The support 230 may include a first region 231, a second region 232, and a connecting portion 233. The connecting portion 233 may connect the first region 231 and the second region 232. The first region 231, the connecting portion 233, and the second region 232 may be integrally formed, but the embodiment is not limited thereto. The second region 232 may be located higher than the first region 231. A recess 235 is formed by the first region 231, the connecting portion 233, and the second region 232. The recess 235 is formed below the second region 232.

[0129] In such a case, the first power semiconductor device 240 is disposed in the recess 235, and the second power semiconductor device 250 is disposed above the second region 232. The first power semiconductor device 240 and the second power semiconductor device 250 may be vertically overlapped with the second region 232 of the support 230 in between.

[0130] Also, a spacer 260 is formed in the recess 235. The spacer 260 is disposed above the first power semiconductor device 240.

[0131] The first power semiconductor device 240 has a first drain electrode 243 disposed on a lower side, and a first gate electrode 241 and a first source electrode 242 disposed on an upper side. In this case, the first drain electrode 243 is electrically connected to the 1-4 signal pattern 211d of the first substrate 210, the first gate electrode 241 is electrically connected to the 1-5 signal pattern 211e of the first substrate 210 via the wire 290, and the first source electrode 242 is electrically connected to the spacer 260.

[0132] When a gate signal is supplied to the first gate electrode 241 of the first power semiconductor device 240 via the wire 290 to turn on the first power semiconductor device 240, a high potential voltage (or a positive voltage) is supplied to the support 230 via the first power semiconductor device 240 and the spacer 260. Thus, the wire 290 and the support 230 should not be electrically shorted because different voltages are supplied to them. However, if the wire 290 is bent into a curved shape or moved to a higher position, an electrical short may occur between the wire 290 and the support 230.

[0133] In order to overcome such a problem, in the power semiconductor module 202 according to the second embodiment, an opening 236 is formed in the support 230. For example, the opening 236 is formed corresponding to the wire 290. For example, the opening 236 is formed in the second region 232 of the support 230. For example, the opening 236 is formed in the connecting portion 233 of the support 230. For example, the opening 236 is formed in the first region 231 of the support 230. As a result, even if the wire 290 is deformed, the wire 290 is positioned in the opening 236 of the support 230, and an electrical short circuit between the support 230 and the wire 290 is prevented.

[0134] FIG. 9 is a cross-sectional view illustrating a power semiconductor module according to a third embodiment.

[0135] The third embodiment is the same as the first or second embodiment except for the shape of the support 230. In the third embodiment, components having the same shape, structure and / or function as those in the first or second embodiment are denoted by the same reference numerals and detailed description thereof will be omitted.

[0136] 9 , the power semiconductor module 203 according to the third embodiment may include a first substrate 210, a second substrate 220, a support 230, a first power semiconductor device 240, and a second power semiconductor device 250. The power semiconductor module 203 according to the third embodiment may include a spacer 260, a plurality of first terminals 270, a plurality of second terminals 280, and a mold 295.

[0137] The support 230 may include a first region 231, a second region 232, and a connecting portion 233. The connecting portion 233 may connect the first region 231 and the second region 232. The first region 231, the connecting portion 233, and the second region 232 may be integrally formed, but are not limited thereto. The second region 232 may be located higher than the first region 231.

[0138] The connecting part 233 may have a shape perpendicular to the ground. In the first or second embodiment, the connecting part 233 has a shape inclined with respect to the ground, whereas in the third embodiment, the connecting part 233 may have a shape perpendicular to the ground.

[0139] According to the third embodiment, since the connecting portion 233 has a shape perpendicular to the ground, the connecting portion 233 is spaced farther from the wire 290, so that the possibility of an electrical short between the support 230 and the wire 290 can be further reduced.

[0140] According to the third embodiment, the connecting portion 233 has a shape perpendicular to the ground, which further increases the rigidity of the support 230 and strengthens the fixation of the support 230, thereby suppressing the left-right displacement of the support 230, thereby further reducing the possibility of an electrical short between the support 230 and the wire 290. In addition, the increased support strength of the support 230 allows the second power semiconductor device 250 to be stably supported.

[0141] FIG. 10 is a cross-sectional view illustrating a power semiconductor module according to a fourth embodiment.

[0142] The fourth embodiment is the same as the first to third embodiments, except that the support 230 and the spacer 260 are integrally formed. In the fourth embodiment, components having the same shape, structure and / or function as those in the first to third embodiments are given the same reference numerals and detailed description thereof will be omitted.

[0143] 10 , a power semiconductor module 204 according to the fourth embodiment may include a first substrate 210, a second substrate 220, a support 230, a first power semiconductor device 240, and a second power semiconductor device 250. The power semiconductor module 204 according to the fourth embodiment may include a spacer 260, a plurality of first terminals 270, a plurality of second terminals 280, and a mold 295.

[0144] The support 230 may include a first region 231, a second region 232, and a connecting portion 233. The connecting portion 233 may connect the first region 231 and the second region 232. The first region 231, the connecting portion 233, and the second region 232 may be integrally formed, but the embodiment is not limited thereto. The second region 232 may be located higher than the first region 231. A recess 235 is formed by the first region 231, the connecting portion 233, and the second region 232. The recess 235 is formed below the second region 232.

[0145] In such a case, the first power semiconductor device 240 is disposed in the recess 235, and the second power semiconductor device 250 is disposed above the second region 232. The first power semiconductor device 240 and the second power semiconductor device 250 may be vertically overlapped with the second region 232 of the support 230 in between.

[0146] Also, a spacer 260 is formed in the recess 235. The spacer 260 is disposed above the first power semiconductor device 240.

[0147] In the power semiconductor module 204 according to the fourth embodiment, the support 230 and the spacer 260 may be integrally formed. That is, the spacer 260 may protrude from the support 230 toward the first power semiconductor device 240.

[0148] As one example, the support 230 may be etched using an etching process, and the unetched region may be formed as the spacer 260. As another example, the spacer 260 may be attached to the underside of the support 230 using an adhesion process. As yet another example, a plurality of metal layers may be formed on the underside of the support 230 using a plurality of deposition processes, and the plurality of metal layers may be formed as the spacer 260. In addition, the support 230 and the spacer 260 may be integrally formed through various processes.

[0149] According to the fourth embodiment, since there is no need to use an adhesive to bond the spacer 260 and the support 230, the process is simplified.

[0150] FIG. 11 is a circuit diagram showing an inverter for an automobile according to the second embodiment.

[0151] The second embodiment is the same as the first embodiment (FIG. 1) except that a plurality of power semiconductor devices 100a1, 100a2, 100b1, 100b2, 100c1, 100c2, 100d1, 100d2, 100e1, 100e2, 100f1, and 100f2 are connected in parallel to each of the arms 100a to 100f.

[0152] Referring to FIG. 11, the inverter 2000 for an automobile according to the second embodiment may include a three-phase inverter, but is not limited thereto. The inverter 2000 for an automobile according to the second embodiment may include a plurality of legs 100A, 100B, and 100C. For example, the first leg 100A, the second leg 100B, and the third leg 100C may be connected in parallel to the load 1200, i.e., the motor, via the first node N1, the second node N2, and the third node N3, respectively. The first leg 100A may include a first arm 100a and a second arm 100b connected in series to each other, the second leg 100B may include a third arm 100c and a fourth arm 100d connected in series to each other, and the third leg 100C may include a fifth arm 100e and a sixth arm 100f connected in series to each other. Here, the first arm 100a, the third arm 100c, and the fifth arm 100e can be referred to as upper arms, and the second arm 100b, the fourth arm 100d, and the sixth arm 100f can be referred to as lower arms.

[0153] The first arm 100a to the sixth arm 100f may each have a plurality of power semiconductor devices 100a1, 100a2, 100b1, 100b2, 100c1, 100c2, 100d1, 100d2, 100e1, 100e2, 100f1, and 100f2 connected in parallel. Although not shown, in each of the first arm 100a to the sixth arm 100f, diodes 100a-2, 100b-2, 100c-2, 100d-2, 100e-2, and 100f-2 may be connected in parallel to a plurality of power semiconductor devices 100a1, 100a2, 100b1, 100b2, 100c1, 100c2, 100d1, 100d2, 100e1, 100e2, 100f1, and 100f2, respectively.

[0154] The first arm 100a may have a plurality of first power semiconductor devices 100a1, 100a2 connected in parallel. The second arm 100b may have a plurality of second power semiconductor devices 100b1, 100b2 connected in parallel. The third arm 100c may have a plurality of first power semiconductor devices 100c1, 100c2 connected in parallel. The fourth arm 100d may have a plurality of second power semiconductor devices 100d1, 100d2 connected in parallel. The fifth arm 100e may have a plurality of first power semiconductor devices 100e1, 100e2 connected in parallel. The sixth arm 100f may have a plurality of second power semiconductor devices 100f1, 100f2 connected in parallel.

[0155] In this case, one side of each of the multiple first power semiconductor devices 100a1, 100a2 in the first arm 100a, one side of each of the multiple first power semiconductor devices 100c1, 100c2 in the third arm 100c, and one side of each of the multiple first power semiconductor devices 100e1, 100e2 in the fifth arm 100e may be commonly connected, where the one side may be a drain electrode.

[0156] The other sides of the first power semiconductor devices 100a1, 100a2 of the first arm 100a are commonly connected to a first node N1, the other sides of the first power semiconductor devices 100c1, 100c2 of the third arm 100c are commonly connected to a second node N2, and the other sides of the first power semiconductor devices 100e1, 100e2 of the fifth arm 100e are commonly connected to a third node N3. Here, the other sides may be source electrodes.

[0157] One side of each of the second power semiconductor devices 100b1, 100b2 in the second arm 100b is commonly connected to a first node N1, one side of each of the second power semiconductor devices 100d1, 100d2 in the fourth arm 100d is commonly connected to a second node N2, and one side of each of the second power semiconductor devices 100f1, 100f2 in the sixth arm 100f is commonly connected to a third node N3, where the one side may be a drain electrode.

[0158] The other side of each of the second power semiconductor devices 100b1, 100b2 in the second arm 100b, the other side of each of the second power semiconductor devices 100d1, 100d2 in the fourth arm 100d, and the other side of each of the second power semiconductor devices 100f1, 100f2 in the sixth arm 100f may be commonly connected, where one side may be a source electrode.

[0159] Meanwhile, the first power semiconductor devices 100a1, 100a2 of the first arm 100a included in the first leg 100A and the second power semiconductor devices 100b1, 100b2 of the second arm 100b included in the second leg 100A may be connected in series. The first power semiconductor devices 100c1, 100c2 of the third arm 100c included in the second leg 100B and the second power semiconductor devices 100d1, 100d2 of the fourth arm 100d included in the second leg 100B may be connected in series. The first power semiconductor devices 100e1, 100e2 of the fifth arm 100e included in the third leg 100C and the second power semiconductor devices 100f1, 100f2 of the sixth arm 100f included in the third leg 100C may be connected in series.

[0160] In this manner, a plurality of power semiconductor devices 100a1, 100a2, 100b1, 100b2, 100c1, 100c2, 100d1, 100d2, 100e1, 100e2, 100f1, and 100f2 are connected in parallel to each of the arms 100a to 100f, thereby improving the current characteristics and enabling high power output.

[0161] Fig. 12 is a plan view illustrating a power semiconductor module according to a fifth embodiment of the present invention, and Fig. 13 is a cross-sectional view illustrating a power semiconductor module according to the fifth embodiment of the present invention.

[0162] The power semiconductor module 205 according to the fifth embodiment may be one of the first leg 100A, the second leg 100B, and the third leg 100C illustrated in Fig. 11. Although not illustrated, the power semiconductor module 205 according to the fifth embodiment may include all of the first leg 100A, the second leg 100B, and the third leg 100C.

[0163] The fifth embodiment is the same as the first to fourth embodiments except for the plurality of first power semiconductor devices 240, 245 and the plurality of second power semiconductor devices 250, 255. In the fifth embodiment, components having the same shape, structure and / or function as the first to fourth embodiments are given the same reference numerals and detailed description thereof will be omitted.

[0164] 12 and 13 , a power semiconductor module 205 according to the fifth embodiment may include a first substrate 210, a second substrate 220, a support 230, a plurality of first power semiconductor devices 240, 245, and a plurality of second power semiconductor devices 250, 255. The power semiconductor module 205 according to the fifth embodiment may include a plurality of spacers 260, 265, a plurality of first terminals 270, a plurality of second terminals 280, and a mold 295.

[0165] The first substrate 210, the second substrate 220, the support 230, the plurality of first terminals 270 and the plurality of second terminals 280 have already been described in the first to fourth embodiments, so a detailed description thereof will be omitted.

[0166] The plurality of spacers 260, 265 are disposed between the first substrate 210 and the support 230. The plurality of spacers 260, 265 are disposed on the plurality of first power semiconductor devices 240, 245, respectively. Although not shown, the plurality of spacers 260, 265 may be integrally formed as a single spacer without being individually divided. Thus, the single spacer is disposed not only on the plurality of first power semiconductor devices 240, 245, but also in the spaces between the plurality of first power semiconductor devices 240, 245.

[0167] The plurality of first power semiconductor devices 240, 245 may be included in the first arm 100a of the first leg 100A, the third arm 100c of the second leg 100B, and / or the fifth arm 100e of the third leg 100C shown in FIG. 11. The plurality of first power semiconductor devices 240, 245 may be connected in parallel. One side of each of the plurality of first power semiconductor devices 240, 245 is commonly connected to the first substrate 210, and the other side of each of the first power semiconductor devices 240, 245 is commonly connected to the plurality of spacers 260, 265. The plurality of spacers 260, 265 may be commonly connected to the support 230. Here, one side may be the first drain electrode 243, and the other side may be the first source electrode 242.

[0168] Meanwhile, the other side of each of the plurality of first power semiconductor devices 240, 245 is connected to the first substrate 210 via a plurality of wires 290, 291. The other side of each of the plurality of first power semiconductor devices 240, 245 may be independently or commonly connected to the first substrate 210 via a plurality of wires 290, 291. Here, the other side may be the first gate electrode 241.

[0169] The second power semiconductor devices 250, 255 may be included in the second arm 100b of the first leg 100A, the fourth arm 100d of the second leg 100B, and / or the sixth arm 100f of the third leg 100C shown in Fig. 11. One side of each of the second power semiconductor devices 250, 255 may be commonly connected to the support 230, and the other side of each of the second power semiconductor devices 250, 255 may be commonly connected to the second substrate 220. Here, the one side may be a second drain electrode 253, and the other side may be a second source electrode 252.

[0170] Meanwhile, the other side of each of the plurality of second power semiconductor devices 250, 255 is coupled to the second substrate 220. The other side of each of the plurality of second power semiconductor devices 250, 255 may be independently or commonly coupled to the second substrate 220. Here, the other side may be a second gate electrode 251.

[0171] Each of the plurality of first power semiconductor devices 240, 245 and each of the plurality of second power semiconductor devices 250, 255 may be vertically stacked. Each of the plurality of first power semiconductor devices 240, 245 and each of the plurality of second power semiconductor devices 250, 255 may be vertically stacked with the support 230 in between. The plurality of first power semiconductor devices 240, 245 and the plurality of second power semiconductor devices 250, 255 may be serially connected to each other via the support 230.

[0172] Meanwhile, although not shown, in order to improve the withstand voltage characteristics, a plurality of first power semiconductor devices 240, 245 included in the first arm 100a, the third arm 100c, and the fifth arm 100e may be connected in series, and a plurality of second power semiconductor devices 250, 255 included in the second arm 100b, the fourth arm 100d, and the sixth arm 100f may be connected in series.

[0173] Although not shown, the plurality of first power semiconductor devices 240, 245 may be connected in parallel in the horizontal direction and in series in the vertical direction, or the plurality of first power semiconductor devices 240, 245 may be connected in parallel in the horizontal direction and in series in the vertical direction.

[0174] The plurality of second power semiconductor devices 250, 255 may be connected in parallel in the horizontal direction or in series in the vertical direction. Also, the plurality of second power semiconductor devices 250, 255 may be connected in parallel in the horizontal direction and in series in the vertical direction.

[0175] According to the fifth embodiment, a plurality of first power semiconductor devices 240, 245 are connected in parallel, and a plurality of second power semiconductor devices 250, 255 are connected in parallel, thereby improving current characteristics and enabling high power output.

[0176] The above detailed description should not be construed as limiting in all respects, but should be considered as illustrative. The scope of the embodiments should be determined by a reasonable analysis of the appended claims, and all modifications within the equivalent scope of the embodiments are included in the scope of the embodiments.

Claims

1. A first substrate; a second substrate formed on the first substrate; a conductive member disposed between the first substrate and the second substrate; a first power semiconductor device disposed between the first substrate and the conductive member; a second power semiconductor device disposed between the conductive member and the second substrate; The conductive member is electrically coupled to the first power semiconductor device and the second power semiconductor device.

2. The power semiconductor module of claim 1 , wherein the first power semiconductor device and the second power semiconductor device at least partially overlap.

3. The power semiconductor module of claim 1 , wherein the first power semiconductor device and the second power semiconductor device are electrically connected in series.

4. the conductive member includes a second region and a connecting portion connected to the second region, The power semiconductor module of claim 1 , wherein the second power semiconductor device is disposed on a surface of the second region.

5. the conductive member includes a first region located lower than the second region and connected to the connecting portion, the conductive member includes a recess formed by the first region, the connection portion, and the second region; The power semiconductor module of claim 4 , wherein the first power semiconductor device is disposed within the recess.

6. The power semiconductor module of claim 1 , further comprising a spacer disposed between the first power semiconductor device and the conductive member.

7. the first power semiconductor device includes a first gate electrode, a first source electrode, and a first drain electrode; the first gate electrode is electrically connected to the first substrate using a wire; the first source electrode is electrically connected to the conductive member; the first drain electrode is electrically connected to the first substrate; The power semiconductor module according to claim 6 , wherein an upper surface of the spacer is positioned higher than an uppermost position of the wires.

8. a plurality of first power semiconductor devices including the first power semiconductor device; a plurality of second power semiconductor devices including the second power semiconductor device; the plurality of first power semiconductor devices are connected in parallel between the first substrate and the conductive member; The power semiconductor module according to claim 1 , wherein the plurality of second power semiconductor devices are coupled in parallel between the conductive member and the second substrate.

9. 2. The power semiconductor module according to claim 1, wherein a current path is formed through the first substrate, the first power semiconductor device, the conductive member, the second power semiconductor device, and the second substrate in that order.

10. providing a first substrate; forming a first power semiconductor device on the first substrate; forming a conductive member on the first power semiconductor device such that the first power semiconductor device is disposed between the first substrate and the conductive member; forming a second power semiconductor device on the conductive member; forming a second substrate over the second power semiconductor device such that the second power semiconductor device is disposed between the conductive member and the second substrate; The method of forming a power semiconductor module, wherein the conductive member is disposed between the first substrate and the second substrate.

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