SiC SUBSTRATE, SiC EPITAXIAL WAFER, SEMICONDUCTOR SUBSTRATE, AND METHOD FOR PRODUCING SiC DEVICE

Abstract

To provide a SiC substrate, a SiC epitaxial wafer, or a semiconductor substrate characterized by resistance to occurrence of warpage.SOLUTION: A SiC substrate according to the present embodiment includes a first main surface and a second main surface opposite the first main surface, wherein each of the first and second main surfaces has an ion-implanted region containing an ion-implanted element within at least a 2 mm width from the outermost edge.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a method for manufacturing a SiC substrate, a SiC epitaxial wafer, a semiconductor substrate, and a SiC device. [Background technology]

[0002] Silicon carbide (SiC) has an electric breakdown field one order of magnitude larger than silicon (Si) and a band gap three times larger. Silicon carbide (SiC) also has properties such as a thermal conductivity about three times higher than silicon (Si). For this reason, silicon carbide (SiC) is expected to be applied to power devices, high-frequency devices, high-temperature operating devices, and the like. For this reason, SiC epitaxial wafers have come to be used in the above-mentioned semiconductor devices in recent years.

[0003] SiC epitaxial wafers are obtained by stacking a SiC epitaxial layer on the surface of a SiC substrate. Hereinafter, the substrate before the SiC epitaxial layer is stacked is referred to as the SiC substrate, and the substrate after the SiC epitaxial layer is stacked is referred to as the SiC epitaxial wafer. SiC substrates are produced by slicing from SiC ingots. SiC devices such as power devices, high frequency devices, and high temperature operating devices are obtained by forming devices in the SiC epitaxial layer of the SiC epitaxial wafer and then chipping the SiC epitaxial wafer.

[0004] SiC substrates and SiC epitaxial wafers may warp due to internal stress during the manufacturing process. For example, SiC epitaxial wafers are prone to warping because they have a SiC epitaxial layer on one side. Warping of SiC epitaxial wafers has adverse effects on semiconductor device processes. For example, warping can cause focus deviations in photolithography processing. Warping can also cause a decrease in the positional accuracy of the wafer during the transfer process.

[0005] For example, Patent Document 1 describes that warping of a SiC substrate can be reduced by alleviating crystallographic stress. For example, Patent Document 1 describes that warping of a SiC substrate can be reduced by implanting ions into one side of the SiC substrate in the direction of curvature of the SiC substrate. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] US Patent Application Publication No. 2021 / 0198804 Summary of the Invention [Problem to be solved by the invention]

[0007] The warpage reduction method described in Patent Document 1 implants ions into either surface depending on the warpage direction of the SiC substrate. The method described in Patent Document 1 is complicated because it is necessary to control which surface and which position to implant ions into depending on whether the SiC substrate is warped in a convex or concave direction.

[0008] The present invention has been made in consideration of the above problems, and has an object to provide a SiC substrate, a SiC epitaxial wafer, or a semiconductor substrate that can suppress warping of the substrate regardless of the warping direction of the substrate, and in which the occurrence of warping is suppressed. [Means for solving the problem]

[0009] The present inventors have found that warpage of a SiC substrate, a SiC epitaxial wafer, or a semiconductor substrate can be reduced by applying a tensile stress in the circumferential direction to both sides near the periphery by ion implantation.

[0010] (1) A SiC substrate according to a first aspect has a first main surface and a second main surface opposite to the first main surface, and the first main surface and the second main surface each have an ion-implanted region containing an ion-implanted element within a width of at least 2 mm from an outer periphery.

[0011] (2) In the SiC substrate according to the above aspect, the ion implantation region may have a depth of 1 μm or more from each of the first main surface and the second main surface.

[0012] (3) In the SiC substrate according to the above aspect, the absolute value of the tensile stress in the circumferential direction in the ion implantation region may be 10 MPa or more.

[0013] (4) The SiC substrate according to the above aspect may have a diameter of 145 mm or more.

[0014] (5) The SiC substrate according to the above aspect may have a diameter of 195 mm or more.

[0015] (6) In the SiC substrate according to the above aspect, the ion-implanted element may be Si or C.

[0016] (7) In the SiC substrate according to the above aspect, the ion-implanted element may be any one selected from the group consisting of Al, B, P, and N.

[0017] (8) A SiC epitaxial wafer according to a second aspect includes the SiC substrate according to the above aspect and a SiC epitaxial layer laminated on one surface of the SiC substrate.

[0018] (9) A SiC epitaxial wafer according to a third aspect has a SiC substrate and a SiC epitaxial layer stacked on one side of the SiC substrate, and a first main surface which is a surface of the SiC epitaxial layer and a second main surface which faces the first main surface and is a surface of the SiC substrate each have an ion-implanted region containing an ion-implanted element within a width of at least 2 mm from the outermost periphery.

[0019] (10) A semiconductor substrate according to a fourth aspect has a first main surface and a second main surface opposite to the first main surface, and the first main surface and the second main surface each have an ion-implanted region containing an ion-implanted element within a width of at least 2 mm from an outermost periphery.

[0020] (11) A fifth aspect of the present invention relates to a method for manufacturing an SiC device, comprising the steps of: implanting ions into a first main surface of an SiC substrate or an SiC epitaxial wafer having an SiC epitaxial layer stacked on one surface of the SiC substrate, and a second main surface opposite the first main surface at a position at least 2 mm away from the outermost periphery, and then forming the device into chips. Effect of the Invention

[0021] In the SiC substrate, SiC epitaxial wafer, or semiconductor substrate according to the above aspect, warping is suppressed. [Brief description of the drawings]

[0022] [Figure 1] FIG. 1 is a plan view of a SiC substrate in accordance with a first embodiment. [Diagram 2] 1 is a cross-sectional view of a SiC substrate according to a first embodiment. [Diagram 3] FIG. 1 is a schematic diagram for explaining a method for measuring a tensile stress applied by ion implantation. [Figure 4] FIG. 13 is a schematic diagram of another example for explaining a method for measuring tensile stress applied by ion implantation. [Diagram 5] 1 is a cross-sectional view of a SiC epitaxial wafer according to a first embodiment. [Figure 6] FIG. 1 is a cross-sectional view of a SiC epitaxial wafer according to a second embodiment. [Figure 7] FIG. 11 is a cross-sectional view of a semiconductor substrate according to a third embodiment. [Figure 8] 4 shows the simulation results of the first embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0023] The SiC substrate and the like according to this embodiment will be described in detail below with reference to the drawings as appropriate. The drawings used in the following description may show characteristic parts in an enlarged scale for the sake of convenience in order to make the characteristics of this embodiment easier to understand, and the dimensional ratios of each component may differ from the actual ones. The materials, dimensions, and the like exemplified in the following description are merely examples, and the present invention is not limited thereto, and may be appropriately modified and implemented within the scope of the present invention.

[0024] In this specification, individual orientations are indicated by [] and collective orientations by <>. For negative indices, a "-" (bar) is placed above the number in crystallography, but in this specification, a negative sign is placed before the number.

[0025] "First embodiment" FIG. 1 is a plan view of a SiC substrate 10 according to the first embodiment. <0001> The figure is a view seen from the direction. The SiC substrate 10 is made of, for example, n-type SiC. The polytype of the SiC substrate 10 is not particularly limited and may be any of 2H, 3C, 4H, and 6H. The SiC substrate 10 is, for example, 4H—SiC.

[0026] The SiC substrate 10 has a substantially circular shape in plan view. The SiC substrate 10 may have a notch 3 for grasping the direction of the crystal axis. Instead of the notch 3, the SiC substrate 10 may have an orientation flat.

[0027] The diameter of the SiC substrate 10 is, for example, 145 mm or more, preferably 149 mm or more. The diameter of the SiC substrate 10 is also 195 mm or more, preferably 199 mm or more. The larger the diameter of the SiC substrate 10, the larger the absolute amount of warping becomes even with the same curvature. A SiC epitaxial wafer with a large warp has a large effect on subsequent processes, and suppression of the warp is required. In other words, the present invention is more effective when applied to a SiC substrate 10 with a large diameter.

[0028] The SiC substrate 10 has an effective area 1 and an edge exclusion area 2. The effective area 1 is an area used for obtaining devices, and is the area of ​​the SiC substrate 10 excluding the edge exclusion area 2. The edge exclusion area 2 is an area within 3 mm from the outer periphery. The edge exclusion area 2 is an area that is generally not used for device fabrication.

[0029] FIG. 2 is a cross-sectional view of the SiC substrate 10 according to the first embodiment. The SiC substrate 10 has a first main surface 10A and a second main surface 10B. The second main surface 10B faces the first main surface 10A. The first main surface 10A may be a Si surface or a C surface. The first main surface 10A and the second main surface 10B may be mirror-finished mirror surfaces with scratches or the like remaining, or CMP-treated surfaces with CMP (Chemical Mechanical Polish), and the degree of polishing may be different between the first main surface 10A and the second main surface 10B. A process-affected layer is formed on the mirror surface with scratches or the like remaining, and almost no process-affected layer is formed on the CMP-treated surface. The process-affected layer is a portion that has been damaged by processing and has a collapsed crystal structure.

[0030] For example, when the first main surface 10A is a mirror-ground surface and the second main surface 10B is a CMP-treated surface, the Twyman effect occurs in the SiC substrate 10 due to the difference in surface conditions between the two surfaces. The Twyman effect is a phenomenon in which, when a difference occurs in the residual stress between the two surfaces of the substrate, a force acts to compensate for the difference in stress between the two surfaces. The Twyman effect can cause the SiC substrate 10 to warp. In other words, the present invention is more effective when applied to a SiC substrate 10 having different surface conditions between the first main surface 10A and the second main surface 10B.

[0031] The SiC substrate 10 has ion implantation regions 4 and 5. The ion implantation region 4 is on the first main surface 10A side of the SiC substrate 10. The ion implantation region 5 is on the second main surface 10B side of the SiC substrate 10. The ion implantation regions 4 and 5 are each located within a width of at least 2 mm from the outermost periphery of the SiC substrate 10. The ion implantation regions 4 and 5 are preferably each located within the edge exclusion region 2. The edge exclusion region 2 is not used for obtaining a device, so even if an ion implantation element is doped, the effect on the finally obtained device is small.

[0032] The ion implantation regions 4 and 5 include an ion implantation element. The ion implantation element is, for example, Si, C, Al, B, P, or N. The ion implantation element may be a rare gas element such as He, Ne, Ar, Kr, or Rd. When the ion implantation element is Si or C, the presence or absence of the ion implantation element can be determined by checking the presence or absence of interstitial atoms at the positions corresponding to the ion implantation regions 4 and 5. The interstitial atoms are detected as point defects, for example, by a photoluminescence method. When the ion implantation element is ion-implanted into the SiC substrate 10, the lattice constant is expanded. For example, when the SiC substrate 10 is 4H-SiC, the reference lattice constant is about 3.08 Å. The lattice constant at the positions corresponding to the ion implantation regions 4 and 5 is expanded from this reference lattice constant.

[0033] When the ion-implanted element is Si or C, it is possible to reduce contamination of the SiC substrate 10. When the ion-implanted element is Al, B, P, or N, it is possible to apply a tensile stress to the SiC substrate 10 and to change the SiC substrate 10 into an n-type or p-type semiconductor.

[0034] Tensile stress is applied to the ion implantation regions 4 and 5 by the ion implantation. As a result, the lattice constant in the ion implantation regions 4 and 5 is wider than the reference lattice constant. For example, the lattice constant in the ion implantation regions 4 and 5 is wider than the lattice constant in the center of the effective region 1.

[0035] The tensile stress applied by ion implantation is calculated as the product of the strain ε and the Young's modulus. The strain ε is expressed as (a 0-a) / a 0 It can be calculated by a 0 is the reference lattice constant. 0 is about 3.08 Å for 4H-SiC. a is the lattice constant determined by X-ray diffraction (XRD). The direction of the stress is determined from the direction of the incident X-rays in X-ray diffraction. The lattice constant a is the reference lattice constant a 0 The larger the strain ε, the larger the absolute value of the applied tensile stress. The tensile stress calculated by the above formula is expressed as a negative value. The larger the absolute value of the tensile stress, the larger the magnitude of the tensile stress. Note that if the value calculated by the above formula is positive, it means that the relevant part is in a state where compressive stress is applied.

[0036] FIG. 3 is a schematic diagram for explaining a method for measuring tensile stress applied by ion implantation. The circumferential direction at the first outer periphery point p1 is a direction (hereinafter referred to as the first direction) perpendicular to the line segment connecting the center C of the SiC substrate 10 and the first outer periphery point p1. The first direction is, for example, the <1-100> direction. When measuring the tensile stress in the circumferential direction at the first outer periphery point p1, X-rays are irradiated from the first direction. By irradiating the X-rays from this circumferential direction to the SiC substrate 10, the lattice constant a in the circumferential direction at the first outer periphery point p1 is obtained. Then, using this lattice constant a, the stress in the circumferential direction at the first outer periphery point p1 is obtained from the above formula. Note that if the measured lattice constant a is the reference lattice constant a, 0 If it is greater, it is considered that a tensile stress has been applied.

[0037] The reference lattice constant is the lattice constant at the first outer periphery point p1 before ion implantation. If it is difficult to obtain the lattice constant before ion implantation, the lattice constant at the center C can be used as the reference lattice constant. The lattice constant at the center C can be obtained by irradiating the center C with X-rays in the same manner as the first outer periphery point p1.

[0038] FIG. 4 is a schematic diagram for explaining another example of a method for measuring tensile stress applied by ion implantation. The circumferential direction at the second outer periphery point p2 is a direction (hereinafter referred to as the second direction) perpendicular to the line segment connecting the center C of the SiC substrate 10 and the second outer periphery point p2. The second direction is the <11-20> direction. When measuring the tensile stress in the circumferential direction at the second outer periphery point p2, X-rays are irradiated from the second direction. By irradiating the X-rays from this circumferential direction to the SiC substrate 10, the lattice constant a in the circumferential direction at the second outer periphery point p2 is obtained. Then, using this lattice constant a, the tensile stress in the circumferential direction at the second outer periphery point p2 is obtained from the above formula.

[0039] In the ion implantation regions 4 and 5, the absolute value of the tensile stress applied in the circumferential direction is preferably 10 MPa or more, and more preferably 30 MPa or more. When a tensile stress is applied in the circumferential direction to the ion implantation regions 4 and 5 located on the outer periphery side of the SiC substrate 10, the SiC substrate 10 expands outward. In other words, the SiC substrate 10 is pulled outward, and warping is less likely to occur.

[0040] The depth D4 of the ion implantation region 4 is preferably 1 μm or more from the first main surface 10A, more preferably 10 μm or more, and even more preferably 30 μm or more. The depth D4 of the ion implantation region 4 is preferably 100 μm or less from the first main surface 10A. The deeper the depth D4 of the ion implantation region 4, the greater the absolute value of the tensile stress caused by the ion implantation, and the greater the effect of suppressing warping of the SiC substrate 10. If the depth D4 of the ion implantation region 4 is too deep, mechanical destruction such as cracks may occur due to excessive stress.

[0041] The depth of the ion implanted region can be measured by secondary ion mass spectrometry (SIMS). The depth of the peak concentration in the SIMS analysis profile can be used. The ion implanted region also exhibits a unique photoluminescence spectrum. By performing photoluminescence measurements at any time while processing the SiC substrate 10 in the depth direction, the depth at which the unique photoluminescence spectrum is no longer observed is determined. This depth can be regarded as the depth of the ion implanted region.

[0042] The depth D5 of the ion implantation region 5 is preferably 1 μm or more from the second main surface 10B, more preferably 10 μm or more, and even more preferably 30 μm or more. The depth D5 of the ion implantation region 5 is preferably 100 μm or less from the second main surface 10B. The deeper the depth D5 of the ion implantation region 5, the greater the absolute value of the tensile stress applied by the ion implantation, and the greater the effect of suppressing warping of the SiC substrate 10. If the depth D5 of the ion implantation region 5 is too deep, mechanical destruction such as cracks may occur due to excessive stress.

[0043] The depth D4 of the ion implantation region 4 and the depth D5 of the ion implantation region 5 may be the same or different.

[0044] Next, an example of a manufacturing method of the SiC substrate 10 according to the first embodiment will be described. The SiC substrate 10 is obtained by slicing a SiC ingot. The SiC ingot is obtained by, for example, a sublimation method. The first main surface 10A and the second main surface 10B of the substrate sliced ​​from the SiC ingot are polished, for example, by grinding, mechanical polishing (MP), and chemical mechanical polishing (CMP) in this order.

[0045] Next, ions are implanted into a portion of the SiC substrate 10 within a width of at least 2 mm from the outermost periphery. Ions accelerated to high energy (for example, several keV to several MeV) are irradiated onto the SiC substrate 10, thereby enabling ion implantation into the SiC substrate 10. Portions of the first main surface 10A and the second main surface 10B into which ions are not desired to be implanted are masked. Ion implantation into a portion of the substrate within a width of at least 2 mm from the outermost periphery forms ion implanted regions 4 and 5.

[0046] When obtaining SiC devices, the planarized SiC substrate 10 after the ion implantation regions 4 and 5 are formed is cut into chips. For example, as shown in Fig. 5, a SiC epitaxial layer 20 is formed on the first main surface 10A of the SiC substrate 10, devices are processed in the SiC epitaxial layer 20, and then the SiC epitaxial wafer 50 is cut into chips, thereby obtaining a plurality of SiC devices.

[0047] In the SiC substrate 10 according to this embodiment, ion implantation regions 4, 5 are formed on the outer periphery of both the first main surface 10A and the second main surface 10B. Tensile stress is applied in the circumferential direction to the ion implantation regions 4, 5 located on the outer periphery side of the SiC substrate 10. Therefore, the SiC substrate 10 according to this embodiment is pulled outward and is less likely to warp. In addition, the SiC substrate 10 according to this embodiment has the ion implantation regions 4, 5 on the outer periphery of both the first main surface 10A and the second main surface 10B, so that warping can be reduced regardless of the curvature direction of the substrate before ion implantation. Therefore, it is not necessary to perform detailed evaluation of the substrate before ion implantation, and it is easy to obtain a SiC substrate 10 with little warping.

[0048] "Second embodiment" 6 is a cross-sectional view of a SiC epitaxial wafer 51 according to the second embodiment. The SiC epitaxial wafer 51 includes a SiC substrate 11 and a SiC epitaxial layer 21. The shape of the SiC epitaxial wafer 51 in plan view is substantially the same as that in FIG.

[0049] The SiC epitaxial wafer 51 has a first main surface 51A and a second main surface 51B. The second main surface 51B faces the first main surface 51A. The first main surface 51A is the surface on which the SiC epitaxial layer 21 is formed. The second main surface 51B coincides with the second main surface 11B of the SiC substrate 11.

[0050] The SiC epitaxial wafer 51 has the SiC epitaxial layer 21 formed on only one surface. The doping concentration of the SiC epitaxial layer 21 is often different from that of the SiC substrate 11. When the doping concentration of the SiC epitaxial layer 21 is different from that of the SiC substrate 11, a difference in lattice constant occurs between the SiC epitaxial layer 21 and the SiC substrate 11. The difference in lattice constant causes the SiC epitaxial wafer 51 to warp.

[0051] The SiC epitaxial wafer 51 has ion implantation regions 6 and 7. The ion implantation region 6 is on the first main surface 51A side of the SiC epitaxial wafer 51. The ion implantation region 6 is in the SiC epitaxial layer 21. The ion implantation region 7 is on the second main surface 51B side of the SiC epitaxial wafer 51. The ion implantation region 7 is in the SiC substrate 11. The ion implantation regions 6 and 7 are each located within a width of at least 2 mm from the outermost periphery of the SiC epitaxial wafer 51. It is preferable that the ion implantation regions 6 and 7 are each located in the edge exclusion region 2.

[0052] The ion implantation regions 6 and 7 include an ion implantation element. The ion implantation element is the same as the ion implantation element used in the ion implantation regions 4 and 5. In the ion implantation regions 6 and 7, the absolute value of the tensile stress applied in the circumferential direction is preferably 10 MPa or more, more preferably 30 MPa or more. The depth D6 of the ion implantation region 6 from the first main surface 51A is the same as the depth of the ion implantation region 4 from the first main surface 10A. The depth D6 may be greater than the thickness of the SiC epitaxial layer 21. The depth D7 of the ion implantation region 7 from the second main surface 51B is the same as the depth of the ion implantation region 5 from the second main surface 10B.

[0053] The SiC epitaxial wafer 51 according to the second embodiment can be fabricated by forming the SiC epitaxial layer 21 on the first main surface 11A of the SiC substrate 11 and then implanting ions into predetermined positions. In addition, a plurality of SiC devices can be obtained by processing devices in the SiC epitaxial layer 21 of the SiC epitaxial wafer 51 and then forming the devices into chips.

[0054] In the SiC epitaxial wafer 51 according to this embodiment, ion implantation regions 6, 7 are formed on the outer periphery of both the first main surface 51A and the second main surface 51B. Therefore, the SiC epitaxial wafer 51 according to this embodiment is less likely to warp, similar to the SiC substrate 10 according to the first embodiment. In addition, the SiC epitaxial wafer 51 according to this embodiment has the ion implantation regions 6, 7 on the outer periphery of both the first main surface 51A and the second main surface 51B, so that warping can be reduced regardless of the curvature direction of the substrate before ion implantation. Therefore, it is not necessary to perform detailed evaluation of the substrate before ion implantation, and it is easy to obtain a SiC epitaxial wafer 51 with little warping.

[0055] "Third embodiment" 7 is a cross-sectional view of a semiconductor substrate 30 according to a third embodiment. The semiconductor substrate 30 is, for example, a Si substrate, a sapphire substrate, or a compound semiconductor substrate (for example, a GaP substrate, a GaAs substrate, an InP substrate, or a GaN substrate). The shape of the semiconductor substrate 30 in plan view is substantially the same as that in FIG.

[0056] The semiconductor substrate 30 has a first main surface 30A and a second main surface 30B. The second main surface 30B faces the first main surface 30A.

[0057] The semiconductor substrate 30 has ion implantation regions 8 and 9. The ion implantation region 8 is on the first main surface 30A side of the semiconductor substrate 30. The ion implantation region 9 is on the second main surface 30B side of the semiconductor substrate 30. The ion implantation regions 8 and 9 are each located within a width of at least 2 mm from the outermost periphery of the semiconductor substrate 30. It is preferable that each of the semiconductor substrates 30 is located within an edge exclusion region 2.

[0058] The ion implantation regions 8 and 9 contain an ion implantation element. The ion implantation element is the same as the ion implantation element used in the ion implantation regions 4 and 5. In the ion implantation regions 8 and 9, the absolute value of the tensile stress applied in the circumferential direction is preferably 10 MPa or more, and more preferably 30 MPa or more. The depth D8 of the ion implantation region 8 from the first main surface 30A is the same as the depth of the ion implantation region 4 from the first main surface 10A. The depth D9 of the ion implantation region 9 from the second main surface 30B is the same as the depth of the ion implantation region 9 from the second main surface 30B.

[0059] The semiconductor substrate 30 according to the third embodiment can be fabricated by implanting ions into predetermined positions of a semiconductor substrate.

[0060] In the semiconductor substrate 30 according to this embodiment, ion implantation regions 8, 9 are formed on the outer periphery of both the first main surface 30A and the second main surface 30B. Therefore, the semiconductor substrate 30 according to this embodiment is less likely to warp, similar to the SiC substrate 10 according to the first embodiment. Furthermore, the semiconductor substrate 30 according to this embodiment has the ion implantation regions 8, 9 on the outer periphery of both the first main surface 30A and the second main surface 30B, so that warping can be reduced regardless of the curvature direction of the substrate before ion implantation. Therefore, it is not necessary to perform detailed evaluation of the substrate before ion implantation, and it is easy to obtain a semiconductor substrate 30 with little warping.

[0061] Although the preferred embodiment of the present invention has been described in detail above, the present invention is not limited to the specific embodiment, and various modifications and changes are possible within the scope of the gist of the present invention described in the claims. EXAMPLES

[0062] Example 1 The amount of warpage of a SiC epitaxial wafer, in which an ion-implanted element is ion-implanted into the outer periphery of both sides of a SiC substrate and a SiC epitaxial layer is laminated on the surface of the SiC substrate, was calculated by simulation. The simulation was performed using the finite element method simulator ANSYS. It was separately confirmed that the simulation using the finite element method simulator ANSYS matched the results of the actual product.

[0063] The simulation was performed using the following procedure. First, the physical properties of the SiC substrate and the surface layer with different stresses were set. The physical properties to be set were the thickness of the SiC substrate, the film thickness of the surface layer, Young's modulus, and Poisson's ratio. The thickness of the SiC substrate was set to 350 μm. The diameter of the SiC substrate was set to 150 mm. The Young's modulus of the SiC substrate was set to 480 GPa, and the Poisson's ratio was set to 0.20. The film thickness of the surface layer was set to 10 μm. The Young's modulus and Poisson's ratio of the surface layer were set to the same values ​​as those of the SiC substrate. It was assumed that the lattice constant of the surface layer was wider than that of the SiC substrate, and a tensile stress of 60 MPa was applied to the surface layer due to the difference in lattice constant between the surface layer and the SiC substrate.

[0064] Under the above conditions, the width and depth of the ion implantation region were changed to determine the amount of warpage of the SiC epitaxial wafer.

[0065] Comparative Example 1 The amount of warpage of the SiC epitaxial wafer in the case where ion implantation was not performed was measured. The amount of warpage of the SiC epitaxial wafer in Comparative Example 1 was 122.4 μm.

[0066] Fig. 8 shows the simulation results of Example 1. As shown in Fig. 8, the wider the ion implantation region was and the deeper it was, the smaller the amount of warpage of the SiC epitaxial wafer became.

[0067] Example 2 In Example 2, the width and depth of the ion implantation region were fixed at 3 mm and 30 μm, respectively, and the tensile stress applied by ion implantation was changed. The tensile stress by ion implantation can be changed by changing the dose of the ion implantation element into the ion implantation region.

[0068] Table 1 shows the simulation results of Example 2. Table 1 also shows the results of Comparative Example 1 for reference.

[0069] [Table 1]

[0070] As shown in Table 1, the greater the absolute value of the tensile stress applied to the outer peripheral edge of the SiC substrate, the more the warpage of the SiC epitaxial wafer was reduced. [Explanation of symbols]

[0071] 1. Effective Area 2 Edge Exclusion Area 3 Notches 4,5,6,7,8,9 Ion implantation area 10. SiC Substrate 10A, 30A, 51A First main surface 10B,30B,51B 2nd main surface 20,21 SiC epitaxial layer 30 Semiconductor Substrate 50,51 SiC epitaxial wafer C center p1 First outer perimeter point p2 Second outer perimeter point

Claims

1. A first main surface and a second main surface opposite to the first main surface, The SiC substrate, wherein the first main surface and the second main surface each have an ion implantation region containing an ion implantation element within a width of at least 2 mm from an outermost periphery.

2. 2 . The SiC substrate according to claim 1 , wherein the ion implantation region has a depth of 1 μm or more from each of the first main surface and the second main surface.

3. The SiC substrate according to claim 1 , wherein an absolute value of the tensile stress in the circumferential direction in the ion implanted region is 10 MPa or more.

4. The SiC substrate according to claim 1 , having a diameter of 145 mm or more.

5. The SiC substrate according to claim 1 , having a diameter of 195 mm or more.

6. The SiC substrate according to claim 1 , wherein the ion-implanted element is Si or C.

7. The SiC substrate according to claim 1 , wherein the ion-implanted element is any one selected from the group consisting of Al, B, P, and N.

8. 2. A SiC epitaxial wafer comprising: the SiC substrate according to claim 1; and a SiC epitaxial layer laminated on one surface of the SiC substrate.

9. A SiC substrate and a SiC epitaxial layer laminated on one surface of the SiC substrate, A SiC epitaxial wafer, wherein a first main surface which is a surface of the SiC epitaxial layer and a second main surface which is opposite to the first main surface and is a surface of the SiC substrate each have an ion implantation region containing an ion implantation element within a width of at least 2 mm from an outermost periphery.

10. A first main surface and a second main surface opposite to the first main surface, The first main surface and the second main surface each have an ion implantation region containing an ion implantation element within a width of at least 2 mm from an outermost periphery of the semiconductor substrate.

11. A method for manufacturing a SiC device, comprising the steps of: implanting ions into a first main surface of a SiC substrate or a SiC epitaxial wafer having a SiC epitaxial layer stacked on one surface of the SiC substrate, and a second main surface opposite the first main surface at a position at least 2 mm away from the outermost periphery, and then forming the substrate into a chip.

Images