Semiconductor device and method for manufacturing the semiconductor device

Abstract

To provide a semiconductor device (a power MOSFET) capable of reducing a manufacturing cost, and provide a method for manufacturing them.SOLUTION: A semiconductor device 100 includes a silicon carbide epitaxy layer 101. In the silicon carbide epitaxy layer, a p-type embedded layer PB and a junction field effect region JF are contained. The junction field effect region is contacted to the p-type embedded layer in a gate electrode region CTG. The semiconductor device further includes: a gate electrode oxide layer 102 that is existed onto the silicon carbide epitaxy layer; a polysilicon layer 103 on the gate electrode oxide layer; an inter-layer dielectric layer 104 on the polysilicon layer; a first concave 109 that penetrates the inter-layer dielectric layer, the polysilicon layer and the gate electrode oxide layer in a source electrode region, and is formed in the silicon carbide epitaxy layer; and a second concave 111 that is formed in the polysilicon layer in the gate electrode region, and of which a bottom surface is higher than an upper surface of the gate electrode oxide.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device, and more particularly to a power MOSFET (MOSFET). [Background technology]

[0002] In conventional power MOSFETs, a photomask must be formed to form the p-type buried layer, which increases costs. In addition, the parasitic capacitance Cgd of conventional power MOSFETs is large, so the switching speed of the transistor is not ideal. To overcome these challenges, a new semiconductor device and a method for manufacturing the semiconductor device are required. Summary of the Invention

[0003] In view of the above, the present invention provides a semiconductor device comprising a silicon carbide epitaxy layer, the silicon carbide epitaxy layer having a p-type buried layer and a junction field effect region, the junction field effect region contacting the p-type buried layer in a gate pole region, the semiconductor device further comprising a gate anodization layer on the silicon carbide epitaxy layer, a polysilicon layer on the gate anodization layer, an interlayer dielectric layer on the polysilicon layer, a first recess formed in the silicon carbide epitaxy layer through the interlayer dielectric layer, the polysilicon layer and the gate anodization layer in a source pole region, and a second recess formed in the polysilicon layer in the gate pole region, the bottom surface of which is higher than the top surface of the gate anodization layer.

[0004] A method for manufacturing a semiconductor device of the present invention includes depositing a first oxide film, a first polysilicon film, and a second oxide film in this order on a silicon carbide epitaxy layer, etching the second oxide film and the first polysilicon film after a pattern of a p-type buried layer is defined, stopping the etching at the first oxide film, implanting a p-type buried layer in the silicon carbide epitaxy layer, depositing a second polysilicon film, etching back the second polysilicon film, implanting a p-type well region above the p-type buried layer, and depositing a third oxide film and a third polysilicon film in this order. a first heavily doped p-type region beneath the heavily doped n-type region and into the p-type well region; and removing the first oxide film, the first polysilicon film, the second oxide film, the second polysilicon film, the third oxide film, the third polysilicon film, the fourth oxide film, and the fourth polysilicon film.

[0005] As described above, in the semiconductor device, the bottom surface of the second recess in the gate electrode region is higher than the top surface of the gate electrode oxide layer, so that the dielectric layer between the gate electrode and the drain electrode is thick. In addition, since there is no overlapping portion between the gate electrode and the drain electrode, the parasitic capacitance Cgd between the gate electrode and the drain electrode is small, and the switching speed can be improved. In addition, when manufacturing the semiconductor device, only one photomask is used, and self-alignment is performed by multiple spacers, and the p-type buried layer, the p-type well region, the heavily doped n-type region, and the heavily doped p-type region PP1 in the source electrode region are defined from the outside to the inside, and the number of photomasks is not increased, so that the cost does not increase. [Brief description of the drawings]

[0006] [Figure 1] 1 is a cross-sectional view of a semiconductor device 100 according to the present invention. [Diagram 2]2 is a flow chart of a method 200 for manufacturing a semiconductor device in accordance with the present invention. [Diagram 3] 2 is another cross-sectional view of the semiconductor device 100. FIG. [Figure 4] 2 is another cross-sectional view of the semiconductor device 100. FIG. [Diagram 5] 2 is another cross-sectional view of the semiconductor device 100. FIG. [Figure 6] 2 is another cross-sectional view of the semiconductor device 100. FIG. [Figure 7] 2 is another cross-sectional view of the semiconductor device 100. FIG. [Figure 8] 2 is another cross-sectional view of the semiconductor device 100. FIG. [Figure 9] 2 is another cross-sectional view of the semiconductor device 100. FIG. [Figure 10] 2 is another cross-sectional view of the semiconductor device 100. FIG. [Figure 11] 2 is another cross-sectional view of the semiconductor device 100. FIG. [Figure 12] 2 is another cross-sectional view of the semiconductor device 100. FIG. [Figure 13] 2 is another cross-sectional view of the semiconductor device 100. FIG. [Figure 14] 2 is another cross-sectional view of the semiconductor device 100. FIG. [Figure 15] 2 is another cross-sectional view of the semiconductor device 100. FIG. [Figure 16] 2 is another cross-sectional view of the semiconductor device 100. FIG. [Figure 17] 2 is another cross-sectional view of the semiconductor device 100. FIG. [Figure 18] 2 is another flow chart of a method 200 for manufacturing a semiconductor device in accordance with the present invention. [Figure 19] 2 is another flow chart of a method 200 for manufacturing a semiconductor device in accordance with the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] FIG. 1 is a cross-sectional view of a semiconductor device 100 according to the present invention. As shown in FIG. 1, the semiconductor device 100 has a unit cell region UC, a gate electrode lead region GL outside the unit cell region UC, and a guard ring region. The semiconductor device 100 has a silicon carbide epitaxy layer 101, a gate electrode oxide layer 102, a polysilicon layer 103, an interlayer dielectric layer 104, a contact spacer 105, an island-like oxide layer 108, a field oxide layer FOX outside the unit cell region UC, a passivation layer 114, and a polyimide layer 115. The silicon carbide epitaxy layer 101 also has a p-type well region 106, a heavily doped n-type region 107, a silicide SC, a p-type buried layer PB, a junction field effect region JF, a heavily doped p-type region PP1, and a heavily doped p-type region PP2 outside the unit cell region UC.

[0008] Specifically, in the silicon carbide epitaxy layer 101, the p-type well region 106 is above the p-type buried layer PB, the heavily doped p-type region PP1 is below the heavily doped n-type region 107 and in the p-type well region 106, the heavily doped n-type region 107 is on the surface of the p-type well region 106 and partially overlaps the heavily doped p-type region PP1, and the depth of the heavily doped p-type region PP1 is greater than the depth of the heavily doped n-type region 107. The junction field effect region JF contacts the p-type buried layer in the gate pole region. The gate anodization layer 102 is above the silicon carbide epitaxy layer 101, and the gate anodization layer 102 overlaps a portion of the heavily doped n-type region 107 and a portion of the p-type well region 106. The polysilicon layer 103 is above the gate anodization layer 102, and the polysilicon layer 103 is formed as the gate pole of the transistor. An interlevel dielectric layer 104 overlies the polysilicon layer 103, and a contact spacer 105 overlies the gate electrode oxide layer 102 and contacts the polysilicon layer 103 and the interlevel dielectric layer 104. An island oxide layer 108 overlies the junction field effect region JF, and the thickness of the island oxide layer 108 is greater than the thickness of the gate electrode oxide layer 102.

[0009] The semiconductor device 100 further has a first recess 109 and a first recess 111. The first recess 109 penetrates the interlayer dielectric layer 102, the polysilicon layer 103, and the gate electrode oxide layer 104 in the source electrode region CTS, and is formed in the silicon carbide epitaxy layer 101. The second recess 111 is formed in the polysilicon layer 103 in the gate electrode region CTG, and the bottom surface of the second recess 111 is the top surface of the island-shaped oxide layer 108, and the bottom surface of the second recess 111 is higher than the top surface of the gate electrode oxide layer 102. The island-shaped oxide layer 108 in the gate electrode region CTG thickens the dielectric layer between the gate electrode and the drain electrode. In addition, since there is no overlapping portion between the gate electrode and the drain electrode, the parasitic capacitance Cgd is reduced, and the switching speed can be improved. Meanwhile, the island-shaped oxide layer 108 allows the polysilicon layer 103 to reduce the tip electric field in the gate electrode region CTG. The metal layer 110 is used to form a source contact and a gate contact. The metal layer 110 is in the first recess 109 and contacts the first heavily doped p-type region PP1 and the heavily doped n-type region 107 through the silicide SC. The metal layer 110 also contacts the polysilicon layer 103 in the gate pole region CTG. The metal layer 110 is disposed on and contacts the interlayer dielectric layer 104 and the contact spacer 105. In the gate pole region CTG, the interlayer dielectric layer 104 is disposed in the second recess 111, so that the metal layer 110 does not contact the polysilicon layer 103 in the second recess 111. The heavily doped p-type region PP2 is outside the unit cell region UC and contacts the p-type well region 106.

[0010] It should be noted that, on the back surface of the silicon carbide epitaxial layer 101, the semiconductor device 100 has a silicon carbide substrate (not shown) below the silicon carbide epitaxial layer 101 and a metal layer (not shown) below the silicon carbide substrate. The metal layer below the silicon carbide substrate is used to form a drain electrode contact, and the composition of the metal layer 110 and the metal layer below the silicon carbide substrate includes, but is not limited to, Ni, Ti, TiN, AlCu, etc. A field oxide layer FOX is provided on the heavily doped p-type region PP2 outside the unit cell region UC. In some embodiments, a passivation layer 114 can be further provided on the metal layer 110 and the field oxide layer FOX, and a polyimide layer 115 can be further provided on the passivation layer 114.

[0011] FIG. 2 is a flow chart of a method 200 for manufacturing a semiconductor device according to the present invention, and FIGS. 3 to 8 are cross-sectional views of the semiconductor device 100, which are used to explain steps S1 to S6 of the method 200. First, in step S1, as shown in FIG. 3, an oxide film OF1, a polysilicon film PF1, and an oxide film OF2 are deposited in this order on a silicon carbide epitaxy layer 101. In step S2, as shown in FIG. 4, after a pattern of a p-type buried layer is defined, the oxide film OF2 and the polysilicon film PF1 are etched, the etching is stopped at the oxide film OF1, and a p-type buried layer PB is implanted in the silicon carbide epitaxy layer 101. In step S3, as shown in FIG. 5, a polysilicon film PF2 is deposited, the polysilicon film PF2 is etched back (the oxide film OF1 is used as an etching stop layer), and a p-type well region 106 is implanted above the p-type buried layer PB. In step S4, as shown in Fig. 7, an oxide film OF3 and a polysilicon film PF3 are deposited in this order (as shown in Fig. 6), the polysilicon film PF3 is etched back (the oxide film OF3 is used as an etching stop layer), and a heavily doped n-type region 107 is implanted in the surface of the p-type well region 106. In step S5, as shown in Fig. 8, an oxide film OF4 and a polysilicon film PF4 are deposited in this order, the polysilicon film PF4 is etched back (the oxide film OF4 is used as an etching stop layer), and a heavily doped p-type region PP1 is implanted below the heavily doped n-type region 107 and in the p-type well region 106. In step S6, the oxide film OF1, the polysilicon film PF1, the oxide film OF2, the polysilicon film PF2, the oxide film OF3, the polysilicon film PF3, the oxide film OF4, and the polysilicon film PF4 are removed.

[0012] In addition, the method 200 further includes steps S7 to S19, as shown in FIG. 18 and FIG. 19. Referring to FIG. 9, in step S7, a junction field effect region JF is formed. In step S8, a heavily doped p-type region PP2 is formed outside the unit cell region UC. In step S9, a field oxide layer FOX is formed on a portion of the heavily doped p-type region PP2, as shown in FIG. 10. In step S10, an island-shaped oxide layer 108 is formed on the junction field effect region JF, as shown in FIG. 11. In step S11, a gate pole oxide layer 102 and a polysilicon layer 103 are deposited, as shown in FIG. 12. In step S12, a second recess 111 is formed in the gate pole region CTG by etching the polysilicon layer 103 to expose the island-shaped oxide layer 108. In step S13, as shown in FIG. 13, an interlayer dielectric layer 104 is deposited. As shown in FIG. 14, in step S14, the interlayer dielectric layer 104 and the polysilicon layer 103 are etched in the source pole region CTS, and the etching is stopped at the gate pole oxide layer 102.

[0013] As shown in FIG. 15, in step S15, a contact spacer 105 is deposited on the interlayer dielectric layer 104 and the gate electrode oxide layer 102. As shown in FIG. 16, in step S16, the contact spacer 105 and the gate electrode oxide layer 102 are etched back to expose the interlayer dielectric layer 104 and the heavily doped n-type region 107. As shown in FIG. 17, in step S17, a blanket etching process is performed to form a first recess 109 in the source pole region CTS to expose the heavily doped p-type region PP1. And the depth of the first recess 109 is greater than the depth of the heavily doped n-type region 107. During the blanket etching process, the silicon carbide epitaxy layer 101 has a high etching selectivity with respect to the field oxide layer FOX, the interlayer dielectric layer 104 and the contact spacer 105. 1, the method 200 further includes a step S18 of depositing a metal layer 110 in the gate pole region CTG and the source pole region CTS, but before depositing the metal layer 110, a silicide SC may be formed on the heavily doped p-type region PP1 and the heavily doped n-type region 107. The method 200 further includes a step S19 of forming another metal layer beneath the silicon carbide substrate below the silicon carbide epitaxy layer 101.

[0014] In the method 200, one photomask is used to self-align a number of spacers (e.g., polysilicon films PF1 to PF4) to define a p-type buried layer PB, a p-type well region 106, a heavily doped n-type region 107, and a heavily doped p-type region PP1 from outside to inside. As shown in the region MS in FIG. 1, the region MS is a region for manufacturing a number of spacers, and the conditions of the heavily doped p-type region PP1 can be freely selected, so there is no need to consider the conditions of the heavily doped p-type region PP2 in the guard ring region GR. When implanting the heavily doped p-type region PP1, according to the method of the present invention, the concentration corresponding to low energy can be omitted and the concentration of the heavily doped n-type region 107 is not affected. By implanting the heavily doped p-type region PP1 while omitting the concentration corresponding to low energy, the concentration of the heavily doped n-type region 107 is increased, which increases the contact area between the silicide SC and the heavily doped n-type region 107 and reduces the contact resistance.

[0015] The features of some embodiments have been outlined above to allow those skilled in the art to better understand the present specification. It is understood by those skilled in the art that other processes and structures can be designed or modified based on the contents of the present invention to achieve the same purpose and / or the same advantages as those of the above examples. It is also understood by those skilled in the art that equivalent structures that do not depart from the spirit and scope of the present invention can be modified, substituted, and altered in various ways without departing from the spirit and scope of the present invention. [Explanation of symbols]

[0016] 100: Semiconductor device 200: Method 101: Silicon carbide epitaxial layer 102: Gate anodization layer 103: Polysilicon layer 104: Interlayer dielectric layer 105: Contact spacer 106: p-type well region 107: Heavily doped n-type region 108: Island oxide layer 109: First dent 110: Metal layer 111: Second dent 114: Passivation layer 115: Polyimide layer FOX: Field oxide layer SC: Silicide PB: p-type buried layer JF: Junction field effect region CTS: Source pole region CTG: gate pole region PP1: heavily doped p-type region PP2: Heavily doped p-type region UC: Unit cell domain GL: Gate electrode lead area GR: Protection Ring Region MS: Area OF1: Oxide film OF2: Oxide film OF3: Oxide film OF4: Oxide film PF1: Polysilicon film PF2: Polysilicon film PF3: Polysilicon film PF4: Polysilicon film S1: Step S2: Step S3: Step S4: Step S5: Step S6: Step

Claims

1. a p-type buried layer; a junction field effect region contacting the p-type buried layer at a gate electrode region; a gate anodization layer overlying the silicon carbide epitaxial layer; a polysilicon layer overlying the gate oxide layer; an interlevel dielectric layer overlying the polysilicon layer; a first recess formed in the silicon carbide epitaxy layer through the interlevel dielectric layer, the polysilicon layer and the gate oxide layer in a source pole region; a second recess formed in the polysilicon layer in the gate electrode region, the second recess having a bottom surface higher than the top surface of the gate electrode layer.

2. 2. The semiconductor device of claim 1 , wherein the silicon carbide epitaxial layer further comprises: a p-type well region overlying the p-type buried layer; a heavily doped n-type region overlying a surface of the p-type well region; a first heavily doped p-type region beneath the heavily doped n-type region and within the p-type well region; The semiconductor device wherein the depth of the first recess is greater than the depth of the heavily doped n-type region.

3. 2. The semiconductor device according to claim 1, further comprising: a contact spacer overlying the gate oxide layer and contacting the interlevel dielectric layer and the polysilicon layer; and an island oxide layer overlying said junction field effect region, said island oxide layer having a thickness greater than a thickness of said gate electrode oxide layer.

4. The semiconductor device according to claim 2, further comprising: A semiconductor device having a first metal layer in the first recess and in contact with the first heavily doped p-type region and the heavily doped n-type region through a silicide.

5. 5. The semiconductor device of claim 4, wherein said first metal layer is further disposed over and in contact with said interlevel dielectric layer and said contact spacer.

6. 5. The semiconductor device of claim 4, wherein said interlevel dielectric layer is disposed in said second recess, and wherein in the second recess, said first metal layer does not contact said polysilicon layer.

7. 2. The semiconductor device according to claim 1, further comprising: a silicon carbide substrate underlying the silicon carbide epitaxy layer; a second metal layer underlying the silicon carbide substrate.

8. 1. A method for manufacturing a semiconductor device, comprising: depositing a first oxide film, a first polysilicon film, and a second oxide film in this order on the silicon carbide epitaxy layer; After a pattern of a p-type buried layer is defined, etching the second oxide film and the first polysilicon film, stopping the etching at the first oxide film, and implanting a p-type buried layer into the silicon carbide epitaxy layer; depositing a second polysilicon film, etching back the second polysilicon film, and implanting a p-type well region above the p-type buried layer; depositing a third oxide film and a third polysilicon film, in that order; etching back the third polysilicon film; and implanting a heavily doped n-type region at a surface of the p-type well region; depositing a fourth oxide film and a fourth polysilicon film, in that order, etching back the fourth polysilicon film, and implanting a first heavily doped p-type region beneath the heavily doped n-type region and into the p-type well region; A method for manufacturing a semiconductor device, comprising removing the first oxide film, the first polysilicon film, the second oxide film, the second polysilicon film, the third oxide film, the third polysilicon film, the fourth oxide film, and the fourth polysilicon film.

9. 9. The method for manufacturing a semiconductor device according to claim 8, further comprising: forming a junction field effect region; forming a second heavily doped p-type region outside the unit cell region; forming a field oxide layer over a portion of the second heavily doped p-type region; forming an island-shaped oxide layer on the junction field effect region; depositing a gate oxide layer and a polysilicon layer; Etching the polysilicon layer in a gate electrode region to expose the oxide island; A method for manufacturing a semiconductor device includes depositing an interlevel dielectric layer.

10. 10. The method for manufacturing a semiconductor device according to claim 9, further comprising: Etching the interlevel dielectric layer and the polysilicon layer and stopping the etch at the gate anodization layer; depositing a contact spacer over the interlevel dielectric layer and the gate oxide layer; etching back the contact spacers and the gate anodization layer to expose the interlevel dielectric layer and the heavily doped n-type region; 1. A method for manufacturing a semiconductor device comprising forming a first recess in a source pole region by a blanket etching process to expose a second heavily doped p-type region, the depth of the first recess being greater than the depth of the heavily doped n-type region.

11. The method for manufacturing a semiconductor device according to claim 10, further comprising: A method for manufacturing a semiconductor device comprising depositing a first metal layer into said gate pole region and said source pole region.

12. 11. The method of claim 10, wherein during a blanket etch process, the silicon carbide epitaxy layer has a high etch selectivity relative to the field oxide layer, the interlevel dielectric layer, and the contact spacers.

13. 9. The method for manufacturing a semiconductor device according to claim 8, further comprising: A method for manufacturing a semiconductor device comprising forming a second metal layer beneath the silicon carbide substrate below the silicon carbide epitaxy layer.

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