Power semiconductor device and power conversion device including the same

Abstract

To provide a power semiconductor device, a power semiconductor module, a power conversion device and a manufacturing method.SOLUTION: A power semiconductor device 101 may include a substrate 110, a first epi layer 111 of first conductivity type disposed on the substrate, a second epi layer 112 of first conductivity type disposed on the first epi layer of first conductivity type, a first well 121 of second conductivity type disposed on the second epi layer of first conductivity type, a first conductivity type source area 141 disposed on the first well of second conductivity type, a gate insulating layer 131 disposed on a bottom and sidewalls of a trench area from which the first conductivity type source area, the first well of second conductivity type, and the second epi layer of first conductivity type are partially removed, a trench gate 132 disposed in the trench on the gate insulating layer, a second well 124 of second conductivity type disposed on the second epi layer of first conductivity type and spaced apart from the gate insulating layer, and an ion implantation connection region 126 of second conductivity type connecting the first well of second conductivity type and the second well of second conductivity type.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The embodiments relate to a power semiconductor element, a power semiconductor module, a power conversion device, and a manufacturing method thereof. [Background technology]

[0002] Power semiconductors are one of the key elements that determine the efficiency, speed, durability and reliability of power electronic systems.

[0003] Recently, with the development of the power electronics industry, the silicon ((Silicon)Si) power semiconductors that have been used until now have reached their physical limits, and research into WBG (Wide Bandgap) power semiconductors such as silicon carbide ((Silicon Carbide)SiC) and gallium nitride ((Galium Nitride)GaN) as replacements is being actively conducted.

[0004] WBG power semiconductor elements have a band gap energy approximately three times that of Si power semiconductor elements, which gives them the following characteristics: low intrinsic carrier concentration, high dielectric breakdown field (approximately 4 to 20 times), high thermal conductivity (approximately 3 to 13 times), and large electron saturation velocity (approximately 2 to 2.5 times).

[0005] These characteristics allow them to operate in high-temperature, high-voltage environments, and they have high switching speeds and low switching losses. Among these, gallium nitride (GaN) power semiconductor elements can be used in low-voltage systems, while silicon carbide (SiC) power semiconductor elements are suitable for high-voltage systems.

[0006] Conventional SiC MOSFET power semiconductors are generally referred to as VDMOSFETs, which stand for vertical diffused structure, or simply as double-diffused structure DMOSFETs. SiC MOSFETs can also be classified into planar MOSFETs and trench MOSFETs according to the channel direction.

[0007] Among these, the trench type MOSFET has a structure in which a channel is formed on the side wall of a trench. For this reason, a gate insulating film is formed on the side wall of the trench, and a gate electrode is formed in the trench.

[0008] SiC MOSFETs have a high on-resistance (R on ) and the trench MOSFET was proposed to reduce this. The trench MOSFET has the advantage of increasing the channel density by forming a channel on the trench sidewall.

[0009] However, trench MOSFETs have a larger electric field in the trench gate oxide, which has a shorter drift distance than the P-base (P-well), and the electric field is concentrated especially at the edge of the trench, which causes the gate oxide to break down earlier, resulting in a reduced breakdown voltage (BV).

[0010] For example, in the case of SiC trench MOSFETs, the breakdown electric field strength is 10 times that of silicon (Si), so SiC semiconductor devices are used under conditions where a voltage nearly 10 times that of Si devices is applied. As a result, the gate insulating film formed in the trench is also subjected to an electric field 10 times stronger than that of silicon devices, which creates the problem that the gate insulating film can easily break down at the corners of the trench.

[0011] In terms of internal technology, research was conducted into placing a bottom P-well under the trench in order to prevent electric field concentration at the trench corners of SiC trench MOSFETs.

[0012] However, even though the bottom P-well prevents the electric field concentration at the trench corners, it contributes to preventing the breakdown voltage drop, and the on-resistance (R on ) are faced with a situation of increasing technical contradictions. Summary of the Invention [Problem to be solved by the invention]

[0013] One of the technical challenges in the embodiment is to prevent the breakdown voltage drop and on-resistance (R on ) to resolve the technical contradiction of increasing

[0014] For example, in one embodiment, a bottom P-well prevents electric field concentration at the trench corners while preventing an increase in on-resistance.

[0015] The technical problems of the embodiments are not limited to those described in this section, but include those that can be understood from the description of the invention. [Means for solving the problem]

[0016] The power semiconductor device according to the embodiment includes a substrate 110, a first epitaxial layer 111 of a first conductivity type disposed on the substrate 110, a second epitaxial layer 112 of a first conductivity type disposed on the first epitaxial layer 111 of the first conductivity type, a first well 121 of a second conductivity type disposed on the second epitaxial layer 112 of the first conductivity type, a first conductive type source region 141 disposed on the first well 121 of the second conductivity type, and a first conductive type source region 141, the first well 121 of the second conductivity type, and the first well 112 of the second conductivity type. The semiconductor device may include a gate insulating layer 131 disposed on a bottom surface and sidewalls of a trench region in which a portion of a second epitaxial layer 112 of a conductive type has been removed, a trench gate 132 disposed in the trench on the gate insulating layer 131, a second well 124 of a second conductive type disposed in the second epitaxial layer 112 of the first conductive type, spaced apart from the gate insulating layer 131, and an ion-implanted connection region 126 of a second conductive type connecting the first well 121 of the second conductive type and the second well 124 of the second conductive type.

[0017] When the ground potential is applied to the first well 121 of the second conductivity type, the ground potential is also applied to the second well 124 of the second conductivity type by the ion implantation connection region 126 of the second conductivity type.

[0018] The second well 124 of the second conductivity type is disposed below the trench and is disposed in a continuous form along the trench region.

[0019] The second conductive type second well 124 is disposed to extend in a first direction Y parallel to the first direction Y, which is the extension direction of the trench gate 132 .

[0020] The second conductive type ion implantation connection region 126 is disposed to extend in a second direction X perpendicular to the first direction Y, which is the extension direction of the trench gate 132 .

[0021] The second conductive type ion implantation connection region 126 connects the second conductive type second wells 124 arranged horizontally in the first direction Y while being spaced apart in the second direction X, and is arranged to extend in the second direction X perpendicular to the first direction Y.

[0022] An upper end of the second conductive type ion implantation connection region 126 is disposed higher than a lower end of the gate insulating layer 131 , and a lower end of the second conductive type ion implantation connection region 126 is disposed lower than a lower end of the gate insulating layer 131 .

[0023] The second conductive type ion-implanted connection region 126 may continuously connect the second conductive type second wells 124 of three or more adjacent cells.

[0024] The second conductive type ion implantation connection region may cross one cell to connect the second conductive type second wells.

[0025] The second conductive type ion implantation connection region may include a first conductive type ion implantation connection region 126a connecting a second conductive type second well 124 arranged under the trench region of the first cell region and a second conductive type second well 124 arranged under the trench region of a third cell region adjacent to the first cell region in the X-axis direction.

[0026] The first ion implantation connection region 126a of the second conductivity type may connect the second well 124 of the second conductivity type in the first cell region and the second well 124 of the second conductivity type in the third cell region to the first well 121 of the second conductivity type above.

[0027] The second conductive type ion implantation connection region may include a second conductive type second ion implantation connection region 126b connecting the second conductive type second well 124 arranged under the trench region of the second cell region and the second conductive type second well 124 arranged under the trench region of a fourth cell region adjacent to the second cell region in the negative (-) direction of the X-axis.

[0028] The second ion implantation connection region 126b of the second conductivity type may connect the second well 124 of the second conductivity type in the second cell region and the second well 124 of the second conductivity type in the fourth cell region to the first well 121 of the second conductivity type above.

[0029] The second well 124 of the second conductivity type may include a 2-1 well 124a of the second conductivity type and a 2-2 well 124b of the second conductivity type disposed at both corners of the trench.

[0030] The second well 124 of the second conductivity type may include a 2-1 well 124a of the second conductivity type and a 2-2 well 124b of the second conductivity type disposed below both corners of the trench in an extension direction of the trench gate 132.

[0031] The second conductive type ion implantation connection region may cross one cell to connect the second conductive type second wells.

[0032] The second conductive type ion implantation connection region may include a first conductive type ion implantation connection region 126a connecting a second conductive type 2-1 well 124a disposed under the trench region of the first cell region and a second conductive type 2-2 well 124b disposed under the trench region of a third cell region adjacent to the first cell region in the X-axis direction.

[0033] The first ion implantation connection region 126a of the second conductivity type may connect the 2-1 well 124a of the second conductivity type in the first cell region and the 2-2 well 124b of the second conductivity type in the third cell region to the first well 121 of the second conductivity type above.

[0034] The second conductive type ion implantation connection region may include a second conductive type second ion implantation connection region 126b connecting a second conductive type 2-2 well 124b arranged under the trench region of the second cell region and a second conductive type 2-1 well 124a arranged under the trench region of a fourth cell region adjacent to the second cell region in the negative (-) direction of the X-axis.

[0035] The second ion implantation connection region 126b of the second conductivity type may connect the 2-2 well 124b of the second conductivity type in the second cell region and the 2-1 well 124a of the second conductivity type in the fourth cell region to the first well 121 of the second conductivity type above.

[0036] Also, a power conversion device according to the embodiment may include any one of the power semiconductor devices. Effect of the Invention

[0037] According to the power semiconductor device and the power conversion device including the same and the method for manufacturing the power semiconductor device according to the embodiment, the on-resistance (R on The present invention has a technical effect of solving the problem of increasing the number of semiconductor devices that can be used at the same time or the problem of adversely affecting the electrical characteristics of the power semiconductor device.

[0038] For example, according to the embodiment, the second well 124 of the second conductivity type is disposed below the trench and is disposed in a continuous form along the trench region, thereby dispersing the electric field concentrated at the trench corners, thereby preventing a breakdown voltage drop in the gate insulating layer and improving the reliability of the gate insulating layer.

[0039] Also, according to the embodiment, the second conductive type ion implantation connection region 126 can connect the second conductive type second well 124 and the second conductive type first well 121. As a result, the second conductive type first well 121 to which the ground potential is applied is connected to the second conductive type second well 124 by the second conductive type ion implantation connection region 126, so that the second conductive type second well 124 is also applied with the ground potential.

[0040] In addition, according to the embodiment, since the second well 124 of the second conductivity type is not in direct contact with the bottom surface of the gate trench, there is an advantage in that there is less risk of an unexpectedly grown oxide being formed in the gate insulating film in terms of thickness and characteristics when a thermal oxidation process is performed to form the gate insulating film.

[0041] In addition, according to the embodiment, a ground potential is applied to the second well 124 of the second conductivity type, which prevents electric field concentration at the trench corners, and thus it is possible to prevent the occurrence of a depletion region in the second well 124 of the second conductivity type, and the on-resistance (R on This has the combined technical effect of preventing an increase in

[0042] In addition, according to the second embodiment, the first ion-implanted connection region 126a of the second conductivity type or the second ion-implanted connection region 126b of the second conductivity type is disposed in only a portion of one side or the other side of the gate insulating layer 131 of each cell to connect the second well 124 of the second conductivity type to the second well 124 of the second conductivity type, thereby providing a composite technical effect of improving current flow.

[0043] In addition, according to the third embodiment, a second conductive type 2-1 well 124a and a second conductive type 2-2 well 124b are disposed separately on the lower sides of both corners of the trench, thereby providing a composite technical effect of improving current flow.

[0044] In addition, according to the fourth embodiment, the first ion-implanted connection region 126a of the second conductivity type or the second ion-implanted connection region 126b of the second conductivity type is disposed in only a portion of one side or the other side of the gate insulating layer 131 of each cell, thereby providing a composite technical effect of improving current flow.

[0045] In addition, according to the fourth embodiment, a second conductive type 2-1 well 124a and a second conductive type 2-2 well 124b are disposed separately on the lower sides of both corners of the trench, thereby providing a composite technical effect of improving current flow.

[0046] The technical effects of the embodiments are not limited to those described in this section, but include those that can be understood from the description of the invention. [Brief description of the drawings]

[0047] [Figure 1] FIG. 1 is a diagram illustrating a configuration example of a power conversion device 1000 according to an embodiment. [Diagram 2] FIG. 2 is a cross-sectional view of a power semiconductor device 100 according to an embodiment. [Diagram 3] FIG. 3 is a three-dimensional cross-sectional view of the power semiconductor element 101 according to the first embodiment. [Figure 4a] FIG. 4a is a cross-sectional view taken along line AA' of the power semiconductor device 101 shown in FIG. [Figure 4b] FIG. 4b is a cross-sectional view taken along line BB' of the power semiconductor element 101 shown in FIG. [Diagram 5] FIG. 5 is a three-dimensional cross-sectional view of a power semiconductor element 102 according to the second embodiment. [Figure 6a] FIG. 6a is a cross-sectional view taken along line AA' of the power semiconductor element 102 shown in FIG. [Figure 6b] FIG. 6b is a cross-sectional view taken along line BB' of the power semiconductor element 102 shown in FIG. [Figure 6c] FIG. 6c is a cross-sectional view taken along line CC' of the power semiconductor element 102 shown in FIG. [Figure 7]FIG. 7 is a three-dimensional cross-sectional view of a power semiconductor element 103 according to the third embodiment. [Figure 8a] FIG. 8a is a cross-sectional view taken along line AA' of the power semiconductor element 103 shown in FIG. [Figure 8b] FIG. 8b is a cross-sectional view taken along line BB' of the power semiconductor element 103 shown in FIG. [Figure 9a] FIG. 9a is a cross-sectional view of a power semiconductor element 104 according to the fourth embodiment. [Figure 9b] FIG. 9b is a cross-sectional view of a power semiconductor element 104 according to the fourth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0048] Hereinafter, the invention according to the embodiment for solving the above problems will be described in more detail with reference to the drawings.

[0049] The suffixes "module" and "section" for components used in the following description are merely given to facilitate the writing of the specification and do not impart any particular significance or role to the components themselves. Therefore, the terms "module" and "section" can be used interchangeably.

[0050] Although terms including ordinal numbers such as first, second, etc. may be used to describe various components, the components are not limited by the terms. The terms are used only to distinguish one component from another component.

[0051] A singular expression includes a plural expression unless the context clearly indicates otherwise.

[0052] In this application, the terms "including," "having," or "comprising" are intended to specify the presence of any feature, number, step, operation, component, part, or combination thereof set forth in the specification, but are not to be understood as precluding the presence or additional possibility of one or more other features, number, steps, operations, components, parts, or combinations thereof.

[0053] (Example) FIG. 1 is a diagram illustrating a configuration example of a power conversion device 1000 according to an embodiment.

[0054] The power conversion device 1000 according to the embodiment can receive DC power from a battery or a fuel cell, convert it into AC power, and supply the AC power to a predetermined load. For example, the power conversion device 1000 according to the embodiment can include an inverter, receive DC power from a battery, convert it into three-phase AC power, and supply it to a motor M, and the motor M can provide power to an electric vehicle, a fuel cell vehicle, etc.

[0055] The power conversion device 1000 according to the embodiment may include a power semiconductor device 100. The power semiconductor device 100 may be, but is not limited to, a Metal Oxide Semiconductor Field Effect Transistor (MOSFET), and may include an Insulated Gate Bipolar Transistor (IGBT).

[0056] For example, the power conversion device 1000 may include a plurality of power semiconductor devices 100a, 100b, 100c, 100d, 100e, and 100f, and may include a plurality of diodes (not shown). Each of the plurality of diodes may be included in the power semiconductor devices 100a, 100b, 100c, 100d, 100e, and 100f in the form of an internal diode, but is not limited thereto, and may be disposed separately.

[0057] The embodiment can convert DC power into AC power by controlling the on / off of the multiple power semiconductor elements 100a to 100f. For example, the power conversion device 1000 according to the embodiment can supply positive polarity power to the motor M by turning on the first power semiconductor element 100a and turning off the second power semiconductor element 100b in a first time interval of one cycle, and supply negative polarity power to the motor M by turning off the first power semiconductor element 100a and turning on the second power semiconductor element 100b in a second time interval of one cycle.

[0058] In the embodiment, a group of power semiconductor elements arranged in series on the high-voltage line and the low-voltage line on the input side can be called an arm. For example, the first power semiconductor element 100a and the second power semiconductor element 100b can form a first arm, the third power semiconductor element 100c and the fourth power semiconductor element 100d can form a second arm, and the fifth power semiconductor element 100e and the sixth power semiconductor element 100f can form a third arm.

[0059] The upper and lower power semiconductor elements in each arm are controlled not to be turned on at the same time. For example, the first and second power semiconductor elements 100a and 100b in the first arm are not turned on at the same time but can be turned on and off alternately.

[0060] A high voltage is applied to each of the power semiconductor elements 100a-100f when the elements are turned off. For example, when the first power semiconductor element 100a is turned on and the second power semiconductor element 100b is turned off, the input voltage is applied to the second power semiconductor element 100b as is. The voltage input to the second power semiconductor element 100b is a relatively high voltage, and the withstand voltage of each of the power semiconductor elements 100a-100f is designed to be at a high level so that the elements can withstand such a high voltage.

[0061] Each of the power semiconductor elements 100a to 100f can conduct a high current when it is turned on. The motor M is driven by a relatively high current, and this high current is supplied to the motor M through the power semiconductors that are turned on.

[0062] A high voltage applied to each of the power semiconductor elements 100a-100f may induce high switching loss. A high current passing through the power semiconductor elements 100a-100f may induce high conduction loss. In order to dissipate heat generated by such losses, the power semiconductor elements 100a-100f may be packaged in a power semiconductor module including a heat dissipation means.

[0063] The power semiconductor device 100 of the embodiment may be a silicon carbide (SiC) power semiconductor device, which is capable of operating in a high temperature and high voltage environment and has a high switching speed and low switching loss.

[0064] Meanwhile, the power conversion device 1000 according to the embodiment may include a plurality of power semiconductor modules.

[0065] For example, the multiple power semiconductor elements 100a to 100f shown in FIG. 1 may be packaged in one power semiconductor module, or the power semiconductor elements constituting each arm may be packaged in one power semiconductor module.

[0066] For example, the first power semiconductor device 100a, the second power semiconductor device 100b, the third power semiconductor device 100c, the fourth power semiconductor device 100d, the fifth power semiconductor device 100e, and the sixth power semiconductor device 100f shown in FIG. 1 may be packaged into one power semiconductor module.

[0067] In order to increase the current capacity, additional power semiconductor elements may be arranged in parallel with each of the power semiconductor elements 100a to 100f. In this case, the number of power semiconductor elements included in the power semiconductor module may be more than six.

[0068] The power converter 1000 according to the embodiment may include a diode-type power semiconductor element in addition to the transistor-type power semiconductor elements 100a to 100f. For example, a first diode (not shown) may be arranged in parallel with the first power semiconductor element 100a, and a second diode (not shown) may be arranged in parallel with the second power semiconductor element 100b. Such diodes may also be packaged together in one power semiconductor module. The diodes may also be arranged in the form of internal diodes in each power semiconductor element.

[0069] Next, the power semiconductor elements constituting each arm may be packaged into one power semiconductor module.

[0070] For example, the first power semiconductor element 100a and the second power semiconductor element 100b constituting the first arm may be packaged in a first power semiconductor module, the third power semiconductor element 100c and the fourth power semiconductor element 100d constituting the second arm may be packaged in a second power semiconductor module, and the fifth power semiconductor element 100e and the sixth power semiconductor element 100f constituting the third arm may be packaged in a third power semiconductor module.

[0071] In addition, there may be additional power semiconductor elements arranged in parallel with each of the power semiconductor elements 100a-100f to increase the current capacity, and in this case, the number of power semiconductor elements included in each power semiconductor module may be more than two. Each arm may also include a diode-type power semiconductor element (not shown) in addition to the transistor-type power semiconductor elements 100a-100f, and such a diode may also be packaged together in one power semiconductor module. The diode may also be arranged in the form of an internal diode in each power semiconductor element.

[0072] Next, FIG. 2 is a cross-sectional view of one of the power semiconductor elements 100 according to the embodiment.

[0073] The power semiconductor device 100 according to the embodiment may include a source electrode 140, a gate electrode 130, and a drain electrode 160 disposed on a lower side of the semiconductor epitaxial layer 110E, the source electrode 140 and the gate electrode 130 being spaced apart from each other on an upper side of the semiconductor epitaxial layer 110E.

[0074] In the MOSFET configuration, the source electrode 140 or the gate electrode 130 may include an Al-based metal, and may include a Ni layer, a Ti layer, a Ni / Ti layer, or a TiN / Ti silicide layer.

[0075] The drain electrode 160 may include a Ni-based metal, such as a Ti layer, a Ni layer, or an Ag layer. For example, the drain electrode 160 may include, but is not limited to, Ti / Ag, Ti / Ni / Ag, NiV / Ag, V(vanadium) / Ni / Ag, etc.

[0076] One of the technical challenges in the embodiment is to prevent the breakdown voltage drop and on-resistance (R on ) to resolve the technical contradiction of increasing

[0077] Hereinafter, technical features of a power semiconductor element according to an embodiment for solving the above technical problem will be described.

[0078] FIG. 3 is a three-dimensional cross-sectional view of the power semiconductor device 101 according to the first embodiment.

[0079] 4a and 4b are cross-sectional views taken along lines AA' and BB', respectively, of the power semiconductor device 101 shown in Fig. 3. Hereinafter, the "first embodiment" may be abbreviated to "embodiment".

[0080] 3, 4a and 4b, the power semiconductor element 101 of the first embodiment may include one or more of a drain electrode 160 (see FIG. 4a), a substrate 110, an epitaxial layer 110E, a first well 121 of a second conductivity type, a first conductivity type source region 141, a source contact region 142 (see FIG. 4a), a second conductivity type contact region 123 (see FIG. 4b), a source electrode 140 (see FIG. 4a), a gate insulating layer 131, a trench gate 132 and an interlayer insulating layer 150 (see FIG. 4a).

[0081] The epitaxial layer 110E may include a first epitaxial layer 111 of a first conductive type and a second epitaxial layer 112 of the first conductive type.

[0082] Additionally, the embodiment may include a first well 121 of a second conductivity type, a second well 124 of the second conductivity type, and an ion-implanted connection region 126 of the second conductivity type.

[0083] The first conductivity type may be N-type, and the second conductivity type may be P-type, but is not limited thereto. For example, the N-type dopant may be N, P, or the like, but is not limited thereto. Also, the P-type dopant may be Al, boron, or the like, but is not limited thereto.

[0084] Specifically, referring to Figures 4a and 4b, the power semiconductor device 101 of the embodiment may include a substrate 110, a first epilayer 111 of a first conductivity type disposed on the substrate 110, and a second epilayer 112 of a first conductivity type disposed on the first epilayer 111 of the first conductivity type.

[0085] The substrate 110, the first conductive type first epitaxial layer 111, and the first conductive type second epitaxial layer 112 may include, but are not limited to, SiC (Silicon Carbide) and may be doped with N-type. For example, the substrate 110 and the first conductive type first and second epitaxial layers 111 and 112 may include, but are not limited to, a 4H-SiC material. For example, the substrate 110 and the first conductive type first and second epitaxial layers 111 and 112 may include 3C-SiC or 6H-SiC.

[0086] The first conductive type first epitaxial layer 111 may include a first conductive type buffer layer (not shown) and a first conductive type drift layer (not shown). The first conductive type first epitaxial layer 111 may be doped at a lower concentration than the substrate 110 to prevent a breakdown voltage (VB) drop.

[0087] In addition, the first conductivity type second epitaxial layer 112 is doped at a higher concentration than the first conductivity type first epitaxial layer 111, thereby functioning as a current spreading layer (CSL), thereby reducing the on-resistance.

[0088] The second conductive type first well 121 may be formed by ion implantation of a second conductive type dopant or by growing a second conductive type epitaxial layer in the first conductive type second epitaxial layer 112. The second conductive type first well 121 may be referred to as a second conductive type base layer, but is not limited thereto.

[0089] Referring to FIG. 4b, the first conductive type source region 141 and the second conductive type contact region 123 may be formed in the second conductive type first well 121 by ion implantation.

[0090] The doping concentrations of the first conductive type source region 141 and the second conductive type contact region 123 may be higher than that of the second conductive type first well 121. The second conductive type contact region 123 may be partially formed as shown in FIG 3. The second conductive type contact region 123 may function to maintain the zero potential of the second conductive type first well 121.

[0091] Next, a gate insulating layer 131 may be formed by a thermal oxidation or deposition process on the bottom and sidewalls of the trench region from which the first conductive type source region 141, the second conductive type first well 121, and a portion of the first conductive type second epitaxial layer 112 have been removed.

[0092] Next, a trench gate 132 may be formed in the trench on the gate insulating layer 131 by a polysilicon deposition process and an etch-back process.

[0093] Next, the source contact region 142 may be formed with the first conductive type source region 141 and / or the second conductive type contact region 123. For example, the source contact region 142 may be formed using Ti or Ni, but is not limited thereto.

[0094] Next, an interlayer insulating layer 150 can be formed on the trench gate 132 by a deposition process of an oxide film or the like.

[0095] Next, the source electrode 140, the gate electrode (not shown), and the drain electrode 160 are formed.

[0096] For example, the source electrode 140 or the gate electrode 130 may include an Al-based metal, and may include a Ni layer, a Ti layer, a Ni / Ti layer, or a TiN / Ti silicide layer. The drain electrode 160 may include a Ni-based metal, and may include a Ti layer, a Ni layer, or an Ag layer. For example, the drain electrode 160 may include, but is not limited to, Ti / Ag, Ti / Ni / Ag, NiV / Ag, V(vanadium) / Ni / Ag, etc.

[0097] Next, referring to FIG. 4b, the embodiment may include a second well 124 of a second conductivity type disposed in the second epitaxial layer 112 of the first conductivity type, spaced apart from the gate insulating layer 131, and an ion-implanted connection region 126 of a second conductivity type connecting the first well 121 of the second conductivity type and the second well 124 of the second conductivity type.

[0098] The second well 124 of the second conductivity type may be disposed below the trench and may be doped at a concentration equal to or lower than the second well 124 of the second conductivity type, but is not limited thereto.

[0099] The second conductive type ion implantation connection region 126 may be doped at a concentration equal to or lower than that of the second conductive type second well 124, but is not limited thereto.

[0100] Referring to FIG. 3, the second well 124 of the second conductivity type is disposed below the trench and is disposed in a continuous form along the trench region.

[0101] The second well 124 of the second conductivity type may be formed by high energy ion implantation or by using a re-growth process. For example, the second epitaxial layer 112 of the first conductivity type may be grown on the first epitaxial layer 111 of the first conductivity type, and then the second well 124 of the second conductivity type may be formed by high energy ion implantation. Alternatively, after the first epitaxial layer 111 of the first conductivity type is formed, the second well 124 of the second conductivity type may be formed by ion implantation, and then the second epitaxial layer 112 of the first conductivity type may be formed.

[0102] The second conductive type second well 124 is disposed to extend in a first direction Y parallel to the first direction Y, which is the extension direction of the trench gate 132 .

[0103] On the other hand, the second conductive type ion implantation connection region 126 is disposed to extend in a second direction X perpendicular to the first direction Y, which is the extension direction of the trench gate 132 .

[0104] The second conductive type ion implantation connection region 126 connects the second conductive type second wells 124 arranged horizontally in the first direction Y while being spaced apart in the second direction X, and is extended in the second direction X perpendicular to the first direction Y.

[0105] An upper end of the second conductive type ion implantation connection region 126 is disposed higher than a lower end of the gate insulating layer 131 , and a lower end of the second conductive type ion implantation connection region 126 is disposed lower than a lower end of the gate insulating layer 131 .

[0106] According to the power semiconductor device and the power conversion device including the same and the method for manufacturing the power semiconductor device according to the embodiment, the on-resistance (R on The present invention has a technical effect of solving the problem of increasing the number of semiconductor devices that can be used at the same time or the problem of adversely affecting the electrical characteristics of the power semiconductor device.

[0107] For example, according to the embodiment, the second well 124 of the second conductivity type is disposed below the trench and is disposed in a continuous form along the trench region, thereby dispersing the electric field concentrated at the trench corners, thereby preventing a breakdown voltage drop in the gate insulating layer and improving the reliability of the gate insulating layer.

[0108] Also, according to the embodiment, the second conductive type ion implantation connection region 126 can connect the second conductive type second well 124 and the second conductive type first well 121. As a result, the second conductive type first well 121 to which the ground potential is applied is connected to the second conductive type second well 124 by the second conductive type ion implantation connection region 126, so that the second conductive type second well 124 is also applied with the ground potential.

[0109] In addition, according to the embodiment, since the second well 124 of the second conductivity type is not in direct contact with the bottom surface of the gate trench, there is an advantage in that there is less risk of an unexpectedly grown oxide being formed in the gate insulating film in terms of thickness and characteristics when a thermal oxidation process is performed to form the gate insulating film.

[0110] Meanwhile, in terms of internal technology, research was conducted on placing a bottom P-well under the trench to prevent electric field concentration at the corners of the trench.

[0111] First, a floating bottom P-well was formed in a floating state separated from the trench gate and the gate insulating layer using the first internal technology.

[0112] This type of “floating lower P-well” has the effect of reducing the electric field concentration at the trench corners and preventing breakdown voltage drop, but research has been done on the problem that charging and discharging occurs continuously and repeatedly inside the floating lower P-well, affecting the potential around the floating lower P-well.

[0113] That is, a problem has been researched in which an unknown internal potential other than the applied external potential is generated in the floating lower P-well, which may adversely affect the electrical characteristics of the power semiconductor device.

[0114] In addition, the floating lower P-well prevents the flow of current in the on-state, reducing the on-resistance (R on / RDS) increases.

[0115] Next, a 'contact bottom P-well' was formed on the bottom of the trench to contact the trench gate insulating layer using the second internal technology.

[0116] By the way, when a "contacting lower P-well" is formed at the bottom of the trench so that it is in contact with the trench gate insulation layer, although there is an effect of alleviating electric field concentration at the trench corners, a problem has been researched in which the forward current characteristics deteriorate due to an increase in the width of the depletion layer in the "contacting lower P-well" that is in contact with the gate insulation layer due to the drain voltage.

[0117] In addition, when the "contact lower P-well" is formed close to the P-base (P-well) so as to contact the trench gate insulating layer, a JFET resistance occurs between the P-base (P-well) and the contact lower P-well, resulting in an on-resistance (R on The problem of increasing

[0118] 3 and 4b, in the embodiment, the second conductive type ion implantation connection region 126 may connect the second conductive type second well 124 and the second conductive type first well 121. As a result, the second conductive type first well 121 to which the ground potential is applied is connected to the second conductive type second well 124 by the second conductive type ion implantation connection region 126, and the second conductive type second well 124 is also applied with the ground potential.

[0119] Therefore, according to the embodiment, by applying a ground potential to the second well 124 of the second conductivity type, which prevents electric field concentration at the trench corners, it is possible to prevent the occurrence of a depletion region in the second well 124 of the second conductivity type, and the on-resistance (R on This has the combined technical effect of preventing an increase in

[0120] Next, FIG. 5 is a three-dimensional cross-sectional view of a power semiconductor device 102 according to a second embodiment.

[0121] 6a to 6c are cross-sectional views taken along lines AA', BB' and CC' of the power semiconductor device 102 shown in FIG. 5, respectively.

[0122] The second embodiment can employ the technical features of the first embodiment described above, and the following description will focus on the features of the second embodiment.

[0123] 5 and 6a to 6c, the power semiconductor element 102 of the second embodiment may include one or more of a drain electrode 160 (see FIG. 6a), a substrate 110, an epitaxial layer 110E, a first well 121 of a second conductivity type, a first conductivity type source region 141, a source contact region 142 (see FIG. 6a), a second conductivity type contact region 123 (see FIG. 6b), a source electrode 140 (see FIG. 6a), a gate insulating layer 131, a trench gate 132, and an interlayer insulating layer 150 (see FIG. 6a).

[0124] The epitaxial layer 110E may include a first epitaxial layer 111 of a first conductive type and a second epitaxial layer 112 of the first conductive type.

[0125] The second embodiment may include a first well 121 of a second conductivity type and a second well 124 of the second conductivity type.

[0126] Unlike the first embodiment, the second embodiment may include a first ion-implanted connection region 126a of a second conductive type and a second ion-implanted connection region 126b of a second conductive type.

[0127] For example, the first embodiment has a structure in which the second conductive type ion-implanted connection region 126 continuously connects the second conductive type second wells 124 of adjacent cells in a stripe structure.

[0128] On the other hand, the second embodiment has a structure in which the first ion-implanted connection region 126a of the second conductivity type or the second ion-implanted connection region 126b of the second conductivity type crosses the cell to connect the second well 124 of the second conductivity type.

[0129] For example, Figures 6b and 6c are cross-sectional views along lines B-B' and CC', respectively, of the power semiconductor element 102 shown in Figure 5, and Figures 6b and 6c are cross-sectional views of the first cell region and the second cell region of the second power semiconductor element 102.

[0130] For example, referring to FIG. 6b, in the first cell region, the first ion implantation connection region 126a of the second conductivity type may be disposed on one side, e.g., the left side, of the gate insulating layer 131 and connect the second well 124 of the second conductivity type to the second well 124 of the second conductivity type.

[0131] Referring to Figures 5 and 6b together, a first ion-implanted connection region 126a of a second conductivity type is disposed between the trench region of the first cell region and the trench region of a third cell region adjacent to the first cell region in the positive (+) direction of the X-axis.

[0132] In this case, the first ion implantation connection region 126a of the second conductivity type can connect the second well 124 of the second conductivity type arranged below the trench region of the first cell region and the second well 124 of the second conductivity type arranged below the trench region of the third cell region adjacent to the first cell region in the X-axis direction.

[0133] In addition, the first ion implantation connection region 126a of the second conductivity type may connect the second well 124 of the second conductivity type in the first cell region and the second well 124 of the second conductivity type in the third cell region to the first well 121 of the second conductivity type above.

[0134] Also, referring to FIG. 6c, in the second cell region, the second ion implantation connection region 126b of the second conductivity type may be disposed on the other side, for example the right side, of the gate insulating layer 131 and connect the second well 124 of the second conductivity type to the second well 124 of the second conductivity type.

[0135] Referring to Figures 5 and 6c together, a second conductive type second ion implantation connection region 126b is disposed between the trench region of the second cell region and the trench region of a fourth cell region adjacent to the second cell region in the negative (-) direction of the X-axis.

[0136] In this case, the second ion implantation connection region 126b of the second conductivity type may connect the second well 124 of the second conductivity type arranged below the trench region of the second cell region and the second well 124 of the second conductivity type arranged below the trench region of the fourth cell region adjacent to the second cell region in the negative (-) direction of the X-axis.

[0137] In addition, the second ion implantation connection region 126b of the second conductivity type may connect the second well 124 of the second conductivity type in the second cell region and the second well 124 of the second conductivity type in the fourth cell region to the first well 121 of the second conductivity type above.

[0138] According to the second embodiment, the second well 124 of the second conductivity type is disposed below the trench and is disposed in a continuous form along the trench region, thereby dispersing the electric field concentrated at the trench corners, thereby preventing a breakdown voltage drop in the gate insulating layer and improving the reliability of the gate insulating layer.

[0139] According to the second embodiment, the first ion implantation connection region 126a of the second conductivity type or the second ion implantation connection region 126b of the second conductivity type can connect the second well 124 of the second conductivity type and the first well 121 of the second conductivity type. As a result, the first well 121 of the second conductivity type to which the ground potential is applied is connected to the second well 124 of the second conductivity type by the first ion implantation connection region 126a of the second conductivity type or the second ion implantation connection region 126b of the second conductivity type, so that the second well 124 of the second conductivity type is also applied with the ground potential.

[0140] As a result, according to the second embodiment, the ground potential is applied to the second well 124 of the second conductivity type, which prevents the electric field concentration at the trench corners, and thus it is possible to prevent the occurrence of a depletion region in the second well 124 of the second conductivity type, and the on-resistance (R on This has the combined technical effect of preventing an increase in

[0141] In addition, according to the second embodiment, the first ion-implanted connection region 126a of the second conductivity type or the second ion-implanted connection region 126b of the second conductivity type is disposed in only a portion of one side or the other side of the gate insulating layer 131 of each cell to connect the second well 124 of the second conductivity type to the second well 124 of the second conductivity type, thereby providing a composite technical effect of improving current flow.

[0142] Next, FIG. 7 is a three-dimensional cross-sectional view of a power semiconductor device 103 according to a third embodiment.

[0143] 8a and 8b are cross-sectional views taken along lines AA' and BB' of the power semiconductor device 103 shown in FIG. 7, respectively.

[0144] The third embodiment can employ the technical features of the first or second embodiment described above, and the following description will focus on the features of the third embodiment.

[0145] 7, 8a and 8b, unlike the first embodiment, the second well 124 of the second conductivity type in the third embodiment may include a 2-1 well 124a of the second conductivity type and a 2-2 well 124b of the second conductivity type disposed at both corners of the trench, respectively.

[0146] For example, the second well 124 of the second conductivity type in the first embodiment is disposed below the trench so as to correspond to the trench width.

[0147] On the other hand, the second well 124 of the third embodiment may include a second conductive type 2-1 well 124a and a second conductive type 2-2 well 124b, which are respectively disposed under both corners of the trench in the extension direction of the trench gate 132.

[0148] According to the third embodiment, the second well 124 of the second conductivity type is disposed below the trench corner, thereby dispersing the electric field concentrated at the trench corner, thereby preventing a breakdown voltage drop in the gate insulating layer and improving the reliability of the gate insulating layer.

[0149] Also, according to the third embodiment, the second conductive type ion implantation connection region 126 can connect the second conductive type second well 124 and the second conductive type first well 121. As a result, the second conductive type first well 121 to which the ground potential is applied is connected to the second conductive type second well 124 by the second conductive type ion implantation connection region 126, so that the second conductive type second well 124 is also applied with the ground potential.

[0150] As a result, according to the third embodiment, the ground potential is applied to the second well 124 of the second conductivity type, which prevents the electric field concentration at the trench corners, and thus it is possible to prevent the occurrence of a depletion region in the second well 124 of the second conductivity type, and the on-resistance (R on This has the combined technical effect of preventing an increase in

[0151] In addition, according to the third embodiment, a second conductive type 2-1 well 124a and a second conductive type 2-2 well 124b are disposed separately on the lower sides of both corners of the trench, thereby providing a composite technical effect of improving current flow.

[0152] Next, FIGS. 9a and 9b are cross-sectional views of a power semiconductor device 104 according to a fourth embodiment.

[0153] The fourth embodiment can employ the technical features of the third embodiment described above, and the following description will focus on the features of the fourth embodiment.

[0154] Unlike the third embodiment, the fourth embodiment may include a first ion-implanted connection region 126a of a second conductivity type and a second ion-implanted connection region 126b of a second conductivity type.

[0155] For example, the third embodiment has a structure in which the second conductive type ion-implanted connection regions 126 are in a striped structure to continuously connect the second conductive type second wells 124 of adjacent cells (see FIG. 7).

[0156] On the other hand, the fourth embodiment has a structure in which the first ion-implanted connection region 126a of the second conductivity type or the second ion-implanted connection region 126b of the second conductivity type crosses the cell to connect the second well 124 of the second conductivity type.

[0157] For example, FIGS. 9a and 9b are cross-sectional views of a first cell region and a second cell region of the fourth power semiconductor device 104. FIG.

[0158] For example, referring to FIG. 9a, in the first cell region, the first ion implantation connection region 126a of the second conductivity type may be disposed on one side, e.g., the left side, of the gate insulating layer 131 and connect the 2-1 well 124a of the second conductivity type and the 2-2 well 124b of the second conductivity type.

[0159] For example, the first ion-implanted connection region 126a of the second conductivity type is disposed between the trench region of the first cell region and the trench region of the third cell region adjacent to the first cell region in the positive (+) direction of the X-axis.

[0160] In this case, the first ion implantation connection region 126a of the second conductivity type can connect the 2-1 well 124a of the second conductivity type arranged below the trench region of the first cell region and the 2-2 well 124b of the second conductivity type arranged below the trench region of the third cell region adjacent to the first cell region in the X-axis direction.

[0161] In addition, the first ion implantation connection region 126a of the second conductivity type may connect the 2-1 well 124a of the second conductivity type in the first cell region and the 2-2 well 124b of the second conductivity type in the third cell region to the first well 121 of the second conductivity type above.

[0162] Also, referring to FIG. 9b, in the second cell region, the second ion implantation connection region 126b of the second conductivity type may be disposed on the other side, for example the right side, of the gate insulating layer 131 and connect the second conductivity type 2-2 well 124b and the second conductivity type 2-1 well 124a.

[0163] For example, the second conductive type second ion implantation connection region 126b is disposed between the trench region of the second cell region and the trench region of the fourth cell region adjacent to the second cell region in the negative (-) direction of the X-axis.

[0164] In this case, the second ion implantation connection region 126b of the second conductivity type may connect the 2-2 well 124b of the second conductivity type arranged below the trench region of the second cell region and the 2-1 well 124a of the second conductivity type arranged below the trench region of the fourth cell region adjacent to the second cell region in the negative (-) direction of the X-axis.

[0165] In addition, the second ion implantation connection region 126b of the second conductivity type may connect the 2-2 well 124b of the second conductivity type in the second cell region and the 2-1 well 124a of the second conductivity type in the fourth cell region to the first well 121 of the second conductivity type above.

[0166] According to the fourth embodiment, the second well 124 of the second conductivity type is disposed under the trench, dispersing the electric field concentrated at the trench corners, thereby preventing a breakdown voltage drop in the gate insulating layer, and improving the reliability of the gate insulating layer.

[0167] In addition, according to the fourth embodiment, the ground potential is applied to the second conductive type 2-1 well 124a and the second conductive type 2-2 well 124b, which prevent the electric field concentration at the trench corners, thereby preventing the occurrence of a depletion region and reducing the on-resistance (R on This has the combined technical effect of preventing an increase in

[0168] In addition, according to the fourth embodiment, the first ion-implanted connection region 126a of the second conductivity type or the second ion-implanted connection region 126b of the second conductivity type is disposed in only a portion of one side or the other side of the gate insulating layer 131 of each cell, thereby providing a composite technical effect of improving current flow.

[0169] In addition, according to the fourth embodiment, a second conductive type 2-1 well 124a and a second conductive type 2-2 well 124b are disposed separately on the lower sides of both corners of the trench, thereby providing a composite technical effect of improving current flow.

[0170] Although the present invention has been described above with reference to an embodiment thereof, it should be readily apparent to a person skilled in the art that the present invention can be modified and changed in various ways without departing from the spirit and scope of the present invention as set forth in the claims below.

Claims

1. A substrate; a first epitaxial layer of a first conductivity type disposed on the substrate; a second epitaxial layer of a first conductivity type disposed on the first epitaxial layer of the first conductivity type; a first well of a second conductivity type disposed on the second epitaxial layer of the first conductivity type; a first conductivity type source region disposed on the first well of the second conductivity type; a gate insulating layer disposed on a bottom surface and a side wall of a trench region in which a portion of the first conductivity type source region, the first conductivity type first well, and the first conductivity type second epitaxial layer are removed; a trench gate disposed in a trench on the gate insulating layer; a second well of a second conductivity type disposed in the second epitaxial layer of the first conductivity type and spaced apart from the gate insulating layer; a second conductive type ion-implanted connection region connecting the first well of the second conductive type and the second well of the second conductive type.

2. 2 . The power semiconductor device of claim 1 , wherein when a ground potential is applied to the first well of the second conductivity type, the second well of the second conductivity type is also applied with the ground potential by the ion-implanted connection region of the second conductivity type.

3. The power semiconductor device of claim 1 , wherein the second well of the second conductivity type is disposed below the trench and is disposed in a continuous form along the trench region.

4. the second well of the second conductivity type is disposed extending in a first direction parallel to the first direction, which is an extension direction of the trench gate; The power semiconductor device of claim 3 , wherein the second conductive type ion implantation connection region is disposed to extend in a second direction perpendicular to the first direction, which is an extension direction of the trench gate.

5. 5. The power semiconductor device of claim 4, wherein the second conductive type ion implantation connection region connects the second conductive type second wells arranged horizontally in the first direction while being spaced apart in the second direction, and is arranged to extend in the second direction perpendicular to the first direction.

6. an upper end of the second conductive type ion implantation connection region is disposed higher than a lower end of the gate insulating layer; The power semiconductor device according to claim 1 , wherein a lower end of the second conductive type ion implantation connection region is disposed lower than a lower end of the gate insulating layer.

7. The power semiconductor device of claim 1 , wherein the second conductive type ion-implanted connection region continuously connects the second conductive type second wells of three or more adjacent cells.

8. the second conductive type ion implantation connection region intersects with one cell as a reference to connect the second conductive type second well; 2. The power semiconductor device of claim 1, wherein the second conductive type ion implantation connection region includes a first ion implantation connection region of a second conductive type connecting a second well of a second conductive type disposed under a trench region of a first cell region and a second well of a second conductive type disposed under a trench region of a third cell region adjacent to the first cell region in an X-axis direction.

9. the second well of the second conductivity type includes a second-1 well of the second conductivity type and a second-2 well of the second conductivity type disposed at both corners of the trench, 2. The power semiconductor device of claim 1, wherein the second well of the second conductivity type includes a 2-1 well of the second conductivity type and a 2-2 well of the second conductivity type, each of which is disposed below both corners of the trench in an extension direction of the trench gate.

10. A power conversion device comprising the power semiconductor element according to any one of claims 1 to 9.

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