Storage device

Abstract

To improve characteristics of a storage device.SOLUTION: A storage device according to an embodiment comprises: a switching element; an electrode that has a first electrode portion; and a resistance change element. The storage device comprises a lamination structure that is laminated in a first direction. The switching element contacts with the electrode in the first direction. A first surface at a side of the switching element of the first electrode portion contacts with a second surface that is wider than the first surface, in the lamination structure.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The embodiment relates to a storage device. [Background technology]

[0002] 2. Description of the Related Art There is known a memory device that stores data using a variable resistance element configured to be able to switch resistance. The variable resistance element is connected in series with a switching element and functions as a memory cell. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2020-043131 A Summary of the Invention [Problem to be solved by the invention]

[0004] Improve the characteristics of the storage device. [Means for solving the problem]

[0005] The memory device of the embodiment includes a switching element, an electrode having a first electrode portion, and a resistance change element, and has a layered structure stacked in a first direction, the switching element and the electrode are in contact in the first direction, and a first surface of the first electrode portion on the switching element side is in contact with a second surface in the layered structure that is wider than the first surface. [Brief description of the drawings]

[0006] [Figure 1] FIG. 1 is a block diagram illustrating a configuration of a storage device according to an embodiment. [Diagram 2] 1 is a circuit diagram for explaining the configuration of a memory cell array of a memory device according to an embodiment. [Diagram 3] FIG. 2 is a plan view illustrating the configuration of a memory cell array of the memory device according to the embodiment. [Figure 4]4 is a cross-sectional view taken along line IV-IV in FIG. 3, showing an example of a cross-sectional structure of the memory cell array of the memory device according to the embodiment. [Diagram 5] 1 is a cross-sectional view illustrating a configuration of a magnetoresistive element of a memory device according to an embodiment. [Figure 6] FIG. 4 is a diagram showing an example of characteristics of a switching element according to the embodiment. [Figure 7] 4 is a flowchart for explaining a manufacturing method of a memory cell array in the memory device according to the embodiment. [Figure 8] 1A to 1C are cross-sectional views illustrating a manufacturing method of a memory cell array in a memory device according to an embodiment. [Figure 9] 1A to 1C are cross-sectional views illustrating a manufacturing method of a memory cell array in a memory device according to an embodiment. [Figure 10] 1A to 1C are cross-sectional views illustrating a manufacturing method of a memory cell array in a memory device according to an embodiment. [Figure 11] 4 is a flowchart for explaining a manufacturing method of a memory cell array in the memory device according to the embodiment. [Figure 12] 1A to 1C are cross-sectional views illustrating a manufacturing method of a memory cell array in a memory device according to an embodiment. [Figure 13] 1A to 1C are cross-sectional views illustrating a manufacturing method of a memory cell array in a memory device according to an embodiment. [Figure 14] 1A to 1C are cross-sectional views illustrating a manufacturing method of a memory cell array in a memory device according to an embodiment. [Figure 15] FIG. 11 is a cross-sectional view showing an example of a cross-sectional structure of a memory cell array of a memory device according to a first modification. [Figure 16] 16 is a cross-sectional view taken along line XVI-XVI in FIG. 11, showing an example of a cross-sectional structure of a memory cell array of a memory device according to a first modification. [Figure 17] 11 is a flowchart illustrating a method for manufacturing a memory cell array in a storage device according to a first modification. [Figure 18] 13 is a cross-sectional view illustrating a manufacturing method of a memory cell array in a memory device according to a first modification. [Figure 19]13 is a top view illustrating a manufacturing method of a memory cell array in a memory device according to a first modification. FIG. [Figure 20] 13 is a cross-sectional view illustrating a manufacturing method of a memory cell array in a memory device according to a first modification. [Figure 21] 13 is a cross-sectional view illustrating a manufacturing method of a memory cell array in a memory device according to a first modification. [Figure 22] 13 is a cross-sectional view illustrating a manufacturing method of a memory cell array in a memory device according to a first modification. [Figure 23] FIG. 11 is a cross-sectional view showing an example of a cross-sectional structure of a memory cell array of a memory device according to a second modification. [Figure 24] FIG. 11 is a cross-sectional view showing an example of a cross-sectional structure of a memory cell array of a memory device according to a third modification. [Diagram 25] FIG. 13 is a cross-sectional view showing an example of a cross-sectional structure of a memory cell array of a memory device according to a fourth modification. [Figure 26] FIG. 13 is a cross-sectional view showing an example of a cross-sectional structure of a memory cell array of a memory device according to a fifth modification. [Figure 27] FIG. 13 is a cross-sectional view showing an example of a cross-sectional structure of a memory cell array in a memory device according to a sixth modification. [Figure 28] FIG. 13 is a cross-sectional view showing an example of a cross-sectional structure of a memory cell array in a memory device according to another example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Hereinafter, the embodiments will be described with reference to the drawings. In the following description, components having the same function and configuration are given a common reference symbol. When multiple components having a common reference symbol are to be distinguished from one another, a subscript is added to the common reference symbol. When no particular distinction is required between multiple components, only the common reference symbol is added to the multiple components, and no subscript is added. Here, the subscript is not limited to a subscript or a superscript, but includes, for example, a lowercase alphabet added to the end of a reference symbol, and an index indicating an array.

[0008] 1. Embodiment A storage device according to an embodiment will be described.

[0009] The storage device according to the embodiment is a storage device that stores data using a resistance change element. More specifically, the storage device according to the embodiment is, for example, a magnetic storage device (MRAM: Magnetoresistive Random Access Memory) using an element having a magnetoresistance effect by a magnetic tunnel junction (MTJ: Magnetic Tunnel Junction) as a resistance change element by a perpendicular magnetization method. In the following description, the resistance change element is also called an MTJ element. In addition, in the following, a case where the storage device is a magnetic storage device including an MTJ element as a resistance change element is shown, but is not limited to this. The storage device may include an element other than the MTJ element as a resistance change element, and the storage device may be, for example, a resistance change memory (ReRAM: Resistive Random Access Memory) and a phase-change memory (PcRAM: Phase-change Random Access Memory), etc.

[0010] 1.1 Configuration The configuration of the storage device according to the embodiment will be described.

[0011] 1.1.1 Storage device configuration Fig. 1 is a block diagram showing the configuration of a memory device according to an embodiment. As shown in Fig. 1, the memory device 1 includes a memory cell array 10, a row selection circuit 11, a column selection circuit 12, a decode circuit 13, a write circuit 14, a read circuit 15, a voltage generation circuit 16, an input / output circuit 17, and a control circuit 18.

[0012] The memory cell array 10 includes a plurality of memory cells MC, each of which is associated with a row and a column. Memory cells MC in the same row are connected to the same word line WL. Memory cells MC in the same column are connected to the same bit line BL.

[0013] The row selection circuit 11 is connected to the memory cell array 10 via the word lines WL. The row selection circuit 11 is supplied with the decoded result (row address) of the address ADD from the decode circuit 13. The row selection circuit 11 sets the word line WL corresponding to the row based on the decoded result of the address ADD to a selected state. Hereinafter, the word line WL set to the selected state is referred to as a selected word line WL. Moreover, the word lines WL other than the selected word line WL are referred to as unselected word lines WL.

[0014] The column selection circuit 12 is connected to the memory cell array 10 via bit lines BL. The column selection circuit 12 is supplied with a decoded result (column address) of the address ADD from the decode circuit 13. The column selection circuit 12 sets a bit line BL corresponding to a column based on the decoded result of the address ADD to a selected state. Hereinafter, the bit line BL set to the selected state is referred to as a selected bit line BL. Also, the bit lines BL other than the selected bit line BL are referred to as unselected bit lines BL.

[0015] The decode circuit 13 decodes an address ADD from the input / output circuit 17. The decode circuit 13 supplies the decoded result of the address ADD to the row selection circuit 11 and the column selection circuit 12. The address ADD includes a column address and a row address to be selected.

[0016] The write circuit 14 writes data to the memory cells MC. The write circuit 14 includes, for example, a write driver (not shown).

[0017] The read circuit 15 reads data from the memory cells MC. The read circuit 15 includes, for example, a sense amplifier (not shown).

[0018] The voltage generating circuit 16 generates voltages for various operations of the memory cell array 10, using a power supply voltage provided from a device external to the storage device 1 (not shown). For example, the voltage generating circuit 16 generates various voltages required for a write operation and outputs them to the write circuit 14. Also, for example, the voltage generating circuit 16 generates various voltages required for a read operation and outputs them to the read circuit 15.

[0019] The input / output circuit 17 is responsible for communication with the outside of the storage device 1. The input / output circuit 17 transfers an address ADD from the outside of the storage device 1 to the decode circuit 13. The input / output circuit 17 transfers a command CMD from the outside of the storage device 1 to the control circuit 18. The input / output circuit 17 transmits and receives various control signals CNT between the outside of the storage device 1 and the control circuit 18. The input / output circuit 17 transfers data DAT from the outside of the storage device 1 to the write circuit 14, and outputs data DAT transferred from the read circuit 15 to the outside of the storage device 1.

[0020] The control circuit 18 controls the operations of the row selection circuit 11, column selection circuit 12, decode circuit 13, write circuit 14, read circuit 15, voltage generation circuit 16, and input / output circuit 17 in the memory device 1 based on the control signal CNT and command CMD.

[0021] 1.1.2 Memory cell array configuration Next, the configuration of the memory cell array of the memory device 1 according to the embodiment will be described with reference to Fig. 2. Fig. 2 is a circuit diagram showing the configuration of the memory cell array of the memory device according to the embodiment. In Fig. 2, the word lines WL are classified and shown by subscripts including the index "<>".

[0022] As shown in FIG. 2, the memory cells MC are arranged in a matrix in the memory cell array 10, and are connected to a plurality of bit lines BL (BL <0> , B.L. <1> , …, BL <n>) and multiple word lines WL (WL <0> , W.L. <1> , …, W.L. <m>) and a pair of M and N (M and N are natural numbers). That is, the memory cell MC<i、j> (0≦i≦M, 0≦j≦N, i and j are natural numbers) are the word lines WL and bit line BL <j>is connected between the

[0023] Memory cell MC<i、j> is a switching element SEL connected in series.<i、j> and magnetoresistance effect element MTJ<i、j> Includes.

[0024] The switching element SEL is a two-terminal switching element. The two-terminal switching element differs from a three-terminal switching element such as a transistor in that it does not include a third terminal. The switching element SEL can be switched between a high resistance state and a low resistance state by a voltage applied between two terminals. The high resistance state is, for example, an off state in which the switching element is electrically non-conductive. The low resistance state is, for example, an on state in which the switching element is electrically conductive. The switching element SEL switches between passing and blocking a current depending on the magnitude of the voltage applied to the corresponding memory cell MC, regardless of the polarity of the voltage applied between the two terminals (regardless of the direction of the current flow). More detailed characteristics of the switching element SEL will be described later.

[0025] The magnetoresistive element MTJ can switch its resistance state between a low resistance state and a high resistance state by a current controlled by the switching element SEL. The magnetoresistive element MTJ functions as a memory element in which data can be written by changing the resistance state, and which retains the written data in a non-volatile manner and can be read.

[0026] Next, the shape of the memory cells MC in the memory cell array 10 and the arrangement of the memory cells MC relative to the bit lines BL and word lines WL will be described with reference to Fig. 3. Fig. 3 shows an example of a plan view for explaining the configuration of the memory cell array of the memory device according to the embodiment. In Fig. 3, three word lines WL <m-1>、WL <m>, and W.L.<m+1> and three bit lines BL <n-1>、BL <n>, and B.L.<n+1> A plurality of memory cells MC are shown provided between the first and second memory cells MC (1≦m≦M-1, 1≦n≦N-1, m and n are natural numbers). For convenience of explanation, an interlayer insulating film is omitted in FIG.

[0027] 3, the memory cell array 10 is provided above a semiconductor substrate 20. In the following description, a plane parallel to the surface of the semiconductor substrate 20 is defined as an XY plane, and a direction perpendicular to the XY plane is defined as a Z direction. In the XY plane, one of a pair of two directions perpendicular to each other is defined as an X direction and a Y direction.

[0028] A plurality of memory cells MC are provided between word lines WL and bit lines BL. In the example of Fig. 3, the word lines WL are provided below the memory cells MC, and the bit lines BL are provided above the memory cells MC, but this is not limiting, and the word lines WL and the bit lines BL may be inverted.

[0029] The word lines WL are aligned along the Y direction. Each of the word lines WL extends along the X direction. The bit lines BL are aligned along the X direction. Each of the bit lines BL extends along the Y direction. The distance between two word lines WL and the distance between two bit lines BL can be set to be substantially equal, for example. One memory cell MC is provided at a portion where one bit line BL and one word line WL intersect.

[0030] Next, the cross-sectional structure of the memory cell array 10 will be described with reference to Fig. 4. Fig. 4 is a cross-sectional view taken along line IV-IV in Fig. 3, showing an example of the cross-sectional structure of the memory cell array of the memory device according to the embodiment.

[0031] The memory cell array 10 is provided above a semiconductor substrate 20 .

[0032] The memory cell array 10 includes a plurality of conductors 21, a plurality of electrodes 22, a plurality of elements 23, a plurality of electrodes 24, a plurality of elements 25, a plurality of electrodes 26, and a plurality of conductors 27. Each of the plurality of electrodes 24 includes electrode portions 24a and 24b.

[0033] For example, a plurality of conductors 21 are provided on the upper surface of the semiconductor substrate 20. Each of the plurality of conductors 21 extends along the X direction. The plurality of conductors 21 are arranged along the Y direction in a region not shown. Each of the plurality of conductors 21 has conductivity and functions as a word line WL. The plurality of conductors 21 are insulated from each other. Note that, although FIG. 4 illustrates a case in which the plurality of conductors 21 are provided on the semiconductor substrate 20, this is not limiting. For example, a layer different from the plurality of conductors 21 and the semiconductor substrate 20 may be provided between them.

[0034] A plurality of electrodes 22 are provided on the upper surface of each of the plurality of conductors 21. The plurality of electrodes 22 provided on the upper surface of the same conductor 21 are aligned in the X direction. Note that, of the plurality of electrodes 22, two electrodes 22 provided on two conductors 21, respectively, are shown in Fig. 4. Each of the plurality of electrodes 22 has, for example, a circular shape along the XY cross section. Each of the plurality of electrodes 22 is used as a lower electrode BE.

[0035] On the upper surface of each of the plurality of electrodes 22, a corresponding one of the plurality of elements 23 is provided. Each of the plurality of elements 23 has, for example, a circular shape along the XY cross section. Each of the plurality of elements 23 is used as a switching element SEL. The plurality of elements 23 includes, for example, a chalcogenide material. More specifically, the element 23 may be, for example, hafnium oxide (HfO), a compound of arsenic, hafnium, and oxygen (AsHfO), tantalum oxide (TaO), titanium oxide (TiO), tungsten oxide (WO), zirconium oxide (ZrO), aluminum oxide (AlO), nickel oxide (NiO), niobium oxide (NbO), a compound of arsenic, silicon, oxygen, and titanium (AsSiOTi), a compound of arsenic, silicon, and oxygen (AsSiO), a compound of arsenic and sulfur (AsS), a compound of zinc and tellurium (ZnTe), a compound of arsenic, zinc, and tellurium (AsZnTe), a compound of silicon, zinc, and tellurium (SiZnTe), a compound of arsenic, silicon, zinc, and tellurium (AsSiZnTe), a compound of germanium selenide, The compound includes at least one material selected from chalcogenides such as silicon, arsenic, selenium, and tellurium (GeSe), a compound of germanium, arsenic, selenium, and tellurium (GeAsSeTe), a compound of germanium and tellurium (GeTe), a compound of carbon and tellurium (CTe), a compound of silicon, arsenic, and tellurium (SiAsTe), a compound of silicon, germanium, arsenic, and tellurium (SiGeAsTe), a compound of germanium, arsenic, and tellurium (GeAsTe), a compound of arsenic and tellurium (AsTe), and a compound of silicon, germanium, arsenic, and selenium (SiGeAsSe), as well as a compound of at least one element selected from carbon (C), nitrogen (N), indium (In), and boron (B) and the chalcogenide. The elements 23 may include at least one material selected from a compound of arsenic and germanium (GeAs) and a compound obtained by combining the compound with at least one element selected from carbon (C), nitrogen (N), indium (In), and boron (B). The elements 23 may have an amorphous structure, for example. The elements 23 may preferably include at least one element selected from Group 5 elements and Group 6 elements.If the elements 23 contain at least one of a group 5 element and a group 6 element, it is possible to increase the density of trap sites and widen the band gap width of the elements 23. This makes it easier to form conductive filaments in the elements 23 by a forming process described later.

[0036] On the upper surface of each of the plurality of elements 23, one of the plurality of electrodes 24 is provided corresponding to the element. Each of the plurality of electrodes 24 is used as an intermediate electrode ME.

[0037] The multiple electrodes 24 will now be described in more detail.

[0038] On the upper surface of each of the plurality of elements 23, one of the plurality of electrode portions 24a is provided corresponding to the plurality of elements 23. Each of the plurality of electrode portions 24a has, for example, a circular shape along the XY cross section. The outer diameter of the lower surface of each of the plurality of electrode portions 24a is smaller than the outer diameter of the upper surface of the element 23 corresponding to the electrode portion 24a. As a result, the area of ​​the lower surface of each of the plurality of electrode portions 24a is smaller than the area of ​​the upper surface of the element 23 corresponding to the electrode portion 24a. The electrode portion 24a contains, for example, carbon (C). The electrode portion 24a has, for example, an amorphous structure.

[0039] On the upper surface of each of the electrode portions 24a, one of the plurality of electrode portions 24b is provided. Each of the plurality of electrode portions 24b has, for example, a circular shape along the XY cross section. The outer diameter of the lower surface of each of the plurality of electrode portions 24b is larger than the outer diameter of the upper surface of the electrode portion 24a corresponding to the electrode portion 24b. As a result, the area of ​​the lower surface of each of the plurality of electrode portions 24b is larger than the area of ​​the upper surface of the electrode portion 24a corresponding to the electrode portion 24b. The electrode portion 24b includes, for example, titanium (Ti), tungsten (W), titanium nitride (TiN), tungsten nitride (WN), titanium nitride having tungsten (TiWN), and the like.

[0040] The outer diameter of each of the multiple electrode portions 24a is smaller than the outer diameter of the upper surface of the element 23 corresponding to the electrode portion 24a and the outer diameter of the lower surface of the electrode portion 24b corresponding to the electrode portion 24a, for example, over the entire length along the Z direction.

[0041] On the upper surface of each of the electrode portions 24b, one of the elements 25 is provided. Each of the elements 25 has, for example, a circular shape along the XY cross section. Each of the elements 25 functions as a magnetoresistance effect element MTJ. The configuration of the element 25 will be described in detail later.

[0042] On the upper surface of each of the plurality of elements 25, one of the plurality of electrodes 26 is provided corresponding to the plurality of elements 25. Each of the plurality of electrodes 26 has, for example, a circular shape along the XY cross section. Each of the plurality of electrodes 26 is used as an upper electrode TE.

[0043] With the above configuration, the multiple structures each including the electrodes 22, 24, and 26 and the elements 23 and 25 are also referred to as multiple stacked structures. Each of the multiple stacked structures corresponds to each of the multiple memory cells MC. With the above configuration, each of the multiple memory cells MC has, for example, a circular shape along the XY cross section.

[0044] A sidewall insulator 40 is provided on each side surface of the multiple laminated structures so as to cover the side surface. The sidewall insulator 40 is provided, for example, to a height equivalent to that of the upper surface of the electrode 26. The sidewall insulator 40 may be made of multiple insulating materials.

[0045] The multiple conductors 27 are aligned along the X direction. Although not shown, each of the multiple conductors 27 extends along the Y direction so as to contact an upper surface of each of the multiple electrodes 26 aligned in the Y direction. Each of the multiple conductors 27 has conductivity and functions as a bit line BL.

[0046] 1.1.3 Magnetoresistance effect element Next, the configuration of the magnetoresistive element MTJ of the memory device 1 according to the embodiment will be described with reference to Fig. 5. Fig. 5 is a cross-sectional view showing the configuration of the magnetoresistive element of the memory device according to the embodiment.

[0047] The element 25 used as the magnetoresistive element MTJ includes a ferromagnetic body 31, a non-magnetic body 32, a ferromagnetic body 33, a non-magnetic body , a ferromagnetic body 35, and a non-magnetic body .

[0048] The ferromagnetic body 31 is a conductive film having ferromagnetism. The ferromagnetic body 31 has an easy axis of magnetization in a direction perpendicular to the film surface (Z direction). The ferromagnetic body 31 includes iron (Fe). The ferromagnetic body 31 may further include at least one element of cobalt (Co) and nickel (Ni). The ferromagnetic body 31 may further include boron (B). More specifically, the ferromagnetic body 31 includes, for example, cobalt iron boron (CoFeB), iron boride (FeB), or cobalt boride (CoB). The ferromagnetic body 31 is used as a memory layer SL.

[0049] A non-magnetic body 32 is provided on the lower surface of the ferromagnetic body 31. The non-magnetic body 32 is an insulating film having a non-magnetic property. The non-magnetic body 32 is used as a tunnel barrier layer TB. The non-magnetic body 32 is provided between the ferromagnetic body 31 and the ferromagnetic body 33, and forms a magnetic tunnel junction together with the ferromagnetic body 31 and the ferromagnetic body 33. The non-magnetic body 32 also functions as a seed material that becomes a nucleus for growing a crystalline film from the interface with the ferromagnetic body 31 in a crystallization process of the ferromagnetic body 31. The non-magnetic body 32 has a NaCl crystal structure with the film surface oriented to the (001) plane. The non-magnetic body 32 contains, for example, magnesium oxide (MgO).

[0050] A ferromagnetic body 33 is provided on the lower surface of the non-magnetic body 32. The ferromagnetic body 33 is a conductive film having ferromagnetism. The ferromagnetic body 33 is used as a reference layer RL. The ferromagnetic body 33 has an easy axis direction perpendicular to the film surface (Z direction). The magnetization direction of the ferromagnetic body 33 is fixed. In the example of FIG. 5, the magnetization direction of the ferromagnetic body 33 is a direction from the ferromagnetic body 33 to the ferromagnetic body 31. Note that "the magnetization direction is fixed" means that the magnetization direction does not change due to a torque of a magnitude that can reverse the magnetization direction of the ferromagnetic body 31. The ferromagnetic body 33 includes at least one compound selected from, for example, cobalt platinum (CoPt), cobalt nickel (CoNi), and cobalt palladium (CoPd).

[0051] A non-magnetic material 34 is provided on the lower surface of the ferromagnetic material 33. The non-magnetic material 34 is a conductive film having non-magnetic properties. The non-magnetic material 34 is used as a spacer layer SP. The non-magnetic material 34 includes at least one element selected from, for example, ruthenium (Ru), osmium (Os), rhodium (Rh), iridium (Ir), vanadium (V), and chromium (Cr).

[0052] A ferromagnetic body 35 is provided on the lower surface of the non-magnetic body 34. The ferromagnetic body 35 is a conductive film having ferromagnetism. The ferromagnetic body 35 is used as a shift cancellation layer SCL. The ferromagnetic body 35 has an easy axis direction perpendicular to the film surface (Z direction). The magnetization direction of the ferromagnetic body 35 is fixed. In the example of FIG. 5, the magnetization direction of the ferromagnetic body 35 is a direction from the ferromagnetic body 33 to the ferromagnetic body 35. The ferromagnetic body 35 includes at least one compound selected from, for example, cobalt platinum (CoPt), cobalt nickel (CoNi), and cobalt palladium (CoPd).

[0053] The ferromagnetic body 33 and the ferromagnetic body 35 are antiferromagnetically coupled by the nonmagnetic body 34. That is, the ferromagnetic body 33 and the ferromagnetic body 35 are coupled so that their magnetization directions are antiparallel to each other. Such a coupled structure of the ferromagnetic body 33, the nonmagnetic body 34, and the ferromagnetic body 35 is called an SAF (Synthetic Anti-Ferromagnetic) structure. Due to the SAF structure, the ferromagnetic body 35 can offset the effect of the leakage magnetic field of the ferromagnetic body 33 on the change in the magnetization direction of the ferromagnetic body 31. As a result, the ferromagnetic body 35 can substantially reduce the leakage magnetic field of the ferromagnetic body 33.

[0054] A non-magnetic body 36 is provided on the lower surface of the ferromagnetic body 35. The non-magnetic body 36 is a conductive film having non-magnetic properties. The non-magnetic body 36 is used as an underlayer UL. The non-magnetic body 38 includes at least one element selected from, for example, zirconium (Zr), hafnium (Hf), tungsten (W), chromium (Cr), molybdenum (Mo), niobium (Nb), titanium (Ti), tantalum (Ta), vanadium (V), ruthenium (Ru), and platinum (Pt).

[0055] The magnetoresistive element MTJ can be in either a low resistance state or a high resistance state depending on whether the relative relationship between the magnetization directions of the memory layer SL and the reference layer RL is parallel or antiparallel. In the embodiment, a write current is passed through the magnetoresistive element MTJ to control the magnetization direction of the memory layer SL relative to the magnetization direction of the reference layer RL. Specifically, a write method is adopted that utilizes a spin transfer torque generated by passing a current through the magnetoresistive element MTJ.

[0056] When a write current Ic0 of a certain magnitude is passed through the magnetoresistive element MTJ in a direction from the memory layer SL to the reference layer RL, i.e., in the direction of the arrow A1 in FIG. 5, the relative relationship between the magnetization directions of the memory layer SL and the reference layer RL becomes parallel. In this parallel state, the resistance value of the magnetoresistive element MTJ becomes the lowest, and the magnetoresistive element MTJ is set to a low resistance state. This low resistance state is called a "P (Parallel) state" and is defined as, for example, a data "0" state.

[0057] Furthermore, when a write current Ic1 larger than the write current Ic0 is passed through the magnetoresistive element MTJ in a direction from the reference layer RL to the memory layer SL, i.e., in the direction of the arrow A2 in FIG. 5, the relative relationship between the magnetization directions of the memory layer SL and the reference layer RL becomes anti-parallel. In this anti-parallel state, the resistance value of the magnetoresistive element MTJ becomes the highest, and the magnetoresistive element MTJ is set to a high resistance state. This high resistance state is called the "AP (Anti-Parallel) state" and is defined as, for example, the state of data "1".

[0058] The method of defining data "1" and data "0" is not limited to the above example. For example, the P state may be defined as data "1" and the AP state may be defined as data "0."

[0059] 1.1.4 Characteristics of switching elements Next, the characteristics of the switching element SEL will be described with reference to Fig. 6. Fig. 6 is a diagram showing an example of the characteristics of a switching element. In Fig. 6, the vertical axis and the horizontal axis respectively represent the current flowing through the switching element SEL and the voltage between the terminals of the switching element SEL.

[0060] When the voltage between the terminals of the switching element SEL in the high resistance state is increased, as shown by the solid line in FIG. 6, at the threshold voltage Vth of the switching element SEL, the resistance between the terminals of the switching element SEL (hereinafter simply referred to as the resistance of the switching element SEL) drops abruptly from a resistance Roff to a resistance Ron (Roff>Ron). That is, the switching element SEL changes from a high resistance state to a low resistance state. This causes a sudden increase in the current flowing through the switching element SEL. On the other hand, when the voltage between the terminals of the switching element SEL in the low resistance state is decreased, for example, at a voltage V1 lower than the threshold voltage Vth, the resistance value increases abruptly from a resistance Ron to a resistance Roff. That is, the switching element SEL changes from a low resistance state to a high resistance state. This causes a sudden decrease in the current flowing through the switching element SEL.

[0061] The memory device 1 is used after changing the state related to the characteristics of the switching element SEL from the initial state to the usage state having the above-mentioned characteristics by performing a forming process before shipping the memory device 1. The high resistance state of the switching element SEL in the initial state has a resistance Ri higher than the resistance Roff of the switching element SEL in the high resistance state in the usage state (Ri>Roff). In the forming process, when the voltage between the terminals of the switching element SEL in the initial state is increased, the resistance value at the threshold voltage Vthi of the switching element SEL drops suddenly from the resistance Ri to the resistance Ron (Ri>Ron), for example, as shown by the dashed line in FIG. 6. The threshold voltage Vthi is higher than the threshold voltage Vth. In the forming process, a voltage is applied between the terminals of the switching element SEL in the initial state to form a conductive filament in the switching element SEL. This changes the state of the switching element SEL from the initial state to the usage state. In addition, the threshold voltage of the switching element SEL drops from the threshold voltage Vthi to the threshold voltage Vth.

[0062] 1.2 Manufacturing method of memory cell array As examples of the method for manufacturing the memory cell array 10 according to the embodiment, a first manufacturing method and a second manufacturing method will be described below.

[0063] 1.2.1 First manufacturing method A first manufacturing method for the memory cell array 10 of the memory device 1 according to the embodiment will be described.

[0064] Fig. 7 is a flow chart for explaining a method for manufacturing a memory cell array in a memory device according to the embodiment. Figs. 8 to 10 are cross-sectional views for explaining a method for manufacturing a memory cell array in a memory device according to the embodiment. Figs. 8 to 10 are cross-sectional views corresponding to Fig. 4.

[0065] In S0, a plurality of conductors 21 are provided as a plurality of word lines WL on the upper surface of a semiconductor substrate 20 serving as a wafer WF. Specifically, a conductor layer is first provided on the upper surface of the semiconductor substrate 20, and then a mask having openings in areas other than the portions corresponding to the word lines WL is formed by photolithography or the like. Then, the conductor layer is divided by anisotropic etching using the formed mask to form a plurality of conductors 21, and holes reaching the semiconductor substrate 20 are formed. The anisotropic etching in this process is, for example, RIE (Reactive Ion Etching). After that, an insulator is provided in the formed holes.

[0066] Next, in S1, as shown in Fig. 8, an electrode layer 122, a switching element layer 123, electrode layers 124a and 124b, a magnetoresistance effect element layer 125, an electrode layer 126, and a plurality of masks M1 are formed in this order on the upper surfaces of the plurality of conductors 21 and an insulator (not shown). In Fig. 7 and the following description, the electrode layer 122, the switching element layer 123, the electrode layers 124a and 124b, the magnetoresistance effect element layer 125, and the electrode layer 126 are also referred to as a BE layer, a SEL layer, an MEa layer, an MEb layer, an MTJ layer, and a TE layer, respectively. The magnetoresistance effect element layer 125 is a laminate in which each layer included in the magnetoresistance effect element MTJ described in Fig. 5 is formed in a flat plate shape in this stacking order. The masks M1 are formed by photolithography or the like to open the electrode layer 122, the switching element layer 123, the electrode layers 124a and 124b, the magnetoresistance effect element layer 125, and the electrode layer 126 except for the portions corresponding to the lower electrode BE, the switching element SEL, the intermediate electrode ME, the magnetoresistance effect element MTJ, and the upper electrode TE to be manufactured. The masks M1 are provided, for example, as a plurality of cylindrical structures arranged in a matrix on the upper surface of the electrode layer 126. The masks M1 include, for example, titanium nitride (TiN), and protect the portions that function as the lower electrode BE, the switching element SEL, the intermediate electrode ME, the magnetoresistance effect element MTJ, and the upper electrode TE in ion beam etching described later.

[0067] Then, in S2, the electrode layer 122, the switching element layer 123, the electrode layers 124a and 124b, the magnetoresistance effect element layer 125, and the electrode layer 126 are etched by ion beam etching. As a result, the portions of the electrode layer 122, the switching element layer 123, the electrode layers 124a and 124b, the magnetoresistance effect element layer 125, and the electrode layer 126 that are not protected by the masks M1 are removed, and the conductor 21 and the insulator (not shown) located below the portions are exposed. Then, the mask M1 is removed. Through the above process, a plurality of stacked structures each including the electrodes 22, 24, and 26, and the elements 23 and 25, are formed from the electrode layer 122, the switching element layer 123, the electrode layers 124a and 124b, the magnetoresistance effect element layer 125, and the electrode layer 126, as shown in FIG. 9.

[0068] Then, in S3, the electrode portion 24a is partially removed as shown in Fig. 10. More specifically, the electrode portion 24a is partially removed from the exposed portion of the electrode portion 24a by dry etching using, for example, oxygen plasma. In the process of S3, the etching selectivity of the electrode portion 24a is higher than the etching selectivity of the conductor 21, the electrodes 22 and 26, the electrode portion 24b, the elements 23 and 25, and the insulator (not shown).

[0069] Next, in S4, after the sidewall insulator 40 is formed, a plurality of conductors 27 are provided. More specifically, the sidewall insulator 40 is formed so as to cover the side surfaces of each of the plurality of stacked structures. Then, an insulator (not shown) is embedded between the plurality of stacked structures on which the sidewall insulator 40 is provided, for example, to a height equal to the upper surface of the electrode 26. Also, after a conductor layer is provided on the upper surfaces of the electrode 26 and the insulator, a mask is formed by photolithography or the like, in which an area other than the portion corresponding to the bit line BL is opened. Then, the conductor layer is divided by anisotropic etching using the formed mask to form a plurality of conductors 27, and holes reaching the insulator are formed. The anisotropic etching in this process is, for example, RIE. Then, an insulator is provided in the formed hole.

[0070] As described above, a configuration corresponding to the memory cell array 10 is formed on the wafer WF by the first manufacturing method. Then, the wafer WF is diced into chip units, and the memory devices 1 are formed.

[0071] 1.2.2 Second manufacturing method A second manufacturing method for the memory cell array 10 of the memory device 1 according to the embodiment will be described.

[0072] Fig. 11 is a flow chart for explaining a method for manufacturing a memory cell array in a memory device according to the embodiment. Figs. 12 to 14 are cross-sectional views for explaining a method for manufacturing a memory cell array in a memory device according to the embodiment. Figs. 12 to 14 are cross-sectional views corresponding to Fig. 4.

[0073] The process of S10 is the same as the process of S0 in the first manufacturing method.

[0074] In S11, as shown in Fig. 12, an electrode layer 122, a switching element layer 123, electrode layers 124a and 124b, and a plurality of masks M2 are formed in this order on the upper surfaces of the plurality of conductors 21 and an insulator (not shown). The plurality of masks M2 are formed by photolithography or the like to open areas of the electrode layer 122, the switching element layer 123, and the electrode layers 124a and 124b except for the areas corresponding to the lower electrode BE, the switching element SEL, and the intermediate electrode ME. The plurality of masks M2 are provided, for example, as a plurality of cylindrical structures arranged in a matrix on the upper surface of the electrode layer 126. The plurality of masks M2 contain, for example, titanium nitride (TiN) and protect the areas that function as the lower electrode BE, the switching element SEL, and the intermediate electrode ME in ion beam etching described later.

[0075] In S12, the electrode layer 122, the switching element layer 123, and the electrode layers 124a and 124b are etched by ion beam etching using the mask M2. As a result, the electrode layer 122, the switching element layer 123, and the electrode layers 124a and 124b are removed from the portions not protected by the masks M2, and the conductor 21 and the insulator (not shown) located below the portions are exposed. Then, the mask M2 is removed. Through the above process, a plurality of structures are formed from the electrode layer 122, the switching element layer 123, and the electrode layers 124a and 124b, each of which includes the electrodes 22 and 24 and the element 23, as shown in FIG.

[0076] In S13, the electrode portion 24a is partially removed, as shown in Figure 14. The process of S13 is substantially similar to the process of S3.

[0077] Next, in S14, a structure including element 25 and electrode 26 in this order is formed on each of a plurality of stacked structures including electrodes 22 and 24, and element 23. Note that the process of S14 is performed, for example, after the plurality of stacked structures including electrodes 22 and 24, and element 23 are embedded with an insulator.

[0078] The process of S15 is the same as the process of S5.

[0079] As described above, a configuration corresponding to the memory cell array 10 is formed on the wafer WF by the second manufacturing method. Then, the wafer WF is diced into chip units in the same manner as in the first manufacturing method, and the memory devices 1 are formed.

[0080] 1.3 Effects of the embodiment According to the embodiment, it is possible to improve the characteristics of the storage device. The effects of the embodiment will be described below.

[0081] The memory cell MC of the memory device 1 according to the embodiment is composed of a stacked structure stacked in the Z direction, including elements 23 and 25, and an electrode 24. The electrode 24 includes electrode portions 24a and 24b. The lower surface of the electrode portion 24a contacts the upper surface of the element 23. The area of ​​the lower surface of the electrode portion 24a is smaller than the area of ​​the upper surface of the element 23. This configuration in which the surface of the electrode portion 24a on the element 23 side contacts a surface in the stacked structure having a larger area than that surface can suppress a decrease in the resistance Roff of the switching element in the OFF state and suppress an increase in the current Ioff flowing through the element 23 in the OFF state. This suppresses erroneous reading during a read operation. Therefore, the characteristics of the memory device can be improved.

[0082] In addition, when the resistance Roff is not sufficiently large compared to the resistance Ron in a memory device, a sneak current may flow to adjacent memory cells around the memory cell in the Z direction during a read operation of the memory cell, which may result in a read error.

[0083] According to the embodiment, the resistance Roff can be increased and the current Ioff can be reduced, compared to the case where the electrodes and the switching elements in contact with each other have substantially equal contact surfaces and the area of ​​the electrodes in the XY plane is continuous or uniform in the Z direction (comparative example). Also, the configuration of the embodiment can maintain the threshold voltage Vth substantially equal to that of the comparative example. Therefore, it is possible to suppress the occurrence of sneak current and suppress erroneous reading without affecting the operation of the storage device 1.

[0084] 2. Variations The above-described embodiment can be modified in various ways, and the modifications will be described below.

[0085] 2.1 First modified example In the above embodiment, the electrode portion 24a has a circular shape when viewed from above, but this is not limited thereto. The electrode portion 24a may have a ring shape when viewed from above.

[0086] The configuration and manufacturing method of the memory device according to the first modification will be described below.

[0087] 2.1.1 Configuration In the memory device according to the first modification, each of the multiple stacked structures includes electrodes 22, 24, and 26, and elements 23 and 25. The configurations of the multiple conductors 21, the multiple electrodes 22, the multiple elements 23, the multiple electrode portions 24b, the multiple elements 25, the multiple electrodes 26, and the multiple conductors 27 are substantially equivalent to those according to the embodiment. The configuration of the electrode portion 24a in the memory device according to the first modification will be described below with reference to FIG. 15 and FIG. 16. FIG. 15 is a cross-sectional view showing an example of the cross-sectional structure of the memory cell array of the memory device according to the first modification. FIG. 16 is a cross-sectional view taken along line XVI-XVI in FIG. 15, showing an example of the cross-sectional structure of the memory cell array of the memory device according to the first modification.

[0088] Each of the multiple electrode parts 24a in the first modified example has, for example, a ring-shaped cross section in the XY plane. The outer diameter of the lower surface of each of the multiple electrode parts 24a is equal to or smaller than the outer diameter of the upper surface of the element 23 corresponding to the electrode part 24a. As a result, also in the first modified example, the area of ​​the lower surface of each of the multiple electrode parts 24a is smaller than the area of ​​the upper surface of the element 23 corresponding to the electrode part 24a. Also, the outer diameter of the upper surface of each of the multiple electrode parts 24a is equal to or smaller than the outer diameter of the lower surface of the electrode part 24b corresponding to the electrode part 24a. As a result, also in the first modified example, the area of ​​the upper surface of each of the multiple electrode parts 24a is smaller than the area of ​​the lower surface of the electrode part 24b corresponding to the electrode part 24a.

[0089] The outer diameter of each of the multiple electrode portions 24a is, for example, equal to or smaller than the outer diameter of the upper surface of the element 23 corresponding to that electrode portion 24a and the outer diameter of the lower surface of the electrode portion 24b corresponding to that electrode portion 24a, over the entire length along the Z direction.

[0090] An insulator 50 is provided on the upper surface of each of the elements 23 in the same layer as the electrode portion 24a. The insulator 50 includes, for example, silicon oxide and silicon nitride. As shown in Fig. 16, the insulator 50 is provided on the upper surface of each of the elements 23 so as to fill the periphery and inner region of the ring-shaped electrode portion 24a in the XY plane.

[0091] 2.1.2 Manufacturing method Next, a method for manufacturing the memory cell array 10 of the memory device 1 according to the first modification will be described.

[0092] Fig. 17 is a flow chart for explaining a method for manufacturing a memory cell array in a memory device according to a first modification. Fig. 18 and Figs. 20 to 22 are cross-sectional views for explaining a method for manufacturing a memory cell array in a memory device according to a first modification. Fig. 19 is a top view for explaining a method for manufacturing a memory cell array in a memory device according to a first modification. Figs. 18 and Figs. 20 to 22 are cross-sectional views corresponding to Fig. 15.

[0093] The process of S20 is equivalent to the process of S0 in the embodiment.

[0094] In S21, as shown in Fig. 18, an electrode layer 122, a switching element layer 123, an insulator layer 150, and a mask M3 are formed in this order on the upper surfaces of a plurality of conductors 21 and an insulator (not shown). The mask M3 has an opening in a region OP corresponding to the electrode portion 24a when viewed from above, by photolithography or the like, as shown in Fig. 19. The mask M3 contains, for example, titanium nitride (TiN), and protects the insulator layer 150 except for the region corresponding to the electrode portion 24a in ion beam etching, which will be described later.

[0095] Next, in S22, the insulator layer 150 is etched by ion beam etching. Also, the mask M3 is removed. Through the above process, as shown in FIG. 20, the portion of the insulator layer 150 that is not protected by the mask M3 is removed, and a hole is formed that exposes the switching element layer 123 located below the portion.

[0096] Then, in S23, as shown in Fig. 21, the electrode portion 24a, the electrode layer 124b, the magnetoresistance effect element layer 125, the electrode layer 126, and a plurality of masks M4 are formed in this order. More specifically, the electrode portion 24a is formed in the hole formed in S22 by using, for example, ALD (Atomic Layer Deposition), CVD (Chemical Vapor Deposition), etc., and CMP (Chemical Mechanical Polishing). In addition, the electrode layer 124b, the magnetoresistance effect element layer 125, the electrode layer 126, and a plurality of masks M4 are formed in this order on the upper surface of the electrode portion 24a and the insulator layer 150. The plurality of masks M4 are formed in the same manner as the plurality of masks M1 formed in S1 in the embodiment.

[0097] The process of S24 is the same as the process of S2 in the embodiment, except that a plurality of masks M4 are used instead of the plurality of masks M1. By the process of S24, a plurality of laminated structures each including electrodes 22, 24, 26, and elements 23 and 25 are formed from the electrode layer 122, the switching element layer 123, the electrode portion 24a, the insulator layer 150, the magnetoresistance effect element layer 125, and the electrode layer 126, as shown in FIG.

[0098] In the process of S25, similar to the process of S4 in the embodiment, a sidewall insulator 40 and a plurality of conductors 27 are formed.

[0099] In this manner, the memory device 1 according to the first modified example is manufactured.

[0100] The first modified example also provides the same effects as the embodiment.

[0101] 2.2 Second variant In the above-described embodiment and the first modified example, the electrode portion 24b is provided on the upper surface of the electrode portion 24a, but this is not limiting. The electrode portion 24a may be provided on the upper surface of the electrode portion 24b.

[0102] In the memory device according to the second modification, the configurations of the plurality of conductors 21, the plurality of electrodes 22, the plurality of elements 23, the plurality of elements 25, the plurality of electrodes 26, and the plurality of conductors 27 are substantially the same as those in the embodiment and the first modification. The configuration of the intermediate electrode ME in the memory device according to the second modification will be described below with reference to FIG. 23. FIG. 23 is a cross-sectional view showing an example of a cross-sectional structure of a memory cell array of the memory device according to the second modification. Note that, in the following, a case will be shown in which the memory device 1 according to the second modification includes an electrode portion 24a having a circular cross section in the XY plane, as in the embodiment, but this is not limited thereto. The memory device 1 according to the second modification may include an electrode portion 24a having a ring-shaped cross section in the XY plane, as in the first modification.

[0103] In the second modification, each of the multiple electrode portions 24b is provided on the upper surface of a corresponding one of the multiple elements 23.

[0104] On the upper surface of each of the plurality of electrode portions 24b, a corresponding one of the plurality of electrode portions 24a is provided. The outer diameter of the lower surface of each of the plurality of electrode portions 24a is smaller than the outer diameter of the upper surface of the electrode portion 24b corresponding to the electrode portion 24a. As a result, the area of ​​the lower surface of each of the plurality of electrode portions 24a is smaller than the area of ​​the upper surface of the electrode portion 24b corresponding to the electrode portion 24a.

[0105] On the upper surface of each of the plurality of electrode portions 24a, a corresponding one of the plurality of elements 25 is provided. The outer diameter of the upper surface of each of the plurality of electrode portions 24a is smaller than the outer diameter of the lower surface of the element 25 corresponding to that electrode portion 24a. As a result, the area of ​​the upper surface of each of the plurality of electrode portions 24a is smaller than the area of ​​the lower surface of the element 25 corresponding to that electrode portion 24a.

[0106] The outer diameter of each of the multiple electrode portions 24a is smaller than the outer diameter of the upper surface of the electrode portion 24b corresponding to that electrode portion 24a and the outer diameter of the lower surface of the element 25 corresponding to that electrode portion 24a, for example, over the entire area along the Z direction.

[0107] When the electrode portion 24a has a ring-shaped cross section, the outer diameter of the lower surface of each of the electrode portions 24a is equal to or smaller than the outer diameter of the upper surface of the electrode portion 24b corresponding to the electrode portion 24a. Also, the outer diameter of the upper surface of each of the electrode portions 24a is equal to or smaller than the outer diameter of the lower surface of the element 25 corresponding to the electrode portion 24a.

[0108] The method for manufacturing the memory device 1 according to the second modification can be the same as the manufacturing method of the embodiment, except for, for example, the order in which the electrode layers 124a and 124b are formed.

[0109] Furthermore, similarly to the first modified example, when the memory device 1 according to the second modified example includes an electrode portion 24a having a ring-shaped cross section in the XY plane, the manufacturing method can be the same as that of the memory device 1 according to the first modified example, except that the electrode layer 124b is formed before forming the electrode portion 24a using the insulator layer 150 and the mask M2.

[0110] The storage device according to the second modification also provides the same effects as those of the embodiment and the first modification.

[0111] 2.3 Third variant In the above-described embodiment, the first modification, and the second modification, the intermediate electrode ME is configured from the electrode portions 24a and 24b, but is not limited to this. The intermediate electrode ME may further include a different configuration in addition to the electrode portions 24a and 24b.

[0112] In the memory device according to the third modification, the configurations of the plurality of conductors 21, the plurality of electrodes 22, the plurality of elements 23, the plurality of elements 25, the plurality of electrodes 26, and the plurality of conductors 27 are substantially the same as those in the embodiment, the first modification, and the second modification. The configuration of the intermediate electrode ME in the memory device according to the third modification will be described below with reference to FIG. 24. FIG. 24 is a cross-sectional view showing an example of a cross-sectional structure of a memory cell array in the memory device according to the third modification. Note that, in the following, a case will be shown in which the memory device 1 according to the third modification includes an electrode portion 24a having a circular cross section in the XY plane, as in the embodiment, but this is not limited thereto. The memory device 1 according to the third modification may include an electrode portion 24a having a ring-shaped cross section in the XY plane, as in the first modification.

[0113] In the third modified example, the intermediate electrode ME includes an electrode portion 24c in addition to the electrode portions 24a and 24b. The configurations of the electrode portions 24a and 24b according to the third modified example are substantially similar to the configurations of the electrode portions 24a and 24b according to the embodiment and the first modified example.

[0114] On the upper surface of each of the plurality of electrode portions 24a, one of the plurality of electrode portions 24c corresponding thereto is provided. The electrode portion 24c has a circular cross section in the XY plane, similar to the electrode portions 24a and 24b. The outer diameter of the lower surface of each of the plurality of electrode portions 24c is larger than the outer diameter of the upper surface of the electrode portion 24a corresponding to the electrode portion 24c. As a result, the area of ​​the lower surface of each of the plurality of electrode portions 24c is larger than the area of ​​the upper surface of the electrode portion 24a corresponding to the electrode portion 24c. Note that the outer diameter of each of the plurality of electrode portions 24a is smaller than the outer diameter of the lower surface of the electrode portion 24c corresponding to the electrode portion 24a and the outer diameter of the upper surface of the electrode portion 24b corresponding to the electrode portion 24a, for example, over the entire area along the Z direction. The electrode portion 24c includes, for example, titanium (Ti), tungsten (W), titanium nitride (TiN), tungsten nitride (WN), titanium nitride (TiWN) having tungsten, and the like.

[0115] When the electrode portion 24a has a ring-shaped cross section, the outer diameter of the upper surface of each of the multiple electrode portions 24a is equal to or smaller than the outer diameter of the lower surface of the electrode portion 24c corresponding to that electrode portion 24a.

[0116] On the upper surface of each of the plurality of electrode portions 24c, one of the plurality of elements 25 is provided correspondingly.

[0117] The manufacturing method of the memory device 1 according to the third modified example can be similar to that of the embodiment, except that in S1 or S11, in addition to the electrode layers 124a and 124b, an electrode layer corresponding to the electrode portion 24c is formed.

[0118] Furthermore, similarly to the first modified example, when the memory device 1 according to the second modified example includes an electrode portion 24a having a ring-shaped cross section in the XY plane, the manufacturing method can be the same as that of the memory device 1 according to the first modified example, except that an electrode layer corresponding to the electrode portion 24c is formed in S23.

[0119] The storage device according to the third modification also provides the same effects as those of the embodiment, the first modification, and the second modification.

[0120] 2.4 Fourth variant In the above-described embodiment, the first modified example, the second modified example, and the third modified example, the intermediate electrode ME is composed of a plurality of electrode portions, but is not limited thereto. The intermediate electrode ME may be composed of only a portion corresponding to the electrode portion 24a.

[0121] The memory device 1 according to the fourth modification includes a plurality of conductors 21, a plurality of electrodes 22, a plurality of elements 23, a plurality of electrodes 24, a plurality of elements 25, a plurality of electrodes 26, and a plurality of conductors 27. In the memory device 1 according to the fourth modification, the configurations of the plurality of conductors 21, the plurality of electrodes 22, the plurality of elements 23, the plurality of elements 25, the plurality of electrodes 26, and the plurality of conductors 27 are substantially equivalent to those of the embodiment, the first modification, the second modification, and the third modification. The configuration of the plurality of electrodes 24 in the memory device according to the fourth modification will be described below with reference to FIG. 25. FIG. 25 is a cross-sectional view showing an example of a cross-sectional structure of a memory cell array of the memory device according to the fourth modification. Note that, in the following, a case will be shown in which the memory device 1 according to the fourth modification includes an electrode 24 having a circular cross section in the XY plane, similar to the electrode portion 24a according to the embodiment, but is not limited thereto. The memory device 1 according to the fourth modification may include an electrode 24 having a ring-shaped cross section in the XY plane, similar to the electrode portion 24a according to the first modification.

[0122] In the fourth modified example, each of the multiple electrodes 24 is provided on the upper surface of a corresponding one of the multiple elements 23. Also, on the upper surface of each of the multiple electrodes 24, a corresponding one of the multiple elements 25 is provided. Thus, in the fourth modified example, the intermediate electrode ME is composed of only the electrode 24. The outer diameter of the lower surface of each of the multiple electrodes 24 is smaller than the outer diameter of the upper surface of the element 23 corresponding to the electrode 24. As a result, the area of ​​the lower surface of each of the multiple electrodes 24 is smaller than the area of ​​the upper surface of the element 23 corresponding to the electrode 24. Also, the outer diameter of the upper surface of each of the multiple electrodes 24 is smaller than the outer diameter of the lower surface of the element 25 corresponding to the electrode 24. As a result, the area of ​​the upper surface of each of the multiple electrodes 24 is smaller than the area of ​​the lower surface of the element 25 corresponding to the electrode 24.

[0123] The outer diameter of each of the multiple electrodes 24 is smaller than the outer diameter of the upper surface of the element 23 corresponding to that electrode 24 and the outer diameter of the lower surface of the element 25 corresponding to that electrode 24, for example, over the entire area along the Z direction.

[0124] When the electrode 24 has a ring-shaped cross section, the outer diameter of the lower surface of each of the multiple electrodes 24 is equal to or smaller than the outer diameter of the upper surface of the element 23 corresponding to that electrode 24. Moreover, the outer diameter of the upper surface of each of the multiple electrodes 24 is equal to or smaller than the outer diameter of the lower surface of the element 25 corresponding to that electrode 24.

[0125] The manufacturing method of the memory device 1 according to the fourth modification can be the same as the manufacturing method of the embodiment, except that, for example, the electrode layer 124b is not formed.

[0126] Furthermore, in the case where the memory device 1 of the fourth variant includes an electrode 24 having a ring-shaped cross section in the XY plane, as in the first variant, the manufacturing method can be the same as that of the memory device 1 of the first variant, except that the electrode layer 124b is not formed.

[0127] The storage device according to the fourth modification also provides the same effects as those of the embodiment, the first modification, the second modification, and the third modification.

[0128] 2.5 Fifth Variation In the above-described embodiment, the first modification, the second modification, the third modification, and the fourth modification, the surface of the intermediate electrode ME or a part thereof facing the switching element SEL is in contact with a surface in the laminated structure having a larger area than the surface, but this is not limited thereto. The surface of the lower electrode BE or a part thereof facing the switching element SEL may be provided so as to be in contact with a surface in the laminated structure having a larger area than the surface.

[0129] The configuration and manufacturing method of the memory device according to the fifth modification will be described below.

[0130] In the fifth modification, the memory cell array 10 includes a plurality of conductors 21, a plurality of electrodes 22, a plurality of elements 23, a plurality of electrodes 24, a plurality of elements 25, a plurality of electrodes 26, and a plurality of conductors 27. The configurations of the plurality of conductors 21, the plurality of elements 23, the plurality of elements 25, the plurality of electrodes 26, and the plurality of conductors 27 according to the fifth modification are substantially equivalent to those according to the embodiment, the first modification, the second modification, the third modification, and the fourth modification. The configuration of the plurality of electrodes 22 and 24 of the memory device 1 according to the fifth modification will be described below with reference to FIG. 26. FIG. 26 is a cross-sectional view showing an example of a cross-sectional structure of a memory cell array of the memory device according to the fifth modification.

[0131] On the upper surface of each of the plurality of electrodes 22, a corresponding one of the plurality of elements 23 is provided. Each of the plurality of electrodes 22 has, for example, a circular shape. The outer diameter of the upper surface of each of the plurality of electrodes 22 is smaller than the outer diameter of the lower surface of the element 23 corresponding to the electrode 22. As a result, the area of ​​the upper surface of each of the plurality of electrodes 22 is smaller than the area of ​​the lower surface of the element 23 corresponding to the electrode 22. Note that the outer diameter of each of the plurality of electrodes 22 is smaller than the outer diameter of the lower surface of the element 23 corresponding to the electrode 22, for example, over the entire area along the Z direction. The electrode 22 contains, for example, carbon (C). The electrode 22 may have an amorphous structure.

[0132] 26 shows a case where the electrode 22 is circular when viewed from above, similar to the electrode portion 24a in the embodiment, but is not limited thereto. The electrode 22 may be ring-shaped when viewed from above, similar to the electrode portion 24a in the first modification. In this case, the outer diameter of the upper surface of each of the multiple electrodes 22 is equal to or smaller than the outer diameter of the lower surface of the element 23 corresponding to that electrode 22.

[0133] On the upper surface of each of the plurality of elements 23, one of the plurality of electrodes 24 is provided corresponding to the plurality of elements 23. The electrodes 24 include, for example, titanium (Ti), tungsten (W), titanium nitride (TiN), tungsten nitride (WN), titanium nitride having tungsten (TiWN), etc. Although not shown, the electrodes 24 may be composed of one or more parts.

[0134] The memory device 1 according to the fifth modified example as described above may be manufactured, for example, in the same manner as in the manufacturing method according to the embodiment, except that an electrode layer 124 is formed instead of electrode layers 124a and 124b, and that in S3 or S13 of the embodiment, instead of partial etching of electrode portion 24a, partial etching of electrode 22 is performed.

[0135] Furthermore, when the memory device 1 of the fifth variant includes an electrode 22 having a ring-shaped cross-section in the XY plane, similar to the electrode portion 24a in the first variant, the multiple electrodes 22 can be formed on the upper surface of the multiple conductors 21, similar to the formation of the electrode portion 24a using the insulator layer 150 and mask M2 in the first variant.

[0136] The fifth modified example also provides the same effects as the embodiment, the first modified example, the second modified example, the third modified example, and the fourth modified example.

[0137] In addition, in FIG. 26, the case where the lower electrode BE is composed of one part is shown, but this is not limited thereto. In the fifth modification, the lower electrode BE may be configured so that a plurality of electrode parts are laminated. In this case, the lower electrode BE is configured so that the surface (upper surface) of one of the plurality of parts (first electrode part) on the switching element SEL side is in contact with a surface in the laminated structure having a larger area than the surface. More specifically, similar to the intermediate electrode ME according to the embodiment and the first modification, the lower electrode BE may be composed of a plurality of electrode parts, and the first electrode part may be in contact with the switching element SEL. Also, similar to the intermediate electrode ME according to the second and third modifications, the lower electrode BE may be composed of a plurality of electrode parts, and the first electrode part may be in contact with the switching element SEL via a second electrode part different from the first electrode part included in the lower electrode BE. Also, in the lower electrode BE according to the fifth modification, a third electrode part different from the first electrode part and the second electrode part may be included between the first electrode part and the conductor 21, similar to the third modification.

[0138] 2.6 Sixth Variation In the above-mentioned embodiment, the first modified example, the second modified example, the third modified example, and the fourth modified example, the case where the surface of the intermediate electrode ME or a part thereof on the switching element SEL side is in contact with a surface in the laminated structure having a larger area than the surface is shown, and in the fifth modified example, the case where the surface of the lower electrode BE or a part thereof on the switching element SEL side is in contact with a surface in the laminated structure having a larger area than the surface is shown, but the present invention is not limited to these. The upper electrode TE and the switching element SEL may be in contact with each other, and the upper electrode TE or a part thereof may be provided so that the surface on the switching element SEL side of the upper electrode TE is in contact with a surface in the laminated structure having a larger area than the surface.

[0139] The configuration and manufacturing method of the memory device according to the sixth modified example will be described below.

[0140] In the sixth modified example, the memory cell array 10 includes a plurality of conductors 21, a plurality of electrodes 22, a plurality of elements 23, a plurality of electrodes 24, a plurality of elements 25, a plurality of electrodes 26, and a plurality of conductors 27. The configurations of the plurality of conductors 21, the plurality of electrodes 22, and the plurality of conductors 27 according to the sixth modified example are substantially equivalent to those according to the embodiment, the first modified example, the second modified example, and the third modified example. The configurations of the plurality of elements 23, the plurality of electrodes 24, the plurality of elements 25, and the plurality of electrodes 26 of the memory device 1 according to the sixth modified example will be described below with reference to FIG. 27. FIG. 27 is a cross-sectional view showing an example of a cross-sectional structure of a memory cell array of the memory device according to the sixth modified example.

[0141] In the sixth modification, one of the plurality of elements 25 is provided on the upper surface of each of the plurality of electrodes 22.

[0142] On the upper surface of each of the plurality of elements 25, one of the plurality of electrodes 24 is provided. The configuration of the electrode 24 is similar to the configuration of the electrode 24 in the fifth modified example, for example.

[0143] On the upper surface of each of the plurality of electrodes 24, one of the plurality of elements 23 is provided.

[0144] On the upper surface of each of the plurality of elements 23, one of the plurality of electrodes 26 corresponding thereto is provided. The outer diameter of the lower surface of each of the plurality of electrodes 26 is smaller than the outer diameter of the upper surface of the element 23 corresponding to that electrode 26. As a result, the area of ​​the lower surface of each of the plurality of electrodes 26 is smaller than the area of ​​the upper surface of the element 23 corresponding to that electrode 26. Note that the outer diameter of each of the plurality of electrodes 26 is smaller than the outer diameter of the upper surface of the element 23 corresponding to that electrode 26, for example, over the entire area along the Z direction. The electrode 26 contains, for example, carbon (C). The electrode 26 may have an amorphous structure.

[0145] 27 shows a case where the electrode 26 is circular when viewed from above, similar to the electrode portion 24a in the embodiment, but is not limited thereto. The electrode 26 may be ring-shaped when viewed from above, similar to the electrode portion 24a in the first modification. In this case, the outer diameter of the lower surface of each of the multiple electrodes 26 is equal to or smaller than the outer diameter of the upper surface of the element 23 corresponding to that electrode 26.

[0146] The memory device 1 according to the sixth modified example as described above can be manufactured in the same manner as the first manufacturing method according to the embodiment, except that the electrode layer 124 is formed instead of the electrode layers 124a and 124b, the stacking order is different, and in S3 of the embodiment, instead of partial etching of the electrode portion 24a, partial etching of the electrode 26 is performed. Also, the memory device 1 according to the sixth modified example can be manufactured in the same manner as the second manufacturing method according to the embodiment, except that instead of the process of S13, partial etching of the electrode 26 is performed after the process of S14 and before the process of S15.

[0147] Furthermore, in the case where the memory device 1 according to the sixth modification includes an electrode 26 having a ring-shaped cross section in the XY plane, similar to the electrode portion 24a in the first modification, for example, in a process corresponding to S21, an electrode layer 124 and a magnetoresistance effect element layer 125 are formed. Also, a mask corresponding to the mask M3 is formed on the upper surface of the magnetoresistance effect element layer 125. Also, in S22 and S23, an electrode 26 may be formed on the upper surface of the switching element layer 123, similar to the formation of the electrode portion 24a using the mask M3 in the first modification. Note that the stacking order of the multiple electrode layers and element layers is different from that in the first modification.

[0148] The sixth modified example also provides the same effects as the embodiment, the first modified example, the second modified example, the third modified example, the fourth modified example, and the fifth modified example.

[0149] In addition, although FIG. 27 shows a case where the upper electrode TE is composed of one part, this is not limited thereto. In the sixth modification, the upper electrode TE may be configured so that a plurality of electrode parts are laminated. In this case, the upper electrode TE is configured so that the surface (lower surface) of one of the plurality of parts (first electrode part) on the switching element SEL side is in contact with a surface in the laminated structure having a larger area than that surface. More specifically, similar to the intermediate electrode ME according to the embodiment and the first modification, the upper electrode TE may be composed of a plurality of electrode parts, and the first electrode part may be in contact with the switching element SEL. Also, similar to the intermediate electrode ME according to the second and third modifications, the upper electrode TE may be composed of a plurality of electrode parts, and the first electrode part may be in contact with the switching element SEL via a second electrode part different from the first electrode part included in the upper electrode TE. Also, in the upper electrode TE according to the sixth modification, a third electrode part different from the first electrode part and the second electrode part may be included between the first electrode part and the conductor 27, similar to the third modification.

[0150] 3. Other In the above-described embodiment, the first modification, the second modification, the third modification, and the fourth modification, the element 25 functioning as a resistance change element is provided above the element 23, but this is not limited thereto. In the configurations of the embodiment, the first modification, the second modification, the third modification, and the fourth modification, the elements 23 and 25 may be interchanged as shown in FIG. 28. FIG. 28 is a cross-sectional view showing an example of a cross-sectional structure of a memory cell array of a storage device according to another example. In this case, the outer diameter of the lower surface of each of the multiple electrodes 24 is smaller than the outer diameter of the upper surface of the element 25 corresponding to the electrode 24. As a result, the area of ​​the lower surface of each of the multiple electrodes 24 is smaller than the area of ​​the upper surface of the element 25 corresponding to the electrode 24. In addition, the outer diameter of the upper surface of each of the multiple electrodes 24 is smaller than the outer diameter of the lower surface of the element 23 corresponding to the electrode 24. As a result, the area of ​​the upper surface of each of the multiple electrodes 24 is smaller than the area of ​​the lower surface of the element 23 corresponding to the electrode 24.

[0151] In FIG. 28, the intermediate electrode ME in contact with the switching element SEL is configured from one portion, but this is not limited thereto. In other examples, the intermediate electrode ME may be configured to have a plurality of electrode portions laminated. In this case, the intermediate electrode ME may be configured such that the surface (upper surface) of one of the plurality of electrode portions (first electrode portion) on the switching element SEL side is in contact with a surface in the laminated structure having a larger area than the surface. More specifically, similar to the intermediate electrode ME according to the embodiment and the first modification, the intermediate electrode ME may be configured from a plurality of electrode portions, and the first electrode portion may be in contact with the switching element SEL. Also, similar to the intermediate electrode ME according to the second and third modifications, the intermediate electrode ME may be configured from a plurality of electrode portions, and the first electrode portion may be in contact with the switching element SEL via a second electrode portion different from the first electrode portion included in the intermediate electrode ME. Also, in the intermediate electrode ME according to other examples, similar to the third modification, a third electrode portion different from the first electrode portion and the second electrode portion may be included between the first electrode portion and the conductor 21.

[0152] In the above-mentioned embodiment, the first modification, the second modification, the third modification, and the fourth modification, at least a part of the electrodes 22, 24, and 26 that contact the element 23 is circular or ring-shaped in the XY plane, but this is not limited thereto. At least a part of the electrodes 22, 24, and 26 that contact the element 23 may be rectangular or any other shape in the XY plane. The surface of at least a part of the electrode on the element 23 side may contact the surface of the element 23 that is wider than the surface in the laminated structure, or the surface of another part of the electrode that is wider than the surface. Such a configuration can be formed, for example, by changing the shape of the region OP in the formation of the electrode portion 24a using the mask M3 in the second modification.

[0153] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0154] 1...memory device, 10...memory cell array, 11...row selection circuit, 12...column selection circuit, 13...decoding circuit, 14...write circuit, 15...read circuit, 16...voltage generation circuit, 17...input / output circuit, 18...control circuit, 20...semiconductor substrate, 21...conductor, 22, 24, 26...electrode, 23, 25...element, 32, 34, 36...non-magnetic material, 31, 33, 35...ferromagnetic material, 41, 42...insulator.< / n> < / m> < / j> < / m> < / n>

Claims

1. a switching element, an electrode having a first electrode portion, and a resistance change element, the switching element including a stacked structure stacked in a first direction; The switching element and the electrode are in contact with each other in the first direction, a first surface of the first electrode portion on the switching element side is in contact with a second surface of the laminated structure, the second surface being larger than the first surface; storage device.

2. The first electrode portion has a circular shape in a plane perpendicular to the first direction. The storage device according to claim 1.

3. The first electrode portion has a ring shape in a plane perpendicular to the first direction. The storage device according to claim 1.

4. The electrode is provided between the switching element and the resistance change element. The storage device according to claim 1.

5. The electrodes sandwich the switching element together with the resistance change element in a first direction. The storage device according to claim 1.

6. The second surface is a surface of the switching element on the electrode side. The storage device according to claim 4 or 5.

7. The electrode is composed of only the first electrode portion. The storage device according to claim 6.

8. the electrode further comprises a second electrode portion; The second electrode portion, together with the switching element, sandwiches the first electrode portion in the first direction. The storage device according to claim 6.

9. the electrode further comprises a second electrode portion; The second surface is a surface of the second electrode portion on the first electrode portion side. The storage device according to claim 4 or 5.

10. the electrode further comprises a third electrode portion; The third electrode portion, together with the second electrode portion, sandwiches the first electrode portion in the first direction. The storage device according to claim 9.

11. A first wiring extending in a second direction perpendicular to the first direction is further provided, The electrode is provided on the first wiring. The storage device according to claim 5.

12. The switching element is a two-terminal switching element. The storage device according to claim 1.

13. the switching element includes a chalcogenide material; The storage device according to claim 1.

14. The switching element contains at least one element selected from the group 5 and the group 6 elements. The storage device according to claim 1.

15. The resistance change element is a magnetoresistance effect element. The storage device according to claim 1.

16. The magnetoresistive effect element is A first ferromagnetic layer; A second ferromagnetic layer; a third ferromagnetic layer provided on the opposite side of the second ferromagnetic layer to the first ferromagnetic layer; a first nonmagnetic layer provided between the first ferromagnetic layer and the second ferromagnetic layer; a second nonmagnetic layer provided between the second ferromagnetic layer and the third ferromagnetic layer; Including, the first nonmagnetic layer contains an oxide of magnesium (Mg); The storage device according to claim 15.

17. the second nonmagnetic layer contains at least one element selected from ruthenium (Ru), osmium (Os), rhodium (Rh), iridium (Ir), vanadium (V), and chromium (Cr); 17. The storage device of claim 16.

18. the third ferromagnetic layer is provided between a substrate and the second ferromagnetic layer; 20. The storage device of claim 17.

19. the second ferromagnetic layer and the third ferromagnetic layer are antiferromagnetically coupled; 20. The storage device of claim 18.

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