Semiconductor storage device

By utilizing a polycrystalline semiconductor film with varying particle sizes to control N-type impurity diffusion, the semiconductor memory device addresses reliability issues related to select gate performance during erasing processes, resulting in enhanced operational reliability.

JP2025042945APending Publication Date: 2025-03-28KIOXIA CORP
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Patent Information

Application Number
JP2023150162
Authority / Receiving Office
JP · JP
Patent Type
Applications
Current Assignee / Owner
Filing Date
2023-09-15
Publication Date
2025-03-28

AI Technical Summary

Technical Problem

Existing semiconductor memory devices face challenges in improving operational reliability due to variations in the diffusion length of N-type impurities, which affect the performance of select gates during erasing processes.

Method used

The semiconductor memory device incorporates a polycrystalline semiconductor film with distinct portions having different average particle sizes, where the portion corresponding to the farthest conductive layer has a smaller particle size than the portions corresponding to multiple conductive layers closer to the substrate, thereby controlling N-type impurity diffusion effectively.

Benefits of technology

This approach enhances the reliability of the semiconductor memory device by improving GIDL generation at the select gate during erasing and ensuring proper operation of select gates, leading to improved overall device performance.

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Abstract

To provide a semiconductor storage device that improves reliability of operations.SOLUTION: A memory cell array includes a laminate SST that is arranged above a substrate and in which a plurality of conductive layers 6 are laminated with an insulating layer 7 interposed therebetween, and a columnar body 40 including a first polycrystalline semiconductor film 42 extending in a lamination direction inside the laminate and a first insulating film 43 extending in the lamination direction between the plurality of conductive layers 6 and the first polycrystalline semiconductor film inside the laminate. The first polycrystalline semiconductor film includes a first portion 42a and a second portion 42b, the first portion corresponding to a first conductive layer which is a conductive layer farthest from the substrate, and the second portion corresponding to two or more conductive layers arranged between the substrate and the first conductive layer. The height of the boundary between the first portion and the second portion from the substrate is between the height of the upper surface of the first conductive layer from the substrate and the height of the upper surface of the second conductive layer from the substrate, the second conductive layer being the conductive layer farthest from the substrate among the two or more conductive layers. The average grain size of the first portion is smaller than the average grain size of the second portion.SELECTED DRAWING: Figure 4
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