Semiconductor driving apparatus

Abstract

To realize an active gate control system capable of sufficiently obtaining a reduction effect of a switching loss even when a turn-off time of a semiconductor element is long.SOLUTION: A drive circuit 50 has a gate driving part 51 controlling gate voltage applied to a control terminal (gate terminal) of a power semiconductor element T1 and switch-driving the power semiconductor element T1 by turning on and turning off the power semiconductor element T1, and a speed switchover part 53 switching a switching speed so as to increase the switching speed of the power semiconductor element T1 at a timing of being delayed from a turn off start of the power semiconductor element T1 by a predetermined time τ.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to an apparatus for driving a semiconductor element. [Background technology]

[0002] Power conversion devices that convert DC power and AC power mutually by the switching operation of semiconductor elements have high conversion efficiency and are therefore widely used in consumer, automotive, railway, substation equipment, etc. In order to achieve even higher efficiency in such power conversion devices, it is necessary to reduce the switching loss that occurs during switching.

[0003] In order to reduce the switching loss of a semiconductor element, it is effective to increase the switching speed by decreasing the value of the gate resistor connected to the gate terminal of the semiconductor element. However, increasing the switching speed tends to increase the surge voltage generated when the semiconductor element is turned off, which may adversely affect the connection destination of the power conversion device.

[0004] To solve the above problem, for example, the technology of Patent Document 1 is known. Patent Document 1 discloses a technology that improves the switching speed while suppressing the surge voltage by switching the gate resistance value just before turning off the semiconductor element to switch the rate of change of the gate voltage and reduce the switching speed. This type of control method for semiconductor elements is called an active gate control method. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Patent No. 6989035 Summary of the Invention [Problem to be solved by the invention]

[0006] In the active gate control method described in Patent Document 1, the drain-source voltage Vds of a semiconductor element is compared with a predetermined reference voltage Vref, and when it is detected that the voltage Vds is greater than the reference voltage Vref, the gate resistance value is changed to reduce the switching speed. However, in this method, when the turn-off time of the semiconductor element is long, for example, at low current or high temperature, the timing at which the switching speed decreases between the start and end of the turn-off of the semiconductor element becomes relatively too early, and as a result, the effect of reducing switching loss may not be sufficiently obtained.

[0007] The present invention has been made in consideration of the above problems, and a main object of the present invention is to realize an active gate control method that can sufficiently obtain the effect of reducing switching losses even when the turn-off time of a semiconductor element is long. [Means for solving the problem]

[0008] The semiconductor driving device according to the present invention includes a gate driving unit that controls a voltage applied to a control terminal of a power semiconductor element and turns on and off the power semiconductor element to switch the power semiconductor element, and a speed switching unit that switches the switching speed so as to increase the switching speed of the power semiconductor element at a timing delayed by a predetermined delay time from the start of turn-off of the power semiconductor element. Effect of the Invention

[0009] According to the present invention, it is possible to realize an active gate control method that can obtain a sufficient effect of reducing switching loss even when the turn-off time of a semiconductor element is long. [Brief description of the drawings]

[0010] [Figure 1] 1 is a block diagram showing a schematic configuration of a motor drive system including a semiconductor drive device according to an embodiment of the present invention. [Diagram 2]1 is a circuit block diagram showing a main configuration of a semiconductor driving device according to an embodiment of the present invention; [Diagram 3] 1 is a diagram showing a circuit configuration of a drive circuit according to a first embodiment of the present invention. [Figure 4] 4 is a time chart showing an example of how each signal changes when a power semiconductor element is turned off in the case where the drive circuit according to the first embodiment of the present invention is applied. [Diagram 5] FIG. 2 is a diagram showing an example of the relationship between the main current and switching characteristics of a power semiconductor element. [Figure 6] FIG. 1 is a diagram showing an example of the relationship between the junction temperature and the switching characteristics of a power semiconductor element. [Figure 7] FIG. 11 is a diagram showing a circuit configuration of a drive circuit according to a second embodiment of the present invention. [Figure 8] FIG. 11 is a diagram showing a circuit configuration of a drive circuit according to a third embodiment of the present invention. [Figure 9] 10 is a time chart showing an example of how each signal changes when a power semiconductor element is turned off in the case where a drive circuit according to a third embodiment of the present invention is applied. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Fig. 1 is a block diagram showing a schematic configuration of a motor drive system including a semiconductor drive device according to an embodiment of the present invention. In the motor drive system shown in Fig. 1, a power conversion device 200 is connected between a motor 900 and a high-voltage battery 901, and drives the motor 900 by converting DC power supplied from the high-voltage battery 901 into AC power and outputting it to the motor 900. A contactor 902 is provided between the power conversion device 200 and the high-voltage battery 901 to control the connection state between them.

[0012] The power conversion device 200 includes a controller 100a, a driver 100b, an inverter circuit 300, and a voltage smoothing capacitor 500. A command (such as a torque command or a rotation command) for driving the motor 900 is input to the power conversion device 200 from a higher-level controller (not shown). The inverter circuit 300 is provided with a plurality of legs, each of which has a plurality of power semiconductor elements arranged on an upper arm and a lower arm, corresponding to the number of phases of the AC power to be output, and these legs are connected in parallel to each other to form a bridge circuit. In the example of FIG. 1, since the motor 900 is a three-phase AC motor, the power conversion device 200 outputs three-phase AC power to the motor 900. Therefore, the inverter circuit 300 is provided with legs for three phases.

[0013] The power conversion device 200 also includes a voltage sensor 10 that measures the voltage of DC power supplied from the high-voltage battery 901, and a current sensor 20 that measures the current of AC power output to the motor 900. The controller 100a generates a drive signal (PWM signal) in response to a command from a higher-level controller based on the voltage value of DC power and the current value of AC power measured by the voltage sensor 10 and the current sensor 20, respectively, and outputs the drive signal to the driver 100b. The driver 100b has a plurality of drive circuits 50 provided for each power semiconductor element of the inverter circuit 300, and each drive circuit 50 controls the switching of each power semiconductor element of the corresponding upper arm or lower arm. This causes the inverter circuit 300 to operate, and the DC power supplied from the high-voltage battery 901 is converted into AC power.

[0014] The voltage smoothing capacitor 500 is connected between the high-voltage battery 901 and the inverter circuit 300, and smoothes the applied voltage of the inverter circuit 300 that fluctuates during power conversion. The voltage across the voltage smoothing capacitor 500 is measured by the voltage sensor 10 as the applied voltage from the high-voltage battery 901 to the inverter circuit 300.

[0015] Next, the drive circuit 50 will be described in detail below with reference to the drawings.

[0016] Fig. 2 is a circuit block diagram showing the main configuration of a semiconductor driving device according to an embodiment of the present invention. The circuit block diagram of Fig. 2 shows the circuit configuration of the main parts of a drive circuit 50 that drives a power semiconductor element T1, which is one of a plurality of power semiconductor elements (e.g., the upper arm of the U phase) that constitutes an inverter circuit 300, as a semiconductor driving device according to an embodiment of the present invention. Note that, although this circuit block diagram shows an example in which the power semiconductor element T1 is configured with a MOSFET, other types of semiconductor elements, such as an IGBT, may also be used.

[0017] As shown in Fig. 1, the power semiconductor element T1 constitutes the inverter circuit 300, and turns on and off the direct current supplied from the high-voltage battery 901 to the inverter circuit 300 in response to the control of the drive circuit 50. Although only one power semiconductor element T1 connected to the drive circuit 50 is shown in Fig. 2, a plurality of power semiconductor elements may be connected in parallel for the purpose of increasing the current capacity, etc. Also, while Fig. 2 shows only a circuit for one arm in one phase as a representative, the present invention can be applied to both the upper and lower arms. Also, the present invention can be applied to each of the UVW phases.

[0018] The drive circuit 50 includes a gate drive unit 51 , a delay unit 52 , and a speed switching unit 53 .

[0019] The gate driver 51 is a circuit that controls a gate voltage applied to a gate terminal, which is a control terminal of the power semiconductor element T1. The gate driver 51 is configured by combining a gate drive IC that outputs a gate voltage in response to a drive signal input from the controller 100a, for example, with its peripheral components.

[0020] The delay unit 52 is a circuit that outputs a switching signal to the speed switching unit 53 to increase the switching speed of the power semiconductor element T1 at a timing delayed by a predetermined delay time from the start of turning off of the power semiconductor element T1 when the gate voltage output from the gate driving unit 51 is an off command for turning off the power semiconductor element T1.

[0021] The speed switching unit 53 is a circuit that, upon receiving a switching signal from the delay unit 52, switches the switching speed of the power semiconductor element T1 so as to increase the switching speed of the power semiconductor element T1.

[0022] The delay unit 52 and the speed switching unit 53 may be realized as functions of a gate drive IC present in the gate drive unit 51, or may be provided in the drive circuit 50 as circuits independent of the gate drive IC.

[0023] Specific examples of the circuit configuration of the drive circuit 50 will be described below with reference to the first to third embodiments.

[0024] (First embodiment) 3 is a diagram showing a circuit configuration of a drive circuit 50 according to a first embodiment of the present invention. The drive circuit 50 of this embodiment includes an integrated circuit IC1 that functions as a gate driver 51 and a delay unit 52, a switching element T2, a turn-on gate resistor Rgon, turn-off gate resistors Rgoff1 and Rgoff2, and a resistor R2.

[0025] The integrated circuit IC1 incorporates a gate control function of the power semiconductor element T1 corresponding to the above-mentioned gate driver 51, and a delay function corresponding to the delay unit 52. The integrated circuit IC1 has a drive signal input terminal PWM to which a drive signal (PWM signal) output from the controller 100a is input, a power supply terminal VCC2 to which a power supply voltage VCC is input, a signal terminal OUT1H to output an ON command for turning on the power semiconductor element T1, a signal terminal OUT1L to output an OFF command for turning off the power semiconductor element T1, a signal terminal OUT2L to output a switching signal for switching the gate resistance value while the power semiconductor element T1 is turned off to increase the switching speed of the power semiconductor element T1, and a ground terminal GND2 connected to a ground potential.

[0026] The ON command output from the signal terminal OUT1H of the integrated circuit IC1 is input to the gate terminal of the power semiconductor element T1 via the turn-on gate resistor Rgon. In response to the input of this ON command, the power semiconductor element T1 turns on, and conduction occurs between the drain terminal, which is the main terminal, and the source terminal.

[0027] The OFF command output from the signal terminal OUT1L of the integrated circuit IC1 is input to the gate terminal of the power semiconductor element T1 via the turn-off gate resistor Rgoff1. In response to the input of this OFF command, the power semiconductor element T1 turns off, cutting off the connection between the drain terminal, which is the main terminal, and the source terminal.

[0028] The turn-off gate resistor Rgoff2 is a gate resistor for increasing the switching speed of the power semiconductor element T1, with one end connected between the gate terminal of the power semiconductor element T1 and the turn-off gate resistor Rgoff1, and the other end connected to the ground potential via the switching element T2. The switching element T2 is an element for switching the conductive state of the turn-off gate resistor Rgoff2, and for example, a bipolar transistor or a MOSFET is used as the switching element T2. A resistor R2 is provided between the switching element T2 and the integrated circuit IC1, and the resistor R2, the turn-off gate resistor Rgoff2, and the switching element T2 constitute the speed switching unit 53 described above.

[0029] The integrated circuit IC1 outputs an OFF command from the signal terminal OUT1L, and then outputs a switching signal from the signal terminal OUT2L at a timing delayed by a predetermined delay time. When the switching element T2 turns on in response to the output of the switching signal from the signal terminal OUT2L, the turn-off gate resistor Rgoff2 is electrically connected in parallel with the turn-off gate resistor Rgoff1 between the integrated circuit IC1 and the gate terminal of the power semiconductor element T1.

[0030] Next, the operation of the power semiconductor element T1 when it is turned off will be described with reference to Fig. 4. Fig. 4 is a time chart showing an example of the change in each signal when the power semiconductor element T1 is turned off in the case where the drive circuit 50 according to the first embodiment of the present invention is applied.

[0031] First, when the power semiconductor element T1 is in the ON state, the signal terminals OUT1L and OUT2L of the integrated circuit IC1 are each in a high impedance state (Hi-Z), and neither an OFF command nor a switching signal is output from these signal terminals. In this state, when a drive signal (PWM signal) corresponding to a turn-off command for the power semiconductor element T1 is input from the controller 100a to the integrated circuit IC1, the integrated circuit IC1 outputs an OFF command to the power semiconductor element T1 at time t0 by changing the voltage of the signal terminal OUT1L to the L level.

[0032] When the OFF command output from the signal terminal OUT1L is input to the gate terminal of the power semiconductor element T1, the power semiconductor element T1 starts to turn off, and the gate voltage Vgs starts to gradually decrease. Then, when the gate voltage Vgs becomes equal to or lower than a predetermined value, the drain-source voltage Vds of the power semiconductor element T1 starts to rise and the drain current Id starts to decrease. At this time, since the switching element T2 is off, the turn-off gate resistor Rgoff2 is not electrically connected to the gate terminal of the power semiconductor element T1. Therefore, a current flows to the gate terminal of the power semiconductor element T1 only through the turn-off gate resistor Rgoff1, and the power semiconductor element T1 is turned off at a switching speed according to the resistance value of the turn-off gate resistor Rgoff1.

[0033] Thereafter, at time t1 when a predetermined delay time τ has elapsed since time t0, the integrated circuit IC1 changes the voltage of the signal terminal OUT2L to the L level, thereby outputting a switching command to the switching element T2.

[0034] When the switching command output from the signal terminal OUT2L is input to the base (gate) terminal of the switching element T2, the switching element T2 is switched from OFF to ON. As a result, the turn-off gate resistor Rgoff2 is electrically connected to the gate terminal of the power semiconductor element T1 in parallel with the turn-off gate resistor Rgoff1. Therefore, a current flows to the gate terminal of the power semiconductor element T1 through both the turn-off gate resistors Rgoff1 and Rgoff2, and the power semiconductor element T1 is turned off at a switching speed according to the combined resistance value of the turn-off gate resistors Rgoff1 and Rgoff2. That is, since the combined resistance value of the turn-off gate resistors Rgoff1 and Rgoff2 is lower than the resistance value of the turn-off gate resistor Rgoff1 alone, the switching speed of the power semiconductor element T1 is increased after time t1.

[0035] Thereafter, when the gate voltage Vgs becomes 0 at time t2, the turn-off of the power semiconductor element T1 is completed, and the drain current Id becomes 0. Incidentally, just before time t2 when the turn-off of the power semiconductor element T1 is completed, a surge voltage occurs that temporarily increases the drain-source voltage Vds.

[0036] As described above, when the drive circuit 50 of this embodiment is used, the switching speed at the time of turning off the power semiconductor element T1 can be increased halfway, so that it is possible to reduce switching loss compared to the case where this is not applied. Such a reduction effect of switching loss is particularly noticeable when the turn-off time of the power semiconductor element T1 is relatively long, for example, at low current or high temperature. Therefore, by applying the drive circuit 50 of this embodiment, it is possible to sufficiently obtain the effect of reducing switching loss even when the turn-off time of the power semiconductor element T1 is long.

[0037] When the drive circuit 50 of this embodiment is applied, the surge voltage that appears in the drain-source voltage Vds of the power semiconductor element T1 just before the turn-off is completed as described above is higher than when the switching speed is not increased halfway through. However, since the original surge voltage is low when the turn-off time of the power semiconductor element T1 is long at low current or high temperature as described above, even if the drive circuit 50 of this embodiment is applied under such conditions, adverse effects due to an increase in the surge voltage are unlikely to occur.

[0038] Next, the effect of applying the present invention will be described with reference to FIG. 5 and FIG.

[0039] Fig. 5 is a diagram showing an example of the relationship between the main current and switching characteristics of the power semiconductor element T1. In Fig. 5(a), graphs 501 and 502 respectively show the relationship between the main current Id and the turn-off time toff of the power semiconductor element T1, and in Fig. 5(b), graphs 511 and 512 respectively show the relationship between the main current Id and the turn-off loss Eoff of the power semiconductor element T1. In these diagrams, the dashed graphs 501 and 511 show the switching characteristics of the power semiconductor element T1 by conventional switching control when the present invention is not applied, and the solid graphs 502 and 512 show the switching characteristics of the power semiconductor element T1 by switching control when the present invention is applied.

[0040] As shown in graphs 501 and 502 in Fig. 5(a), the smaller the main current Id is, the longer the turn-off time toff is. In addition, if the value of the main current Id at the time when the above-mentioned delay time τ has elapsed from the start of turn-off is Iτ, the turn-off time toff is shortened by applying the present invention when the main current Id is smaller than this current value Iτ. In other words, since the present invention increases the switching speed of the power semiconductor element T1 after the delay time τ has elapsed, it can be seen that the turn-off time toff can be shortened under the condition that the turn-off time toff is longer than the delay time τ.

[0041] Furthermore, as shown in graphs 511 and 512 in Fig. 5(b), the smaller the main current Id is, the smaller the turn-off loss Eoff is. Moreover, by applying the present invention when the main current Id is smaller than the above-mentioned current value Iτ at the delay time τ, the turn-off time toff is shortened, and the turn-off loss Eoff is thereby reduced. That is, in the present invention, the switching speed of the power semiconductor element T1 is increased after the delay time τ has elapsed, and therefore it is understood that the turn-off loss Eoff can be reduced under the condition that the turn-off time toff is longer than the delay time τ.

[0042] Fig. 6 is a diagram showing an example of the relationship between the junction temperature and the switching characteristics of the power semiconductor element T1. In Fig. 6(a), graphs 601 and 602 respectively show the relationship between the junction temperature Tj and the turn-off time toff of the power semiconductor element T1, and in Fig. 6(b), graphs 611 and 612 respectively show the relationship between the junction temperature Tj and the turn-off loss Eoff of the power semiconductor element T1. In these diagrams, the dashed graphs 601 and 611 show the switching characteristics of the power semiconductor element T1 by conventional switching control when the present invention is not applied, and the solid graphs 602 and 612 show the switching characteristics of the power semiconductor element T1 by switching control when the present invention is applied.

[0043] As shown in graphs 601 and 602 in Fig. 6(a), the higher the junction temperature Tj, the longer the turn-off time toff. In addition, if the value of the junction temperature Tj at the time when the above-mentioned delay time τ has elapsed from the start of turn-off is Tτ, the turn-off time toff is shortened by applying the present invention when the junction temperature Tj is higher than this temperature Tτ. In other words, since the present invention increases the switching speed of the power semiconductor element T1 after the delay time τ has elapsed, it can be seen that the turn-off time toff can be shortened under the condition that the turn-off time toff is longer than the delay time τ.

[0044] Furthermore, as shown in graphs 611 and 612 in Fig. 6(b), the lower the junction temperature Tj, the smaller the turn-off loss Eoff. Also, by applying the present invention when the junction temperature Tj is higher than the above-mentioned temperature Tτ at the delay time τ, the turn-off time toff is shortened, and the turn-off loss Eoff is reduced. That is, in the present invention, the switching speed of the power semiconductor element T1 is increased after the delay time τ has elapsed, and therefore it is understood that the turn-off loss Eoff can be reduced under the condition that the turn-off time toff is longer than the delay time τ.

[0045] In practice, it is preferable to consider a region in which it is desired to exert a switching loss reduction effect based on the switching characteristics of the power semiconductor element T1, and set the delay time τ accordingly.

[0046] Second Embodiment Fig. 7 is a diagram showing a circuit configuration of a drive circuit 50 according to a second embodiment of the present invention. The drive circuit 50 of this embodiment differs from the circuit configuration of Fig. 3 described in the first embodiment in that a delay unit 52 is provided separately from the integrated circuit IC1.

[0047] In this embodiment, the delay unit 52 outputs a switching command to the switching element T2 when a predetermined delay time τ has elapsed since the OFF command was output from the signal terminal OUT1L, similar to the switching signal from the signal terminal OUT2L described in the first embodiment. When the switching element T2 is switched from OFF to ON in response to this switching command, the turn-off gate resistor Rgoff2 is electrically connected to the gate terminal of the power semiconductor element T1 in parallel with the turn-off gate resistor Rgoff1, and the switching speed of the power semiconductor element T1 is increased. The delay unit 52 can be realized by any circuit configuration generally used as a delay circuit, such as an integrating circuit combining a resistor and a capacitor, or a circuit using a comparator.

[0048] (Third embodiment) Fig. 8 is a diagram showing a circuit configuration of a drive circuit 50 according to a third embodiment of the present invention. The drive circuit 50 of this embodiment differs from the circuit configuration of Fig. 3 described in the first embodiment in that a speed switching unit 53 further includes a resistor R1 and diodes D1 and D2.

[0049] The resistor R1 and the diodes D1 and D2 function as a disabling circuit that disables the operation of the speed switching unit 53 in response to the drain-source voltage Vds of the power semiconductor element T1. Generally, the drive circuit 50 is provided with a detection circuit for the drain-source voltage Vds of the power semiconductor element T1 as a circuit for realizing a DESAT type short-circuit protection function that protects the power semiconductor element T1 from an overcurrent caused by a short circuit. The above-mentioned disabling circuit may be configured using a part of this detection circuit.

[0050] When a switching signal is output from the signal terminal OUT2L of the integrated circuit IC1, if the drain-source voltage Vds of the power semiconductor element T1 becomes equal to or greater than a predetermined value, the power supply voltage VCC is input to the base (gate) terminal of the switching element T2 via the resistor R1 and the diode D2. As a result, the switching element T2, which was switched from off to on by the switching signal, is switched off again, and the operation of the speed switching unit 53 is disabled.

[0051] Next, the operation of the power semiconductor element T1 when it is turned off will be described with reference to Fig. 9. Fig. 9 is a time chart showing an example of how each signal changes when the power semiconductor element T1 is turned off in the case where the drive circuit 50 according to the third embodiment of the present invention is applied.

[0052] In FIG. 9, between time t0 and time t2, the same operations as those in FIG. 4 described in the first embodiment are performed.

[0053] Now, let us assume that some kind of abnormality causes the delay time τ to become shorter than the set value. In this case, the switching speed is increased at an earlier stage than expected, and if this continues, as shown by dotted line A in Figure 9, the drain-source voltage Vds will increase significantly before turn-off is complete, causing the surge voltage to become excessive and exceeding the withstand voltage.

[0054] In the drive circuit 50 of this embodiment, as shown in FIG. 8, a disabling circuit of the resistor R1 and the diodes D1 and D2 is provided in the speed switching unit 53. In this disabling circuit, when the drain-source voltage Vds becomes equal to or greater than a predetermined value at time t2, a current flows from the power supply voltage VCC to the diode D2 via the resistor R1, and the output voltage Vdesat of the diode D2 rises. As a result, regardless of the output of the switching signal from the signal terminal OUT2L, the switching element T2 is switched from on to off, disabling the operation of the speed switching unit 53, and the switching speed of the power semiconductor element T1 returns to the state before time t1. Therefore, as shown by the solid line B in FIG. 9, the change in the drain-source voltage Vds can be suppressed, and the occurrence of a surge voltage can be suppressed.

[0055] As described above, when the drive circuit 50 of this embodiment is used, it is possible to suppress the surge voltage while obtaining a sufficient effect of reducing switching loss, even if the delay time τ becomes shorter for some reason.

[0056] According to each of the embodiments of the present invention described above, the following advantageous effects are achieved.

[0057] (1) A drive circuit 50, which is a semiconductor drive device, includes a gate drive unit 51 that controls a gate voltage applied to a control terminal (gate terminal) of a power semiconductor element T1 and turns on and off the power semiconductor element T1 to switch the power semiconductor element T1, and a speed changeover unit 53 that changes the switching speed so as to increase the switching speed of the power semiconductor element T1 at a timing delayed by a predetermined delay time τ from the start of turning off the power semiconductor element T1. As a result, an active gate control method that can sufficiently obtain the effect of reducing switching losses can be realized even when the turn-off time of the power semiconductor element T1 is long.

[0058] (2) The drive circuit 50 further includes a turn-off gate resistor Rgoff1 that is electrically connected to the gate terminal when the power semiconductor element T1 starts to turn off. The speed switching unit 53 also includes a turn-off gate resistor Rgoff2 that is electrically connected to the gate terminal of the power semiconductor element T1 in parallel with the turn-off gate resistor Rgoff1 at a timing delayed by a predetermined delay time τ from the start of turn-off of the power semiconductor element T1. This makes it possible to reliably switch the switching speed and increase the switching speed of the power semiconductor element T1.

[0059] (3) The drive circuit 50 further includes a delay unit 52 that outputs a predetermined switching signal after a delay time τ from the start of turn-off of the power semiconductor element T1. The speed switching unit 53 has a switching element T2 that is turned on in response to the switching signal output from the delay unit 52, and the turn-off gate resistor Rgoff2 is electrically connected to the gate terminal of the power semiconductor element T1 via the switching element T2. This makes it possible to reliably switch the switching speed at a timing delayed by the predetermined delay time τ from the start of turn-off of the power semiconductor element T1.

[0060] (4) The speed switching unit 53 may have a disabling circuit composed of the resistor R1 and the diodes D1 and D2 shown in Fig. 8, and by using this disabling circuit, the switching element T2 may be switched from on to off when the voltage Vds between the main terminals of the power semiconductor element T1 becomes equal to or higher than a predetermined value. In this way, if the drain-source voltage Vds rises too quickly when the power semiconductor element T1 is turned off, the operation of the speed switching unit 53 is disabled, the switching speed is returned to its original value, and the surge voltage can be suppressed.

[0061] The present invention is not limited to the above-described embodiment, and other embodiments that are within the scope of the technical concept of the present invention are also included in the scope of the present invention as long as they do not impair the characteristics of the present invention. Also, the above-described embodiment may be combined with a number of modified examples. [Explanation of symbols]

[0062] 10: voltage sensor, 20: current sensor, 50: drive circuit, 51: gate drive unit, 52: delay unit, 53: speed switching unit, 100a: controller, 100b: driver, 200: power conversion device, 300: inverter circuit, 500: voltage smoothing capacitor, 900: motor, 901: high voltage battery, T1: power semiconductor element, T2: switching element, Rgon: turn-on gate resistor, Rgoff1, Rgoff2: turn-off gate resistors, R1, R2: resistors, D1, D2: diodes

Claims

1. a gate driver for controlling a voltage applied to a control terminal of a power semiconductor device to turn on and off the power semiconductor device, thereby switching the power semiconductor device; A speed switching unit that switches the switching speed so as to increase the switching speed of the power semiconductor element at a timing delayed by a predetermined delay time from the start of turn-off of the power semiconductor element. Semiconductor drive device.

2. a first resistor portion electrically connected to the control terminal when the power semiconductor element starts to turn off; The speed switching unit has a second resistor unit that is electrically connected to the control terminal in parallel with the first resistor unit at a timing delayed by a predetermined delay time from the start of turn-off of the power semiconductor element.

2. The semiconductor driving device according to claim 1.

3. a delay unit that outputs a predetermined switching signal after the delay time from the start of turning off the power semiconductor element, the speed switching unit has a switching element that is turned on in response to the switching signal output from the delay unit, The second resistor portion is electrically connected to the control terminal via the switching element.

3. The semiconductor driving device according to claim 2.

4. The speed changeover unit changes the switching element from on to off when a voltage between main terminals of the power semiconductor element becomes equal to or higher than a predetermined value.

4. The semiconductor driving device according to claim 3.

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