Electronic component

Abstract

To provide an electronic component capable of improving a voltage resistance.SOLUTION: An electronic component 1 comprises: a substrate 2; a plurality of laminated capacitors 10 mounted onto a first main surface 2a of the substrate 2; and a sealing part 11 that is formed of a resin and seals the plurality of laminated capacitors 10. A first external electrode 13 and a second external electrode 14 of each laminated capacitor 10 are mounted by a solder H to the substrate 2, and at least one part of the adjacent laminated capacitors 10 are overlapped in view from a direction along the first main surface 2a of the substrate 2, the direction being an opposite direction of a pair of side surfaces 12e and 12f of an element 12. In the adjacent laminated capacitors 10, lamination directions of a plurality of internal electrodes 15A and 15B are the same, and a distance between the adjacent laminated capacitors 10 is 1 / 2 a height of each laminated capacitor 10 mounted onto the substrate 2.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to electronic components. [Background technology]

[0002] There is known an electronic component that includes a substrate and a plurality of multilayer capacitors mounted on the substrate (see, for example, Patent Document 1). The plurality of multilayer capacitors are used, for example, for smoothing purposes, and are arranged side by side on the substrate. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2023-101721 A Summary of the Invention [Problem to be solved by the invention]

[0004] Multilayer capacitors may undergo electrostrictive deformation when a voltage is applied. In multilayer capacitors, electrostrictive deformation generates stress in the element body, which may damage the element body. In multilayer capacitors, the electrostrictive deformation increases as the voltage applied increases. For this reason, in electronic components, the voltage that can be applied to multilayer capacitors is limited, and high voltages cannot be applied.

[0005] An object of one aspect of the present invention is to provide an electronic component that can improve the withstand voltage. [Means for solving the problem]

[0006] (1) An electronic component according to one aspect of the present invention comprises a substrate, a plurality of multilayer capacitors mounted on a mounting surface of the substrate, and a sealing portion formed of resin and sealing the plurality of multilayer capacitors, each of the plurality of multilayer capacitors comprises an element body formed by stacking a plurality of dielectric layers and having a pair of end faces and four side faces connecting the pair of end faces, an external electrode disposed on the element body, and a plurality of internal electrodes disposed within the element body and opposed in a stacking direction of the plurality of dielectric layers, the external electrodes of the multilayer capacitor are mounted on the substrate by solder, adjacent multilayer capacitors at least partially overlap when viewed in a direction in which the pair of side faces of the element body face each other and along the mounting surface of the substrate, the stacking directions of the multiple internal electrodes in adjacent multilayer capacitors are the same, and the distance between adjacent multilayer capacitors is equal to or less than half the height of the multilayer capacitor mounted on the substrate.

[0007] An electronic component according to one aspect of the present invention includes a sealing portion that seals a plurality of multilayer capacitors. As a result, in the electronic component, the sealing portion can suppress electrostrictive deformation of the multilayer capacitors. Also, in the electronic component, the multilayer capacitors are mounted (joined) to a substrate by solder. Therefore, in the electronic component, the multilayer capacitors are firmly joined to the substrate, and electrostrictive deformation of the multilayer capacitors can be suppressed.

[0008] In electronic components, when electrostrictive deformation occurs in a multilayer capacitor, the side of the element body is deformed. Specifically, the element body expands in the stacking direction due to electrostrictive deformation, and as a result, the side faces facing in the stacking direction are deformed (curved) in a convex shape. Also, the side faces facing in a direction perpendicular to the stacking direction are deformed in a concave shape toward the inside of the element body. In view of such a phenomenon, in electronic components, when viewed from the opposing direction of a pair of side faces of the element body and along the mounting surface of the board, at least a part of adjacent multilayer capacitors overlap, and the stacking directions of adjacent multilayer capacitors are the same. Also, in electronic components, the distance between adjacent multilayer capacitors is 1 / 2 or less of the height of the multilayer capacitor mounted on the board. In addition, in electronic components, a plurality of multilayer capacitors are sealed by a sealing portion. The sealing portion is filled between adjacent multilayer capacitors.

[0009] As a result, when a voltage is applied to the multilayer capacitor, in each of the adjacent multilayer capacitors, a force pressing the sealing portion due to expansion acts, or a force pulling the sealing portion toward the multilayer capacitor acts. In the electronic component, since the stacking direction of the adjacent multilayer capacitors is the same, the directions of the above-mentioned forces acting on the adjacent multilayer capacitors are opposite. Therefore, the adjacent multilayer capacitors can be prevented from deforming each other. Therefore, in the electronic component, electrostrictive deformation of the multilayer capacitor can be prevented, making it possible to apply a high voltage. As a result, the withstand voltage of the electronic component can be improved.

[0010] (2) In the electronic component of (1) above, the plurality of multilayer capacitors have the same configuration, shape, and dimensions, and are arranged so as to overlap when viewed in the direction in which a pair of side surfaces of the element body face each other and along the mounting surface of the substrate. In this configuration, forces in opposite directions effectively act on adjacent multilayer capacitors. Therefore, in the electronic component, the adjacent multilayer capacitors can be more reliably prevented from deforming relative to each other.

[0011] (3) In the electronic component of (1) or (2) above, the multilayer capacitor may be arranged so that the lamination direction of the multiple internal electrodes is perpendicular to the mounting surface. In this configuration, when a voltage is applied to the multilayer capacitor, a force acts on each of the adjacent multilayer capacitors to pull the sealing portion toward the multilayer capacitor. In the electronic component, since the lamination direction of adjacent multilayer capacitors is the same, the directions of the above-mentioned forces acting on the adjacent multilayer capacitors are opposite. Therefore, the adjacent multilayer capacitors can be prevented from deforming relative to each other.

[0012] (4) In any one of the electronic components (1) to (3) above, the number of laminated dielectric layers of the multilayer capacitor may be 100 or more, and the length of the element body in the lamination direction may be 1.0 mm or more. In this configuration, electrostrictive deformation is likely to occur in the multilayer capacitor. Therefore, in the case of such a multilayer capacitor, the above configuration is particularly effective in improving the withstand voltage.

[0013] (5) In the electronic component of any one of (1) to (4) above, the distance between the mounting surface of the substrate and the element body of the multilayer capacitor facing the mounting surface may be 0.2 mm or less, and a sealing portion may be disposed between the mounting surface and the element body. In this configuration, the entire multilayer capacitor is covered by the sealing portion, so that electrostrictive deformation in the multilayer capacitor can be further suppressed.

[0014] (6) In the electronic component according to any one of (1) to (6) above, the sealing portion may be made of a silicone resin or an epoxy resin. With this configuration, electrostrictive deformation in the multilayer capacitor can be effectively suppressed.

[0015] (7) In any one of the electronic components (1) to (6) above, the height of the sealing portion from the mounting surface may be at least twice the height of the multilayer capacitors mounted on the mounting surface. With this configuration, the sealing portion can effectively suppress electrostrictive deformation of the multiple multilayer capacitors. Effect of the Invention

[0016] According to one aspect of the present invention, the withstand voltage can be improved. [Brief description of the drawings]

[0017] [Figure 1] FIG. 1 is a perspective view showing an electronic component. [Diagram 2] FIG. 2 is a top view of the electronic component. [Diagram 3] FIG. 3 is a side view of the electronic component. [Figure 4] FIG. 4 is a perspective view of the multilayer capacitor. [Diagram 5] FIG. 5 is an exploded perspective view of the multilayer capacitor. [Figure 6] FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. [Figure 7] FIG. 7 is a side view of the multilayer capacitor. [Figure 8] FIG. 8 is a cross-sectional view of an electronic component according to another embodiment. [Figure 9] FIG. 9 is a top view of an electronic component according to another embodiment. [Figure 10] FIG. 10 is a top view of an electronic component according to another embodiment. [Figure 11] FIG. 11 is a top view of an electronic component according to another embodiment. [Figure 12] FIG. 12 is a top view of an electronic component according to another embodiment. [Figure 13] FIG. 13 is a top view of an electronic component according to another embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0018] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the description of the drawings, the same or corresponding elements are designated by the same reference numerals, and duplicated explanations will be omitted.

[0019] An electronic component 1 will be described with reference to Figures 1 to 3. Figure 1 is a perspective view of the electronic component according to one embodiment. Figure 2 is a top view of the electronic component. Figure 3 is a side view of the electronic component.

[0020] As shown in Fig. 1 to Fig. 3, electronic component 1 includes substrate 2, a plurality of multilayer capacitors 10, and sealing portion 11. Electronic component 1 may include terminal electrodes. For ease of explanation, a first direction D1, a second direction D2, and a third direction D3 are defined in Fig. 1. In Fig. 2, sealing portion 11 is omitted. In Fig. 3, sealing portion 11 is indicated by a two-dot chain line.

[0021] The substrate 2 is, for example, a PCB (Printed Circuit Board). The substrate 2 has a first main surface 2a, a second main surface 2b facing the first main surface 2a, and a side surface 2c connecting the first main surface 2a and the second main surface 2b. The substrate 2 has, for example, a rectangular shape when viewed from the opposing direction of the first main surface 2a and the second main surface 2b (third direction D3). The first main surface 2a is a mounting surface on which a plurality of multilayer capacitors 10 are mounted. The second main surface 2b constitutes the lower surface (bottom surface) of the electronic component 1. The side surface 2c constitutes the side surface of the electronic component 1.

[0022] 2, the substrate 2 is provided with a first land electrode 3, a second land electrode 4, a third land electrode 5, a fourth land electrode 6, a fifth land electrode 7, and a sixth land electrode 8. The first land electrode 3, the second land electrode 4, the third land electrode 5, the fourth land electrode 6, the fifth land electrode 7, and the sixth land electrode 8 each have, for example, a rectangular shape.

[0023] The first land electrode 3, the second land electrode 4, the third land electrode 5, the fourth land electrode 6, the fifth land electrode 7, and the sixth land electrode 8 are arranged on the first main surface 2a of the substrate 2. The first land electrode 3 and the second land electrode 4 are arranged at a predetermined interval in the second direction D2. The third land electrode 5 and the fourth land electrode 6 are arranged at a predetermined interval in the second direction D2. The fifth land electrode 7 and the sixth land electrode 8 are arranged at a predetermined interval in the second direction D2.

[0024] The first land electrode 3, the third land electrode 5, and the fifth land electrode 7 are arranged at a predetermined interval in the first direction D1. The second land electrode 4, the fourth land electrode 6, and the sixth land electrode 8 are arranged at a predetermined interval in the first direction D1.

[0025] Fig. 4 is a perspective view of the multilayer capacitor 10. Fig. 5 is an exploded perspective view of the multilayer capacitor 10. As shown in Figs. 4 and 5, the multilayer capacitor 10 includes an element body 12, a first external electrode 13, a second external electrode 14, and a plurality of internal electrodes 15A, 15B. In the following description, the three multilayer capacitors 10 may be distinguished and described as a multilayer capacitor 10A, a multilayer capacitor 10B, and a multilayer capacitor 10C. In this embodiment, the multilayer capacitor 10A, the multilayer capacitor 10B, and the multilayer capacitor 10C have the same configuration, shape, and dimensions.

[0026] The element body 12 has a rectangular parallelepiped shape. The rectangular parallelepiped shape includes a rectangular parallelepiped shape with chamfered corners and ridges, and a rectangular parallelepiped shape with rounded corners and ridges. The element body 12 has, as outer surfaces, a pair of end faces 12a, 12b, a pair of main faces (side faces) 12c, 12d, and a pair of side faces 12e, 12f. The end faces 12a, 12b face each other. The main faces 12c, 12d face each other. The side faces 12e, 12f face each other. The main face 12d is a mounting surface, and is a surface that faces the substrate 2 (first main face 2a) when the multilayer capacitor 10 is mounted on the substrate 2, for example.

[0027] As shown in FIG. 5, the element body 12 is configured by stacking a plurality of dielectric layers 16. In this embodiment, the element body 12 is configured by stacking, for example, 100 or more dielectric layers 16. The stacking direction of the dielectric layers 16 is the opposing direction of the pair of main surfaces 12c, 12d of the element body 12. Each dielectric layer 16 is configured by, for example, a sintered body of a ceramic green sheet containing a dielectric material. The dielectric material includes, for example, a BaTiO3-based, Ba(Ti,Zr)O3-based, or (Ba,Ca)TiO3-based dielectric ceramic. In the actual element body 12, each dielectric layer 16 is integrated to such an extent that the boundaries between the dielectric layers 16 are not visible.

[0028] The first external electrode 13 is arranged on one end face 12a of the element body 12. The second external electrode 14 is arranged on the other end face 12b of the element body 12. The first external electrode 13 is arranged on the end face 12a of the element body 12, parts of the main faces 12c and 12d, and parts of the side faces 12e and 12f. The second external electrode 14 is arranged on the end face 12b of the element body 12, parts of the main faces 12c and 12d, and parts of the side faces 12e and 12f.

[0029] The first external electrode 13 and the second external electrode 14 are made of a conductive material (for example, Ni or Cu). A plating layer may be formed on the surface of the first external electrode 13 and the second external electrode 14. The plating layer may have a layer structure made of a Cu plating layer, a Ni plating layer, and a Sn plating layer, or a layer structure made of a Ni plating layer and a Sn plating layer.

[0030] The internal electrodes 15A, 15B are arranged in the element body 12. A plurality of the internal electrodes 15A, 15B are arranged. The plurality of internal electrodes 15A are connected to the first external electrode 13. The plurality of internal electrodes 15B are connected to the second external electrode 14. The internal electrodes 15A, 15B are made of a conductive material (such as Ni or Cu). Note that, although seven internal electrodes 15A, 15B are shown in FIG. 7 as an example, the number of the internal electrodes 15A, 15B is not limited to this.

[0031] 2, the multilayer capacitor 10A is disposed on a first land electrode 3 and a second land electrode 4. Specifically, a first external electrode 13 of the multilayer capacitor 10A is disposed on the first land electrode 3, and a second external electrode 14 of the multilayer capacitor 10A is disposed on the second land electrode 4. The first external electrode 13 and the first land electrode 3 are joined by solder H. The second external electrode 14 and the second land electrode 4 are joined by solder H.

[0032] The multilayer capacitor 10B is disposed on the third land electrode 5 and the fourth land electrode 6. Specifically, the first external electrode 13 of the multilayer capacitor 10B is disposed on the third land electrode 5, and the second external electrode 14 of the multilayer capacitor 10B is disposed on the fourth land electrode 6. The first external electrode 13 and the third land electrode 5 are joined by solder H. The second external electrode 14 and the fourth land electrode 6 are joined by solder H.

[0033] The multilayer capacitor 10C is disposed on a fifth land electrode 7 and a sixth land electrode 8. Specifically, a first external electrode 13 of the multilayer capacitor 10C is disposed on the fifth land electrode 7, and a second external electrode 14 of the multilayer capacitor 10C is disposed on the sixth land electrode 8. The first external electrode 13 and the fifth land electrode 7 are joined by solder H. The second external electrode 14 and the sixth land electrode 8 are joined by solder H.

[0034] The first land electrode 3, the third land electrode 5, and the fifth land electrode 7 may be one component (member). That is, the first external electrodes 13 of the multilayer capacitor 10A, the multilayer capacitor 10B, and the multilayer capacitor 10C may be disposed on one land electrode. The second land electrode 4, the fourth land electrode 6, and the sixth land electrode 8 may be one component. That is, the second external electrodes 14 of the multilayer capacitor 10A, the multilayer capacitor 10B, and the multilayer capacitor 10C may be disposed on one land electrode.

[0035] In addition, the first land electrode 3, the second land electrode 4, the third land electrode 5, the fourth land electrode 6, the fifth land electrode 7, and the sixth land electrode 8 may be embedded in the substrate 2. For example, the first land electrode 3, the second land electrode 4, the third land electrode 5, the fourth land electrode 6, the fifth land electrode 7, and the sixth land electrode 8 may be flush with the first main surface 2a of the substrate 2.

[0036] In this embodiment, the multilayer capacitor 10A, the multilayer capacitor 10B, and the multilayer capacitor 10C are arranged at the same position in the second direction D2. That is, the multilayer capacitor 10A, the multilayer capacitor 10B, and the multilayer capacitor 10C are aligned in the second direction D2. The multilayer capacitor 10A, the multilayer capacitor 10B, and the multilayer capacitor 10C overlap each other when viewed from the first direction D1 (the opposing direction of the pair of side surfaces 12f, 12e and along the first main surface 2a of the substrate 2). That is, none of the multilayer capacitor 10A, the multilayer capacitor 10B, and the multilayer capacitor 10C protrudes in the second direction D2 when viewed from the first direction D1 or the third direction D3.

[0037] 6, the multilayer capacitor 10A, the multilayer capacitor 10B, and the multilayer capacitor 10C have the same stacking direction of the internal electrodes 15A, 15B. The multilayer capacitor 10A, the multilayer capacitor 10B, and the multilayer capacitor 10C are arranged such that the stacking direction of the internal electrodes 15A, 15B is along the third direction D3. The multilayer capacitor 10A, the multilayer capacitor 10B, and the multilayer capacitor 10C are arranged such that the stacking direction of the internal electrodes 15A, 15B is perpendicular to the first main surface 2a of the substrate 2.

[0038] 2 and 3, the distance P1 between adjacent multilayer capacitors 10A and 10B is equal to or less than 1 / 2 (50%) of the height T1 of the multilayer capacitor 10 (P1≦H1 / 2). In this embodiment, the distance P1 is the distance between the element body 12 of the multilayer capacitor 10A and the element body 12 of the multilayer capacitor 10B.

[0039] The distance P2 between adjacent multilayer capacitors 10B and 10C is equal to or less than ½ the height T1 of the multilayer capacitor 10 (P2≦H1 / 2). In this embodiment, the distance P2 is the distance between the element body 12 of the multilayer capacitor 10B and the element body 12 of the multilayer capacitor 10C.

[0040] 3, in this embodiment, the height T1 of the multilayer capacitor 10 is the length of the element body 12 in the third direction D3 (the distance between the pair of main surfaces 12c, 12d). The height T1 of the multilayer capacitor 10 is the height of the multilayer capacitor 10 in a state where it is mounted on a substrate 2. The height T1 of the multilayer capacitor 10 is, for example, 1.0 mm or more. The height T1 of the multilayer capacitor 10 may be the length of a portion that is the maximum dimension in the third direction D3. For example, the height T1 of the multilayer capacitor 10 may be the length of the first external electrode 13 and the second external electrode 14 in the third direction D3.

[0041] 7, in this embodiment, a space S is formed between the first main surface 2a of the substrate 2 and the element body 12 of the multilayer capacitor 10. The distance P3 between the first main surface 2a of the substrate 2 and the element body 12 of the multilayer capacitor 10 is, for example, 0.2 mm or less, and preferably 0.1 mm or less.

[0042] As shown in FIG. 1, the sealing portion 11 seals (covers) a plurality of multilayer capacitors 10. The sealing portion 11 has, for example, a substantially rectangular parallelepiped shape. The sealing portion 11 is made of resin. The resin that can be used is generally a resin that is used for potting and molding. The resin is, for example, a silicone resin, an epoxy resin, or the like. The sealing portion 11 may or may not have transparency (it may be opaque).

[0043] The sealing portion 11 is provided to protect the multilayer capacitor 10. The sealing portion 11 has a function of suppressing electrostrictive deformation of the multilayer capacitor 10. The sealing portion 11 also has a function of suppressing the application of external forces to the multilayer capacitor 10, a function of electrically insulating the multilayer capacitor 10 from the outside, a function of protecting the multilayer capacitor 10 from dust, dirt, and the like.

[0044] The sealing portion 11 has a main surface 11a and four side surfaces 11b as outer surfaces. The main surface 11a constitutes the top surface of the electronic component 1. The four side surfaces 11b constitute the side surfaces of the electronic component 1.

[0045] 3, the height T2 of the sealing portion 11 (the distance between the first main surface 2a of the substrate 2 and the main surface 11a of the sealing portion 11) is at least twice the height T1 of the multilayer capacitor 10. As shown in Fig. 4, the sealing portion 11 is disposed (filled) in the space S between the first main surface 2a of the substrate 2 and the element body 12 of the multilayer capacitor 10.

[0046] As described above, the electronic component 1 according to this embodiment includes a sealing portion 11 that seals a plurality of multilayer capacitors 10. As a result, in the electronic component 1, the sealing portion 11 can suppress electrostrictive deformation of the multilayer capacitors 10. Furthermore, in the electronic component 1, the multilayer capacitors 10 are mounted (joined) to the substrate 2 with solder H. Therefore, in the electronic component 1, the multilayer capacitors 10 are firmly joined to the substrate 2, and electrostrictive deformation of the multilayer capacitors 10 can be suppressed.

[0047] In the electronic component 1, when electrostrictive deformation occurs in the multilayer capacitor 10, the main surfaces 12c, 12d and the side surfaces 12e, 12f of the element body 12 are deformed. Specifically, the element body 12 expands in the stacking direction of the internal electrodes 15A, 15B due to electrostrictive deformation, and the main surfaces 12c, 12d facing each other in the stacking direction are deformed (curved) in a convex shape. In addition, the side surfaces 12e, 12f facing each other in a direction perpendicular to the stacking direction are deformed in a concave shape toward the inside of the element body 12. In view of this phenomenon, in the electronic component 1, the adjacent multilayer capacitors 10 overlap each other when viewed from the first direction D1, and the stacking directions of the multiple internal electrodes 15A, 15B in the adjacent multilayer capacitors 10 are the same. In addition, in the electronic component 1, the distances P1, P2 between the adjacent multilayer capacitors 10 are equal to or less than ½ of the height T1 of the multilayer capacitor 10 mounted on the substrate 2. In the electronic component 1, a plurality of multilayer capacitors 10 are sealed with a sealing portion 11. The sealing portion 11 fills the gaps between adjacent multilayer capacitors 10.

[0048] In the electronic component 1 according to this embodiment, the multilayer capacitor 10 is arranged such that the lamination direction of the multiple internal electrodes 15A, 15B is perpendicular to the first main surface 2a (mounting surface) of the substrate 2. In this configuration, when a voltage is applied to the multilayer capacitor 10, a force acts on each of the adjacent multilayer capacitors 10, pulling the sealing portion 11 toward the multilayer capacitor 10. In the electronic component 1, since the lamination directions of the adjacent multilayer capacitors 10 are the same, the directions of the force acting on the adjacent multilayer capacitors 10 are opposite. Therefore, the adjacent multilayer capacitors 10 can be prevented from deforming each other. Therefore, in the electronic component 1, electrostrictive deformation of the multilayer capacitor 10 can be prevented, and a high voltage can be applied. As a result, the electronic component 1 can improve the withstand voltage.

[0049] In the electronic component 1 according to this embodiment, the number of laminated dielectric layers 16 of the multilayer capacitor 10 is 100 or more. In the multilayer capacitor 10, the length of the element body 12 in the lamination direction (the opposing direction of the pair of main surfaces 12c, 12d) is 1.0 mm or more. In this configuration, electrostrictive deformation is likely to occur in the multilayer capacitor 10. Therefore, in the case of such a multilayer capacitor 10, the above configuration is particularly effective in improving the withstand voltage.

[0050] In the electronic component 1 according to this embodiment, the distance between the first main surface 2a of the substrate 2 and the main surface 12d of the element body 12 of the multilayer capacitor 10 is 0.2 mm or less. In the electronic component 1, a sealing portion 11 is disposed between the first main surface 2a of the substrate 2 and the main surface 12d of the element body 12. In this configuration, the entire multilayer capacitor 10 is covered by the sealing portion 11, so that the occurrence of electrostrictive deformation in the multilayer capacitor 10 can be further suppressed.

[0051] In the electronic component 1 according to this embodiment, the sealing portion 11 is made of a silicone resin or an epoxy resin. With this configuration, the occurrence of electrostrictive deformation in the multilayer capacitor 10 can be effectively suppressed.

[0052] In the electronic component 1 according to this embodiment, the height T2 of the sealing portion 11 from the first main surface 2a of the substrate 2 is at least twice the height T1 of the multilayer capacitors 10 mounted on the first main surface 2a of the substrate 2. In this configuration, the sealing portion 11 can effectively suppress electrostrictive deformation of the multiple multilayer capacitors 10.

[0053] Although the embodiment of the present invention has been described above, the present invention is not necessarily limited to the above-described embodiment, and various modifications are possible without departing from the gist of the present invention.

[0054] In the above embodiment, the substrate 2 has a rectangular shape as an example, but the shape of the substrate 2 is not limited to this.

[0055] In the above embodiment, the sealing portion 11 has a substantially rectangular parallelepiped shape as an example, but the shape of the sealing portion 11 is not limited to this.

[0056] In the above embodiment, an example has been described in which the first external electrode 13 and the second external electrode 14 have the configuration shown in Fig. 4. However, the configuration of the first external electrode 13 and the second external electrode 14 is not limited to this, and may be, for example, L-shaped.

[0057] In the above embodiment, the multilayer capacitor 10A, the multilayer capacitor 10B, and the multilayer capacitor 10C have been described as having the same configuration, shape, and dimensions. However, the multilayer capacitor 10A, the multilayer capacitor 10B, and the multilayer capacitor 10C may have different configurations. In this case, the distances P1 and P2 are set based on the multilayer capacitor 10 having the largest height T1.

[0058] In the above embodiment, the multilayer capacitor 10A, the multilayer capacitor 10B, and the multilayer capacitor 10C are arranged such that the stacking direction of the internal electrodes 15A, 15B is aligned with the third direction D3. That is, the multilayer capacitor 10A, the multilayer capacitor 10B, and the multilayer capacitor 10C are arranged such that the stacking direction of the internal electrodes 15A, 15B is perpendicular to the first main surface 2a of the substrate 2. However, as shown in Fig. 8, the multilayer capacitor 10A, the multilayer capacitor 10B, and the multilayer capacitor 10C may be arranged such that the stacking direction of the internal electrodes 15A, 15B is aligned with the first direction D1.

[0059] In this configuration, when a voltage is applied to the multilayer capacitor 10, a force pressing the sealing portion 11 acts on each of the adjacent multilayer capacitors 10 due to expansion. In the electronic component 1, the stacking direction of adjacent multilayer capacitors 10 is the same, so the directions of the above-mentioned force acting on adjacent multilayer capacitors 10 are opposite. This makes it possible to prevent adjacent multilayer capacitors 10 from deforming each other. Therefore, in the electronic component 1, electrostrictive deformation of the multilayer capacitors 10 can be suppressed, making it possible to apply a high voltage. As a result, the electronic component 1 can improve its withstand voltage.

[0060] In the above embodiment, the multilayer capacitor 10A, the multilayer capacitor 10B, and the multilayer capacitor 10C are arranged at the same position in the second direction D2. That is, the multilayer capacitor 10A, the multilayer capacitor 10B, and the multilayer capacitor 10C are arranged at the same position in the second direction D2. However, the arrangement of the multilayer capacitor 10A, the multilayer capacitor 10B, and the multilayer capacitor 10C is not limited to this.

[0061] As shown in Fig. 9, in electronic component 1A, multilayer capacitor 10A, multilayer capacitor 10B, and multilayer capacitor 10C may be arranged in a staggered pattern. As shown in Fig. 10, in electronic component 1B, multilayer capacitor 10A, multilayer capacitor 10B, and multilayer capacitor 10C may be arranged with their positions shifted in a step-like manner in second direction D2.

[0062] 11, in electronic component 1C, multilayer capacitor 10A, multilayer capacitor 10B, and multilayer capacitor 10C may be arranged such that the intervals between adjacent multilayer capacitors 10A, 10B, and 10C are not uniform (the intervals are different). In this configuration, distance P1 is the shortest distance between multilayer capacitor 10A and multilayer capacitor 10B. Distance P2 is the shortest distance between multilayer capacitor 10B and multilayer capacitor 10C.

[0063] In the above embodiment, an example has been described in which three multilayer capacitors 10 are mounted. However, the number of multilayer capacitors 10 in the electronic component is not limited to this. In the electronic component, the number of multilayer capacitors 10 mounted may be two, or four or more. As shown in FIG. 12, six multilayer capacitors 10 are mounted in an electronic component 1D. In the electronic component 1D, three multilayer capacitors 10 arranged side by side in a first direction D1 are arranged in two rows in a second direction D2.

[0064] In addition to the above embodiments, an electronic component 1E may have, for example, two multilayer capacitors 10 stacked and arranged in a third direction D3 as shown in Fig. 13. In the two stacked multilayer capacitors 10, the first external electrodes 13 and the second external electrodes 14 are electrically connected to each other by a bonding member (conductive adhesive, solder) or the like. EXAMPLES

[0065] The present invention will be described in more detail below based on examples and comparative examples, but the present invention is not limited to the following examples.

[0066] <Electronic component manufacturing> Example 1 The laminated capacitor element had a length L (distance between a pair of end faces) of 3.2 mm, a width W (distance between a pair of side faces) of 2.5 mm, and a height T (distance between a pair of main faces) of 2.5 mm. The dielectric layer forming the laminated capacitor element had a thickness of 4.9 μm. In the internal electrodes, the distance between the end faces (L-Gap) was 196 μm, and the distance between the side faces (W-Gap) was 180 μm. The first external electrode and the second external electrode were formed by forming a Cu baked layer and then plating the baked layer with Ni / Sn.

[0067] The multilayer capacitor was mounted on a glass epoxy board using Sn-Ag-Cu solder. In the electronic component according to Example 1, three multilayer capacitors were mounted. The three multilayer capacitors were electrically connected in parallel. The multilayer capacitors were arranged so that the lamination direction of the multiple internal electrodes was perpendicular to the mounting surface of the board. As shown in FIG. 2, the three multilayer capacitors were arranged so that the length L of the element body was aligned. The distance between adjacent multilayer capacitors was 45% of the height of the element body. The distance between the element body of the multilayer capacitor and the board was 0.1 mm. The multilayer capacitor was sealed with silicone resin to form a sealing portion. The height of the sealing portion was 2.1 times the height of the element body. In this manner, the electronic component according to Example 1 was obtained.

[0068] Example 2 An electronic component according to Example 2 was obtained by producing an electronic component in the same manner as in Example 1, except that the height of the sealing portion was set to 1.5 times the height of the element body.

[0069] Example 3 An electronic component according to Example 3 was obtained by manufacturing the electronic component in the same manner as in Example 1, except that the height of the sealing portion was set to 1.5 times the height of the element body and the sealing portion was formed from epoxy resin.

[0070] Example 4 An electronic component according to Example 4 was obtained by manufacturing an electronic component in the same manner as in Example 1, except that the multilayer capacitor was arranged so that the lamination direction of multiple internal electrodes was horizontal to the mounting surface of the substrate as shown in FIG. 8 and the height of the sealing portion was set to 1.5 times the height of the element body.

[0071] Example 5 An electronic device according to Example 4 was obtained by manufacturing the electronic device in the same manner as in Example 1, except that two multilayer capacitors were used.

[0072] Example 6 An electronic component according to Example 6 was obtained by manufacturing the electronic component in the same manner as in Example 1, except that two multilayer capacitors were used and the height of the sealing portion was 1.5 times the height T of the element body.

[0073] Example 7 An electronic component according to Example 7 was obtained by manufacturing an electronic component in the same manner as in Example 1, except that the multilayer capacitor and the substrate were joined via a connecting member (metal terminal), the distance between the element body of the multilayer capacitor and the substrate was 0.8 mm, and the height of the sealing portion was 1.5 times the height of the element body.

[0074] Comparative Example 1 An electronic component according to Comparative Example 1 was obtained by producing the electronic component in the same manner as in Example 1, except that no sealing portion was provided.

[0075] Comparative Example 2 An electronic component according to Comparative Example 2 was obtained by manufacturing an electronic component in the same manner as in Example 1, except that the distance between adjacent multilayer capacitors was 70% of the height of the element body and the height of the sealing portion was 1.5 times the height T of the element body.

[0076] Comparative Example 3 Of the three multilayer capacitors, two multilayer capacitors were arranged so that the stacking direction of the multiple internal electrodes was perpendicular to the mounting surface of the substrate, and the stacking direction of one internal electrode arranged between the two multilayer capacitors was horizontal to the mounting surface of the substrate, and the height of the sealing portion was set to 1.5 times the height T of the element body. Except for this, an electronic component was manufactured in the same manner as in Example 1, to obtain an electronic component according to Comparative Example 3.

[0077] Comparative Example 4 An electronic component according to Comparative Example 4 was obtained by manufacturing the electronic component in the same manner as in Example 1, except that one multilayer capacitor was mounted and the height of the sealing portion was set to 1.5 times the height T of the element body.

[0078] <Measurement method> The voltage at which the electronic components were broken was measured with a voltage of 10 V / sec and a current threshold of 10 mA. The voltages of 10 electronic components of Examples 1 to 7 and Comparative Examples 1 to 4 were measured, and the median of the voltages was taken as the breakdown voltage. The measurement results are shown in Table 1.

[0079] [Table 1]

[0080] In electronic components, the breakdown voltage required as the withstand voltage is 300V or more, preferably 320V or more, and more preferably 340V or more. As shown in Table 1, the breakdown voltage of all of the electronic components according to Examples 1 to 7 was 300V or more. The breakdown voltage of all of the electronic components according to Comparative Examples 1 to 4 was less than 300V. As described above, it was confirmed that the withstand voltage could be improved in the electronic components according to Examples 1 to 7. [Explanation of symbols]

[0081] 1, 1A, 1B, 1C, 1D, 1E...electronic component, 2...substrate, 2a...first main surface (mounting surface) 10, 10A, 10B, 10C...multilayer capacitor, 11...sealing portion, 12...element body, 12a, 12b...end surface, 12c, 12d...main surface (side surface), 12e, 12f...side surface, 15A, 15B...internal electrode, 16...dielectric layer, H...solder, T1...height, T2...height, P1, P2, P3...distance, P3...distance.

Claims

1. A substrate; a plurality of multilayer capacitors mounted on a mounting surface of the substrate; a sealing portion formed of a resin and sealing the plurality of multilayer capacitors; Each of the plurality of multilayer capacitors comprises: an element body formed by stacking a plurality of dielectric layers, the element body having a pair of end faces and four side faces connecting the pair of end faces; An external electrode disposed on the element body; a plurality of internal electrodes disposed within the element body and arranged opposite to each other in a stacking direction of the plurality of dielectric layers; the external electrodes of the multilayer capacitor are mounted on the substrate by solder; adjacent multilayer capacitors at least partially overlap each other when viewed in a direction in which the pair of side surfaces of the element body face each other and along the mounting surface of the substrate; In the adjacent multilayer capacitors, the lamination directions of the plurality of internal electrodes are the same, an electronic component, wherein the distance between adjacent multilayer capacitors is equal to or less than half the height of the multilayer capacitor mounted on the substrate.

2. Each of the plurality of multilayer capacitors has the same configuration, shape, and size, 2. The electronic component according to claim 1, wherein the plurality of multilayer capacitors are arranged so as to overlap when viewed in a direction in which the pair of side surfaces of the element body face each other and along the mounting surface of the substrate.

3. 3. The electronic component according to claim 1, wherein the multilayer capacitor is arranged such that the lamination direction of the plurality of internal electrodes is perpendicular to the mounting surface.

4. the number of laminations of the dielectric layers of the multilayer capacitor is 100 or more, 3. The electronic component according to claim 1, wherein the length of the element body in the stacking direction is 1.0 mm or more.

5. a distance between the mounting surface of the substrate and the element body of the multilayer capacitor facing the mounting surface is 0.2 mm or less; The electronic component according to claim 1 , wherein the sealing portion is disposed between the mounting surface and the element body.

6. The electronic component according to claim 1 , wherein the resin is a silicone resin or an epoxy resin.

7. 3. The electronic component according to claim 1, wherein a height of the sealing portion from the mounting surface is at least twice a height of the multilayer capacitor mounted on the mounting surface.

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