Semiconductor module

Abstract

To provide a semiconductor module which can set normal drive capability.SOLUTION: A semiconductor module comprises first and second switching devices Q1, Q2 serially connected between first potential and second potential, a higher potential side driving circuit HVIC output adjustable to the Q1, and a lower potential side driving circuit LVIC output adjustable to the Q2. The HVIC includes: a terminal which receives a drive signal, a data signal, a clock signal, and an enable signal transmitted from the outside; a first level shift unit for level-shifting the drive signal; a shift register unit constituted by a plurality of flip-flops; a lower voltage side setting value holding unit which extracts a record of the shift register by the enable signal; a write signal generation unit which generates a write signal by the drive signal and the enable signal; a second level shift unit which level-shifts information on the lower voltage side setting value holding unit by the write signal; a higher voltage side setting value holding unit which has the same information as the information on the lower voltage side setting value holding unit; and a decoder which changes output current capability in the higher voltage side setting value holding unit.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor module, and more particularly to a semiconductor module incorporating a power transistor and a drive circuit that drives the power transistor. [Background technology]

[0002] 2. Description of the Related Art Semiconductor modules are known that incorporate a micro processing unit (MPU) having a function for generating a pulse width modulation (PWM) signal and internally generate a PWM signal that controls a switching device based on a signal from an external controller.

[0003] On the other hand, in order to change the operating characteristics of a semiconductor module, communication is required between an external controller and an internal controller to receive data for the change from the outside, as well as a trigger signal that determines the timing of the change from the outside. This requires terminals for this purpose, which poses the problem that the module cannot be made smaller.

[0004] In this regard, Patent Document 1 discloses a semiconductor module whose operating characteristics are changeable. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2020-205702 A Summary of the Invention [Problem to be solved by the invention]

[0006] On the other hand, in the configuration shown in Patent Document 1, there occurs a period (dV / dt period) in which the voltage in the high-voltage region in the drive device that drives the complementarily driven power transistors fluctuates suddenly, and a negative potential period due to undershoot occurs. During this period, the voltage level conversion (level shift circuit) that transmits the signal of the setting value for setting the drive capacity cannot transmit the signal, and there is a problem that the drive capacity setting does not become a normal value.

[0007] The present disclosure is intended to solve the above-mentioned problems, and has an object to provide a semiconductor module that allows normal driving capability setting. [Means for solving the problem]

[0008] One aspect of the present disclosure includes a first and second switch elements connected in series between a first potential and a second potential lower than the first potential and operating in a complementary manner, a high-potential side drive circuit including a first driver connected to a first gate of the first switch element and capable of adjusting an output to the first gate, and a low-potential side drive circuit connected to a second gate of the second switch element and including a second driver capable of adjusting an output to the second gate, the high-potential side drive circuit including terminals for receiving a drive signal, a data signal, a clock signal, and an enable signal, which are data communication signals transmitted from an external controller, a first level shift unit for level-shifting the drive signal to a high potential and outputting it to the first driver, and a plurality of flip-flops connected in cascade, the high-potential side drive circuit including a first driver connected to a first gate of the first switch element and capable of adjusting an output to the second gate, the high-potential side drive circuit including terminals for receiving a drive signal, a data signal, a clock signal, and an enable signal, which are data communication signals transmitted from an external controller, a first level shift unit for level-shifting the drive signal to a high potential and outputting it to the first driver, and a first driver for level-shifting the drive signal to a high potential and outputting it to the first driver. the first driver includes a shift register in which a data signal is recorded in a flip-flop in response to an enable signal, and the recorded data is moved to an adjacent flip-flop each time a data signal is stored in the flip-flop; a low-voltage side set value holding unit that extracts and records the recorded contents of the plurality of flip-flops of the shift register in response to an enable signal; a write signal generation unit that generates a write signal based on the drive signal and the enable signal; a second level shift unit that level-shifts the information held in the low-voltage side set value holding unit to a high potential in response to the write signal; a high-voltage side set value holding unit that is connected via the second level shift unit and records the same information as the information recorded in the low-voltage side set value holding unit; and a decoder that varies the output current capacity of the first driver in response to the record in the high-voltage side set value holding unit. Effect of the Invention

[0009] A semiconductor module according to a disclosure allows normal setting of driving capability. [Brief description of the drawings]

[0010] [Figure 1] FIG. 1 is a diagram illustrating an outline of a configuration of a semiconductor module according to a first embodiment. [Diagram 2] FIG. 2 is a diagram illustrating a circuit configuration of a first level shift section 10 according to the first embodiment. [Diagram 3]1 is a diagram illustrating configurations of a driver 30 and a shift register section 38 according to the first embodiment. [Figure 4] 2 is a diagram illustrating the configurations of high-voltage side set value holding section 16 and second level shift section 18 according to the first embodiment. FIG. [Diagram 5] FIG. 11 is a diagram illustrating setting information held in a controller (MCU) 2 according to the first embodiment. [Figure 6] 11 is a diagram illustrating a timing chart of output of write signal TM1 according to the first embodiment. FIG. [Figure 7] FIG. 11 is another diagram illustrating a timing chart of output of write signal TM1 according to the first embodiment. [Figure 8] FIG. 11 is a diagram illustrating an outline of a configuration of a semiconductor module according to a second embodiment. [Figure 9] FIG. 11 is a diagram illustrating a timing chart of output of write signal TM1 according to the second embodiment. [Figure 10] FIG. 11 is a diagram illustrating an outline of a configuration of a semiconductor module according to a third embodiment. [Figure 11] FIG. 13 is a diagram illustrating an outline of a configuration of a semiconductor module according to a fourth embodiment. [Figure 12] 13 is a diagram illustrating the configurations of a high-voltage side set value holding section 16A and a second level shift section 18A according to the fourth embodiment. FIG. [Figure 13] FIG. 13 is a diagram illustrating an outline of a configuration of a semiconductor module according to a fifth embodiment. [Figure 14] 13 is a diagram illustrating configurations of a high-voltage side set value holding section 16B, a second level shift section 18B, and a low-voltage side shift register section 21 according to a fifth embodiment. FIG. [Figure 15] FIG. 13 is a diagram illustrating a timing chart of output of write signal TM1 according to the fifth embodiment. [Figure 16] FIG. 13 is another diagram illustrating a timing chart of output of write signal TM1 according to the fifth embodiment. [Figure 17]FIG. 23 is a diagram illustrating an outline of a configuration of a semiconductor module according to a sixth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. In the following, the same or corresponding parts in the drawings are denoted by the same reference characters, and their description will not be repeated in principle.

[0012] Embodiment 1 FIG. 1 is a diagram for explaining an outline of the configuration of a semiconductor module according to a first embodiment. Referring to FIG. 1, the semiconductor module includes power transistors (switching elements) Q1 and Q2, and a drive circuit for driving the gates of the power transistors Q1 and Q2. The power transistor Q1 is provided between a high potential HV and an output node OUT. The power transistor Q2 is provided between the output node OUT and a ground potential VSS side. The drive circuit includes a high-side output capability variable gate device HVIC (high potential side drive circuit) and a low-side output capability variable gate device LVIC (low potential side drive circuit). The high-side output capability variable gate device HVIC is provided corresponding to the gate of the power transistor Q1. The low-side output capability variable gate device LVIC is provided corresponding to the gate of the power transistor Q2. The power transistors Q1 and Q2 operate complementarily by gate drive of the high-side output capability variable gate device HVIC and the low-side output capability variable gate device LVIC. The output node OUT is connected to a motor or the like as a load, for example.

[0013] The controller (MCU) 2 outputs a data communication signal for driving the power transistors Q1 and Q2 to the high-side output capability variable gate device HVIC and the low-side output capability variable gate device LVIC. The high-side output capability variable gate device HVIC and the low-side output capability variable gate device LVIC drive the power transistors Q1 and Q2, respectively, in accordance with the data communication signal from the controller 2. The high-side output capability variable gate device HVIC has input terminals HIN, SI, CK, and EN. The high-side output capability variable gate device HVIC also has an output terminal HO. The input terminal HIN receives a high-side drive signal from the controller 2. The input terminal SI receives a data signal from the controller 2. The input terminal CK receives a clock signal from the controller 2. The input terminal EN receives an enable signal from the controller 2. The output terminal HO is connected to the gate of the power transistor Q1.

[0014] The high side output capability variable gate device HVIC includes a first level shift section 10 that level-shifts the high side drive signal to a high potential, a write signal generation section 24, a shift register section 22, a low voltage side set value holding section 20, a second level shift section 18, a high voltage side set value holding section 16, a decoder 14, and a driver 12.

[0015] The shift register section 22 is configured by cascading a plurality of DT flip-flops. The shift register section 22 records a data signal input in accordance with a data signal, a clock signal, and an enable signal, and shifts the data signal to an adjacent DT flip-flop. In this example, a 3-bit data signal (D1 to D3) is held in the shift register section 22 and output to the low-voltage side setting value holding section 20.

[0016] In accordance with the enable signal, low-voltage side set value holding unit 20 holds the information held in shift register unit 22. Specifically, low-voltage side set value holding unit 20 holds the information held in shift register unit 22 in accordance with the falling or rising edge of the enable signal.

[0017] The second level shift section 18 shifts the level of the data signal, which is 3-bit information held in the low-voltage side set value holding section 20, to a high potential in accordance with the write signal TM1 generated by the write signal generating section 24.

[0018] High-voltage side set value holding section 16 holds information of the 3-bit data signal (D1 to D3) level-shifted by second level shift section .

[0019] The decoder 14 performs a decoding process based on the data signals (D1 to D3) held in the high-voltage side set value holding unit 16, and outputs the result to the driver 12.

[0020] In this example, a high voltage region HVR is shown, and the first level shift section 10, part of the second level shift section 18, the driver 12, the decoder 14, and the high voltage side set value holding section 16 are provided in this region.

[0021] The write signal generating unit 24 outputs a write signal TM1 based on the high side drive signal and the enable signal.

[0022] The low side output capability variable gate device LVIC has input terminals LIN, SIL, CKL, and ENL. The low side output capability variable gate device LVIC also has an output terminal LO. The input terminal LIN receives a low side drive signal from the controller 2. The input terminal SIL receives a data signal from the controller 2. The input terminal CKL receives a clock signal from the controller 2. The input terminal ENL receives an enable signal from the controller 2. The output terminal LO is connected to the gate of the power transistor Q2.

[0023] The low-side output capability variable gate device LVIC includes a shift register section 38 , a set value holding section 36 , a decoder 34 , and a driver 30 .

[0024] The shift register section 38 is configured by cascading a plurality of DT flip-flops. The shift register section 38 records a data signal input in accordance with a data signal, a clock signal, and an enable signal, and shifts the data signal to an adjacent DT flip-flop. In this example, a 3-bit data signal (D1 to D3) is held in the shift register section 38 and output to the setting value holding section 36.

[0025] The set value holding section 36 holds the information held in the shift register section 38 in accordance with the enable signal. The set value holding section 36 holds the information held in the shift register section 22 in accordance with the falling or rising edge of the enable signal.

[0026] The decoder 34 performs a decoding process based on the data signals (D1 to D3) held in the set value holding unit 36, and outputs the result to the driver 30.

[0027] In this example, a case will be described in which information recorded in low-voltage side setting value holding unit 20 is transmitted to high-voltage side setting value holding unit 16 by write signal TM1 generated by write signal generating unit 24 based on a high-side drive signal and an enable signal, thereby avoiding communication during periods when the voltage in the high-voltage region HVR, during which the second level shift unit 18 cannot transmit signals, fluctuates rapidly (dV / dt periods) and negative voltage periods.

[0028] 2 is a diagram illustrating a circuit configuration of the first level shift section 10 according to the embodiment 1. With reference to FIG. 2, the first level shift section 10 includes an on-off one-shot pulse circuit 100, high voltage MOS transistors 102 and 104, an SR flip-flop 106, inverters 114 and 116, diodes 112 and 118, and resistance elements 108 and 110.

[0029] The on-off one-shot pulse circuit 100 outputs a one-shot pulse when it is on / off (when the input signal rises / falls). The on-off one-shot pulse circuit 100 outputs a one-shot pulse to the gate of the high voltage MOS transistor 102 when it is on (when the input signal rises). The on-off one-shot pulse circuit 100 outputs a one-shot pulse to the gate of the high voltage MOS transistor 104 when it is off (when the input signal falls). The node N0 is connected to the terminal VB. A floating power supply 120 is connected between the terminal VB and the terminal VS. A terminal VSS connected to the ground potential GND is connected to the node N1. The high voltage MOS transistors 102, 104 are connected in parallel between the node N0 and the node N1. A resistor element 108 is provided between the source side of the high voltage MOS transistor 102 and the node N0. A resistor element 110 is provided between the source side of the high voltage MOS transistor 104 and the node N0. The anode side of the diode 112 is connected to the terminal VS which is at an intermediate potential, and the cathode side is connected to the connection node between the resistance element 108 and the high voltage MOS transistor 102. The anode side of the diode 118 is connected to the terminal VS which is at an intermediate potential, and the cathode side is connected to the connection node between the resistance element 110 and the high voltage MOS transistor 104. The diodes 112 and 118 clamp the cathode voltage to a drop from the voltage of the terminal VS to the diode VF voltage, and adjust it so that it does not exceed the withstand voltages of the inverters 114 and 116 and the resistance elements 108 and 110.

[0030] When the high voltage MOS transistor 102 is off, the potential of the connection node between the resistance element 108 and the high voltage MOS transistor 102 is set to a high potential. Therefore, the output signal of the inverter 114 is set to an "L" level. Similarly, when the high voltage MOS transistor 104 is off, the potential of the connection node between the resistance element 110 and the high voltage MOS transistor 104 is set to a high potential. Therefore, the output signal of the inverter 116 is set to an "L" level.

[0031] When the high voltage MOS transistor 102 is driven (ON), the potential of the connection node between the resistance element 108 and the high voltage MOS transistor 102 drops. Accordingly, the output signal of the inverter 114 is set to the "H" level. Similarly, when the high voltage MOS transistor 104 is driven (ON), the potential of the connection node between the resistance element 110 and the high voltage MOS transistor 104 drops. Therefore, the output signal of the inverter 116 is set to the "H" level.

[0032] The on-off one-shot pulse circuit 100 outputs a one-shot pulse when it is on (when the input signal rises). This turns on the high-voltage MOS transistor 102. This makes the connection node with the resistance element 108 go to the "L" level, and the inverter 114 outputs the "H" level. That is, the RS flip-flop is set to "1". The on-off one-shot pulse circuit 100 outputs a one-shot pulse when it is off (when the input signal falls). This turns on the high-voltage MOS transistor 104. This makes the connection node with the resistance element 110 go to the "L" level, and the inverter 116 outputs the "H" level. That is, the RS flip-flop is reset to "0".

[0033] With this configuration, the drive signal input to the on-off one-shot pulse circuit 100 is level-shifted to a high potential and held in the RS flip-flop 106. The RS flip-flop 106 outputs the held data signal from the terminal D0OUT.

[0034] 3 is a diagram illustrating the configuration of the driver 30 and the shift register unit 38 according to the first embodiment. With reference to FIG. 3, the shift register unit 38 configures a shift register by cascading a plurality of flip-flops (DT-FFs) 200 to 202. A data signal input from an input terminal SIL is input to a D input of the leading flip-flop 200, and a Q output of the leading flip-flop 200 is input to a D input of a next-stage flip-flop 201. A Q output of the next-stage flip-flop 201 is input to a D input of a next-stage flip-flop 202. The Q outputs of the flip-flops 200 to 202 are output to the set value holding unit 36 ​​as data D3, D2, and D1.

[0035] The clock signal input from the input terminal CKL is input to the clock inputs of all the flip-flops 200 to 202. The data signal input in accordance with the clock input is transmitted to the next flip-flop and held by the next flip-flop.

[0036] The set value holding unit 36 ​​includes a plurality of flip-flops (DT-FF) 203-205. The flip-flop 203 receives data D3, which is the output of the flip-flop 200, at its D input. The flip-flop 204 receives data D2, which is the output of the flip-flop 201, at its D input. The flip-flop 205 receives data D1, which is the output of the flip-flop 202, at its D input. An enable signal input from an input terminal ENL is input to the clock inputs of all of the flip-flops 203-205.

[0037] Therefore, the flip-flops 203-205 of the set value holding unit 36 ​​hold the data D3, D2, D1 which are the Q outputs of the flip-flops 200-202 in accordance with the enable signal input from the input terminal ENL, and output them to the decoder 34. The set value holding unit 36 ​​holds 3-bit information (D1-D3). The decoder 34 decodes the 3-bit information into 8 patterns of signals.

[0038] The driver 30 has a plurality of drivers DD connected in parallel to the gate of the power transistor Q2. All but one of the plurality of drivers DD are connected to the gate of the power transistor Q2 via a switch SW, and the connection and disconnection to the gate of the power transistor Q2 are controlled by turning the switch SW on and off. The on / off control of the switch SW is controlled by a set value, which is the Q output of the flip-flops 200 to 202. The decoder 34 decodes the 3-bit information of the set value holding unit 36 ​​into 8 patterns of signals and executes the on / off control of the switch SW.

[0039] The switch SW of the driver 30 is turned on according to eight patterns of signals output from the decoder 34. If the number of switches SW of the driver 30 is increased, it is possible to increase the number of drivers DD that drive the power transistor Q2. Therefore, the driving capability of the driver 30 can be increased. In this way, the driving capability can be variably set according to the set value. Note that while the configuration of the driver 30 of the low side output capability variable gate device LVIC has been described in FIG. 3, the configuration of the shift register section 22 and the driver 12 of the high side output capability variable gate device HVIC is similar.

[0040] Fig. 4 is a diagram illustrating the configurations of high-voltage side set value holding section 16 and second level shift section 18 according to embodiment 1. With reference to Fig. 4, high-voltage side set value holding section 16 has a plurality of flip-flops 106A to 106C.

[0041] The second level shift section 18 includes a plurality of flip-flops (DT-FF) 101A to 101C, on-off one-shot pulse circuits 100A to 100C, high voltage MOS transistors 102A to 102C and 104A to 104C, SR flip-flops 106A to 106C, inverters 114A to 114C and 116A to 116C, diodes 112A to 112C and 118A to 118C, and resistance elements 108A to 108C and 110A to 110C.

[0042] Flip-flop 101A is triggered by write signal TM1 to hold data D3 held in low-voltage side set value holding unit 20. Flip-flop 101B is triggered by write signal TM1 to hold data D2 held in low-voltage side set value holding unit 20. Flip-flop 101C is triggered by write signal TM1 to hold data D1 held in low-voltage side set value holding unit 20.

[0043] The on-off one-shot pulse circuit 100A outputs a one-shot pulse when data D3 is on / off (when the input signal rises / falls). The on-off one-shot pulse circuit 100A outputs a one-shot pulse to the gate of the high voltage MOS transistor 102A when it is on (when the input signal rises). The on-off one-shot pulse circuit 100A outputs a one-shot pulse to the gate of the high voltage MOS transistor 104A when it is off (when the input signal falls). The node N0 is connected to the terminal VB. A floating power supply 120 is connected between the terminal VB and the terminal VS. A terminal VSS connected to the ground potential GND is connected to the node N1. The high voltage MOS transistors 102A, 104A are connected in parallel between the node N0 and the node N1. A resistor element 108A is provided between the source side of the high voltage MOS transistor 102A and the node N0. A resistor 110A is provided between the source of the high voltage MOS transistor 104A and the node N0. The anode of a diode 112A is connected to a terminal VS which is at an intermediate potential, and the cathode is connected to a connection node between the resistor 108A and the high voltage MOS transistor 102A. The anode of a diode 118A is connected to a terminal VS which is at an intermediate potential, and the cathode is connected to a connection node between the resistor 110A and the high voltage MOS transistor 104A.

[0044] When the high voltage MOS transistor 102A is off, the potential of the connection node between the resistance element 108A and the high voltage MOS transistor 102A is set to a high potential. Therefore, the output signal of the inverter 114A is set to an "L" level. Similarly, when the high voltage MOS transistor 104A is off, the potential of the connection node between the resistance element 110A and the high voltage MOS transistor 104A is set to a high potential. Therefore, the output signal of the inverter 116A is set to an "L" level.

[0045] When the high voltage MOS transistor 102A is driven (ON), the potential of the connection node between the resistance element 108A and the high voltage MOS transistor 102A drops. Accordingly, the output signal of the inverter 114A is set to the "H" level. Similarly, when the high voltage MOS transistor 104A is driven (ON), the potential of the connection node between the resistance element 110A and the high voltage MOS transistor 104A drops. Therefore, the output signal of the inverter 116A is set to the "H" level.

[0046] The on-off one-shot pulse circuit 100A outputs a one-shot pulse when the data D3 is on (when the input signal rises). This turns on the high-voltage MOS transistor 102A. This makes the connection node with the resistance element 108A go to the "L" level, and the inverter 114A outputs the "H" level. That is, the RS flip-flop sets "1". The on-off one-shot pulse circuit 100A outputs a one-shot pulse when the data D3 is off (when the input signal falls). This turns on the high-voltage MOS transistor 104A. This makes the connection node with the resistance element 110A go to the "L" level, and the inverter 116A outputs the "H" level. That is, the RS flip-flop A is reset to "0".

[0047] With this configuration, data D3 input to the on-off one-shot pulse circuit 100A is level-shifted to a high potential and held in the RS flip-flop 106A. The RS flip-flop 106A outputs the held data signal from a terminal D3OUT.

[0048] The on-off one-shot pulse circuit 100B outputs a one-shot pulse when the data D2 is on / off (when the input signal rises / falls). The on-off one-shot pulse circuit 100B outputs a one-shot pulse to the gate of the high voltage MOS transistor 102B when it is on (when the input signal rises). The on-off one-shot pulse circuit 100B outputs a one-shot pulse to the gate of the high voltage MOS transistor 104B when it is off (when the input signal falls). The node N0 is connected to the terminal VB. A floating power supply 120 is connected between the terminal VB and the terminal VS. The terminal VSS, which is connected to the ground potential GND, is connected to the node N1. The high voltage MOS transistors 102B, 104B are connected in parallel between the node N0 and the node N1. A resistor element 108B is provided between the source side of the high voltage MOS transistor 102B and the node N0. A resistor 110B is provided between the source of the high voltage MOS transistor 104B and node N0. The anode of a diode 112B is connected to a terminal VS which is at an intermediate potential, and the cathode is connected to a connection node between the resistor 108B and the high voltage MOS transistor 102B. The anode of a diode 118B is connected to a terminal VS which is at an intermediate potential, and the cathode is connected to a connection node between the resistor 110B and the high voltage MOS transistor 104B.

[0049] When the high voltage MOS transistor 102B is off, the potential of the connection node between the resistance element 108B and the high voltage MOS transistor 102B is set to a high potential. Therefore, the output signal of the inverter 114B is set to an "L" level. Similarly, when the high voltage MOS transistor 104B is off, the potential of the connection node between the resistance element 110B and the high voltage MOS transistor 104B is set to a high potential. Therefore, the output signal of the inverter 116B is set to an "L" level.

[0050] When the high voltage MOS transistor 102B is driven (ON), the potential of the connection node between the resistance element 108B and the high voltage MOS transistor 102B drops. Accordingly, the output signal of the inverter 114B is set to the "H" level. Similarly, when the high voltage MOS transistor 104B is driven (ON), the potential of the connection node between the resistance element 110B and the high voltage MOS transistor 104B drops. Therefore, the output signal of the inverter 116B is set to the "H" level.

[0051] The on-off one-shot pulse circuit 100B outputs a one-shot pulse when the data D2 is on (when the input signal rises). This turns on the high-voltage MOS transistor 102B. This makes the connection node with the resistance element 108B go to the "L" level, and the inverter 114B outputs the "H" level. That is, the RS flip-flop is set to "1". The on-off one-shot pulse circuit 100B outputs a one-shot pulse when the data D2 is off (when the input signal falls). This turns on the high-voltage MOS transistor 104B. This makes the connection node with the resistance element 110B go to the "L" level, and the inverter 116B outputs the "H" level. That is, the RS flip-flop is reset to "0".

[0052] With this configuration, data D2 input to the on-off one-shot pulse circuit 100B is level-shifted to a high potential and held in the RS flip-flop 106B. The RS flip-flop 106B outputs the held data signal from a terminal D2OUT.

[0053] The on-off one-shot pulse circuit 100C outputs a one-shot pulse when the data D1 is on / off (when the input signal rises / falls). The on-off one-shot pulse circuit 100C outputs a one-shot pulse to the gate of the high-voltage MOS transistor 102C when it is on (when the input signal rises). The on-off one-shot pulse circuit 100C outputs a one-shot pulse to the gate of the high-voltage MOS transistor 104C when it is off (when the input signal falls). The node N0 is connected to the terminal VB. A floating power supply 120 is connected between the terminal VB and the terminal VS. A terminal VSS connected to the ground potential GND is connected to the node N1. The high-voltage MOS transistors 102C, 104C are connected in parallel between the node N0 and the node N1. A resistor element 108C is provided between the source side of the high-voltage MOS transistor 102C and the node N0. A resistor 110C is provided between the source of the high voltage MOS transistor 104C and the node N0. An anode of a diode 112C is connected to a terminal VS which is at an intermediate potential, and a cathode of the diode 112C is connected to a connection node between the resistor 108C and the high voltage MOS transistor 102C. An anode of a diode 118C is connected to a terminal VS which is at an intermediate potential, and a cathode of the diode 118C is connected to a connection node between the resistor 110C and the high voltage MOS transistor 104C.

[0054] When the high voltage MOS transistor 102C is off, the potential of the connection node between the resistance element 108C and the high voltage MOS transistor 102C is set to a high potential. Therefore, the output signal of the inverter 114C is set to an "L" level. Similarly, when the high voltage MOS transistor 104C is off, the potential of the connection node between the resistance element 110C and the high voltage MOS transistor 104C is set to a high potential. Therefore, the output signal of the inverter 116C is set to an "L" level.

[0055] When the high voltage MOS transistor 102C is driven (ON), the potential of the connection node between the resistance element 108C and the high voltage MOS transistor 102C drops. Accordingly, the output signal of the inverter 114C is set to the "H" level. Similarly, when the high voltage MOS transistor 104C is driven (ON), the potential of the connection node between the resistance element 110C and the high voltage MOS transistor 104C drops. Therefore, the output signal of the inverter 116C is set to the "H" level.

[0056] The on-off one-shot pulse circuit 100C outputs a one-shot pulse when the data D1 is on (when the input signal rises). This turns on the high-voltage MOS transistor 102C. This makes the connection node with the resistance element 108C go to the "L" level, and the inverter 114C outputs the "H" level. That is, the RS flip-flop is set to "1". The on-off one-shot pulse circuit 100C outputs a one-shot pulse when the data D1 is off (when the input signal falls). This turns on the high-voltage MOS transistor 104C. This makes the connection node with the resistance element 110C go to the "L" level, and the inverter 116C outputs the "H" level. That is, the RS flip-flop is reset to "0".

[0057] With this configuration, data D1 input to the on-off one-shot pulse circuit 100C is level-shifted to a high potential and held in the RS flip-flop 106C. The RS flip-flop 106C outputs the held data signal from a terminal D1OUT.

[0058] Fig. 5 is a diagram illustrating setting information held by controller (MCU) 2 according to the first embodiment. Referring to Fig. 5, a driving power table is provided in the memory of controller (MCU) 2. For example, a plurality of setting value data defining the driving power of the drivers of high side output capacity variable gate device HVIC (upper gate) and low side output capacity variable gate device LVIC (lower gate) is stored.

[0059] In this example, as the setting value data of the driver driving capabilities, data P1, P2 for the driver on the upper arm side and data P3, P4 for the driver on the lower arm side are stored.

[0060] In addition to the driving capability of the driver, "other 1" is also shown as an example that specifies other capabilities, but this is not specified in this embodiment.

[0061] The controller 2 reads out data as necessary using the driving force table, and stores the data in the shift register section 22 of the high side output capability variable gate device HVIC (upper gate) and the shift register section 38 of the low side output capability variable gate device LVIC (lower gate).

[0062] This makes it possible to make the driving capabilities of the driver 12 and the driver 30 variable.

[0063] On the other hand, as described above, there is a possibility that a period (dV / dt period) in which the voltage in the high-voltage region in the drive device that drives the complementarily driven power transistors changes suddenly and a negative potential period due to undershoot may occur.

[0064] During this period, the voltage level conversion (level shift circuit) that transmits a signal of the setting value for setting the driving capacity cannot transmit a signal, and the driving capacity setting does not become a normal value.

[0065] The write signal generating unit 24 according to the first embodiment adjusts the timing of outputting the write signal TM1 in accordance with the high side drive signal. The above problem is avoided by performing signal transmission in accordance with the timing of the write signal TM1.

[0066] Fig. 6 is a diagram illustrating a timing chart of output of write signal TM1 according to embodiment 1. Referring to Fig. 6, at time T0, the recorded contents of the multiple flip-flops of shift register unit 22 are extracted and recorded in low-voltage side set value holding unit 20 at the timing of the falling edge (or either the rising edge) of the enable signal, and then at time T1, the low-side drive signal of input terminal LIN falls.

[0067] At time T2, the gate signal is outputted from the output terminal LO to the "L" level, turning off the power transistor Q2.

[0068] Then, at time T3, the high side drive signal at the input terminal HIN rises in a complementary manner, and at time T4, the gate signal is output from the output terminal HO to the "H" level, turning on the power transistor Q1.

[0069] As a result, the potential of the connection node between power transistor Q1 and power transistor Q2 rises during the period from time T5 to time T6. As a result, a period (dV / dt period) occurs during which the voltage of the high-voltage region HVR of the high-side output capability variable gate device HVIC fluctuates rapidly. During this period, signals cannot be transmitted in the voltage level conversion (level shift circuit), and there is a possibility that settings cannot be made normally.

[0070] Therefore, in the first embodiment, the write signal generating section 24 raises the write signal TM1 at time T7 after the period of the sudden change.

[0071] As a result, the data signals (D1 to D3) held in low-voltage side set value holding unit 20 are held in high-voltage side set value holding unit 16 via second level shift unit 18. Then, after decoder 14 converts the signals into eight patterns, the driving capability of driver 12 is changed.

[0072] The write signal generating unit 24 outputs the write signal TM1 after a delay time DL1 from the rising edge of the high side drive signal from the input terminal HIN until the gate signal rises from the output terminal HO, a delay time DL2 until the power transistor Q1 turns on, and a period during which the voltage of the high voltage region HVR fluctuates (dV / dt) caused by the power transistor Q1 turning on. This makes it possible to record in the high voltage side set value holding unit 16 while avoiding a period during which the voltage level conversion (level shift circuit) cannot transmit a signal. The write signal generating unit 24 outputs the write signal TM1 after a predetermined period has elapsed after the rising edge of the high side drive signal from the input terminal HIN. The predetermined period is set to a period longer than the total period of the delay times DL1 and DL2 and the fluctuating predetermined period (dV / dt).

[0073] Fig. 7 is another diagram illustrating a timing chart of output of write signal TM1 according to embodiment 1. Referring to Fig. 7, at time T0, the recorded contents of the multiple flip-flops of shift register unit 22 are extracted and recorded in low-voltage side setting value holding unit 20 at the timing of the falling edge (or either the rising edge) of the enable signal, and then at time T11, the high-side drive signal of input terminal HIN falls.

[0074] At time T12, the gate signal is outputted from the output terminal HO to the "L" level, turning off the power transistor Q1.

[0075] Then, at time T13, the low-side drive signal at the input terminal LIN rises in a complementary manner, and at time T14, the gate signal is outputted from the output terminal LO to the "H" level, turning on the power transistor Q2.

[0076] As a result, during the period from time T15 to time T16, the potential of the connection node between the power transistor Q1 and the power transistor Q2 drops suddenly. As a result, a period occurs in which the voltage of the high-voltage region HVR of the high-side output capability variable gate device HVIC fluctuates suddenly (VS negative potential period). During this period, the voltage of the high-voltage region HVR is negative, so signals cannot be transmitted in the voltage level conversion (level shift circuit), and there is a possibility that settings cannot be made normally.

[0077] Therefore, in the first embodiment, the write signal generating unit 24 raises the write signal TM1 at time T17 after the period when the voltage of the high voltage region HVR of the high side output capability variable gate device HVIC becomes a negative voltage.

[0078] As a result, the data signals (D1 to D3) held in low-voltage side set value holding unit 20 are held in high-voltage side set value holding unit 16 via second level shift unit 18. Then, after being converted into eight patterns of signals by decoder 14, the driving capability of driver 12 is changed.

[0079] The write signal generating unit 24 outputs the write signal TM1 after a delay time DL3 from the fall of the high side drive signal until the gate signal from the output terminal HO falls, a dead time (DEAD TIME) set so that the power transistors Q1 and Q2 do not turn on at the same time, a delay time DL4 from the rise of the low side drive signal until the gate signal rises from the output terminal LO, a delay time DL5 until the power transistor Q2 turns on, and a period in which the high voltage region HVR becomes negative voltage caused by the power transistor Q2 turning on. This makes it possible to record in the high voltage side set value holding unit 16 while avoiding a period in which the voltage level conversion (level shift circuit) cannot transmit a signal. The write signal generating unit 24 outputs the write signal TM1 after a predetermined period has elapsed after the fall of the high side drive signal from the input terminal HIN. The predetermined period is set to a period longer than the total period of the delay times DL3, DL4, DL5, the dead time (DEAD TIME), and the VS negative potential period.

[0080] Embodiment 2 Fig. 8 is a diagram illustrating an outline of the configuration of a semiconductor module according to a second embodiment. With reference to Fig. 8, the semiconductor module according to the second embodiment differs from the semiconductor module according to the first embodiment in that a signal from an output terminal LO of a low side output capability variable gate device LVIC (low potential side drive circuit) is provided as an input of a high side output capability variable gate device HVIC (high potential side drive circuit). Specifically, the high side output capability variable gate device HVIC is provided with a new input terminal LOS. The input terminal LOS receives an input of a signal from an output terminal LO of the low side output capability variable gate device LVIC (low potential side drive circuit).

[0081] Moreover, the write signal generation unit 24 is changed to a write signal generation unit 24A. The write signal generation unit 24A outputs a write signal TM1 based on the high side drive signal, the low side drive signal, and the enable signal.

[0082] Fig. 9 is a diagram illustrating a timing chart of output of write signal TM1 according to embodiment 2. With reference to Fig. 9, at time T20, the recorded contents of the multiple flip-flops of shift register unit 22 are extracted and recorded in low-voltage side set value holding unit 20 at the timing of the falling edge (or either the rising edge) of the enable signal, and then at time T21, the high-side drive signal of input terminal HIN falls.

[0083] At time T22, the gate signal is outputted from the output terminal HO to the "L" level, turning off the power transistor Q1.

[0084] Then, at time T23, the low-side drive signal at the input terminal LIN rises in a complementary manner, and at time T24, the gate signal is outputted from the output terminal LO to the "H" level, turning on the power transistor Q2.

[0085] Accordingly, a period from time T25 to time T26 occurs during which the voltage of the high voltage region HVR of the high side output capability variable gate device HVIC becomes a negative voltage.

[0086] In this example, at time T27 after the period during which the voltage is negative, the write signal generating section 24A raises the write signal TM1.

[0087] As a result, the data signals (D1 to D3) held in low-voltage side set value holding unit 20 are held in high-voltage side set value holding unit 16A via second level shift unit 18A. Then, after being converted into eight patterns of signals by decoder 14, the driving capability of driver 12 is changed.

[0088] The write signal generating unit 24A outputs the write signal TM1 after a delay time DL5 from when the gate signal from the output terminal LO rises until the power transistor Q2 turns on, and after the period when the high voltage region HVR becomes negative voltage due to the power transistor Q2 turning on. This makes it possible to record in the high voltage side set value holding unit 16 while avoiding the period when the voltage level conversion (level shift circuit) cannot transmit signals. The write signal generating unit 24 outputs the write signal TM1 after a predetermined period has elapsed after the low side drive signal from the input terminal LOS rises. The predetermined period is set to a period longer than the total period of the delay time DL5 and the VS negative potential period.

[0089] The rising edge of the high side drive signal is the same as that described with reference to FIG.

[0090] The configuration according to the second embodiment makes it possible to accurately record in high-voltage side set value holding section 16 while avoiding periods in which the voltage level conversion (level shift circuit) cannot transmit signals.

[0091] Embodiment 3 Fig. 10 is a diagram for explaining an outline of the configuration of a semiconductor module according to a third embodiment. Referring to Fig. 10, the semiconductor module according to the third embodiment differs from the semiconductor module according to the second embodiment in that a write signal TM1 of a high side output capability variable gate device HVIC (low potential side drive circuit) is provided as an input of a low side output capability variable gate device LVIC (high potential side drive circuit). Specifically, the high side output capability variable gate device HVIC is provided with a new output terminal TOUT. In addition, the low side output capability variable gate device LVIC is provided with a new input terminal TIN. The input terminal TIN receives the write signal TM1 via an output terminal TOUT of the high side output capability variable gate device HVIC (low potential side drive circuit).

[0092] Furthermore, the low-side output capability variable gate device LVIC has a two-stage set value holding section. Specifically, instead of the set value holding section 36, a first set value holding section 36A and a second set value holding section 36B are provided.

[0093] The first set value holding section 36A holds the information held in the shift register section 38 in accordance with the enable signal.

[0094] The second set value holding unit 36B further holds the information held in the first set value holding unit 36A in accordance with the write signal TM1.

[0095] With this configuration, the setting value information of the low side output capability variable gate device LVIC is updated at the same time that the setting value information of the high side output capability variable gate device HVIC (low potential side drive circuit) is updated in accordance with the write signal TM1.

[0096] In the configurations according to the above-mentioned first and second embodiments, there were cases where the setting value information was updated only for the low-side output capability variable gate device LVIC, but in the configuration according to the present third embodiment, the setting value information is updated by the same write signal TM1, so that adjustment of the driving capabilities can be performed simultaneously, enabling efficient changes.

[0097] Embodiment 4 Fig. 11 is a diagram illustrating an outline of the configuration of a semiconductor module according to embodiment 4. Referring to Fig. 11, the semiconductor module according to embodiment 4 differs from the semiconductor module according to embodiment 3 in that second level shift unit 18 is replaced with second level shift unit 18A, and that high-voltage side set value holding unit 16 is replaced with high-voltage side set value holding unit 16A.

[0098] The second level shift section 18A is composed of a pulse generating section 230 and a plurality of high voltage MOS transistors, in this example, four high voltage MOS transistors.

[0099] Fig. 12 is a diagram illustrating the configurations of high-voltage side set value holding section 16A and second level shift section 18A according to embodiment 4. With reference to Fig. 14, high-voltage side set value holding section 16A has a plurality of flip-flops (DT-FF) 205A to 205C.

[0100] The second level shift section 18A includes a pulse generating section 230, a delay circuit 220, high-voltage MOS transistors 202A to 202D, inverters 204, 214A to 214C, diodes 212A to 212D, resistive elements 208A to 108C, 110A to 110C, and AND circuits 201A to 201C.

[0101] The pulse generating section 230 generates and outputs a one-shot pulse signal using the write signal TM1 as a trigger. The delay circuit 220 outputs a signal obtained by delaying the one-shot pulse signal to the gate of the high-voltage MOS transistor 202A.

[0102] The AND circuit 201A outputs the result of an AND logic operation based on the one-shot pulse signal generated by the pulse generating section 230 and the data D3 held in the low-voltage side set value holding section 20 to the gate of the voltage-resistant MOS transistor 202B.

[0103] The node N0 is connected to the terminal VB. A floating power supply 120 is connected between the terminal VB and the terminal VS. A terminal VSS connected to the ground potential GND is connected to the node N1. The high voltage MOS transistors 202A and 202B are connected in parallel between the nodes N0 and N1. A resistor element 210A is provided between the source side of the high voltage MOS transistor 202A and the node N0. A resistor element 210B is provided between the source side of the high voltage MOS transistor 202B and the node N0. The anode side of the diode 212A is connected to the terminal VS which is an intermediate potential, and the cathode side is connected to the connection node between the resistor element 210A and the high voltage MOS transistor 202A. The anode side of the diode 212B is connected to the terminal VS which is an intermediate potential, and the cathode side is connected to the connection node between the resistor element 210B and the high voltage MOS transistor 202B.

[0104] The AND circuit 201B outputs the result of an AND logic operation based on the one-shot pulse signal generated by the pulse generating section 230 and the data D2 held in the low-voltage side set value holding section 20 to the gate of the voltage-resistant MOS transistor 202C.

[0105] The high voltage MOS transistors 202C and 202D are connected in parallel between the node N0 and the node N1. A resistor element 210C is provided between the source side of the high voltage MOS transistor 202C and the node N0. A resistor element 210D is provided between the source side of the high voltage MOS transistor 202D and the node N0. The anode side of the diode 212C is connected to a terminal VS which is an intermediate potential, and the cathode side is connected to a connection node between the resistor element 210C and the high voltage MOS transistor 202C. The anode side of the diode 212D is connected to a terminal VS which is an intermediate potential, and the cathode side is connected to a connection node between the resistor element 210D and the high voltage MOS transistor 202D.

[0106] When the high voltage MOS transistor 202C is off, the potential of the connection node between the resistance element 210C and the high voltage MOS transistor 202C is set to a high potential. Therefore, the output signal of the inverter 214B is set to the "L" level. When the high voltage MOS transistor 202C is driven (on), the potential of the connection node between the resistance element 210C and the high voltage MOS transistor 202C drops. Accordingly, the output signal of the inverter 214B is set to the "H" level.

[0107] When the high voltage MOS transistor 202D is off, the potential of the connection node between the resistance element 210D and the high voltage MOS transistor 202D is set to a high potential. Therefore, the output signal of the inverter 214C is set to an "L" level. When the high voltage MOS transistor 202D is driven (on), the potential of the connection node between the resistance element 210D and the high voltage MOS transistor 202D drops. Accordingly, the output signal of the inverter 214C is set to an "H" level.

[0108] The AND circuit 201C outputs the result of an AND logic operation based on the one-shot pulse signal generated by the pulse generating section 230 and the data D1 held in the low-voltage side set value holding section 20 to the gate of the voltage-resistant MOS transistor 202D.

[0109] The high voltage MOS transistors 202B-202D are driven based on the one-shot pulse from the pulse generating section 230 and the data D3-D1 held in the low voltage side set value holding section 20. Also, a signal that serves as a trigger for the flip-flops 205A-205C is driven according to the delayed signal from the delay circuit 220. In response to this, data "1" or "0" is set in the flip-flops 205A-205C based on the data D3-D1.

[0110] With this configuration, the data D3 to D1 input to the second level shift section 18A is level-shifted to a high potential and held in the flip-flops 205A to 205C. The flip-flops 205A to 205C output the held data signals from the terminals D3OUT to D1OUT.

[0111] On the other hand, in the case of the configuration of high-voltage side set value holding unit 16A according to the fourth embodiment, it is possible to configure the circuit using four high-voltage MOS transistors. Reducing the number of high-voltage MOS transistors reduces the number of components and simplifies the layout configuration.

[0112] In addition, although a 3-bit configuration is described in this example, the configuration is simple even when expanded to a number of more bits.

[0113] Embodiment 5. FIG. 13 is a diagram for explaining an outline of the configuration of a semiconductor module according to the fifth embodiment. Referring to FIG. 13, the semiconductor module according to the fifth embodiment differs from the semiconductor module according to the fourth embodiment in that the configurations of second level shift section 18A and high-voltage side set value holding section 16A are changed. Specifically, high-voltage side set value holding section 16A is replaced with high-voltage side set value holding section 16B, and the number of bits is changed to an 8-bit configuration. Eight DT flip-flops are provided. The second level shift section 18A is replaced with second level shift section 18B. Second level shift section 18B includes a high-voltage side shift register section 17.

[0114] Further provided are a clock generating section 19 which generates an internal clock INCK, a low-voltage side shift register section 21 which operates in accordance with the internal clock INCK of the clock generating section 19, and a counter 15.

[0115] Also, the low side output capability variable gate device LVIC is different in that it has been expanded from 3 bits to 8 bits. The write signal generating unit 24A outputs a write signal TM1 to the clock generating unit 19. The clock generating unit 19 generates an internal clock INCK in accordance with the write signal TM1. The low voltage side shift register unit 21 sequentially holds the data signals held by the low voltage side set value holding unit 20 in accordance with the internal clock INCK, and transfers them to the high voltage side shift register unit 17 as a transfer signal D.

[0116] The high-voltage side shift register unit 17 receives a level-converted signal input via a high-voltage MOS transistor. Specifically, the high-voltage side shift register unit 17 receives and holds a level-converted signal input for the transfer signal D in accordance with the internal clock INCK. The information held in the low-voltage side shift register unit 21 is transferred to the high-voltage side shift register unit 17 in accordance with the internal clock INCK.

[0117] The counter 15 counts the internal clock INCK and outputs a control signal CT at a predetermined count timing.

[0118] Specifically, eight counts of the internal clock INCK are required until all the information held in the low-voltage side set value holding unit 20 is transferred from the low-voltage side shift register unit 21 to the high-voltage side shift register unit 17. The counter 15 outputs the control signal CT when it has counted the internal clock INCK eight times. The eight DT flip-flops of the high-voltage side set value holding unit 16B hold the information of the high-voltage side shift register unit 17 in accordance with the control signal CT.

[0119] The low-side output capability variable gate device LVIC has a two-stage set value holding section. Specifically, instead of the set value holding section 36, a first set value holding section 36A and a second set value holding section 36B are provided.

[0120] The first setting value holding unit 36A holds the information held in the shift register unit 38 in accordance with the enable signal. The second setting value holding unit 36B further holds the information held in the first setting value holding unit 36A in accordance with the control signal CT.

[0121] With this configuration, even when the number of bits is expanded, there is no need to increase the number of high-voltage MOS transistors, and the number of high-voltage MOS transistors can be reduced, reducing the number of components and simplifying the layout configuration.

[0122] Fig. 14 is a diagram illustrating the configurations of high-voltage side set value holding section 16B, second level shift section 18B, and low-voltage side shift register section 21 according to embodiment 5. Referring to Fig. 14, high-voltage side set value holding section 16B has a plurality of flip-flops 203, 204, ....

[0123] The second level shift section 18B includes a high-voltage side shift register section 17, high-voltage MOS transistors 202A to 202C, diodes 212A to 212C, resistance elements 210A to 210C, and inverters 214A to 214C.

[0124] The low-voltage side shift register unit 21 has a plurality of cascaded flip-flops 240, 241,... Each of the flip-flops 240, 241,... receives an input of the internal clock INCK and sequentially transfers the data held therein to the subsequent flip-flop. In this example, the low-voltage side shift register unit 21 has eight flip-flops and sequentially outputs the data held therein as a transfer signal D to the high-voltage side shift register unit 17 in accordance with the input of the internal clock INCK.

[0125] The transfer signal D is input to the gate of the high voltage MOS 202C. The internal clock INCK is input to the gate of the high voltage MOS 202B. The control signal CT of the counter 15 is input to the gate of the high voltage MOS 202A. The node N0 is connected to the terminal VB. The floating power supply 120 is connected between the terminal VB and the terminal VS. The terminal VSS, which is connected to the ground potential GND, is connected to the node N1. The high voltage MOS transistors 202A, 202B, and 202C are connected in parallel between the node N0 and the node N1. A resistor element 210A is provided between the source side of the high voltage MOS transistor 202A and the node N0. A resistor element 210B is provided between the source side of the high voltage MOS transistor 202B and the node N0. A resistor element 210C is provided between the source side of the high voltage MOS transistor 202C and the node N0. The anode side of diode 212A is connected to terminal VS which is at an intermediate potential, and the cathode side is connected to a connection node between resistance element 210A and high voltage MOS transistor 202A. Inverter 214A outputs a signal from the connection node as a clock input to high voltage side set value holding unit 16B.

[0126] The anode side of the diode 212B is connected to a terminal VS which is an intermediate potential, and the cathode side is connected to a connection node between the resistance element 210B and the high-voltage MOS transistor 202B. The inverter 214B outputs a signal from the connection node as a clock input to the high-voltage shift register section 17. The anode side of the diode 212C is connected to a terminal VS which is an intermediate potential, and the cathode side is connected to a connection node between the resistance element 210C and the high-voltage MOS transistor 202C. The inverter 214C outputs a signal from the connection node as a data input to the high-voltage shift register section 17.

[0127] With this configuration, data D sequentially transferred from the low-voltage side shift register section 21 is level-shifted to a high potential and then transferred to the high-voltage side shift register section 17 .

[0128] The high-voltage side shift register unit 17 sequentially stores the transfer signal D, which is sequentially transferred from the low-voltage side shift register unit 21 in accordance with the internal clock INCK and the transfer signal D, in eight flip-flops.

[0129] The data held in high-voltage side shift register section 17 is held in high-voltage side set value holding section 16 B in accordance with a control signal CT of counter 15 .

[0130] In addition, although an 8-bit configuration is described in this example, the configuration is simple even when expanded to a number of more bits.

[0131] Fig. 15 is a diagram illustrating a timing chart of output of write signal TM1 according to embodiment 5. Referring to Fig. 15, at time T30, the recorded contents of the multiple flip-flops of shift register unit 22 are extracted and recorded in low-voltage side set value holding unit 20 at the timing of the falling edge (or either the rising edge) of the enable signal, and then at time T31, the low-side drive signal of input terminal LIN falls.

[0132] At time T32, the gate signal is outputted from the output terminal LO to the "L" level, turning off the power transistor Q2.

[0133] Then, at time T33, the high side drive signal at the input terminal HIN rises in a complementary manner, and at time T34, the gate signal is output from the output terminal HO to the "H" level, turning on the power transistor Q1.

[0134] As a result, the potential of the connection node between the power transistor Q1 and the power transistor Q2 rises during the period from time T35 to time T36. As a result, a period (dV / dt period) occurs during which the voltage of the high-voltage region HVR of the high-side output capability variable gate device HVIC fluctuates rapidly. During this period, signals cannot be transmitted in the voltage level conversion (level shift circuit), and there is a possibility that settings cannot be made normally.

[0135] Therefore, in the fifth embodiment, the write signal generating section 24 raises the write signal TM1 at time T37 after the period of the sudden change.

[0136] At time T38, the clock generating unit 19 outputs the internal clock INCK in response to the input of the write signal TM1. Accordingly, the low-voltage side shift register unit 21 transfers the transfer signal D to the high-voltage side shift register unit 17 in response to the internal clock INCK. The high-voltage side shift register unit 17 holds the transfer signal D in sequence in response to the internal clock INCK.

[0137] Counter 15 counts the internal clock INCK, and at time T39, outputs the control signal CT after counting eight times. High-voltage side set value holding unit 16B holds the data held in high-voltage side shift register unit 17 in a flip-flop in accordance with the control signal CT.

[0138] As a result, the data signals (D1 to D8) held in low-voltage side set value holding unit 20 are held in high-voltage side set value holding unit 16 via low-voltage side shift register unit 21 and high-voltage side shift register unit 17. Then, after decoder 14 converts the signals into 256 patterns, the driving capability of driver 12 is changed.

[0139] The write signal generating unit 24 outputs the write signal TM1 after a delay time DL1 from the rising edge of the high side drive signal from the input terminal HIN until the gate signal rises from the output terminal HO, a delay time DL2 until the power transistor Q1 turns on, and a period during which the voltage of the high voltage region HVR fluctuates (dV / dt) caused by the power transistor Q1 turning on. This makes it possible to record in the high voltage side set value holding unit 16B while avoiding a period during which the voltage level conversion (level shift circuit) cannot transmit a signal. The write signal generating unit 24 outputs the write signal TM1 after a predetermined period has elapsed after the rising edge of the high side drive signal from the input terminal HIN. The predetermined period is set to a period longer than the total period of the delay times DL1 and DL2 and the fluctuating predetermined period (dV / dt).

[0140] Fig. 16 is another diagram illustrating a timing chart of output of write signal TM1 according to embodiment 5. Referring to Fig. 16, at time T40, the recorded contents of the multiple flip-flops in shift register unit 22 are extracted and recorded in low-voltage side setting value holding unit 20 at the timing of the falling edge (or either the rising edge) of the enable signal, and then at time T41, the high side drive signal at input terminal HIN falls.

[0141] At time T42, the gate signal is output from the output terminal HO at the "L" level, turning off the power transistor Q1. Then, at time T43, the low-side drive signal at the input terminal LIN rises in a complementary manner. Then, at time T44, the gate signal is output from the output terminal LO at the "H" level, turning on the power transistor Q2.

[0142] As a result, during the period from time T45 to time T46, the potential of the connection node between power transistor Q1 and power transistor Q2 drops suddenly. As a result, a period occurs in which the voltage of the high-voltage region HVR of the high-side output capability variable gate device HVIC fluctuates suddenly (VS negative potential period). During this period, the voltage of the high-voltage region HVR is negative, so signals cannot be transmitted in the voltage level conversion (level shift circuit), and there is a possibility that settings cannot be made normally.

[0143] Therefore, in the fifth embodiment, the write signal generating unit 24 raises the write signal TM1 at time T47 after the period when the voltage of the high voltage region HVR of the high side output capability variable gate device HVIC becomes a negative voltage.

[0144] At time T48, the clock generating unit 19 outputs the internal clock INCK in response to the input of the write signal TM1. Accordingly, the low-voltage side shift register unit 21 transfers the transfer signal D to the high-voltage side shift register unit 17 in response to the internal clock INCK. The high-voltage side shift register unit 17 holds the transfer signal D in sequence in response to the internal clock INCK.

[0145] Counter 15 counts the internal clock INCK, and at time T49, outputs the control signal CT after counting eight times. High-voltage side set value holding unit 16B holds the data held in high-voltage side shift register unit 17 in a flip-flop in accordance with the control signal CT.

[0146] As a result, the data signals (D1 to D8) held in low-voltage side set value holding unit 20 are held in high-voltage side set value holding unit 16 via low-voltage side shift register unit 21 and high-voltage side shift register unit 17. Then, after decoder 14 converts the signals into 256 patterns, the driving capability of driver 12 is changed.

[0147] The write signal generating unit 24A outputs the write signal TM1 after a delay time DL5 from when the gate signal from the output terminal LO rises until the power transistor Q2 turns on, and after a period in which the high voltage region HVR becomes a negative voltage caused by the power transistor Q2 turning on. This makes it possible to record in the high voltage side set value holding unit 16 while avoiding a period in which the voltage level conversion (level shift circuit) cannot transmit a signal. The write signal generating unit 24A outputs the write signal TM1 after a predetermined period has elapsed after the low side drive signal from the input terminal LOS rises. The predetermined period is set to a period longer than the total period of the delay time DL5 and the VS negative potential period.

[0148] With the configuration according to the fifth embodiment, even when the number of bits is expanded, the number of high voltage MOS transistors can be reduced, the number of components can be reduced, and the layout configuration can be simplified.

[0149] Embodiment 6 Fig. 17 is a diagram illustrating an outline of a configuration of a semiconductor module according to a sixth embodiment. With reference to Fig. 17, the semiconductor module according to the sixth embodiment differs from the semiconductor module according to the first embodiment in that power transistors (switching elements) Q1 and Q2 are replaced with SiC-MOSFETs QA1 and QA2.

[0150] The other configurations are the same. The same can be applied to SiC-MOSFETs. SiC-MOSFETs have large variations in Vth and individual variations in output characteristics, but the configuration according to the above embodiment makes it possible to suppress variations as a semiconductor module by adjusting the output capacity of the driver. The same can be applied to other embodiments.

[0151] The embodiments disclosed herein are also intended to be combined appropriately within a range that is not inconsistent. The embodiments disclosed herein should be considered to be illustrative and not restrictive in all respects. The scope of the present disclosure is indicated by the claims, not the above description, and is intended to include all modifications within the meaning and scope of the claims. [Explanation of symbols]

[0152] 2 controller, 10 first level shift section, 12, 30, DD driver, 14, 34 decoder, 15 counter, 16, 16A, 16B high voltage side set value holding section, 17 high voltage side shift register section, 18, 18A, 18B second level shift section, 19 clock generation section, 20 low voltage side set value holding section, 21 low voltage side shift register section, 22, 38 shift register section, 23 pulse generation section, 24, 24A write signal generation section, 36 set value holding section, 36A first set value holding section, 36B second set value holding section, 100 on-off one-shot pulse circuit.

Claims

1. a first switch element and a second switch element connected in series between a first potential and a second potential lower than the first potential and operating in a complementary manner; a high-side driver circuit including a first driver connected to a first gate of the first switch element and capable of adjusting an output to the first gate; a low potential side drive circuit including a second driver connected to a second gate of the second switch element and capable of adjusting an output to the second gate; The high potential side driver circuit comprises: terminals for receiving a drive signal, a data signal, a clock signal, and an enable signal, which are data communication signals transmitted from an external controller; a first level shift unit that level-shifts the drive signal to a high potential and outputs the drive signal to the first driver; a first shift register configured by cascading a plurality of flip-flops, a data signal being recorded in the flip-flop in response to the clock signal and the enable signal, and the data recorded in the flip-flop being moved to an adjacent flip-flop every time the data signal is stored in the flip-flop; a low-voltage side setting value holding unit that extracts and records the recorded contents of the plurality of flip-flops of the first shift register in response to the enable signal; a write signal generating unit that generates a write signal based on the drive signal and the enable signal; a second level shift unit that level-shifts the information held by the low-voltage side set value holding unit to a high potential in response to the write signal; a high-voltage side setting value holding unit connected via the second level shift unit and storing the same information as that stored in the low-voltage side setting value holding unit; a first decoder for varying the output current capability of the first driver in accordance with the record of the high-voltage side set value holding unit.

2. 2. The semiconductor module according to claim 1, wherein said write signal generating section activates said write signal after a predetermined period has elapsed in accordance with a rising or falling edge of said drive signal.

3. 3. The semiconductor module according to claim 2, wherein the write signal generating section receives an input of a drive signal from the low potential side drive circuit and activates the write signal based on an output of the drive signal.

4. The low potential side drive circuit comprises: terminals for receiving a second drive signal, a second data signal, a second clock signal, and a second enable signal, which are data communication signals transmitted from an external controller; a second shift register configured by cascading a plurality of flip-flops, a second data signal being recorded in the flip-flop in response to the second clock signal and the second enable signal, and data being recorded in the flip-flop every time the second data signal is stored in the flip-flop is moved to an adjacent flip-flop; a first setting value holding unit that extracts and records the recorded contents of the plurality of flip-flops of the second shift register in response to the second enable signal; a second setting value storage unit that stores the same information as the information stored in the first setting value storage unit in response to the write signal; 2. The semiconductor module according to claim 1, further comprising a second decoder for varying an output current capability of said second driver in accordance with the record of said second set value holding section.

5. The second level shift unit is a pulse generating unit that outputs the information held by the low-voltage side set value holding unit as a one-shot pulse signal in accordance with the write signal; a plurality of high voltage transistors driven in accordance with respective outputs of the pulse generating unit; 2. The semiconductor module according to claim 1, wherein said high-voltage side set value holding section includes a plurality of flip-flop circuits connected to said high-voltage transistor and storing the same information as that stored in said low-voltage side set value holding section.

6. a low-voltage side shift register configured by cascading a plurality of flip-flops, in which a data signal of the low-voltage side setting value holding unit is recorded in the flip-flop in response to an internal clock signal, and the recorded data is moved to an adjacent flip-flop every time the data signal is stored in the flip-flop; The second level shift unit is a high-side shift register configured by cascading a plurality of flip-flops, in which a data signal of the low-side shift register is recorded in the flip-flop in response to the internal clock signal, and the recorded data is moved to an adjacent flip-flop every time the data signal is stored in the flip-flop; 2. The semiconductor module according to claim 1, further comprising a plurality of high-voltage transistors arranged between said low-voltage side shift register and said high-voltage side shift register, said high-voltage transistors being driven in accordance with said internal clock signal and a data signal of said low-voltage side shift register.

7. 7. The semiconductor module according to claim 1, wherein the first and second switch elements correspond to SiC MOSFETs.

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