Oscillator circuit

Abstract

To provide an oscillator circuit capable of generating a rectangle wave AC signal with a duty ratio of approximately 50%.SOLUTION: An oscillator circuit includes: a ring oscillator; a first transistor having a gate end connected to an output end of the ring oscillator and a drain end connected to a first node; a second transistor having a drain end and a gate end connected to the first node; a third transistor having a gate end connected to the first node and a drain end connected to a second node; a fourth transistor having a gate end connected to the first node and a drain end connected to a third node; a fifth transistor having a drain end connected to the second node and a source end connected to the third node; and a buffer having an input end connected to the second node.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The embodiment relates to an oscillator circuit. [Background technology]

[0002] As an oscillator for driving a charge pump circuit, an oscillation circuit using a ring oscillator is known. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2011-61462 [Patent Document 2] Patent Publication No. 11-150467 [Patent Document 3] Patent Publication No. 2001-292056 Summary of the Invention [Problem to be solved by the invention]

[0004] An oscillator circuit capable of generating a square wave AC signal with a duty ratio of approximately 50% is provided. [Means for solving the problem]

[0005] The oscillator circuit according to the embodiment includes a ring oscillator, a first transistor having a gate terminal connected to an output terminal of the ring oscillator and a drain terminal connected to a first node, a second transistor having a drain terminal and a gate terminal connected to the first node, a third transistor having a gate terminal connected to the first node and a drain terminal connected to a second node, a fourth transistor having a gate terminal connected to the first node and a drain terminal connected to a third node, a fifth transistor having a drain terminal connected to the second node and a source terminal connected to the third node, and a buffer having an input terminal connected to the second node. [Brief description of the drawings]

[0006] [Figure 1] FIG. 1 is a block diagram showing an example of the configuration of a semiconductor device using an oscillator circuit according to an embodiment. [Diagram 2] FIG. 2 is a circuit diagram showing an example of a configuration of an oscillator circuit according to an embodiment. [Diagram 3] FIG. 3 is a waveform diagram showing an example of the time fluctuation of the voltage applied to each node and the current flowing through each transistor during operation of the oscillator circuit according to the embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Hereinafter, an embodiment will be described with reference to the drawings. In the following description, components having substantially the same functions and configurations are denoted by the same reference numerals. When it is not necessary to distinguish between elements represented by reference numerals containing the same letters, these elements are referred to by reference numerals containing only letters.

[0008] In the following description, when a first element is "connected" to another second element, it includes the first element being indirectly connected to the second element through an intermediate element that is always or selectively conductive, or directly connected to the second element without an intermediate element.

[0009] 1. Configuration 1.1 Overall structure First, the configuration of a semiconductor device using an oscillator circuit according to an embodiment will be described with reference to Fig. 1. Fig. 1 is a block diagram showing an example of the configuration of a semiconductor device using an oscillator circuit according to an embodiment.

[0010] 1, the semiconductor device 100 includes an oscillator circuit 1 and a charge pump circuit 2. The oscillator circuit 1 outputs a square wave AC signal Fr to the charge pump circuit 2. The charge pump circuit 2 operates using the input square wave AC signal Fr as a clock signal. The charge pump circuit 2 boosts an input voltage to a predetermined voltage and outputs a boost signal Vout to the outside of the semiconductor device 100. The semiconductor device 100 is used, for example, in a motor control driver (MCD: Motor Control Driver).

[0011] 1.2 Oscillator circuit configuration Next, the configuration of the oscillator circuit according to the embodiment will be described with reference to Fig. 2. Fig. 2 is a circuit diagram showing an example of the configuration of the oscillator circuit according to the embodiment.

[0012] The oscillator circuit 1 includes transistors 11, 31, 32, 33, 61, 62, 63, and 64, a current source 12, a resistor 13, a capacitor 14, a transistor group 20, an inverter group 40, a capacitor group 50, and a buffer 70. The oscillator circuit 1 generates and outputs an AC signal by utilizing the delay of the inverters.

[0013] The transistors 11, 31, 32, 33, 61, 62, 63, and 64 include, for example, metal oxide semiconductor field effect transistors (MOSFETs). The transistors 11, 31, 32, and 33 include, for example, P-type MOSFETs. The transistors 61, 62, 63, and 64 include, for example, N-type MOSFETs.

[0014] The transistor 11 has a drain terminal and a gate terminal connected to the node N1, and a source terminal and a back gate terminal supplied with a voltage VCC. The voltage VCC is a power supply voltage that drives the oscillator circuit 1.

[0015] The current source 12 has an input terminal connected to the node N1 and an output terminal supplied with a voltage GND, which is a ground voltage, for example 0 V.

[0016] Resistor 13 has a first end connected to node N1 and a second end connected to node N2.

[0017] Capacitor 14 has a first end supplied with voltage VCC and a second end connected to node N2.

[0018] The resistor 13 and the capacitor 14 function together as a low-pass filter. In other words, they attenuate signals above a certain frequency. The resistor 13 and the capacitor 14 suppress high-frequency noise originating from the current source from being superimposed on the inverter group 40.

[0019] The transistor group 20 supplies current to each inverter of the inverter group 40. The transistor group 20 includes n transistors, where n is an odd number equal to or greater than 3. Fig. 2 shows the case where n = 5. The case where n = 5 will be described below.

[0020] The transistor group 20 includes transistors 21, 22, 23, 24, and 25. The transistors 21, 22, 23, 24, and 25 include, for example, P-type MOSFETs.

[0021] Transistor 21 has a drain terminal connected to node N11, a source terminal and a back gate terminal supplied with voltage VCC, and a gate terminal connected to node N2.

[0022] Transistor 22 has a drain terminal connected to node N12, a source terminal and a back gate terminal supplied with voltage VCC, and a gate terminal connected to node N2.

[0023] Transistor 23 has a drain terminal connected to node N13, a source terminal and a back gate terminal supplied with voltage VCC, and a gate terminal connected to node N2.

[0024] Transistor 24 has a drain terminal connected to node N14, a source terminal and a back gate terminal supplied with voltage VCC, and a gate terminal connected to node N2.

[0025] Transistor 25 has a drain terminal connected to node N15, a source terminal and a back gate terminal supplied with voltage VCC, and a gate terminal connected to node N2.

[0026] Transistor 31 has a drain terminal connected to node N3, a source terminal and a back gate terminal supplied with voltage VCC, and a gate terminal connected to node N2.

[0027] Transistor 32 has a drain terminal connected to node N4, a source terminal supplied with voltage VCC, and a gate terminal connected to node N2.

[0028] The transistor 33 has a drain terminal connected to a node N5, a source terminal connected to a node N4, a gate terminal connected to a node N2, and a back gate terminal supplied with a voltage VCC.

[0029] The transistors 11, 21, 22, 23, 24, 25, 31, 32, and 33 configure a current mirror CMC1. The current mirror CMC1 mirrors the current flowing through the transistor 11 and determines the currents flowing through the transistors 21, 22, 23, 24, 25, 31, 32, and 33.

[0030] The inverter group 40 includes inverters in the same number as the number n of transistors included in the transistor group 20. In the example shown in Fig. 2, five inverters are included. This case will be described below.

[0031] The inverter group 40 includes inverters 41, 42, 43, 44, and 45. The outputs of the inverters 41, 42, 43, 44, and 45 are input to other inverters, and are connected in this order in a ring shape. Hereinafter, for a particular inverter, the inverter that is the input source of a signal is called the "previous stage" inverter, and the inverter that is the output destination of the signal is called the "next stage" inverter.

[0032] The inverter 41 includes, for example, transistors 41a and 41b. The transistors 41a and 41b include, for example, N-type MOSFETs. The transistor 41a includes a drain terminal and a gate terminal connected to a node N11, a source terminal connected to a node N12, and a back gate terminal supplied with a voltage GND. The transistor 41b includes a drain terminal connected to the node N12, a source terminal and a back gate terminal supplied with a voltage GND, and a gate terminal connected to the node N11.

[0033] The inverter 42 includes, for example, transistors 42a and 42b. The transistors 42a and 42b include, for example, N-type MOSFETs. The transistor 42a includes a drain terminal and a gate terminal connected to the node N12, a source terminal connected to the node N13, and a back gate terminal supplied with the voltage GND. The transistor 42b includes a drain terminal connected to the node N13, a source terminal and a back gate terminal supplied with the voltage GND, and a gate terminal connected to the node N12.

[0034] The inverter 43 includes, for example, transistors 43a and 43b. The transistors 43a and 43b include, for example, N-type MOSFETs. The transistor 43a includes a drain terminal and a gate terminal connected to a node N13, a source terminal connected to a node N14, and a back gate terminal supplied with a voltage GND. The transistor 43b includes a drain terminal connected to the node N14, a source terminal and a back gate terminal supplied with a voltage GND, and a gate terminal connected to the node N13.

[0035] The inverter 44 includes, for example, transistors 44a and 44b. The transistors 44a and 44b include, for example, N-type MOSFETs. The transistor 44a includes a drain terminal and a gate terminal connected to a node N14, a source terminal connected to a node N15, and a back gate terminal supplied with a voltage GND. The transistor 44b includes a drain terminal connected to the node N15, a source terminal and a back gate terminal supplied with a voltage GND, and a gate terminal connected to the node N14.

[0036] The inverter 45 includes, for example, transistors 45a and 45b. The transistors 45a and 45b include, for example, N-type MOSFETs. The transistor 45a includes a drain terminal and a gate terminal connected to a node N15, a source terminal connected to a node N11, and a back gate terminal supplied with a voltage GND. The transistor 45b includes a drain terminal connected to the node N11, a source terminal and a back gate terminal supplied with a voltage GND, and a gate terminal connected to the node N15.

[0037] Of the transistors included in the inverter group 40, the transistors 41a, 42a, 43a, 44a, and 45a function as pull-up resistors, while the transistors 41b, 42b, 43b, 44b, and 45b function as switches that determine the output of the inverters.

[0038] Each of the inverters 41, 42, 43, 44, and 45 inverts a signal input from the previous inverter and outputs it to the next inverter. That is, when an "H" (High) level voltage is input from the previous inverter, an "L" (Low) level voltage is output to the next inverter. When an "L" level voltage is input from the previous inverter, an "H" level voltage is output to the next inverter.

[0039] The capacitor group 50 includes one less transistor than the number n of transistors included in the transistor group 20. In the example shown in Fig. 2, the capacitor group 50 includes four transistors. This case will be described below.

[0040] The capacitor group 50 includes, for example, transistors 51, 52, 53, and 54. The transistors 51, 52, 53, and 54 include, for example, MOSFETs.

[0041] The transistor 51 is a replica transistor in which the drain terminal and the source terminal are shorted. The transistor 51 has a drain terminal, a source terminal, and a back gate terminal to which a voltage GND is supplied, and a gate terminal connected to a node N12. The transistor 51 functions as a capacitor having capacitance between the gate terminal and the drain terminal, and between the gate terminal and the source terminal. The gate-drain capacitance of the transistor 51 is approximately equal to the gate-drain capacitance of a transistor 61, which will be described later. The gate-source capacitance of the transistor 51 is approximately equal to the gate-source capacitance of a transistor 61, which will be described later.

[0042] The transistor 52 is a replica transistor in which the drain terminal and the source terminal are shorted. The transistor 52 has a drain terminal, a source terminal, and a back gate terminal to which a voltage GND is supplied, and a gate terminal connected to a node N13. The transistor 52 functions as a capacitor having capacitance between the gate terminal and the drain terminal, and between the gate terminal and the source terminal. The gate-drain capacitance of the transistor 52 is approximately equal to the gate-drain capacitance of a transistor 61, which will be described later. The gate-source capacitance of the transistor 52 is approximately equal to the gate-source capacitance of a transistor 61, which will be described later.

[0043] The transistor 53 is a replica transistor in which the drain terminal and the source terminal are shorted. The transistor 53 has a drain terminal, a source terminal, and a back gate terminal to which a voltage GND is supplied, and a gate terminal connected to a node N14. The transistor 53 functions as a capacitor having capacitance between the gate terminal and the drain terminal, and between the gate terminal and the source terminal. The gate-drain capacitance of the transistor 53 is approximately equal to the gate-drain capacitance of a transistor 61, which will be described later. The gate-source capacitance of the transistor 53 is approximately equal to the gate-source capacitance of a transistor 61, which will be described later.

[0044] The transistor 54 is a replica transistor in which the drain terminal and the source terminal are shorted. The transistor 54 has a drain terminal, a source terminal, and a back gate terminal to which a voltage GND is supplied, and a gate terminal connected to a node N15. The transistor 54 functions as a capacitor having capacitance between the gate terminal and the drain terminal, and between the gate terminal and the source terminal. The gate-drain capacitance of the transistor 54 is approximately equal to the gate-drain capacitance of a transistor 61, which will be described later. The gate-source capacitance of the transistor 54 is approximately equal to the gate-source capacitance of a transistor 61, which will be described later.

[0045] The inverter group 40 and the capacitor group 50 function together as a ring oscillator RO. The ring oscillator RO outputs a clock signal having an amplitude voltage V0. The voltage V0 is the voltage VCC minus the voltage drop due to the load capacitance inside the ring oscillator RO.

[0046] The transistor 61 has a drain terminal connected to the node N3, a source terminal supplied with a voltage GND, and a gate terminal connected to a node N11. The threshold voltage of the transistor 61 is expressed as α×V0, where α is a constant satisfying 0<α<1, and V0 is an amplitude voltage of the ring oscillator RO. For example, α=0.8.

[0047] Transistor 62 has a drain terminal and a gate terminal connected to node N3, and a source terminal and a back gate terminal supplied with voltage GND.

[0048] The transistor 63 has a drain terminal connected to a node N4, a source terminal and a back gate terminal supplied with a voltage GND, and a gate terminal connected to a node N3.

[0049] Transistor 64 has a drain terminal connected to node N5, a source terminal and a back gate terminal supplied with voltage GND, and a gate terminal connected to node N3.

[0050] The transistors 62, 63, and 64 configure a current mirror CMC2. The current mirror CMS2 mirrors the current flowing through the transistor 62 and determines the current flowing through the transistors 63 and 64.

[0051] The buffer 70 has an input terminal connected to the node N5 and an output terminal connected to a node N7. The buffer 70 shapes an input AC signal (for example, a trapezoidal wave) and outputs a square wave AC signal Fr to the charge pump circuit 2.

[0052] The buffer 70 includes, for example, inverters 71 and 72. Each of the inverters 71 and 72 inverts and outputs an input signal. That is, each of the inverters 71 and 72 outputs a voltage of an "L" level when a voltage of an "H" level is input, and outputs a voltage of an "H" level when a voltage of an "L" level is input.

[0053] The inverter 71 includes, for example, transistors 71a and 71b. The transistor 71a includes, for example, a P-type MOSFET. The transistor 71a includes a drain terminal connected to a node N6, a source terminal and a back gate terminal supplied with a voltage VCC, and a gate terminal connected to a node N5. The transistor 71b includes, for example, an N-type MOSFET. The transistor 71b includes a drain terminal connected to a node N6, a source terminal and a back gate terminal supplied with a voltage GND, and a gate terminal connected to a node N5.

[0054] The inverter 72 includes, for example, transistors 72a and 72b. The transistor 72a includes, for example, a P-type MOSFET. The transistor 72a includes a drain terminal connected to a node N7, a source terminal and a back gate terminal supplied with a voltage VCC, and a gate terminal connected to a node N6. The transistor 72b includes, for example, an N-type MOSFET. The transistor 72b includes a drain terminal connected to the node N7, a source terminal supplied with a voltage GND, and a gate terminal and a back gate terminal connected to the node N6.

[0055] The buffer 70 has a threshold voltage of VCC / 2, which is half the power supply voltage VCC. That is, when the voltage of the node N5 is higher than VCC / 2, the buffer 70 outputs VCC, and when the voltage of the node N5 is lower than VCC / 2, the buffer 70 outputs GND.

[0056] 2.Operation The operation of the oscillator circuit according to the embodiment will be described with reference to FIG. 3. FIG. 3 is a waveform diagram showing an example of the time fluctuation of the voltage applied to each node and the current flowing through each transistor during the operation of the oscillator circuit according to the embodiment. Part (a) of FIG. 3 shows the time fluctuation of the voltage applied to node N11, which is the output signal of the ring oscillator RO. Part (b) of FIG. 3 shows the time fluctuation of the voltage applied to node N3. Part (c) of FIG. 3 shows the time fluctuation of the voltage applied to node N4. Part (d) of FIG. 3 shows the time fluctuation of the voltage applied to node N6. Part (e) of FIG. 3 shows the time fluctuation of the voltage applied to node N7. Part (f) of FIG. 3 shows the time fluctuation of the drain current flowing through transistor 33. Part (g) of FIG. 3 shows the time fluctuation of the drain current flowing through transistor 64.

[0057] When a current flows through the inverter group 40, each inverter outputs a voltage of "H" level and a voltage of "L" level alternately at a constant period T. That is, the ring oscillator RO generates a clock output. The voltage applied to the node N11, which is the output end of the ring oscillator RO, fluctuates as shown in part (a) of FIG.

[0058] 3A, the waveform of the voltage applied to the node N11 shows an asymmetric shape at the time of the voltage rise and fall. Specifically, the voltage rises slowly at the time of the voltage rise, but drops quickly at the time of the voltage fall. This is because, at the time of the voltage rise, the parasitic capacitance of the capacitor group 50 and the transistor 61 is charged in each stage of the inverter group 40, and the voltage rise is slowed down.

[0059] 3(a), in the same oscillation cycle, the time when the voltage applied to the node N11 rises to α×V0 is defined as t1, and the time when the voltage applied to the node N11 falls to GND is defined as t3.

[0060] In the period before time t1, as shown in parts (b), (c), and (d) of Figure 3, voltage VCC is applied to node N3, voltage V1 is applied to node N4, and GND is applied to node N5. At this time, transistor 32 is in a pinch-off state because the potential difference between its drain and source is large, and voltage V1 is a voltage that is lower than power supply voltage VCC by the pinch-off voltage of transistor 32 (e.g., 0.4 V).

[0061] At time t1, the voltage of node N3 drops rapidly to GND, as shown in part (b) of FIG. 3. At this time, the pinch-off state of transistor 32 is released, and the voltage of node N4 rises rapidly to VCC, as shown in part (c) of FIG. 3. As a result, at time t1, the voltage of node N5 is GND, and a potential difference VCC occurs between the drain and source of transistor 33, so that a drain current of magnitude ICC flows through transistor 33, as shown in part (f) of FIG. 3. The drain current of transistor 33 becomes a source current to the input terminal of buffer 70, and the voltage of node N5 gradually rises from time t1, as shown in part (d) of FIG. 3.

[0062] In the same oscillation cycle, the time when the voltage of node N5 rises to VCC for the first time after time t1 is defined as t2. At time t2, the potential difference between the drain and source of transistor 33 disappears, and the drain current flowing through transistor 33 stops, as shown in part (f) of FIG.

[0063] During the period from time t2 to time t3, as shown in parts (b), (c), and (d) of FIG. 3, GND is applied to node N3, and voltage VCC is applied to nodes N4 and N5.

[0064] At time t3, the drain and source terminals of the transistor 61 are insulated, so that the voltage of the node N3 starts to gradually rise, as shown in part (b) of FIG. 3. Since the transistors 62, 63, and 64 form a current mirror CMC2, a current corresponding to the voltage fluctuation of the node N3 flows through each transistor. As a result, the voltage of the node N4 gradually drops, as shown in part (c) of FIG. 3. Also, at time t3, the voltage of the node N5 is VCC, and a potential difference VCC occurs between the drain and source of the transistor 64, so that a drain current of magnitude ICC flows through the transistor 64, as shown in part (f) of FIG. 3. The drain current of the transistor 64 becomes a sink current for the input terminal of the buffer 70, so that the voltage of the node N5 gradually drops from time t3, as shown in part (d) of FIG. 3.

[0065] In the same oscillation cycle, the time when the voltage of node N5 drops to GND for the first time after time t3 is defined as t4. At time t4, the potential difference between the drain and source of transistor 64 disappears, and the drain current flowing through transistor 64 stops, as shown in part (f) of FIG. 3. Note that, as shown in part (b) of FIG. 3, the voltage of node N3 rises to VCC before and after time t4. Also, as shown in part (c) of FIG. 3, the voltage of node N4 drops to V1 before time t4 and maintains voltage V1 thereafter. Thus, the potential state of each node is reset to the state before the voltage of node N11 began to rise.

[0066] The magnitude ICC of the drain current flowing through transistor 33 and the potential difference between the drain and source from time t1 to t2 are equal to the magnitude ICC of the drain current flowing through transistor 64 and the potential difference between the drain and source from time t3 to t4. Therefore, the length of the period from time t1 to t2 is equal to the length of the period from time t3 to t4. Therefore, at node N5 shown in part (d) of FIG. 3, the slew rate during the voltage rise from time t1 to t2 and the slew rate during the voltage drop from time t3 to t4 are equal.

[0067] When the voltage fluctuation at node N5 shown in part (d) of Fig. 3 is input to the buffer 70, a square wave signal shown in part (e) of Fig. 3 is output. The period T' of the output square wave signal is approximately equal to the output period T of the inverter group 40. Also, the period (A) during which the output voltage is VCC and the period (B) during which the output voltage is GND, shown in part (e) of Fig. 3, are approximately equal.

[0068] 3. Effects The configuration according to this embodiment can provide an oscillator circuit capable of generating a square wave AC signal with a duty ratio of approximately 50% without using a frequency divider, etc. The effect of this embodiment will be described in detail.

[0069] In the configuration according to the present embodiment, a current mirror circuit is connected to the clock output, and the output of the current mirror circuit is received at the upstream and downstream of the node N5. With this configuration, the source current flowing through the transistor 33 connected upstream of the node N5 and the sink current flowing through the transistor 64 connected downstream of the node N5 are equal in magnitude, so that the slew rate at the time of voltage rise and the slew rate at the time of voltage fall in the output clock signal are approximately equal. Therefore, the duty ratio of the square wave AC signal Fr obtained by shaping this clock signal is adjusted to approximately 50%. This makes it possible to satisfy the characteristics of a system whose behavior depends on the duty ratio of the input clock signal, such as a charge pump. In addition, since the duty ratio of the clock signal can be adjusted to approximately 50% without adding a frequency divider or the like, it is possible to suppress an increase in power consumption and an increase in chip area.

[0070] Furthermore, in the configuration according to this embodiment, the output end of the current mirror connected upstream of node N5 is connected to the middle part of two-stage transistors 32 and 33, so that when the voltage of node N5 drops, the voltage is controlled to drop to GND. This suppresses the phenomenon in which the duty ratio does not become uniform at approximately 50% due to the voltage of node N5 not dropping completely to GND.

[0071] In addition, in a configuration in which the duty ratio is adjusted to 50% without using a frequency divider, the duty ratio of the clock signal output from the ring oscillator is required to be 50%. In the configuration according to this embodiment, transistors 51, 52, 53, and 54 having the same capacitance as the gate-drain capacitance and gate-source capacitance of the transistor 61 connected to the output terminal of the inverter group are connected as replicas to each stage of the inverter group 40. With this configuration, the load capacitance is adjusted to the same level in each stage of the inverter group 40, so that the duty ratio of the signal output from the ring oscillator RO can be corrected to approximately 50%.

[0072] 4. Modifications The oscillator circuit 1 according to the embodiment described above can be modified in various ways. Modifications are shown below.

[0073] The configuration of the inverters 41, 42, 43, 44, 45, 71, and 72 in the oscillator circuit 1 is not limited to that described in this embodiment. For example, the inverters 41, 42, 43, 44, and 45 may be composed of P-type MOSFETs and N-type MOSFETs.

[0074] 5. Other Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0075] 1. Oscillation circuit 2. Charge pump circuit 11, 21, 22, 23, 24, 25, 31, 32, 33, 41a, 41b, 42a, 42b, 43a, 43b, 44a, 44b, 45a, 45b, 51, 52, 53, 54, 61, 62, 63, 64, 71a, 71b, 72a, 72b...Transistors 12…Current source 13. Resistance 14…Capacitor 20...Transistor group 40...Inverter group 41, 42, 43, 44, 45, 71, 72...Inverter 50...Capacitor group 70…Buffer 100...Semiconductor device RO...Ring oscillator

Claims

1. A ring oscillator and a first transistor having a gate terminal connected to the output terminal of the ring oscillator and a drain terminal connected to a first node; a second transistor having a drain terminal and a gate terminal connected to the first node; a third transistor having a gate terminal connected to the first node and a drain terminal connected to the second node; a fourth transistor having a gate terminal connected to the first node and a drain terminal connected to a third node; a fifth transistor having a drain terminal connected to the second node and a source terminal connected to the third node; a buffer having an input connected to the second node; An oscillator circuit comprising:

2. a sixth transistor having a drain terminal connected to the third node; 2. The oscillator circuit according to claim 1.

3. a seventh transistor having a drain terminal and a gate terminal connected to the fourth node; a current source having a first end connected to the fourth node; Further comprising: a gate terminal of the fifth transistor and a gate terminal of the sixth transistor are connected to the fourth node; 3. The oscillator circuit according to claim 2.

4. the first transistor, the second transistor, the third transistor, and the fourth transistor have a first conductivity type; the fifth transistor, the sixth transistor, and the seventh transistor have a second conductivity type different from the first conductivity type; 4. The oscillator circuit according to claim 3.

5. The ring oscillator comprises: a first inverter, a second inverter, and a third inverter; a first capacitor and a second capacitor; Including, the first inverter has an input connected to a fifth node and an output connected to a sixth node; the second inverter has an input connected to the sixth node and an output connected to a seventh node; the third inverter has an input connected to the seventh node and an output connected to the fifth node; the first capacitor has a first end connected to the sixth node and a second end connected to ground; the second capacitor has a first end connected to the seventh node and a second end connected to ground; the first transistor has a gate terminal connected to the fifth node; 2. The oscillator circuit according to claim 1.

6. the first capacitor includes an eighth transistor having a gate terminal connected to the sixth node, and a drain terminal and a source terminal grounded; the second capacitor includes a ninth transistor having a gate terminal connected to the sixth node, and a drain terminal and a source terminal grounded; 6. The oscillator circuit according to claim 5.

7. a gate-source capacitance of the eighth transistor and a gate-source capacitance of the ninth transistor are each substantially equal to a gate-source capacitance of the first transistor; a gate-drain capacitance of the eighth transistor and a gate-drain capacitance of the ninth transistor are each substantially equal to a gate-drain capacitance of the first transistor; 7. The oscillator circuit according to claim 6.

8. the second inverter includes an odd number of inverters; 6. The oscillator circuit according to claim 5.

9. A ring oscillator and a current mirror circuit having an input terminal connected to the output terminal of the ring oscillator, a first output terminal, and a second output terminal; a buffer having an input terminal to which a source current based on a first current flowing through the first output terminal of the current mirror circuit and a sink current based on a second current flowing through the second output terminal of the current mirror circuit are input; Equipped with The magnitude of the source current and the magnitude of the sink current are approximately equal. Oscillator circuit.

10. The first output terminal of the current mirror circuit is Connected between two series-connected transistors, 10. The oscillator circuit according to claim 9.

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