Multilayer electronic component and method for manufacturing multilayer electronic component

Abstract

To provide a multilayer electronic component in which a phenomenon of electrical field being concentrated in an end of an internal electrode is reduced, and a method for manufacturing the same.SOLUTION: A multilayer electronic component according to one embodiment of the present invention includes: a body which includes a plurality of dielectric layers, a first internal electrode, a second internal electrode 122, and margin patterns 123, 124, the first and second internal electrodes being alternately disposed in a first direction with the dielectric layer interposed therebetween, the margin pattern being disposed in a position different from the first and second internal electrodes in the first direction and being disposed so as not to overlap the first internal electrode or the second internal electrode in the first direction; and a first external electrode and a second external electrode 132 which are disposed on the body.SELECTED DRAWING: Figure 6

Description

[Technical field]

[0001] The present invention relates to a multilayer electronic component and a method for manufacturing a multilayer electronic component. [Background technology]

[0002] Multilayer ceramic capacitors (MLCCs), which are one type of multilayer electronic component, are chip-type capacitors that are mounted on printed circuit boards of various electronic products, such as visual devices such as liquid crystal displays (LCDs) and plasma display panels (PDPs), computers, smartphones, mobile phones, and circuits such as on-board chargers (OBCs) and DC-DC converters for electric vehicles, to charge or discharge electricity.

[0003] Multilayer ceramic capacitors have the advantages of being small yet having high capacitance and being easy to mount, and therefore can be used as components of various electronic devices. As various electronic devices such as computers and mobile devices become smaller and have higher output, there is an increasing demand for smaller multilayer ceramic capacitors with higher capacitance.

[0004] With the trend toward miniaturization and high capacitance of multilayer ceramic capacitors, it is becoming increasingly important to increase the capacitance per unit volume of the multilayer ceramic capacitor. As a solution for achieving miniaturization and high capacitance of the multilayer ceramic capacitor, there have been attempts to reduce the thickness of the internal electrodes and increase the number of layers.

[0005] In addition, as applications in automotive electrical components and the like increase, high reliability in various environments is required. In order to ensure high reliability, it is important to improve the connectivity and thickness uniformity of the internal electrodes and disperse the concentration of the electric field. In addition, excellent high-temperature load life is required to ensure high reliability in various environments.

[0006] However, when the thickness of the internal electrodes is reduced and the number of layers is increased, the internal electrodes may bend or aggregate due to a step between a capacitance forming portion and a margin portion of the multilayer ceramic capacitor, which may cause a problem of reduced connectivity of the internal electrodes.In addition, when the thickness of the internal electrodes is reduced and the number of layers is increased, the distance between the internal electrodes may decrease, which may cause a reduction in the breakdown voltage (BDV) of the multilayer ceramic capacitor.

[0007] In addition, the phenomenon of electric field concentration at the ends of the internal electrodes may become more severe as the internal electrodes or dielectric layers become thinner, and may become even more severe when a high voltage is applied. This phenomenon of electric field concentration at the ends of the internal electrodes may be another cause of a decrease in the breakdown voltage (BDV) of the multilayer ceramic capacitor. Summary of the Invention [Problem to be solved by the invention]

[0008] One of the problems to be solved by the present invention is to provide a multilayer electronic component in which the phenomenon of electric field concentration at the ends of internal electrodes is alleviated.

[0009] One of the problems to be solved by the present invention is to provide a multilayer electronic component in which the step between a capacitance forming portion and a margin portion is reduced.

[0010] One of the problems to be solved by the present invention is to provide a multilayer electronic component having improved capacitance.

[0011] One of the problems to be solved by the present invention is to provide a multilayer electronic component having an excellent high-temperature accelerated life.

[0012] However, the problem to be solved by the present invention is not limited to the above, and can be more easily understood in the course of describing specific embodiments of the present invention. [Means for solving the problem]

[0013] A multilayer electronic component according to one embodiment of the present invention includes a plurality of dielectric layers, a first internal electrode, a second internal electrode, and a margin pattern, the first and second internal electrodes being arranged alternately in a first direction with the dielectric layers in between, and the margin pattern being arranged at a position different from the first and second internal electrodes along the first direction, and the multilayer electronic component may include a main body arranged so as not to overlap the first internal electrodes or the second internal electrodes in the first direction, and an external electrode arranged on the main body.

[0014] A method for manufacturing a multilayer electronic component according to one embodiment of the present invention may include a lamination step of alternately laminating a first sheet having a first pattern arranged on a first ceramic sheet and a second sheet having a second pattern arranged on a second ceramic sheet in a first direction, and disposing a third sheet having a third pattern arranged on a third ceramic sheet between the first sheet and the second sheet, and laminating the sheets so that the third pattern does not overlap with the first pattern or the second pattern to obtain a laminate; a sintering step of sintering the laminate to obtain a main body; and a step of forming external electrodes on the main body. Effect of the Invention

[0015] One of the various effects of the present invention is that the phenomenon of electric field concentration at the ends of the internal electrodes can be alleviated by adjusting the position and shape of the margin pattern.

[0016] One of the various effects of the present invention is that it is possible to provide a multilayer electronic component in which the step between the capacitance forming portion and the margin portion is reduced by adjusting the position and shape of the margin pattern.

[0017] One of the various effects of the present invention is that the capacitance of the multilayer electronic component can be improved.

[0018] One of the various effects of the present invention is that it is possible to improve the high temperature load life of a multilayer electronic component.

[0019] However, the various and beneficial advantages and effects of the present invention are not limited to the above, and can be more easily understood in the course of describing specific embodiments of the present invention. [Brief description of the drawings]

[0020] [Figure 1] 1 is a schematic perspective view of a multilayer electronic component according to an embodiment of the present invention; [Figure 2a] FIG. 2 is a plan view illustrating an internal electrode and a margin pattern of the multilayer electronic component according to the embodiment. [Figure 2b] FIG. 2 is a plan view illustrating an internal electrode and a margin pattern of the multilayer electronic component according to the embodiment. [Figure 2c] FIG. 2 is a plan view illustrating an internal electrode and a margin pattern of the multilayer electronic component according to the embodiment. [Figure 2d] FIG. 2 is a plan view illustrating an internal electrode and a margin pattern of the multilayer electronic component according to the embodiment. [Diagram 3] 2 is a schematic cross-sectional view taken along line II' of FIG. 1; [Figure 4] 2 is a schematic cross-sectional view taken along line II-II' in FIG. 1; [Diagram 5] 2 is a schematic cross-sectional view taken along line III-III' in FIG. 1. [Figure 6] 4 is a schematic cross-sectional view taken along line IV-IV' in FIG. [Figure 7] 1 is a plan view illustrating a state in which internal electrodes are arranged on a ceramic sheet according to an embodiment of the present invention; [Figure 8] FIG. 2 is a plan view illustrating a state in which a margin pattern is arranged on a ceramic sheet according to an embodiment. [Figure 9a] FIG. 2 is a plan view illustrating an internal electrode and a margin pattern according to an embodiment; [Figure 9b]FIG. 2 is a plan view illustrating an internal electrode and a margin pattern according to an embodiment; [Figure 9c] FIG. 2 is a plan view illustrating an internal electrode and a margin pattern according to an embodiment; [Figure 9d] FIG. 2 is a plan view illustrating an internal electrode and a margin pattern according to an embodiment; [Figure 10a] FIG. 2 is a plan view illustrating an internal electrode and a margin pattern according to an embodiment; [Figure 10b] FIG. 2 is a plan view illustrating an internal electrode and a margin pattern according to an embodiment; [Figure 10c] FIG. 2 is a plan view illustrating an internal electrode and a margin pattern according to an embodiment; [Figure 10d] FIG. 2 is a plan view illustrating an internal electrode and a margin pattern according to an embodiment; [Figure 11a] FIG. 2 is a plan view illustrating an internal electrode and a margin pattern according to an embodiment; [Figure 11b] FIG. 2 is a plan view illustrating an internal electrode and a margin pattern according to an embodiment; [Figure 11c] FIG. 2 is a plan view illustrating an internal electrode and a margin pattern according to an embodiment; [Figure 11d] FIG. 2 is a plan view illustrating an internal electrode and a margin pattern according to an embodiment; [Figure 12a] FIG. 2 is a plan view illustrating an internal electrode and a margin pattern according to an embodiment; [Figure 12b] FIG. 2 is a plan view illustrating an internal electrode and a margin pattern according to an embodiment; [Figure 12c] FIG. 2 is a plan view illustrating an internal electrode and a margin pattern according to an embodiment; [Figure 12d] FIG. 2 is a plan view illustrating an internal electrode and a margin pattern according to an embodiment; [Figure 13a] FIG. 2 is a plan view illustrating an internal electrode and a margin pattern according to an embodiment; [Figure 13b]FIG. 2 is a plan view illustrating an internal electrode and a margin pattern according to an embodiment; [Figure 13c] FIG. 2 is a plan view illustrating an internal electrode and a margin pattern according to an embodiment; [Figure 13d] FIG. 2 is a plan view illustrating an internal electrode and a margin pattern according to an embodiment; [Figure 14a] FIG. 2 is a plan view illustrating an internal electrode and a margin pattern according to an embodiment; [Figure 14b] FIG. 2 is a plan view illustrating an internal electrode and a margin pattern according to an embodiment; [Figure 14c] FIG. 2 is a plan view illustrating an internal electrode and a margin pattern according to an embodiment; [Figure 14d] FIG. 2 is a plan view illustrating an internal electrode and a margin pattern according to an embodiment; [Figure 15a] FIG. 2 is a plan view illustrating an internal electrode and a margin pattern according to an embodiment; [Figure 15b] FIG. 2 is a plan view illustrating an internal electrode and a margin pattern according to an embodiment; [Figure 15c] FIG. 2 is a plan view illustrating an internal electrode and a margin pattern according to an embodiment; [Figure 15d] FIG. 2 is a plan view illustrating an internal electrode and a margin pattern according to an embodiment; [Figure 16a] FIG. 2 is a plan view illustrating an internal electrode and a margin pattern according to an embodiment; [Figure 16b] FIG. 2 is a plan view illustrating an internal electrode and a margin pattern according to an embodiment; [Figure 16c] FIG. 2 is a plan view illustrating an internal electrode and a margin pattern according to an embodiment; [Figure 16d] FIG. 2 is a plan view illustrating an internal electrode and a margin pattern according to an embodiment; [Figure 17a] FIG. 2 is a plan view illustrating an internal electrode and a margin pattern according to an embodiment; [Figure 17b]FIG. 2 is a plan view illustrating an internal electrode and a margin pattern according to an embodiment; [Figure 17c] FIG. 2 is a plan view illustrating an internal electrode and a margin pattern according to an embodiment; [Figure 17d] FIG. 2 is a plan view illustrating an internal electrode and a margin pattern according to an embodiment; [Figure 18a] FIG. 2 is a plan view illustrating an internal electrode and a margin pattern according to an embodiment; [Figure 18b] FIG. 2 is a plan view illustrating an internal electrode and a margin pattern according to an embodiment; [Figure 18c] FIG. 2 is a plan view illustrating an internal electrode and a margin pattern according to an embodiment; [Figure 18d] FIG. 2 is a plan view illustrating an internal electrode and a margin pattern according to an embodiment; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0021] Hereinafter, the embodiments of the present invention will be described with reference to specific embodiments and the accompanying drawings. However, the embodiments of the present invention can be modified into various other forms, and the scope of the present invention is not limited to the embodiments described below. Furthermore, the embodiments of the present invention are provided to more completely explain the present invention to those skilled in the art. Therefore, the shapes and sizes of elements in the drawings may be exaggerated for clearer explanation, and elements indicated by the same reference numerals in the drawings are the same elements.

[0022] In order to clearly explain the present invention in the drawings, parts that are not relevant to the explanation are omitted, and the size and thickness of each component shown in the drawings are arbitrarily shown for convenience of explanation, so the present invention is not necessarily limited to those shown in the drawings. Components that have the same function within the same concept are described using the same reference numerals. Furthermore, throughout the specification, when a part is said to "include" a certain component, this does not exclude other components, but means that the part may further include other components, unless otherwise specified to the contrary.

[0023] In the drawings, the first direction can be defined as the stacking direction or thickness T direction, the second direction can be defined as the length L direction, and the third direction can be defined as the width W direction.

[0024] Multilayer Electronic Components FIG. 1 is a schematic perspective view of a multilayer electronic component according to one embodiment of the present invention, FIGS. 2a, 2b, 2c, and 2d are plan views each showing an internal electrode and margin pattern of a multilayer electronic component according to one embodiment, FIG. 3 is a schematic cross-sectional view taken along line I-I' in FIG. 1, FIG. 4 is a schematic cross-sectional view taken along line II-II' in FIG. 1, FIG. 5 is a schematic cross-sectional view taken along line III-III' in FIG. 1, and FIG. 6 is a schematic cross-sectional view taken along line IV-IV' in FIG. 1.

[0025] A multilayer electronic component 100 according to one embodiment of the present invention will be described in detail below with reference to Figures 1 to 6. Also, a multilayer ceramic capacitor (hereinafter referred to as "MLCC") will be described as an example of the multilayer electronic component, but the present invention is not limited thereto and can also be applied to various multilayer electronic components that use ceramic materials, such as inductors, piezoelectric elements, varistors, thermistors, and the like.

[0026] A multilayer electronic component 100 according to one embodiment of the present invention includes a plurality of dielectric layers 111, a first internal electrode 121, a second internal electrode 122, and margin patterns 123, 124, the first and second internal electrodes being alternately arranged in a first direction sandwiching the dielectric layers, the margin pattern being arranged at a position different from the first and second internal electrodes 121, 122 along the first direction, and may include a main body 110 arranged so as not to overlap the first internal electrode or the second internal electrode in the first direction, and external electrodes 131, 132 arranged on the main body.

[0027] According to one embodiment of the present invention, the multilayer electronic component includes a plurality of dielectric layers 111, a first internal electrode 121, a second internal electrode 122, and margin patterns 123, 124, and the first and second internal electrodes are arranged alternately in a first direction sandwiching the dielectric layers, and the margin pattern is arranged at a position different from the first and second internal electrodes 121, 122 along the first direction and is arranged so as not to overlap with the first internal electrode or the second internal electrode in the first direction. This makes it possible to mitigate the phenomenon of electric field concentration at the ends of the internal electrodes and to mitigate the step between the capacitance forming portion and the margin portion, thereby improving the capacitance and high temperature load life of the multilayer electronic component.

[0028] Each component of the multilayer electronic component 100 will now be described in detail.

[0029] The body 110 may include a plurality of dielectric layers 111, a first internal electrode 121, a second internal electrode 122, and margin patterns 123, .

[0030] Although there is no particular limitation on the specific shape of the body 110, the body 110 may be hexahedral or a similar shape as shown in the figure. Due to shrinkage of the ceramic powder contained in the body 110 during the firing process, the body 110 may not be a hexahedral shape with perfectly straight lines, but may have a substantially hexahedral shape.

[0031] The main body 110 may have first and second surfaces 1, 2 facing in a first direction, third and fourth surfaces 3, 4 connected to the first and second surfaces 1, 2 and facing in the second direction, and fifth and sixth surfaces 5, 6 connected to the first and second surfaces 1, 2, connected to the third and fourth surfaces 3, 4, and facing in the third direction.

[0032] A marginal region where the internal electrodes 121, 122 are not arranged overlaps the dielectric layer 111, and thus a step occurs due to the thickness of the internal electrodes 121, 122, and the corners connecting the first surface and the third to fifth surfaces and / or the corners connecting the second surface and the third to fifth surfaces may have a shape that is shrunk toward the center in the first direction of the main body 110 when viewed based on the first surface or the second surface. Alternatively, due to the shrinkage behavior during the sintering process of the main body, the corners connecting the first surface 1 and the third to sixth surfaces 3, 4, 5, 6 and / or the corners connecting the second surface 2 and the third to sixth surfaces 3, 4, 5, 6 may have a shape that is shrunk toward the center in the first direction of the main body 110 when viewed based on the first surface or the second surface. Alternatively, in order to prevent chipping defects, the corners connecting each surface of the body 110 may be rounded through a separate process, so that the corners connecting the first surface and the third to sixth surfaces and / or the corners connecting the second surface and the third to sixth surfaces may have a rounded shape.

[0033] On the other hand, in order to suppress steps caused by the internal electrodes 121, 122, if the internal electrodes are cut after stacking so as to be exposed on the fifth and sixth surfaces 5, 6 of the main body, and then a single dielectric layer or two or more dielectric layers are stacked in the third direction (width direction) on both side surfaces of the capacitance forming portion Ac to form margin portions 114, 115, the portions connecting the first surface to the fifth and sixth surfaces, and the portions connecting the second surface to the fifth and sixth surfaces, do not need to have a contracted form.

[0034] The plurality of dielectric layers 111 forming the main body 110 are in a fired state, and the boundaries between adjacent dielectric layers 111 can be integrated to such an extent that they are difficult to confirm without using a scanning electron microscope (SEM). There is no particular limit to the number of laminated dielectric layers, and this can be determined in consideration of the size of the laminated electronic component. For example, the main body can be formed by laminating 400 or more dielectric layers.

[0035] The dielectric layer 111 can be formed by manufacturing a ceramic slurry containing ceramic powder, an organic solvent, and a binder, applying and drying the slurry on a carrier film to provide a ceramic green sheet, and then firing the ceramic green sheet. The ceramic powder is not particularly limited as long as sufficient capacitance can be obtained. For example, barium titanate (BaTiO3)-based powder can be used as the ceramic powder. As a more specific example, the ceramic powder can be one or more of BaTiO3, (Ba 1- xCa x )TiO3 (0 < x < 1), Ba(Ti 1-y Ca y )O3 (0 < y < 1), (Ba 1-x Ca x )(Ti 1-y Zr y )O3 (0 < x < 1, 0 < y < 1), and Ba(Ti 1-y Zr y )O3 (0 < y < 1).

[0036] According to the present invention, even when the thicknesses of the plurality of dielectric layers 111 are thin, it is possible to prevent a decrease in the high-temperature load life. When the thickness of the dielectric layer is thick, the high-temperature load life can be further improved. Therefore, the average thickness td of the dielectric layer 111 does not need to be particularly limited and can be arbitrarily set according to desired characteristics and applications. As a specific example, the average thickness of the dielectric layer 111 may be 300 nm or more and 10 μm or less. Also, the average thickness of at least one or more of the plurality of dielectric layers 111 may be 300 nm or more and 10 μm or less.

[0037] Here, the average thickness of the dielectric layer 111 may refer to the average size in the first direction of the dielectric layer 111 disposed between the internal electrodes 121 and 122. The average thickness of the dielectric layer 111 may be measured by scanning the cross sections of the body 110 in the first and second directions with a scanning electron microscope (SEM) at a magnification of 10,000. More specifically, the thickness may be measured at a number of points of one dielectric layer 111, for example, 30 points equally spaced in the second direction, and an average value may be measured. The 30 equally spaced points may be designated by a capacitance forming unit Ac, which will be described later. Furthermore, if such an average value measurement is extended to 10 dielectric layers 111 and an average value is measured, the average thickness of the dielectric layer 111 may be further generalized.

[0038] The internal electrodes 121, 122 may be arranged alternately with the dielectric layers 111 in the first direction.

[0039] The internal electrodes 121, 122 may include first and second internal electrodes 121, 122. The first and second internal electrodes 121, 122 may be alternately arranged to face each other across the dielectric layer 111 constituting the body 110, and may be connected to the third and fourth surfaces 3, 4 of the body 110, respectively. Specifically, one end of the first internal electrode 121 may be connected to the third surface, and one end of the second internal electrode 122 may be connected to the fourth surface. That is, in one embodiment, the internal electrodes 121, 122 may contact the third surface 3 or the fourth surface 4.

[0040] 2a to 2d, the first internal electrode 121 may be spaced apart from the fourth surface 4 and exposed through the third surface 3, and the second internal electrode 122 may be spaced apart from the third surface 3 and exposed through the fourth surface 4. A first external electrode 130 may be disposed on the third surface 3 of the main body and connected to the first internal electrode 121, and a second external electrode 140 may be disposed on the fourth surface 4 of the main body and connected to the second internal electrode 122.

[0041] That is, the first internal electrode 121 is not connected to the second external electrode 132 but is connected to the first external electrode 131, and the second internal electrode 122 is not connected to the first external electrode 131 but is connected to the second external electrode 132. Therefore, the first internal electrodes 121 may be formed at a certain distance apart on the fourth surface 4, and the second internal electrodes 122 may be formed at a certain distance apart on the third surface 3. At this time, the first and second internal electrodes 121 and 122 may be electrically isolated from each other by the dielectric layer 111 disposed therebetween.

[0042] There are no particular limitations on the material forming the internal electrodes 121 and 122, and any material having excellent electrical conductivity can be used. For example, the internal electrodes 121 and 122 can include one or more of nickel (Ni), copper (Cu), palladium (Pd), silver (Ag), gold (Au), platinum (Pt), tin (Sn), tungsten (W), titanium (Ti), and alloys thereof.

[0043] The internal electrodes 121 and 122 may be formed by printing a conductive paste for internal electrodes, which contains at least one of nickel (Ni), copper (Cu), palladium (Pd), silver (Ag), gold (Au), platinum (Pt), tin (Sn), tungsten (W), titanium (Ti), and alloys thereof, on a ceramic green sheet. The method for printing the conductive paste for internal electrodes may be a screen printing method or a gravure printing method, but the present invention is not limited thereto.

[0044] The average thickness of the internal electrodes 121, 122 is not particularly limited and can be set arbitrarily according to the desired characteristics and applications. As a specific example, the average thickness of the internal electrodes 121, 122 may be 300 nm or more and 10 μm or less. In addition, the average thickness of at least one of the multiple internal electrodes 121, 122 may be 300 nm or more and 10 μm or less.

[0045] The average thickness of the internal electrodes 121 and 122 may be calculated by determining five points, two on the left side and two on the right side of the reference point, at equal intervals based on a point where the center line of the length direction of the body and the center line of the thickness direction of the body meet, for a total of five internal electrode layers, two upper layers and two lower layers, among the internal electrode layers extracted from an image obtained by scanning a cross section in the length and thickness direction (LT) cut at the center of the width direction of the body 110 using a scanning electron microscope (SEM). The average thickness of each point may be calculated by measuring the thickness of each point and calculating an average value based on a point where the center line of the length direction of the body and the center line of the thickness direction of the body meet.

[0046] 3 to 6, the body 110 may include a capacitance forming portion Ac in which a capacitance is formed, the capacitance forming portion Ac including a first internal electrode 121 and a second internal electrode 122 arranged to face each other across a dielectric layer 111, and cover portions 112 and 113 formed on the upper and lower portions of the capacitance forming portion Ac in a first direction.

[0047] The capacitance forming portion Ac is a portion that contributes to forming the capacitance of the capacitor, and can be formed by repeatedly laminating a plurality of first and second internal electrodes 121, 122 with the dielectric layer 111 interposed therebetween.

[0048] Referring to Figures 3 to 6, the cover parts 112, 113 may include an upper cover part 112 arranged at the upper part of the capacitance forming part Ac in the first direction and a lower cover part 113 arranged at the lower part of the capacitance forming part Ac in the first direction.

[0049] The upper cover part 112 and the lower cover part 113 may be formed by stacking a single dielectric layer or two or more dielectric layers on the upper and lower surfaces of the capacitance forming part Ac in the thickness direction, respectively, and may basically serve to prevent damage to the internal electrodes due to physical or chemical stress.

[0050] The upper cover part 112 and the lower cover part 113 do not include an internal electrode and may include the same material as the dielectric layer 111 .

[0051] That is, the upper cover part 112 and the lower cover part 113 may include a ceramic material, for example, a barium titanate (BaTiO3) based ceramic material.

[0052] On the other hand, there is no need to particularly limit the thickness of the covers 112 and 113. For example, the thickness of the covers 112 and 113 may be 10 to 300 μm. However, in order to more easily achieve a smaller size and higher capacity of the multilayer electronic component, the thickness of the covers 112 and 113 may be 15 μm or less.

[0053] The average thickness of the cover parts 112, 113 may mean the size in the first direction, and may be the average value of the size in the first direction of the cover parts 112, 113 measured at five equally spaced points on the upper or lower part of the capacitance forming portion Ac.

[0054] 4 to 6, margin portions 114 and 115 may be disposed on the side surfaces of the capacitance forming portion Ac.

[0055] The margin portions 114, 115 may include a first margin portion 114 disposed on the fifth surface 5 of the body 110 and a second margin portion 115 disposed on the sixth surface 6. That is, the margin portions 114, 115 may be disposed on both end surfaces of the ceramic body 110 in the width direction.

[0056] The margin portions 114, 115 may refer to the regions between both ends of the first and second internal electrodes 121, 122 and the boundary surface of the body 110 in a cross-section of the body 110 cut in the width-thickness (WT) direction, as shown in FIG. 5.

[0057] The margins 114 and 115 essentially serve to prevent damage to the internal electrodes due to physical or chemical stress.

[0058] The margin portions 114 and 115 may be formed by applying a conductive paste to the ceramic green sheets, except for the areas where the margin portions are to be formed, to form internal electrodes.

[0059] In addition, in order to suppress steps caused by the internal electrodes 121, 122, the laminated internal electrodes can be cut so as to be exposed on the fifth and sixth faces 5, 6 of the main body, and then a single dielectric layer or two or more dielectric layers can be laminated in the third direction (width direction) on both side faces of the capacitance forming portion Ac to form margin portions 114, 115.

[0060] On the other hand, there is no need to particularly limit the width of the marginal portions 114, 115. For example, the width of the marginal portions 114, 115 may be 5 to 300 μm. However, in order to more easily achieve a smaller size and higher capacity of the multilayer electronic component, the average width of the marginal portions 114, 115 may be 15 μm or less.

[0061] The average width of the margin portions 114 and 115 may refer to the average size in the third direction of the region where the internal electrode is separated from the fifth surface and the average size in the third direction of the region where the internal electrode is separated from the sixth surface, and may be an average value of the sizes in the third direction of the margin portions 114 and 115 measured at five equally spaced points on the side of the capacitance forming portion Ac.

[0062] Therefore, in one embodiment, the average size in the third direction of the regions where the internal electrodes 121 and 122 are separated from the fifth and sixth faces may be 15 μm or less.

[0063] The external electrodes 131 , 132 may be disposed on the third surface 3 and the fourth surface 4 of the body 110 .

[0064] The external electrodes 131 and 132 may include first and second external electrodes 131 and 132 disposed on the third and fourth surfaces 3 and 4 of the body 110, respectively, and connected to the first and second internal electrodes 121 and 122, respectively.

[0065] In this embodiment, a structure in which the multilayer electronic component 100 has two external electrodes 131, 132 is described, but the number and shapes of the external electrodes 131, 132 can be changed depending on the configuration of the internal electrodes 121, 122 and other purposes.

[0066] Meanwhile, the external electrodes 131, 132 may be formed using any material having electrical conductivity, such as a metal, and the specific material may be determined taking into consideration electrical characteristics, structural stability, etc., and may further have a multi-layer structure.

[0067] For example, the external electrodes 131 and 132 may include an electrode layer disposed on the body 110 and a plating layer formed on the electrode layer.

[0068] As a more specific example of the electrode layer, the electrode layer may be a firing electrode including a conductive metal and glass, or a resin-based electrode including a conductive metal and resin.

[0069] The electrode layer may be formed by sequentially forming a fired electrode and a resin-based electrode on the main body. The electrode layer may be formed by transferring a sheet containing a conductive metal onto the main body, or by transferring a sheet containing a conductive metal onto the fired electrode. The electrode layer may be formed of a plating layer, or may be formed by using a deposition method such as sputtering or ALD (Atomic layer deposition).

[0070] The conductive metal contained in the electrode layer may be any material having excellent electrical conductivity, but is not limited thereto. For example, the conductive metal may be one or more of nickel (Ni), copper (Cu), and alloys thereof.

[0071] The plating layer serves to improve mounting characteristics. The type of plating layer is not particularly limited, and may be a plating layer containing one or more of Ni, Sn, Pd, and alloys thereof, or may be formed of multiple layers.

[0072] As a more specific example of the plating layer, the plating layer may be a Ni plating layer or a Sn plating layer, or may be a form in which a Ni plating layer and a Sn plating layer are sequentially formed on an electrode layer, or a form in which a Sn plating layer, a Ni plating layer and a Sn plating layer are sequentially formed. The plating layer may include a plurality of Ni plating layers and / or a plurality of Sn plating layers. The plating layer may be a form in which a Ni plating layer and a Pd plating layer are sequentially formed on an electrode layer.

[0073] There is no need to particularly limit the size of the multilayer electronic component 100. Since the present invention is advantageous for miniaturization and high capacity, it can be applied to the size of small IT products, and since high reliability can be ensured in various environments, it can be applied to the size of automotive electrical products that require high reliability.

[0074] According to one embodiment of the invention, the body 110 may include margin patterns 123, 124.

[0075] The margin patterns 123 and 124 are disposed on the dielectric layer 111 on which the internal electrodes 121 and 122 are not disposed, and serve to reduce the step between the capacitance forming portion and the margin portion.

[0076] Specifically, referring to FIGS. 2a to 2d and 3 to 6, the margin patterns 123 and 124 may be disposed at positions different from the first internal electrode 121 and the second internal electrode 122 in the first direction, and may be disposed so as not to overlap the first internal electrode 121 or the second internal electrode 122 in the first direction. The margin patterns 123 and 124 being disposed at positions different from the first internal electrode 121 and the second internal electrode 122 in the first direction means that the positions of the margin patterns in the first direction are different from the positions of the first and second internal electrodes 121 and 122 in the first direction. The positions of the margin patterns 123 and 124 in the first direction may be between the position of the first internal electrode 121 in the first direction and the position of the second internal electrode 122 in the first direction.

[0077] As a result, by arranging the first margin pattern 123 in the area where the first internal electrode 121 is not formed and arranging the second margin pattern 124 in the area where the second internal electrode 122 is not formed, the step due to the difference in the degree of stacking of the internal electrodes can be effectively alleviated, and the phenomenon of reduction in capacitance due to deformation of the internal electrodes 121, 122 and the dielectric layer 111 can be mitigated.

[0078] In addition, since the margin patterns 123, 124 are arranged at positions different from the first and second internal electrodes 121, 122 along the first direction, the phenomenon of the electric field concentrating at the ends of the first and second internal electrodes 121, 122 can be mitigated, thereby mitigating the phenomenon of dielectric breakdown occurring under high voltage.

[0079] Therefore, in one embodiment of the multilayer electronic component according to the present invention, the margin patterns 123, 124 are arranged at positions different from the first and second internal electrodes 121, 122 along the first direction and are arranged so as not to overlap the first internal electrodes or the second internal electrodes in the first direction, thereby improving the capacitance and high temperature load life.

[0080] Meanwhile, in order to improve the effect of compensating for the step, the margin patterns 123 and 124 preferably contain a metal component that is difficult to diffuse into the dielectric layer 111, and preferably contain a conductive metal in order to suppress the phenomenon of electric field concentration at the ends of the internal electrodes 121 and 122. Specifically, the margin patterns 123 and 124 may contain a conductive metal like the internal electrodes 121 and 122.

[0081] However, the conductive metal contained in the margin patterns 123, 124 does not necessarily have to be the same as the conductive metal contained in the internal electrodes 121, 122. However, if the conductive metal contained in the margin patterns 123, 124 is the same as the conductive metal contained in the internal electrodes 121, 122, the effect of reducing the step according to the present invention can be further improved.

[0082] 2a to 2d, the margin patterns 123 and 124 according to an embodiment may include a first margin pattern 123 arranged so as not to overlap the first internal electrode 121 in the first direction and a second margin pattern 124 arranged so as not to overlap the second internal electrode 122 in the first direction. Thus, by forming the margin patterns 123 and 124 at the margins of the first internal electrode 121 and the second internal electrode 122, respectively, the effect of reducing the step can be further improved.

[0083] In an embodiment, at least a portion of the first margin pattern 123 may be arranged to overlap at least a portion of the region of the first internal electrode separated from the fourth surface in the first direction, and at least a portion of the second margin pattern 124 may be arranged to overlap at least a portion of the region of the second internal electrode separated from the third surface in the first direction. This makes it possible to more effectively reduce the phenomenon of electric field concentration at the ends of the first and second internal electrodes 121 and 122.

[0084] 2a to 2d, the first margin pattern 123 and the second margin pattern 124 may be disposed apart from the third to fifth surfaces 3, 4, 5, and 6. As a result, the first margin pattern 123 and the second margin pattern 124 may be disposed so as not to be connected to the external electrodes 131 and 132, and the phenomenon of electric field concentration at the ends of the first and second internal electrodes 121 and 122 may be more effectively mitigated while mitigating steps.

[0085] When the first margin pattern 123 and the second margin pattern 124 are connected to the first and second external electrodes 131 and 132, respectively, the distance at which the first margin pattern 123 is separated from the second external electrode 132 and the distance at which the second margin pattern 124 is separated from the first external electrode 131 are short, which may cause a short circuit. In addition, the first margin pattern 123 and the second margin pattern 124 may affect the capacitance and withstand voltage characteristics of the multilayer electronic component 100, and the first and second margin patterns 123 and 124 are more likely to warp and have a lowered connectivity than the first and second internal electrodes 121 and 122, which may make it difficult to achieve effective capacitance and withstand voltage. In addition, it may be difficult to alleviate the phenomenon of electric field concentration at the ends of the first and second internal electrodes 121 and 122.

[0086] The margin patterns 123, 124 are preferably arranged so as not to overlap with the internal electrodes included in the capacitance forming portion Ac, and are preferably arranged sufficiently adjacent to the first and second internal electrodes 121, 122 so as to prevent warping and loss of connectivity of the internal electrodes in the margin portions.

[0087] Specifically, when viewed from the first direction, the distance between the first internal electrode 121 and the first margin pattern 123 may be 30 μm or less, and the distance between the second internal electrode 122 and the second margin pattern 124 may be 30 μm or less. This makes it possible to effectively prevent warping of the internal electrodes and deterioration of connectivity due to steps.

[0088] Meanwhile, there is no need to particularly limit the lower limit of the distance between the first internal electrode 121 and the first margin pattern 123, and the lower limit of the distance between the second internal electrode 122 and the second margin pattern 124, but they can be determined taking into consideration the printing resolution of the internal electrodes 121, 122 and the margin patterns 123, 124.

[0089] Specifically, when viewed from the first direction, the distance between the first internal electrode 121 and the first margin pattern 123 may be greater than or equal to 0.5 μm and less than or equal to 30 μm, and the distance between the second internal electrode 122 and the second margin pattern 124 may be greater than or equal to 0.5 μm and less than or equal to 30 μm.

[0090] The distance between the first internal electrode 121 and the first margin pattern 123, and the distance between the second internal electrode 122 and the second margin pattern 124 may mean the distance between the internal electrodes 121, 122 and the margin patterns 123, 124 in the second direction in the cross sections of the multilayer electronic component in the first and second directions. In this case, the distance between the internal electrodes 121, 122 and the margin patterns 123, 124 in the second direction in the cross sections of the multilayer electronic component in the first and second directions may be generalized by measuring the average value of the distance between five internal electrode layers located above and five internal electrode layers located below the center in the first direction and their corresponding margin patterns in the second direction in the cross sections of the multilayer electronic component in the first and second directions polished to the center in the third direction.

[0091] In addition, the distance between the first internal electrode 121 and the first margin pattern 123 and the distance between the second internal electrode 122 and the second margin pattern 124 may mean the distance between the internal electrodes 121, 122 and the margin patterns 123, 124 in the third direction in the cross sections of the multilayer electronic component in the first and third directions. In this case, the distance between the internal electrodes 121, 122 and the margin patterns 123, 124 in the third direction in the cross sections in the first and third directions may be generalized by measuring the average value of the distance between the five internal electrode layers located above and the five internal electrode layers located below the center in the first direction and the corresponding margin patterns in the third direction in the cross sections of the multilayer electronic component in the first and third directions polished to the center in the second direction.

[0092] Meanwhile, the first margin pattern 123 and the second margin pattern 124 are preferably disposed sufficiently spaced apart from the third to sixth surfaces 3, 4, 5, and 6 of the body 110 to prevent connection with the external electrodes 131 and 132 and to prevent a decrease in moisture resistance reliability. Specifically, in one embodiment, the first margin pattern 123 and the second margin pattern 124 may be disposed 15 μm or more away from the third to sixth surfaces 3, 4, 5, and 6. More preferably, the first margin pattern 123 and the second margin pattern 124 may be disposed 15 μm or more and 150 μm or less away from the third to sixth surfaces 3, 4, 5, and 6.

[0093] The positions in the first direction of the first margin pattern 123 and the second margin pattern 124 may be determined in relation to the positions in the first direction of the first internal electrode 121 and the second internal electrode 122. Specifically, in one embodiment, the position in the first direction of the first margin pattern 123 may be between the position in the first direction of the first internal electrode 121 and the position in the first direction of the second internal electrode 122, and the position in the first direction of the second margin pattern 124 may be between the position in the first direction of the second internal electrode 122 and the position in the first direction of the second internal electrode 122.

[0094] In one embodiment, the first margin pattern 123 may be in a form surrounding the first internal electrode 121, and the second margin pattern 124 may be in a form surrounding the second internal electrode 122. This may mean that, when viewed from a first direction as in FIGS. 2a to 2d, the first margin pattern 123 is arranged to surround the surface of the first internal electrode 121 facing the fourth surface 4, the surface facing the fifth surface 5, and the surface facing the sixth surface 6, and the second margin pattern 124 is arranged to surround the surface of the second internal electrode facing the third surface 3, the surface facing the fifth surface 5, and the surface facing the sixth surface 6.

[0095] The width and length of the margin patterns 123, 124 can be adjusted in accordance with the relationship between the length of the length margin and the width of the width margin. Specifically, if the margin patterns 123, 124 are excessively concentrated in the width margin and the length margin, they may be exposed to the third to sixth surfaces 3, 4, 5, and 6 of the main body 110, and if the margin patterns are insufficiently concentrated in the width margin and the length margin, the effect of reducing the step may be reduced. Thus, according to one embodiment, if the width and length of the margin patterns are appropriately adjusted in accordance with the relationship between the width of the width margin and the length margin, the margin patterns 123, 124 are prevented from being exposed to the outside of the main body 110, and a sufficient effect of reducing the step can be obtained.

[0096] Specifically, referring to Figures 2a to 2d, the area where the first internal electrode 121 is separated from the fifth surface 5 can be defined as the 1-1 width margin, the area where the first internal electrode 121 is separated from the fourth surface 5 can be defined as the first length margin, the size of the 1-1 width margin in the third direction can be defined as WM1, and the size of the margin pattern overlapping with the 1-1 width margin in the third direction can be defined as WMP1.

[0097] At this time, if WMP1 / WM1 and LMP1 / LM1 are less than 0.33, the first margin pattern 123 may not be formed sufficiently, resulting in an insufficient step reduction effect. If WMP1 / WM1 and LMP1 / LM1 are more than 0.54, the first margin pattern 123 and the first internal electrode 121 may be formed to overlap each other when viewed from the first direction.

[0098] Therefore, in one embodiment, when the size in the second direction of the first length margin is LM1 and the size in the second direction of the margin pattern overlapping with the first length margin is LMP1, by making WMP1 / WM1 and LMP1 / LM1 greater than or equal to 0.33 and less than or equal to 0.54, it is possible to prevent exposure of the margin patterns 123, 124 to the outside of the main body 110 and obtain a sufficient step reduction effect.

[0099] On the other hand, when WMP1 / WM1 is 0.37 to 0.54 and LMP1 / LM1 is 0.33 to 0.51, the effect of preventing the margin patterns 123 and 124 from being exposed to the outside of the body 110 and the effect of reducing the step may be more significant.

[0100] 2a to 2d, the region where the first internal electrode 121 and the fourth surface 4 are separated is referred to as a first length margin, the region where the second internal electrode 122 and the third surface 3 are separated is referred to as a second length margin, the region where the first internal electrode 121 and the fifth surface 5 are separated is referred to as a 1-1 width margin, the region where the first internal electrode 121 and the sixth surface 6 are separated is referred to as a 1-2 width margin, the region where the second internal electrode 122 and the fifth surface 5 are separated is referred to as a 2-1 width margin, If the region where the pole 122 and the sixth face 6 are separated is the 2-2 width margin, the size of the first length margin in the second direction is expressed as LM1, the size of the second length margin in the second direction is expressed as LM2, the size of the 1-1 width margin in the third direction is expressed as WM1, the size of the 1-2 width margin in the third direction is expressed as WM1', the size of the 2-1 width margin in the third direction is WM2, and the size of the 2-2 width margin in the third direction is WM2'. The first width margin includes the 1-1 width margin and the 1-2 width margin, and the second width margin includes the 2-1 width margin and the 2-2 width margin.

[0101] In addition, the second direction size of first margin pattern 123 overlapping with the first length margin is expressed as LMP1, the second direction size of second margin pattern 124 overlapping with the second length margin is expressed as LMP2, the third direction size of first margin pattern 123 overlapping with the 1-1 width margin is expressed as WMP1, the third direction size of first margin pattern 123 overlapping with the 1-2 width margin is expressed as WMP1', the third direction size of second margin pattern 124 overlapping with the 2-1 width margin is expressed as WMP2, and the third direction size of second margin pattern 124 overlapping with the 2-2 width margin is expressed as WMP2'.

[0102] In one embodiment, WMP1' / WM1 may be 0.33 to 0.54, preferably 0.37 to 0.54, so that the margin patterns 123 and 124 can be prevented from being exposed to the outside of the body 110 and the step reduction effect can be improved.

[0103] In one embodiment, WMP2 / WM2 may be 0.33 to 0.54, preferably 0.37 to 0.54, so that the margin patterns 123 and 124 can be prevented from being exposed to the outside of the body 110 and the step reduction effect can be improved.

[0104] In one embodiment, WMP2' / WM2' may be 0.33 to 0.54, preferably 0.37 to 0.54, so that the margin patterns 123 and 124 can be prevented from being exposed to the outside of the body 110 and the step reduction effect can be improved.

[0105] In one embodiment, LMP2 / LM2 may be 0.33 to 0.54, preferably 0.33 to 0.51, which can improve the effect of preventing the margin patterns 123 and 124 from exposing the body 110 to the outside and the effect of reducing the step.

[0106] Meanwhile, in this specification, for convenience of explanation, the above-mentioned LM1, LM2, WM1, WM1', WM2, WM2', LMP1, LPM2, WMP1, WMP1', WMP2 and WMP2' are shown in Figures 2a to 2d, which are plan views of the internal electrodes and margin patterns viewed from a first direction.

[0107] The above LM1, LM2, LMP1, and LPM2 may be average values ​​measured at five internal electrode layers located above and five internal electrode layers located below the center in the first direction and corresponding margin patterns in a cross section in the first and second directions polished to the center in the third direction of the multilayer electronic component 100, based on the center in the first direction.

[0108] The above WM1, WM1', WM2, WM2', WMP1, WMP1', WMP2 and WMP2' may be average values ​​measured at five internal electrode layers positioned above and five internal electrode layers positioned below the center in the first direction and their corresponding margin patterns in a cross section in the first direction and a cross section in the third direction polished to the center in the second direction of the multilayer electronic component 100.

[0109] The internal electrodes and margin patterns of the multilayer electronic components 100 according to various embodiments will be described in detail below.

[0110] 9a, 9b, 9c and 9d are plan views that are schematic diagrams of internal electrodes and margin patterns according to an embodiment.

[0111] 9a, 9b, 9c and 9d, the first internal electrode 121 according to one embodiment may include a first internal pattern 121a connected to the third surface 3 and spaced apart from the fourth, fifth and sixth surfaces 4, 5 and 6, and a first dummy pattern 121b spaced apart from the first internal pattern and connected to the fourth surface 4 and spaced apart from the third, fifth and sixth surfaces 3, 5 and 6, and the second internal electrode 122 may include a second internal pattern 122a connected to the fourth surface 4 and spaced apart from the third, fifth and sixth surfaces 3, 5 and 6, and a second dummy pattern 122b spaced apart from the second internal pattern and connected to the third surface 3 and spaced apart from the fourth, fifth and sixth surfaces 4, 5 and 6.

[0112] At this time, the first margin pattern 123 may be arranged to overlap the area where the first internal electrode is separated from the fifth and sixth faces and the space where the first internal pattern and the first dummy pattern are separated, and the second margin pattern 124 may be arranged to overlap the area where the second internal electrode is separated from the fifth and sixth faces and the space where the second internal pattern and the second dummy pattern are separated. Thus, even if the internal electrodes 121 and 122 have a structure including the dummy patterns 121b and 122b, the step can be reduced by forming the margin pattern entirely in the area where the internal patterns or the dummy patterns are not formed.

[0113] 10a, 10b, 10c and 10d are plan views each showing a schematic diagram of an internal electrode and a margin pattern according to an embodiment.

[0114] 10a, 10b, 10c and 10d, the first internal electrode 121 according to one embodiment includes a 1-1 internal pattern 121c connected to the third surface 3 and spaced apart from the fourth, fifth and sixth surfaces 4, 5 and 6, and a 1-2 internal pattern 121d spaced apart from the 1-1 internal pattern and connected to the fourth surface 4 and spaced apart from the third, fifth and sixth surfaces 3, 5 and 6, and the second internal electrode 122 may have a floating pattern 122e spaced apart from the third to sixth surfaces 3, 4, 5 and 6.

[0115] At this time, the first margin pattern 123 may be arranged to overlap the area where the first internal electrode is separated from the fifth and sixth faces and the space where the 1-1 internal pattern and the 1-2 internal pattern are separated, and the second margin pattern 124 may be arranged to overlap the space where the second internal electrode is separated from the third to fifth faces. As a result, even if the internal electrode 122 has a structure including the floating pattern 122e, the step can be reduced by forming the margin pattern entirely in the area where no internal pattern or floating pattern is formed.

[0116] 11a, 11b, 11c and 11d are plan views each showing a schematic diagram of an internal electrode and a margin pattern according to an embodiment.

[0117] 11a, 11b, 11c and 11d, when the area of ​​the first internal electrode 121 separated from the fifth surface 5 is defined as a 1-1 width margin, the area of ​​the first internal electrode 121 separated from the sixth surface 6 is defined as a 1-2 width margin, and the area of ​​the first internal electrode 121 separated from the fourth surface is defined as a first length margin, the first margin pattern 123' can be arranged to overlap any one of the 1-1 and 1-2 width margins and the first length margin in the first direction.

[0118] Similarly, when the area of ​​the second internal electrode 122 separated from the fifth surface 5 is defined as the 2-1 width margin, the area of ​​the second internal electrode 122 separated from the sixth surface 6 is defined as the 2-2 width margin, and the area of ​​the second internal electrode 122 separated from the third surface 3 is defined as the second length margin, the second margin pattern 124' can be arranged to overlap one of the 2-1 and 2-2 width margins and the second length margin in the first direction.

[0119] In this case, when the first margin pattern 123' is arranged to overlap the 1-2 width margin in the first direction, the second margin pattern 124' can be arranged to overlap the 2-1 width margin in the first direction, and when the first margin pattern 123' is arranged to overlap the 1-1 width margin in the first direction, the second margin pattern 124' can be arranged to overlap the 2-2 width margin in the first direction. In this way, the first margin pattern 123' and the second margin pattern 124' do not overlap each other in the first direction at the width margin, thereby reducing a step caused by the overlapping formation of the margin patterns 123' and 124' in the first direction.

[0120] 12a, 12b, 12c and 12d are plan views each showing an internal electrode and margin pattern according to one embodiment, and FIG. 13a, 13b, 13c and 13d are plan views each showing an internal electrode and margin pattern according to one embodiment.

[0121] The structure in which the first margin pattern 123' is arranged to overlap one of the 1-1 and 1-2 width margins and the first length margin in the first direction, and the second margin pattern 124' is arranged to overlap one of the 2-1 and 2-2 width margins and the second length margin in the first direction can also be applied to the case in which the internal electrodes 121, 122 have dummy patterns 121b, 122b or have a floating pattern 122e.

[0122] 12a, 12b, 12c and 12d, the first internal electrode 121 according to one embodiment includes a first internal pattern 121a connected to the third surface 3 and spaced apart from the fourth, fifth and sixth surfaces 4, 5 and 6, and a first dummy pattern 121b spaced apart from the first internal pattern and connected to the fourth surface 4 and spaced apart from the third, fifth and sixth surfaces 3, 5 and 6, and the second internal electrode 122 includes a second internal pattern 122a connected to the fourth surface 4 and spaced apart from the third, fifth and sixth surfaces 3, 5 and 6, and a second dummy pattern 122b spaced apart from the second internal pattern and connected to the third surface 3 and spaced apart from the fourth, fifth and sixth surfaces 4, 5 and 6.

[0123] In this case, the first margin pattern 123' according to one embodiment may be arranged to overlap in the first direction with one of the 1-1 width margin and the 1-2 width margin of the first internal electrode 121 and the area where the first internal pattern and the first dummy pattern are separated, and the second margin pattern 124' may be arranged to overlap in the first direction with one of the 2-1 width margin and the 2-2 width margin and the second length margin of the second internal electrode 122.

[0124] 13a, 13b, 13c and 13d, the first internal electrode 121 according to one embodiment includes a 1-1 internal pattern 121c connected to the third surface 3 and spaced apart from the fourth, fifth and sixth surfaces 4, 5 and 6, and a 1-2 internal pattern 121d spaced apart from the 1-1 internal pattern and connected to the fourth surface 4 and spaced apart from the third, fifth and sixth surfaces 3, 5 and 6, and the second internal electrode 122 includes a floating pattern 122e spaced apart from the third to sixth surfaces 3, 4, 5 and 6.

[0125] In this case, the first margin pattern 123' according to one embodiment may be arranged to overlap in the first direction with either one of the 1-1 width margin and the 1-2 width margin of the first internal electrode 121 and the area where the 1-1 internal pattern and the 1-2 internal pattern are separated from each other.

[0126] 13b, the first margin pattern 123' is depicted as overlapping the 1-1 width margin of the first internal electrode 121 in the first direction, but the first margin pattern 123' of the first internal electrode 121 arranged in another layer may have a structure overlapping the 1-2 width margin of the first internal electrode 122 in the first direction. Meanwhile, in one embodiment, since the second internal electrode 122 includes the floating pattern 122e, the second margin pattern 124 may be arranged to overlap at least one of the regions of the second internal electrode 122 separated from the third surface 3, the region separated from the fourth surface 4, the region separated from the fifth surface 5, and the region separated from the sixth surface 6 in the first direction.

[0127] 14a, 14b, 14c and 14d are plan views that are schematic diagrams of internal electrodes and margin patterns according to an embodiment.

[0128] 14a, 14b, 14c and 14d, in one embodiment, the internal electrodes 121, 122 may include main portions 121-1, 122-1, which are areas where the first and second internal electrodes 121, 122 overlap in a first direction to form a capacitance, and lead portions 121-2, 122-2, which are larger in size in a third direction than the main portions and extend from the main portions to the third surface 3 or the fourth surface 4.

[0129] As a result, the step that occurs because the margin patterns 123, 124 are not formed in an area separated from the third surface 3 or the fourth surface 4 can be mitigated by arranging the lead portions 121-2, 122-2 which are larger in size in the third direction than the main portions 121-1, 122-1.

[0130] 15a, 15b, 15c and 15d are plan views each showing a schematic diagram of an internal electrode and a margin pattern according to an embodiment.

[0131] 15a, 15b, 15c and 15d, the first internal electrode 121 according to one embodiment may include a first internal pattern 121a connected to the third surface 3 and spaced apart from the fourth, fifth and sixth surfaces 4, 5 and 6, and a first dummy pattern 121b spaced apart from the first internal pattern and connected to the fourth surface 4 and spaced apart from the third, fifth and sixth surfaces 3, 5 and 6, and the second internal electrode 122 may include a second internal pattern 122a connected to the fourth surface 4 and spaced apart from the third, fifth and sixth surfaces 3, 5 and 6, and a second surface dummy pattern 122b spaced apart from the second internal pattern and connected to the third surface 3 and spaced apart from the fourth, fifth and sixth surfaces 4, 5 and 6.

[0132] The first internal pattern 121a may include a main portion 121a-1, which is an area where the first internal pattern and the second internal pattern overlap in the first direction, and a lead portion 121a-2, which is larger in size in the third direction than the main portion 121a-1 and extends from the main portion 121a-1 to the third surface 3, and the first dummy pattern 121b may include a main portion 121b-1 and a lead portion 121b-2, which is larger in size in the third direction than the main portion 121b-1 and extends from the main portion 121b-1 to the fourth surface 4.

[0133] Similarly, the second internal pattern 121b may include a main portion 122a-1, which is an area where the first internal pattern and the second internal pattern overlap in the first direction, and a lead portion 122a-2, which is larger in size in the third direction than the main portion 122a-1 and extends from the main portion 122a-1 to the fourth surface 4, and the second dummy pattern 122b may include a main portion 122b-1 and a lead portion 122b-2, which is larger in size in the third direction than the main portion 122b-1 and extends from the main portion 122b-1 to the third surface 3.

[0134] In this case, in one embodiment, the first margin pattern 123 may be arranged to overlap in the first direction with the 1-1 width margin and the 1-2 width margin, and the area where the first internal pattern 121a and the first dummy pattern 121b are separated, and the second margin pattern 124 may be arranged to overlap in the first direction with the 2-1 width margin and the 2-2 width margin, and the area where the second internal pattern 122a and the second dummy pattern 122b are separated.

[0135] 16a, 16b, 16c and 16d are plan views each showing a schematic diagram of an internal electrode and a margin pattern according to an embodiment.

[0136] The first internal electrode 121 according to one embodiment includes a 1-1 internal pattern 121c connected to the third surface 3 and spaced apart from the fourth, fifth and sixth surfaces 4, 5 and 6, and a 1-2 internal pattern 121d spaced apart from the 1-1 internal pattern and connected to the fourth surface 4 and spaced apart from the third, fifth and sixth surfaces 3, 5 and 6, and the second internal electrode 122 includes a floating pattern 122e spaced apart from the third to sixth surfaces 3, 4, 5 and 6.

[0137] The 1-1 internal pattern 121c includes a main portion 121c-1 and a lead portion 121c-2 that is larger in the third direction than the main portion 121c-1 and extends from the main portion 121c-1 to the third surface 3, and the 1-2 internal pattern 121d includes a main portion 121d-1 and a lead portion 121d-2 that is larger in the third direction than the main portion 121d-1 and extends from the main portion 121d-1 to the fourth surface 4.

[0138] In this case, the first margin pattern 123' according to one embodiment may be arranged to overlap in the first direction with the 1-1 width margin, the 1-2 width margin of the first internal electrode 121, and the area in which the first internal pattern 121c and the second internal pattern 121d are spaced apart.

[0139] In this case, the second margin pattern 124 may be arranged so as to overlap in the first direction with at least one of the regions of the second internal electrode 122 spaced apart from the third surface 3, the region spaced apart from the fourth surface 4, the region spaced apart from the fifth surface 5, and the region spaced apart from the sixth surface 6.

[0140] 17a, 17b, 17c and 17d are plan views that are schematic diagrams of internal electrodes and margin patterns according to an embodiment.

[0141] 17a, 17b, 17c, and 17d, the margin patterns 123'', 124'' according to an embodiment may be composed of a plurality of spaced apart patterns. Thus, by forming the margin patterns 123'', 124'' in at least one region of the length margin and width margin of the internal electrodes 121, 122, the step can be reduced and the adhesive strength between the dielectric layers 111 can be improved, thereby improving the capacitance and high temperature load life of the multilayer electronic component 100 and also improving the strength of the component itself.

[0142] 18a, 18b, 18c and 18d are plan views that are schematic diagrams of internal electrodes and margin patterns according to an embodiment.

[0143] 18a, 18b, 18c, and 18d, the margin patterns 123''' and 124''' according to an embodiment may be arranged to overlap only the width margin and not the length margin. That is, when a region of the first internal electrode 121 separated from the fifth and sixth surfaces is defined as a first width margin, a region of the first internal electrode 121 separated from the fourth surface is defined as a first length margin, a region of the second internal electrode 122 separated from the fifth and sixth surfaces is defined as a second width margin, and a region of the second internal electrode 122 separated from the third surface is defined as a second length margin, the first and second margin patterns 123''' and 124''' may be arranged to overlap the first and second margins but not overlap the first and second length margins. In this case, the margin patterns 123''' and 124''' may have a line shape when observed from the stacking direction. Also, as shown in Figures 18a, 18b, 18c and 18d, margin patterns 123'''', 124'''' may be arranged so as to overlap both width margins, but this is not limited to this and they may be arranged so as to overlap only one of the width margins.

[0144] Manufacturing method for multilayer electronic components FIG. 7 is a plan view illustrating a schematic state in which internal electrodes are arranged on a ceramic sheet according to one embodiment, and FIG. 8 is a plan view illustrating a schematic state in which a margin pattern is arranged on a ceramic sheet according to one embodiment.

[0145] A method for manufacturing a multilayer electronic component according to one embodiment of the present invention will be described below with reference to FIGS.

[0146] A method for manufacturing a multilayer electronic component according to one embodiment of the present invention may include a lamination step of alternately laminating a first sheet having a first pattern 221 arranged on a first ceramic sheet 211 and a second sheet having a second pattern 222 arranged on a second ceramic sheet 212 in a first direction, and disposing a third sheet having a third pattern 223, 224 arranged on a third ceramic sheet 123 between the first sheet and the second sheet, and laminating the third pattern so that it does not overlap with the first pattern or the second pattern to obtain a laminate, a sintering step of sintering the laminate to obtain a main body 110, and a step of forming external electrodes on the main body.

[0147] The ceramic sheets 211, 212, 213, and 214 can be divided into a first ceramic sheet 211, a second ceramic sheet 212, a third-1 ceramic sheet 213, and a third-2 ceramic sheet 214.

[0148] The ceramic sheets 211, 212, 213, and 214 may be formed of a ceramic paste containing a ceramic powder, an organic solvent, a dispersant, and a binder. The ceramic powder may contain raw materials for forming the dielectric layer 111 of the multilayer electronic component 100.

[0149] Referring to FIG. 7, a first pattern 221 may be disposed on a first ceramic sheet 211, and a second pattern 222 may be disposed on a second ceramic sheet 212. As shown in FIG.

[0150] An example of a method for forming the first pattern 221 and the second pattern 222 is a method of screen printing or gravure printing a conductive paste containing a conductive metal onto the first ceramic sheet 211 and the second ceramic sheet 212, but is not limited to this. A thin film deposition method such as sputtering or vacuum deposition of the conductive metal onto the first ceramic sheet 211 and the second ceramic sheet 212 can also be used.

[0151] The first pattern 221 and the second pattern 222 may include a conductive metal. The conductive metal is not particularly limited, and a material having excellent electrical conductivity may be used. For example, the conductive metal may include one or more of nickel (Ni), copper (Cu), palladium (Pd), silver (Ag), gold (Au), platinum (Pt), tin (Sn), tungsten (W), titanium (Ti), and alloys thereof.

[0152] The first pattern 221 and the second pattern 222 may be a plurality of patterns arranged at intervals in a direction perpendicular to the stacking direction.

[0153] The first pattern 221 may be sintered to form the first internal electrode 121 , and the second pattern 222 may be sintered to form the second internal electrode 122 .

[0154] In the lamination step according to an embodiment of the present invention, a third sheet having third patterns 223, 224 arranged on third ceramic sheets 213, 214 may be disposed between the first sheet and the second sheet.

[0155] At this time, the first sheet and the second sheet may be stacked with an offset by the distance between adjacent cutting lines CL in the second direction, and the third patterns 223, 224 of the third sheet may be stacked so as not to overlap the first pattern 221 or the second pattern 222.

[0156] 8, the third patterns 223 and 224 may surround the first and second patterns 221 and 222 when viewed from the stacking direction. However, the third patterns 223 and 224 may not overlap the first and second patterns 221 and 222 when viewed from the stacking direction. However, each pattern constituting the third patterns 223 and 224 may not completely surround the first and second patterns 221 and 222 when viewed from the first direction. Specifically, each unit pattern of the third patterns 223 and 224 may be spaced apart based on a cutting line CL described below, and may have a shape symmetrical to each other based on the cutting line CL.

[0157] Meanwhile, the third patterns 223 and 224 preferably include a component that is difficult to diffuse into the ceramic sheets 211, 212, 213, and 214 in order to improve the effect of compensating for the step, and preferably include a conductive metal in order to suppress the phenomenon of electric field concentration at the ends of the internal electrodes 121 and 122. Specifically, the third patterns 223 and 224 may include a conductive metal like the first and second patterns 221 and 222.

[0158] However, the conductive metal contained in the third patterns 223, 224 does not necessarily have to be the same as the conductive metal contained in the first and second patterns 221, 222. However, if the conductive metal contained in the third patterns 223, 224 is the same as the conductive metal contained in the first and second patterns 221, 222, the effect of reducing steps according to the present invention can be further improved.

[0159] 8, the third patterns 223, 224 may be arranged and laminated on a ceramic sheet (third ceramic sheet) different from the first pattern 221 and the second pattern 222 which form the internal electrodes 121, 122 after sintering. Thus, the third patterns 223, 224 may form margin patterns 123, 124 which are arranged at positions different from the first and second internal electrodes 121, 122 in the first direction after sintering and are arranged not to overlap the first internal electrode 121 or the second internal electrode 122 in the first direction.

[0160] After the lamination step, referring to Fig. 7 and Fig. 8, after the step of forming the first to third sheet laminate, a cutting step of cutting along a cutting line CL may be performed. The cutting line CL in Fig. 7 and the cutting line CL in Fig. 8 may be the same cutting line. The cutting line CL may be a straight line passing through the center of each pattern of the first and second patterns 211 and 212 and a straight line crossing the center of the space between the patterns, but deviations may occur depending on the process.

[0161] The cutting step can be followed by a sintering step in which the laminate is sintered to obtain a body.

[0162] The temperature in the sintering step is not particularly limited, but for example, the sintering can be performed at 1000 to 1300° C. The sintering can be performed in a reducing atmosphere.

[0163] After the sintering step, a step of forming external electrodes 131 and 132 on the body 110 may be performed.

[0164] The external electrodes 131 and 132 may be formed by transferring a sheet containing a conductive metal, or by sequentially forming a fired electrode and a conductive resin layer containing a conductive metal and a resin on the laminate.

[0165] The third sheet includes a 3-1 sheet having a 3-1 pattern 223 disposed on a 3-1 ceramic sheet 213, and a 3-2 sheet having a 3-2 pattern 224 disposed on a 3-2 ceramic sheet 214, and the laminating step may be a step of laminating the 3-1 sheet and the 3-2 sheet alternately disposed in a first direction. As a result of sequentially laminating the first sheet, the 3-1 sheet, the second sheet, and the 3-2 sheet, the 3-1 pattern 223 forming the first margin pattern 123 after sintering may be disposed so as not to overlap the first pattern 221 in the first direction, and the 3-2 pattern 224 forming the second margin pattern 124 after sintering may be disposed so as not to overlap the second pattern 222 in the first direction. That is, in one embodiment, the 3-1 pattern can be arranged so as not to overlap the first pattern in the first direction, and the 3-2 pattern can be arranged so as not to overlap the second pattern in the first direction.

[0166] In an embodiment, when viewed from the first direction, the distance between the first pattern 221 and the 3-1 pattern 223 may be 30 μm or less, and the distance between the second pattern 222 and the 3-2 pattern 224 may be 30 μm or less. Thus, after sintering, the distance between the first internal electrode 121 and the first margin pattern 123 may be adjusted to 30 μm or less, and the distance between the second internal electrode 122 and the second margin pattern 124 may be adjusted to 30 μm or less.

[0167] In an embodiment, when viewed from the first direction, the distance between the first pattern 221 and the 3-1 pattern 223 may be 0.5 μm to 30 μm, and the distance between the second pattern 222 and the 3-2 pattern 224 may be 0.5 μm to 30 μm. Thus, after sintering, the distance between the first internal electrode 121 and the first margin pattern 123 may be adjusted to 0.5 μm to 30 μm, and the distance between the second internal electrode 122 and the second margin pattern 124 may be adjusted to 0.5 μm to 30 μm.

[0168] Although the embodiment of the present invention has been described in detail above, the present invention is not limited to the above-mentioned embodiment and the accompanying drawings, but is limited by the scope of the accompanying claims. Therefore, various substitutions, modifications and changes can be made by a person having ordinary knowledge in the art within the scope of the technical idea of ​​the present invention described in the claims, and these also belong to the scope of the present invention.

[0169] In addition, the expression "one embodiment" used in the present invention does not mean the same embodiment, but is provided to emphasize and describe each unique feature that is different from the others. However, the above-mentioned embodiment does not exclude being realized in combination with the features of another embodiment. For example, even if a matter described in a particular embodiment is not described in another embodiment, it can be understood as a description related to the other embodiment, unless there is a description that is opposite or contradictory to the matter in the other embodiment.

[0170] The terms used in the present invention are merely used to describe one embodiment and are not intended to limit the present invention. In this case, a singular expression includes a plural expression unless the context clearly indicates otherwise. [Explanation of symbols]

[0171] 100: Multilayer electronic components 110: Main unit 111: Dielectric layer 112, 113: Cover part 114, 115: Margin 121, 122: Internal electrode 123, 124: Margin pattern 211, 212, 213, 214: Ceramic sheets 221, 222: First and second patterns 223, 224: Pattern 3-1, Pattern 3-2

Claims

1. a body including a plurality of dielectric layers, a first internal electrode, a second internal electrode, and a margin pattern; an external electrode disposed on the body; The first and second internal electrodes are alternately arranged in a first direction with the dielectric layer therebetween, The margin pattern is arranged at a position different from the first and second internal electrodes along the first direction, and is arranged so as not to overlap the first internal electrodes or the second internal electrodes in the first direction.

2. the plurality of margin patterns include a first margin pattern arranged so as not to overlap the first internal electrode in the first direction, and a second margin pattern arranged so as not to overlap the second internal electrode in the first direction, 2. The multilayer electronic component according to claim 1, wherein the first margin patterns and the second margin patterns are alternately arranged in the first direction.

3. 3. The multilayer electronic component according to claim 2, wherein the main body includes first and second surfaces facing the first direction, third and fourth surfaces connected to the first and second surfaces and facing the second direction, and fifth and sixth surfaces connected to the first to fourth surfaces and facing the third direction.

4. the first internal electrode is connected to the third surface and spaced apart from the fourth, fifth and sixth surfaces; the second internal electrode is connected to the fourth surface and spaced apart from the third, fifth and sixth surfaces; 4. The multilayer electronic component according to claim 3, wherein the first and second margin patterns are disposed apart from the third to sixth surfaces.

5. 5. The multilayer electronic component according to claim 4, wherein, when viewed from the first direction, a distance between the first internal electrode and the first margin pattern is 30 μm or less, and a distance between the second internal electrode and the second margin pattern is 30 μm or less.

6. 5. The multilayer electronic component according to claim 4, wherein, when viewed from the first direction, a distance between the first internal electrode and the first margin pattern is 0.5 μm or more and 30 μm or less, and a distance between the second internal electrode and the second margin pattern is 0.5 μm or more and 30 μm or less.

7. 4. The multilayer electronic component according to claim 3, wherein the first and second margin patterns are disposed at a distance of 15 μm or more from the third to sixth surfaces.

8. 2. The multilayer electronic component according to claim 1, wherein a position of the margin pattern in the first direction is between a position of the first internal electrode and a position of the second internal electrode in the first direction.

9. When a region where the first internal electrode is separated from the fifth surface is defined as a 1-1 width margin, a region where the first internal electrode is separated from the fourth surface is defined as a first length margin, a size in a third direction of the 1-1 width margin is defined as WM1, a size in a third direction of a margin pattern overlapping with the 1-1 width margin is defined as WMP1, a size in a second direction of the first length margin is defined as LM1, and a size in a second direction of a margin pattern overlapping with the first length margin is defined as LMP1, 5. The multilayer electronic component according to claim 4, wherein WMP1 / WM1 and LMP1 / LM1 satisfy 0.33 or more and 0.54 or less.

10. 10. The multilayer electronic component according to claim 9, wherein the WMP1 / WM1 is equal to or greater than 0.37 and equal to or less than 0.54, and the LMP1 / LM1 is equal to or greater than 0.33 and equal to or less than 0.

51.

11. 5 . The multilayer electronic component according to claim 4 , wherein, when viewed from the first direction, the first margin pattern surrounds the first internal electrode, and the second margin pattern surrounds the second internal electrode.

12. When a region of the first internal electrode spaced apart from the fifth surface is defined as a 1-1 width margin, a region of the first internal electrode spaced apart from the sixth surface is defined as a 1-2 width margin, and a region of the first internal electrode spaced apart from the fourth surface is defined as a 1 length margin, 5. The multilayer electronic component according to claim 4, wherein the first margin pattern is arranged to overlap one of the 1-1 and 1-2 width margins and the first length margin in the first direction.

13. When a region where the first internal electrode is separated from the fifth and sixth surfaces is defined as a first width margin, a region where the first internal electrode is separated from the fourth surface is defined as a first length margin, a region where the second internal electrode is separated from the fifth and sixth surfaces is defined as a second width margin, and a region where the second internal electrode is separated from the third surface is defined as a second length margin, 5. The multilayer electronic component according to claim 4, wherein the first and second margin patterns are arranged so as to overlap the first and second width margins and not to overlap the first and second length margins.

14. 2. The multilayer electronic component according to claim 1, wherein the margin pattern is composed of a plurality of spaced apart patterns.

15. the first internal electrode includes a first internal pattern connected to the third surface and spaced apart from the fourth, fifth and sixth surfaces, and a first dummy pattern spaced apart from the first internal pattern and connected to the fourth surface and spaced apart from the third, fifth and sixth surfaces, 4. The multilayer electronic component according to claim 3, wherein the second internal electrode includes a second internal pattern connected to the fourth surface and spaced apart from the third, fifth, and sixth surfaces, and a second dummy pattern spaced apart from the second internal pattern and connected to the third surface.

16. the first margin pattern is disposed to overlap a region where the first internal electrode is separated from the fifth and sixth surfaces and a space where the first internal pattern and the first dummy pattern are separated from each other; 16. The multilayer electronic component according to claim 15, wherein the second margin pattern is arranged to overlap a region where the second internal electrode is separated from the fifth and sixth faces and a space where the second internal pattern and the second dummy pattern are separated.

17. the first internal electrode includes a 1-1 internal pattern connected to the third surface and spaced apart from the fourth, fifth and sixth surfaces, and a 1-2 internal pattern spaced apart from the 1-1 internal pattern connected to the fourth surface and spaced apart from the third, fifth and sixth surfaces, 4. The multilayer electronic component according to claim 3, wherein the second internal electrodes include floating patterns disposed apart from the third to sixth faces.

18. the first margin pattern is disposed to overlap a region where the first internal electrode is separated from the fifth and sixth surfaces and a space where the 1-1 internal pattern and the 1-2 internal pattern are separated from each other; 18. The multilayer electronic component according to claim 17, wherein the second margin pattern is arranged so as to overlap with spaces in which the second internal electrodes are spaced apart from the third to fifth surfaces.

19. a lamination step of alternately laminating a first sheet having a first pattern arranged thereon and a second sheet having a second pattern arranged thereon in a first direction, and disposing a third sheet having a third pattern arranged thereon between the first sheet and the second sheet, and laminating the first sheet and the second sheet such that the third pattern does not overlap the first pattern or the second pattern to obtain a laminate; a sintering step for sintering the laminate to obtain a body; and forming an external electrode on the body.

20. the third sheet includes a 3-1 sheet having a 3-1 pattern disposed on a 3-1 ceramic sheet, and a 3-2 sheet having a 3-2 pattern disposed on a 3-2 ceramic sheet; 20. The method of claim 19, wherein the laminating step comprises laminating the 3-1 ceramic sheet and the 3-2 ceramic sheet such that the 3-1 ceramic sheet and the 3-2 ceramic sheet are alternately arranged in a first direction.

21. 21. The method for manufacturing a multilayer electronic component according to claim 20, wherein the 3-1 pattern is arranged so as not to overlap the first pattern in the first direction, and the 3-2 pattern is arranged so as not to overlap the second pattern in the first direction.

22. 22. The method for producing a multilayer electronic component according to claim 21, wherein, when viewed from the first direction, a distance between the first pattern and the 3-1 pattern is 30 μm or less, and a distance between the second pattern and the 3-2 pattern is 30 μm or less.

23. 22. The method for producing a multilayer electronic component according to claim 21, wherein, when viewed from the first direction, a distance between the first pattern and the 3-1 pattern is 0.5 μm or more and 30 μm or less, and a distance between the second pattern and the 3-2 pattern is 0.5 μm or more and 30 μm or less.

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