Printed circuit board

Abstract

To provide: a printed circuit board on which an electronic component, a semiconductor chip and the like are mounted, the printed circuit board being capable of implementing a metal post having a fine pitch; and the like.SOLUTION: The present invention relates to a printed circuit board which includes: a wiring portion including one or more insulating layers 110, one or more wiring layers 120 respectively disposed on or in the one or more insulating layers, a first pad 141 disposed on a lowermost insulating layer, of the one or more insulating layers, and a second pad 142 disposed on an uppermost insulating layer, of the one or more insulating layers; a first solder resist layer 171 disposed on a lower side of the wiring portion to cover at least a portion of the first pad, the first solder resist layer having a first opening, on the first pad; a second solder resist layer disposed on an upper side of the wiring portion to cover at least a portion of the second pad; a first surface treatment layer disposed on at least a portion of the first pad; and a barrier layer disposed on the first solder resist layer, the barrier layer having a thickness thinner than that of the first pad.SELECTED DRAWING: Figure 3a

Description

[Technical field]

[0001] The present invention relates to printed circuit boards. [Background technology]

[0002] Recently, with the development of artificial intelligence (AI) technology, multi-chip packages including memory chips such as HBM (High Bandwidth Memory) and processor chips such as CPU (Central Processing Unit), GPU (Graphics Processing Unit), ASIC (Application Specific Integrated Circuit), and FPGA (Field Programmable Gate Array) are being used to process data that has increased exponentially. In particular, the number of CPU and GPU cores in server products is increasing rapidly, making it necessary to respond to finer chip metal post pitches. In particular, research is ongoing to form finer pads on the substrate for connection between the chip and the substrate, and to improve the reliability of the connection between the chip and the substrate while also improving yield. Summary of the Invention [Problem to be solved by the invention]

[0003] One of the various objects of the present invention is to provide a printed circuit board capable of realizing metal posts having a fine pitch in a printed circuit board for mounting electronic components, semiconductor chips, and the like.

[0004] Another of the various objects of the present invention is to provide a printed circuit board which is capable of preventing defects caused by galvanic corrosion from occurring between the pads and the surface treatment layer on the lower surface when forming metal posts on the upper surface.

[0005] Another of the various objects of the present invention is to provide a printed circuit board that can improve reliability. [Means for solving the problem]

[0006] One of several solutions proposed through the present invention is to provide a printed circuit board including a wiring section including one or more insulating layers, one or more wiring layers respectively disposed on or within the one or more insulating layers, a first pad disposed on a lowermost insulating layer of the one or more insulating layers, and a second pad disposed on an uppermost insulating layer of the one or more insulating layers, a first solder resist layer disposed below the wiring section and covering at least a portion of the first pad and having a first opening on the first pad, a second solder resist layer disposed above the wiring section and covering at least a portion of the second pad, a first surface treatment layer disposed on at least a portion of the first pad, and a barrier layer disposed on the first solder resist layer, wherein the thickness of the barrier layer is thinner than the thickness of the first pad.

[0007] Another of several solutions proposed through the present invention is to provide a printed circuit board including a wiring section including one or more insulating layers, one or more wiring layers respectively disposed on or within the one or more insulating layers, a first pad disposed on the lowermost insulating layer of the one or more insulating layers, and a second pad disposed on the uppermost insulating layer of the one or more insulating layers, a first solder resist layer disposed below the wiring section and covering at least a portion of the first pad and having a first opening on the first pad, a second solder resist layer disposed above the wiring section and covering at least a portion of the second pad, a first surface treatment layer disposed on at least a portion of the first pad, and a barrier layer disposed on the first solder resist layer, wherein the barrier layer includes an inorganic oxide film. Effect of the Invention

[0008] Among the various effects of the present invention, one effect is that it is possible to provide a printed circuit board capable of realizing metal posts having a fine pitch in a printed circuit board for mounting electronic components, semiconductor chips, and the like.

[0009] Another advantage of the present invention is that it provides a printed circuit board that can prevent defects caused by galvanic corrosion from the pads and surface treatment layer on the lower surface when forming metal posts on the upper surface.

[0010] Another advantage of the present invention is that it provides a printed circuit board with improved reliability. [Brief description of the drawings]

[0011] [Figure 1] FIG. 1 is a block diagram illustrating a schematic example of an electronic device system. [Diagram 2] FIG. 1 is a perspective view illustrating an example of an electronic device. [Figure 3a] FIG. 1 is a cross-sectional view illustrating a schematic configuration of a printed circuit board according to an example. [Figure 3b] FIG. 1 is a cross-sectional view illustrating a schematic configuration of a printed circuit board according to an example. [Figure 4a] FIG. 11 is a cross-sectional view illustrating a printed circuit board according to another example. [Figure 4b] FIG. 11 is a cross-sectional view illustrating a printed circuit board according to another example. [Diagram 5] 1A to 1C are cross-sectional views illustrating a method for manufacturing a printed circuit board according to an embodiment of the present invention. [Figure 6] 1A to 1C are cross-sectional views illustrating a method for manufacturing a printed circuit board according to an embodiment of the present invention. [Figure 7] 1A to 1C are cross-sectional views illustrating a method for manufacturing a printed circuit board according to an embodiment of the present invention. [Figure 8] 1A to 1C are cross-sectional views illustrating a method for manufacturing a printed circuit board according to an embodiment of the present invention. [Figure 9] 1A to 1C are cross-sectional views illustrating a method for manufacturing a printed circuit board according to an embodiment of the present invention. [Figure 10] 1A to 1C are cross-sectional views illustrating a method for manufacturing a printed circuit board according to an embodiment of the present invention. [Figure 11] 1A to 1C are cross-sectional views illustrating a method for manufacturing a printed circuit board according to an embodiment of the present invention. [Figure 12]1A to 1C are cross-sectional views illustrating a method for manufacturing a printed circuit board according to an embodiment of the present invention. [Figure 13] 1A to 1C are cross-sectional views illustrating a method for manufacturing a printed circuit board according to an embodiment of the present invention. [Figure 14] 1A to 1C are cross-sectional views illustrating a method for manufacturing a printed circuit board according to an embodiment of the present invention. [Figure 15] 1A to 1C are cross-sectional views illustrating a method for manufacturing a printed circuit board according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] The present invention will now be described with reference to the accompanying drawings, in which the shapes and sizes of elements may be exaggerated or reduced for clarity.

[0013] electronic equipment FIG. 1 is a block diagram illustrating an example of an electronic device system.

[0014] Referring to the drawing, an electronic device 1000 accommodates a main board 1010. Chip-related components 1020, network-related components 1030, and other components 1040 are physically and / or electrically connected to the main board 1010. These are also connected to other electronic components described below to form various signal lines 1090.

[0015] The chip-related components 1020 include, but are not limited to, memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), and flash memory; application processor chips such as central processors (e.g., CPU), graphic processors (e.g., GPU), digital signal processors, encryption processors, microprocessors, and microcontrollers; and logic chips such as analog-to-digital converters and ASICs (application-specific ICs). Needless to say, the chip-related components 1020 may include other types of chip-related electronic components. Needless to say, these chip-related components 1020 may be combined with each other. The chip-related components 1020 may be in the form of a package including the above-mentioned chips and electronic components.

[0016] The network-related components 1030 may include, but are not limited to, any other wireless and wired protocols designated as Wi-Fi (e.g., IEEE 802.11 family), WiMAX (e.g., IEEE 802.16 family), IEEE 802.20, LTE (long term evolution), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPS, GPRS, CDMA, TDMA, DECT, Bluetooth, 3G, 4G, 5G, and beyond, as well as any of a number of other different wireless or wired standards and protocols. It should be understood that the network-related components 1030 may also be combined with the chip-related components 1020 and with each other.

[0017] The other components 1040 include high-frequency inductors, ferrite inductors, power inductors, ferrite beads, LTCC (low temperature co-firing ceramics), EMI (electromagnetic interference) filters, MLCC (multi-layer ceramic capacitors), etc. However, the other components 1040 are not limited to these, and may also include passive elements in the form of chip components used for various other different applications. It goes without saying that the other components 1040 may be combined with the chip-related components 1020 and / or the network-related components 1030.

[0018] Depending on the type of electronic device 1000, the electronic device 1000 may include other electronic components that may or may not be physically and / or electrically coupled to the main board 1010. Examples of other electronic components include, but are not limited to, a camera module 1050, an antenna module 1060, a display 1070, and a battery 1080. The other electronic components may include, but are not limited to, an audio codec, a video codec, a power amplifier, a compass, an accelerometer, a gyroscope, a speaker, a mass storage device (e.g., a hard disk drive), a compact disk (CD), a digital versatile disk (DVD), and the like. Needless to say, other electronic components used for various purposes may be included depending on the type of electronic device 1000.

[0019] The electronic device 1000 may be a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automotive, etc. However, the electronic device 1000 is not limited to these, and may be any other electronic device that processes data.

[0020] FIG. 2 is a perspective view that illustrates an example of an electronic device.

[0021] Referring to the drawings, the electronic device may be, for example, a smartphone 1100. A motherboard 1110 is housed inside the smartphone 1100, and various components 1120 are physically and / or electrically connected to the motherboard 1110. In addition, other components such as a camera module 1130 and / or a speaker 1140 that may or may not be physically and / or electrically connected to the motherboard 1110 are housed inside the smartphone 1100. Some of the components 1120 may be the above-mentioned chip-related components, for example, a component package 1121, but are not limited thereto. The component package 1121 may be in the form of a printed circuit board on which electronic components including active components and / or passive components are surface-mounted. Alternatively, the component package 1121 may be in the form of a printed circuit board in which active components and / or passive components are built-in. Meanwhile, it goes without saying that the electronic device is not necessarily limited to the smartphone 1100, and may be other electronic devices as described above.

[0022] Printed Circuit Board 3a and 3b are schematic cross-sectional views of a printed circuit board according to an example.

[0023] 3a, the printed circuit board according to an example may include a wiring part 100 including one or more insulating layers 110, one or more wiring layers 120 disposed on or within the one or more insulating layers 110, a first pad 141 disposed on the lowermost insulating layer of the one or more insulating layers 110, and a second pad 142 disposed on the uppermost insulating layer of the one or more insulating layers 110. The printed circuit board according to an example may also include a first solder resist layer 171 disposed below the wiring part 100, covering at least a portion of the first pad 141, and having a first opening 171O, a first surface treatment layer 161 disposed on at least a portion of the first pad 141, a barrier layer 180 disposed on the first solder resist layer 171, a second solder resist layer 172 disposed on the upper side of the wiring part 100, and a metal post 150 disposed on the second solder resist layer 172. A second surface treatment layer 162 may be further included on the metal post 150. In this case, the barrier layer 180 may include an inorganic oxide film, and the thickness of the barrier layer 180 may be thinner than the thickness of the first pad 141 and thinner than the thickness of the first surface treatment layer 161.

[0024] Since the printed circuit board according to the example includes the barrier layer 180 on the first solder resist layer 171, at least a portion of the first surface treatment layer 161 disposed on the first pad 141 can be covered by the barrier layer 180. Since the first surface treatment layer 161 is covered by the barrier layer 180, galvanic corrosion due to etching can be prevented from occurring in the step of forming the metal post 150 on the second pad 142.

[0025] Galvanic corrosion may occur when two metals having different electrochemical properties such as standard reduction potential are electrically connected and exposed to a corrosive solution, and refers to a phenomenon in which corrosion occurs in the metal that is more active or has a lower standard reduction potential value among the two metals. The first surface treatment layer 161 may preferably include gold (Au) at the outermost portion, and the second pad 142 may preferably include copper (Cu). In order to form the metal post 150 on the second pad 142, the second pad 142 and the first surface treatment layer 161 may be simultaneously exposed to an etching solution for soft etching in a step of pretreating the second pad 142 through the second opening 172O of the second solder resist layer 172. As a result, the second pad 142 including copper (Cu) having a relatively low standard reduction potential acts as a negative electrode, and the first surface treatment layer 161 including gold (Au) having a relatively high standard reduction potential acts as a positive electrode, causing galvanic corrosion to occur between the second pad 142 and the first surface treatment layer 161. More specifically, galvanic corrosion may occur in the second pad 142, causing defects in the second pad 142, and the metal post 150 disposed on the second pad 142 may also cause defects. Meanwhile, the metal materials of the first surface treatment layer 161 and the second pad 142 are not necessarily limited thereto, and may include all cases in which galvanic corrosion may occur between the first surface treatment layer 161 and the second pad 142 due to differences in standard reduction potential.

[0026] As described above, in the printed circuit board according to an example, the first surface processing layer 161 is disposed on the first pad 141, and then the barrier layer 180 is formed on the first solder resist layer 171, so that the second pad 142 and the first surface processing layer 161 can be prevented from being simultaneously exposed to an etching solution in the pre-processing step of the second pad 142. More specifically, the barrier layer 180 is conformally disposed along the lower surface of the first surface processing layer 161, the inner wall of the first opening 171O formed in the first solder resist layer 171, and the lower surface of the first solder resist layer 171, so that galvanic corrosion of the second pad 142 can be prevented. Meanwhile, the barrier layer 180 may include a thin oxide film, but is not necessarily limited thereto.

[0027] The printed circuit board according to the embodiment can prevent galvanic corrosion of the second pads 142, and therefore can prevent defects even if the second pads 142 and the metal posts 150 are designed to have a fine pitch. Therefore, this can be advantageous for connecting a configuration having a fine pitch, such as a semiconductor chip, to the upper side of the wiring unit 100.

[0028] The insulating layer 110 may be composed of one or more insulating layers 110, and may include a first insulating layer 111 which is a core layer and a second insulating layer 112 which is a build-up insulating layer. The insulating layer 110 may include an insulating material. The insulating material may include a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide, or a material including an inorganic filler, an organic filler, and / or a glass fiber (Glass Fiber, Glass Cloth, and / or Glass Fabric) together with such a resin. The insulating material may be a photosensitive material and / or a non-photosensitive material. For example, the insulating material of the insulating layer 110 may be an insulating material of ABF (Ajinomoto Build-up Film), but is not limited thereto, and may include PPG (Prepreg), RCC (Resin Coated Copper), PID (Photo Imageable Dielectric), FR-4, BT (Bismaleimide Triazine), etc. However, it is not limited thereto, and other materials having excellent rigidity such as a glass material may be used as necessary.

[0029] The wiring layer 120 can be composed of one or more wiring layers, and can include a first wiring layer 121 arranged on the first insulating layer 111, and a second wiring layer 122 as a build-up wiring layer arranged on or within the second insulating layer 112.

[0030] The wiring layer 120 may include a metal material. The metal material may be copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), lead (Pb), titanium (Ti), or an alloy thereof. The metal material may preferably include copper (Cu), but is not limited thereto, and the first wiring layer 121 and the second wiring layer 122 may include different metal materials. The wiring layer 120 may perform various functions according to the design. For example, it may include a signal pattern, a power pattern, a ground pattern, etc., but is not limited thereto, and may function as a pad for mounting electronic components and chips, or as a stopper for forming a cavity. Each of these patterns may have various forms, such as a line, a plane, and a pad. The wiring layers 120 may have different pitches according to their functions. When a high density fine pitch is required in the wiring layers 120 for connection to a connecting structure or a semiconductor chip, etc., the spacing between the wiring layers 120 may be narrow, and when other signal connections, etc. are performed, the spacing between the wiring layers 120 may be wider.

[0031] The wiring layer 120 may be formed by any one of a semi-additive process (SAP), a modified semi-additive process (MSAP), a tenting (TT), or a subtractive process, but is not limited thereto. The wiring layer 120 may include, but is not limited to, an electroless plating layer (or chemical copper) as a seed layer and an electrolytic plating layer (or electrolytic copper) as a plating layer. A sputtering layer may be formed as the electroless plating layer instead of chemical copper. If necessary, a copper foil may be further included.

[0032] The wiring unit 100 of the printed circuit board according to an example may include a via layer 130 that connects the wiring layers 120 to each other. The via layer 130 may be composed of one or more via layers, and may include a first via layer 131 as a through via that penetrates the first insulating layer 111, and a second via layer 132 as a build-up via layer that penetrates at least a portion of the second insulating layer 112.

[0033] The first via layer 131 may include a metal layer formed on the wall surface of a through hole penetrating the first insulating layer 111, and a plug filling the metal layer. The metal layer may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof, and may preferably include copper (Cu), but is not limited thereto. The plug may include an ink of an insulating material. The metal layer may include, but is not limited to, an electroless plating layer (or chemical copper) and an electrolytic plating layer (or electrolytic copper). A sputtering layer may be formed instead of the electroless plating layer, or both may be included. The first via layer 131 may perform various functions according to the design. For example, it may include a ground via, a power via, a signal via, etc.

[0034] The second via layer 132 may include microvias. The microvias may be filled vias that fill a via hole, or may be conformal vias that are arranged along the wall surface of a via hole. The microvias may be arranged in a stacked type and / or staggered type. The second via layer 132 may include a metal, and the metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof, and may preferably include copper (Cu), but is not limited thereto. The second via layer 132 may include an electroless plating layer (or chemical copper) and an electrolytic plating layer (or electrolytic copper), but is not limited thereto. A sputtering layer may be formed instead of the electroless plating layer, or both may be included. The second via layer 132 may perform various functions depending on the design of the layer. For example, they may include ground vias, power vias, signal vias, and the like.

[0035] The printed circuit board according to an example may include a first pad 141 under the wiring part 100. The first pad 141 may be disposed on the insulating layer disposed at the lowest side of the second insulating layer 112 or in the insulating layer disposed at the lowest side of the second insulating layer 112. In FIG. 3a, the first pad 141 is illustrated as being disposed on the second insulating layer 112 and protruding from the lower side of the second insulating layer 112, but is not necessarily limited thereto. The first pad 141 may have a so-called coreless structure in which the first pad 141 is embedded under the second insulating layer 112. The first pad 141 may be connected to at least a portion of the second wiring layer 122 through one of the second via layers 132.

[0036] The first pad 141 may include a metal material, and the metal material may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or an alloy thereof, and may preferably include copper (Cu), but is not limited thereto. The first pad 141 is disposed at the bottom of the printed circuit board and may function as a connection pad so that the bottom surface of the printed circuit board may be connected to other components such as a main board. However, without being limited thereto, the first pad 141 may also function as a means for connecting to a component having a fine pitch, such as a semiconductor chip, and the pitch may be designed in various ways depending on the function. The first pad 141 may perform various functions depending on the design. For example, it may include a ground pad, a power pad, a signal pad, etc. Here, the signal pad may include a pad for electrically connecting various signals other than ground, power, etc., such as a data signal, etc.

[0037] The printed circuit board according to an example may include a second pad 142 on the upper side of the wiring part 100. The second pad 142 may be disposed on the uppermost insulating layer of the second insulating layer 112 or in the uppermost insulating layer of the second insulating layer 112. In FIG. 3a, the second pad 142 is disposed on the second insulating layer 112 and is shown to protrude upward from the second insulating layer 112, but the present invention is not limited thereto, and the second pad 142 may also have a structure embedded in the second insulating layer 112. In this case, since the second pad 142 may have a pad structure with a finer pitch than the first pad 141, as a non-limiting example, the structure in which the second pad 142 is embedded in the second insulating layer 112 is more preferable than the structure in which the first pad 141 is embedded in the second insulating layer 112. The second pad 142 may be connected to at least a portion of the second wiring layer 122 through one via layer 130 of the second via layer 132.

[0038] The second pads 142 may include a metal material, and examples of the metal material may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof, and may preferably include copper (Cu), but are not limited thereto. The second pads 142 may be disposed on the top side of the printed circuit board, and may be an area for mounting electronic components and chips, or may be connected to a circuit pattern for signal connection with other pads. The second pads 142 may perform various functions according to the design. For example, they may include ground pads, power pads, signal pads, and the like. Here, the signal pads may include pads for electrical connection of various signals, such as data signals, other than ground and power. When a high density fine pitch is required for mounting a semiconductor chip, etc., the spacing between the second pads 142 may be narrow, and when mounting an electronic component, the spacing between the second pads 142 may be wider. Furthermore, the second pads 142 in the area where a semiconductor chip or the like is mounted through another component such as the connecting structure 200 may be formed with a narrower spacing.

[0039] The first pad 141 and the second pad 142 may each be formed by any one of a Semi Additive Process (SAP), a Modified Semi Additive Process (MSAP), a Tenting (TT), or a subtractive method, but are not limited thereto, and may be formed using a method available to a person having ordinary knowledge in the art.

[0040] The printed circuit board according to an example may include a first solder resist layer 171 and a second solder resist layer 172 respectively disposed on the lower side and the upper side of the wiring portion 100. The first solder resist layer 171 may be disposed on the insulating layer disposed on the lowermost side of the second insulating layer 112, and the second solder resist layer 172 may be disposed on the insulating layer disposed on the uppermost side of the second insulating layer 112.

[0041] The first solder resist layer 171 and the second solder resist layer 172 are disposed on the outermost side of the printed circuit board, and can protect the printed circuit board from the outside. The first solder resist layer 171 and the second solder resist layer 172 can use a known solder resist, and each of the first solder resist layer 171 and the second solder resist layer 172 includes a thermosetting resin and an inorganic filler dispersed in the thermosetting resin, but does not need to include glass fiber. The insulating resin may be a photosensitive insulating resin, and the filler may be an inorganic filler and / or an organic filler, but is not limited thereto, and other polymer materials may be used as necessary. When a photosensitive insulating resin is used as the solder resist layer, it may be advantageous for forming fine openings, but is not limited thereto, and fine openings can also be formed by including a non-photosensitive insulating resin and forming fine openings with a UV laser.

[0042] The first solder resist layer 171 may have a first opening 171O, and at least a portion of the first pad 141 may be exposed by the first opening 171O. That a portion of the first pad 141 may be exposed by the first opening 171O may mean that the first solder resist layer 171 covers the first pad 141, but does not cover the first pad 141 in the region where the first opening 171O is formed. That is, it may mean that not only the first pad 141 is exposed to the outside of the printed circuit board, but also the first solder resist layer 171 does not cover a portion of the first pad 141, so that a portion of the first pad 141 may be connectable to another component.

[0043] Meanwhile, in Fig. 3a, the first opening 171O of the first solder resist layer 171 is shown exposing a part of the upper surface of the first pad 141, but the first solder resist layer 171, the first opening 171O, and the first pad are not limited to being aligned in a solder mask defined (SMD) form, and may be aligned in a non-solder mask defined (NSMD) form, and the relationship between the first pad 141 and the first solder resist layer 171 is not limited to that shown in the drawing. When aligned in the NSMD form, the width of the first opening 171O of the first solder resist layer 171 may be formed wider than the width of the first pad 141, and not only the upper surface of the first pad 141 is exposed by the first solder resist layer 171, but also the side of the first pad 141 may be exposed by the first solder resist layer 171.

[0044] The second solder resist layer 172 may cover at least a portion of the second pad 142. In addition, the metal post 150 may penetrate a portion of the second solder resist layer 172 and may have a structure protruding from the second solder resist layer 172. The metal post 150 protruding from the second solder resist layer 172 may mean that the upper surface of the metal post 150 may be located higher than the upper surface of the solder resist layer 160.

[0045] The second solder resist layer 172 may further expose at least a portion of the second pad 142 through the second opening, and the second opening may be filled with the metal post 150. At this time, the width of the lower end of the metal post 150 in the region where the metal post 150 and the second pad 142 contact each other may be formed to be smaller than the width of the second pad 142. Meanwhile, as described above, the width of the second opening formed in the second solder resist layer 172 may also have various widths like the width of the first opening 171O, so the width of the metal post 150 may be formed to be wider than the width of the second pad 142.

[0046] The printed circuit board according to an example may further include a first surface treatment layer 161 disposed on at least a portion of the first pad 141. The first surface treatment layer 161 may include any one of nickel (Ni), palladium (Pd), and gold (Au), and may also be realized with a plurality of these metal layers. For example, the first surface treatment layer 161 may be at least a portion of an ENEPIG (Electroless Nickel Electroless Palladium Immersion Gold) structure, or at least a portion of an ENIG (Electroless Nickel Immersion Gold) structure. In this case, the first surface treatment layer 161 may include a gold (Au) plating layer on the outermost side. The gold (Au) plating layer may be formed by electroless plating, and preferably may be formed by displacement plating. The first surface treatment layer 161 may improve the adhesion and signal transmission between the first pad 141 and the connection member. In FIG. 3a, the first surface treatment layer 161 is illustrated as being composed of one layer, but is not limited thereto. The first surface processing layer 161 may be realized by a plurality of metal layers as described above, but the boundaries between them may not be clearly distinguished.

[0047] The first surface processing layer 161 can cover at least a part of the first pad 141. The first surface processing layer 161 can cover a part of the first pad 141 exposed by the first opening 171O of the first solder resist layer 171. At this time, since the first surface processing layer 161 can be formed after the first opening 171O is formed in the first solder resist layer 171, when the shape of the first opening 171O has an NSMD structure different from that of FIG. 3a, the first surface processing layer 161 may be disposed so as to cover the side surface of the first pad 141.

[0048] Since the first surface treatment layer 161 may include a gold (Au) plating layer on the outermost side, there is a possibility that galvanic corrosion may occur in the second pad 142.

[0049] The printed circuit board according to an example may include a barrier layer 180 disposed on the first solder resist layer 171. Referring to FIG. 3a, the barrier layer 180 may be disposed on the lower surface of the first solder resist layer 171, and may be disposed along the inner wall of the first opening 171O and at least a part of the first surface treatment layer 161. The barrier layer 180 may be disposed to cover a part of the first surface treatment layer 161, so that the first surface treatment layer 161 may not be exposed to the outside. That is, since the barrier layer 180 covers the first surface treatment layer 161, galvanic corrosion may be prevented in the process of pretreating the second pad 142 before forming the metal post 150. In particular, the barrier layer 180 may cover a gold (Au) plating layer disposed on the outermost side of the first surface treatment layer 161.

[0050] The barrier layer 180 may include an oxide film containing an inorganic oxide. The inorganic oxide may be an alumina film, for example, Al 2 O 3 The oxide film may be, but is not limited to, TiO 2 , ZnO, SiO 2 The barrier layer 180 may be an oxide film including a metal oxide such as SiO 2 , SiO 2 , and the like. The barrier layer 180 may be a coating layer formed using a thin film deposition method, for example, ALD (Atomic Layer Deposition) or MVD (Molecular Vapor Deposition). In this case, a thin oxide film can be formed by the deposition method, and as a non-limiting example, the barrier layer 180 may include a thin film having a thickness of less than 100 nm, for example, about 1 nm to 10 nm. The barrier layer 180 may be thinner than the first pad 141 and may be thinner than the first surface treatment layer 161. The barrier layer 180 has a nanoscale thickness, while the first pad 141 and the first surface treatment layer 161 may have a microscale thickness, and therefore the thickness of the barrier layer 180 may be thinner than the first pad 141 and the first surface treatment layer 161.

[0051] Meanwhile, since the barrier layer 180 may include a thin inorganic oxide film, the first pad 141 and the first surface treatment layer 161 may be electrically isolated from other components connected to the lower part of the printed circuit board. For example, when the printed circuit board is mounted on a main board via a connecting metal, the barrier layer 180 may be located between the first pad 141 and the first surface treatment layer 161 and the connecting metal. However, when the oxide film included in the barrier layer 180 is a metal oxide, a connecting metal containing a metal material of the same element as the metal oxide of the barrier layer 180 may be used. For example, when the barrier layer 180 is Al 2 O 3 In the case where the interconnect metal is formed, the interconnect metal may be selected to include aluminum (Al). In this case, the Al of the barrier layer 180 at the stage where the interconnect metal is formed may be 2 O 3 In the region where the connection metal and the barrier layer 180 contact each other, aluminum (Al) elements diffuse, and a portion of the oxide film of the barrier layer 180 may be removed from the portion where the connection metal and the barrier layer 180 contact each other. As a result, the first pad 141 and the first surface treatment layer 161 may be electrically connected to other components through the connection metal. Therefore, when the printed circuit board is electrically connected to other components, such as a main board, through the connection metal, even if a portion of the barrier layer 180 is not visible in the region where the connection metal and the barrier layer 180 contact each other, this may be a phenomenon due to the above-mentioned diffusion, and therefore may fall within the scope of the present invention.

[0052] The printed circuit board according to an example may further include a metal post 150 disposed on at least a portion of the second pad 142. The metal post 150 may be disposed on the second pad 142 and may penetrate at least a portion of the second solder resist layer 172. The metal post 150 may include a metal material. The metal material may be copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), lead (Pb), titanium (Ti), or an alloy thereof. The metal material may preferably include, but is not limited to, copper (Cu). The metal post 150 may be a region for mounting electronic components and chips, and may be configured to protrude in order to facilitate connection when the electronic components and chips are mounted on the second pad 142. The metal post 150 may perform various functions according to the design of the second pad 142. The metal post 150 may electrically transmit and receive signals to and from the pad 120.

[0053] In the case where a high density fine pitch is required for mounting a semiconductor chip or the like in the second pads 142, not only the interval between the second pads 142 but also the interval between the metal posts 150 may be narrowed. By disposing the metal posts 150 on the second pads 142, even if a fine pitch semiconductor chip is mounted, the possibility of a short circuit of the connecting member 400 disposed between the semiconductor chip and the metal posts 150 can be reduced, and the failure of the semiconductor chip being detached can also be reduced. In addition, by disposing the metal posts 150 on the second pads 142, it is possible to ensure adhesion through the metal posts 150 compared to a structure in which the connecting member 400 is disposed directly on the second pads 142, thereby improving the reliability of the printed circuit board.

[0054] The metal post 150 may be formed by any one of SAM (Semi Additive Process), MSAP (Modified Semi Additive Process), TT (Tenting), or subtractive methods, but is not limited thereto, and may be formed using any method available to a person having ordinary skill in the art.

[0055] The printed circuit board according to an example may further include a second surface treatment layer 162 disposed on at least a portion of the metal post 150. The second surface treatment layer 162 may include any one of nickel (Ni), palladium (Pd), and gold (Au), and may be realized by a plurality of these metal layers. For example, the second surface treatment layer 162 may be at least a portion of an ENEPIG (Electroless Nickel Electroless Palladium Immersion Gold) structure, or at least a portion of an ENIG (Electroless Nickel Immersion Gold) structure. The second surface treatment layer 162 is not limited thereto, and may include an OSP (Organic Solder Passivation) structure including an organic substance. The second surface treatment layer 162 may improve the adhesion and signal transmission between the metal post 150 and the connection member. In FIG. 3a, the second surface treatment layer 162 is illustrated as being configured by one layer, but is not limited thereto, and the second surface treatment layer 162 may be realized by a plurality of metal layers as described above.

[0056] The second surface treatment layer 162 can cover at least a portion of the metal post 150. In FIG. 3a, the second surface treatment layer 162 is shown as covering the top surface of the metal post 150, but is not limited thereto and may be disposed to further cover the exposed side surface of the metal post 150.

[0057] The printed circuit board according to an embodiment may further include a connecting structure 200 and an adhesive layer 210. The connecting structure 200 may be connected to an electronic component such as a semiconductor chip, and may have a bridge structure, for example. The connecting structure 200 may include a body having a pattern realized on an insulating material, and may include a connection part 201 for connecting to the wiring part 100. The connecting structure 200 may be an organic substrate, or may be a silicon bridge having a circuit realized on a silicon wafer or the like. The connecting structure 200 may be, but is not limited to, one semiconductor chip embedded in the wiring part 100 of the printed circuit board.

[0058] The connection structure 200 may be disposed in a cavity that penetrates at least a portion of the second insulating layer 112 and may be embedded by the second insulating layer 112. An adhesive layer 210 may be further included to mount the connection structure 200 in the cavity. The structure and mounting of the connection structure 200 may be formed using structures and methods available to a person of ordinary skill in the art.

[0059] Referring to FIG. 3b, an example of a printed circuit board may further include semiconductor chips 301, 302 disposed on the metal posts 150, and may further include a connecting member 400 connecting the metal posts 150 and the semiconductor chips 301, 302 to each other.

[0060] The semiconductor chips 301 and 302 may be integrated circuits (ICs) in which several hundred to several million or more circuits are integrated in one chip. Each of these may be a processor chip such as a central processor (e.g., CPU), a graphics processor (e.g., GPU), a field programmable gate array (FPGA), a digital signal processor, an encryption processor, a microprocessor, or a microcontroller, specifically, an application processor (AP: Application Processor), but is not limited thereto, and may be a logic chip such as an analog-to-digital converter or an application-specific IC (ASIC) memory controller (MC: Memory Controller) chip, or a memory chip such as a dynamic random access memory (DRAM) chip, a static random access memory (SRAM) chip, a flash memory chip, a phase-change random access memory (PRAM) chip, a magnetic random access memory (MRAM) chip, a resistive random access memory (RRAM) chip, an electrically erasable and programmable read-only memory (EEPROM) chip, or a high bandwidth memory (HBM), and it goes without saying that these may be arranged in combination with each other.

[0061] The semiconductor chip 200 may be composed of a body and connection pads, and the surface on which the connection pads for connection to the metal post 150 are arranged may be an active surface, and the opposite surface may be an inactive surface, but is not limited thereto, and may be capable of double-sided connection, and may have a three-dimensional structure in some cases. The semiconductor chips 301 and 302 may be formed based on an active wafer, and in this case, silicon (Si), germanium (Ge), gallium arsenide (GaAs), etc. may be used as the base material for the body. Various circuits may be formed within the semiconductor chips 301 and 302, and at least some of these circuits may be connected to the connection pads.

[0062] The connecting members 400 may be formed of a conductive material, for example, solder, but the material of the connecting members 400 is not particularly limited thereto. Also, the connection method of the connecting members 400 is not limited thereto, and may be configured with a land, a ball, a pin, etc. Also, the connecting members 400 may be formed in a multi-layer or single layer. When formed in a multi-layer, it may include copper pillars and solder, and when formed in a single layer, it may include tin-silver solder or copper, but is not limited thereto.

[0063] 3b shows two semiconductor chips 301, 302 arranged on a printed circuit board, but is not limited thereto. In particular, the semiconductor chips 301, 302 are shown as being connected die-to-die via the connecting structure 200, but is not necessarily limited thereto. The number and arrangement of the semiconductor chips 301, 302, and the number, interval, arrangement, etc. of the connecting member 400 are not particularly limited, and can be easily modified by ordinary engineers according to design matters.

[0064] The printed circuit board according to the example is not limited to the configuration shown in Figures 3a and 3b, and may further include other configurations in some cases, i.e., may further include configurations that can be utilized by a person having ordinary skill in the art.

[0065] 4a and 4b are cross-sectional views that show schematic diagrams of a printed circuit board according to another example.

[0066] 4a and 4b, the printed circuit board according to the other example may have a different arrangement of the barrier layer 180 compared to the printed circuit board according to the one example.

[0067] The barrier layer 180 of the printed circuit board according to another example may not be disposed in the first opening 171O, and may not be disposed on the first surface processing layer 161. This may be a result of performing a step of removing a part of the barrier layer 180 after preventing galvanic corrosion in the step of forming the metal post 150 using the barrier layer 180. This may be a result of performing a step of selectively removing a part of the barrier layer 180, such as dry etching, so that the barrier layer 180 does not cover the first opening 171O and the first surface processing layer 161. Since the barrier layer 180 may include an oxide film, if the barrier layer 180 is not disposed on the first surface processing layer 161, it may be easier to connect the first pad 141 through the first surface processing layer 161 when the printed circuit board is bonded to another component.

[0068] On the other hand, among the configurations other than the contents regarding the arrangement and shape of the barrier layer 180, the configurations similar to those of the printed circuit board of one example can also be applied to the printed circuit board of another example, so duplicated explanations regarding this will be omitted.

[0069] Printed circuit board manufacturing method 5 to 15 are cross-sectional views that are schematic diagrams illustrating a method for manufacturing a printed circuit board according to an example.

[0070] The method for manufacturing a printed circuit board according to an example may include the steps of preparing a wiring portion 100, forming a first solder resist layer 171 under the wiring portion 100, forming a second solder resist layer 172 over the wiring portion 100, forming a first opening 171O in the first solder resist layer so that at least a part of the first pad 141 is exposed, forming a first surface treatment layer 161 on the exposed part of the first pad 141, forming a barrier layer on the first solder resist layer, and forming a metal post on the second pad. In this case, the method for manufacturing a printed circuit board according to an example may not include the step of removing the entire barrier layer, and the barrier layer 180 may remain on the first solder resist layer 171 in the printed circuit board.

[0071] 5, the method may include a step of preparing a wiring unit 100. The wiring unit 100 may include one or more insulating layers 110, one or more wiring layers 120 disposed on or within the one or more insulating layers 110, a first pad 141 disposed on a lowermost insulating layer of the one or more insulating layers 110, and a second pad 142 disposed on an uppermost insulating layer of the one or more insulating layers 110. The step of preparing the wiring unit 100 may include a step of forming a first wiring layer 121 on the first insulating layer 111, and a step of forming a second insulating layer 112 on the first insulating layer 111 to form a second wiring layer 122. The method may include a step of forming the first pad 141 and the second pad 142 on the second insulating layer 112 disposed on the outermost side. At this time, the steps of forming the insulating layer 110 and the wiring layer 120 may be performed by a known build-up process.

[0072] Meanwhile, the manufacturing method of the printed circuit board according to an example may further include a step of forming a cavity penetrating at least a portion of the second insulating layer 112, attaching and mounting the connecting structure 200 with an adhesive layer 210, and embedding the connecting structure 200 in the second insulating layer 112, but is not necessarily limited thereto.

[0073] The method may include a step of forming a first solder resist layer 171 on the lower side of the wiring portion 100, and a step of forming a second solder resist layer 172 on the upper side of the wiring portion 100. The respective solder resist layers may be formed simultaneously, but are not necessarily limited to this. The method of forming the first solder resist layer 171 and the second solder resist layer 172 may be any method known in the art for forming solder resists, without any limitations.

[0074] 6, a step of forming a first opening 171O in the first solder resist layer 171 may be performed. The first opening 171O may be formed on the first pad 141, and at least a portion of the first pad 141 may be exposed through the first opening 171O. The shape of the first opening 171O is not limited to the SMD structure shown in FIG. 6, and may have an NSMD structure, as described above for the printed circuit board. The method of forming the first opening 171O in the first solder resist layer 171 may be any method for forming an opening that is known in the art.

[0075] 7, a step of forming a first surface treatment layer 161 on at least a portion of the first pad 141 may be performed. The first surface treatment layer 161 may be formed of a plurality of metal layers by repeating electroless plating as described above with respect to the printed circuit board, and the outermost surface of the first surface treatment layer 161 may include a gold (Au) plating layer.

[0076] 8, the method may include forming a barrier layer 180 on the first solder resist layer 171. The barrier layer 180 may be formed using a thin film deposition method, for example, an atomic layer deposition (ALD) method, a molecular vapor deposition (MVD) method, etc. Since the deposition method may be a method with excellent step coverage, the barrier layer 180 may be disposed along the lower surface of the first solder resist layer 171, the inner wall of the first opening 171O, and a part of the first surface treatment layer 161.

[0077] 9, the method may include forming a second opening 172O in the second solder resist layer 172. At this time, the second pad 142 may be exposed through the second opening 172O. The method for forming the opening in the second solder resist layer 172 may be performed by UV laser processing or the like, but is not necessarily limited thereto, and the method for forming the second opening 172O in the second solder resist layer 172 may be any method for forming a known opening without limitation. At this time, the second opening 172O may be formed by a physical method, and may have a downward tapered shape, but is not necessarily limited thereto.

[0078] Thereafter, a pretreatment for forming the metal post 150 may be performed. As the pretreatment, a desmear process may be performed to remove residues formed on the second solder resist layer 172, and soft etching may be performed to process the exposed surface of the second pad 142. When the printed circuit board is exposed to an etching solution to perform the soft etching, an oxidation / reduction reaction may occur between the second pad 142 containing copper (Cu) and the first surface treatment layer 161 containing gold (Au), and galvanic corrosion may occur in the second pad 142. However, since the method for manufacturing the printed circuit board according to an example includes a step of forming a barrier layer 180 to cover the first surface treatment layer 161 before performing the pretreatment for forming the metal post 150, the first surface treatment layer 161 may not be exposed to the etching solution. Therefore, the second pad 142 may be protected from galvanic corrosion. Meanwhile, the metal material constituting the second pad 142 and the metal material constituting the first surface treatment layer 161 are not limited thereto, as described above with respect to the printed circuit board.

[0079] Thereafter, referring to FIGS. 10 to 15, a step of forming a metal post 150 and a second surface treatment layer 162 on the second pad 142 may be performed.

[0080] 10, a seed layer 150' may be formed. The seed layer 150' may be formed by electroless plating, or may be formed by chemical copper plating, but is not limited thereto, and may be formed by a sputtering method.

[0081] 11, a dry film resist (DFR) may be formed. Before plating, a plating resist may be formed.

[0082] 12, a plating layer 150'' may be formed. The plating layer 150'' may be formed by performing electrolytic plating using the seed layer 150'.

[0083] Referring to FIG. 13, a second surface treatment layer 162 may be formed on the plating layer 150 ″ of the metal post 150 .

[0084] Referring to FIG. 14, the dry film resist (DFR) may be removed.

[0085] Referring to FIG. 15, portions of the seed layer 150 ′ may be removed to complete the metal posts 150 .

[0086] The step of forming the metal post 150 is not limited thereto, and can be formed using a method available to a person having ordinary skill in the art. Meanwhile, the steps of forming the metal post 150 and the second surface processing layer 162 are not necessarily limited to the contents shown in Figs. 10 to 15, and depending on the case, the step of forming the second surface processing layer 162 can be performed after completing the metal post 150. In this case, the step corresponding to Fig. 12 can be performed last.

[0087] On the other hand, the method for manufacturing a printed circuit board according to an embodiment is not necessarily limited to the contents shown in FIGS. 5 to 15, and can be appropriately modified and changed as necessary.

[0088] In addition, the method for manufacturing a printed circuit board according to another example may include the step of removing a portion of the barrier layer 180 to expose the first surface treatment layer 161. The step of removing the portion of the barrier layer 180 is preferably performed after the step of forming the metal post 150 and the second surface treatment layer 162, but is not necessarily limited thereto.

[0089] In the present invention, the meaning of a cross section can mean a cross-sectional shape when an object is cut vertically or a cross-sectional shape when the object is viewed from the side, and the meaning of a plane can mean a shape when an object is cut horizontally or a planar shape when the object is viewed from the top or bottom.

[0090] In the present invention, for convenience, the terms "upper side, upper part, top surface" and the like are used to mean a direction toward a surface on which an electronic component can be mounted based on a cross section of a drawing, and the terms "lower side, lower part, bottom surface" and the like are used to mean the opposite direction. However, this is a definition of the direction for convenience of explanation, and it goes without saying that the scope of the claims is not particularly limited by the description of the direction.

[0091] In the present invention, "connected" is a concept including not only direct connection but also indirect connection via an adhesive layer or the like. Furthermore, "electrically connected" is a concept including both physical connection and no connection. Furthermore, expressions such as "first, second" are used to distinguish one component from another component, and do not limit the order and / or importance of the components. In some cases, the first component may be named the second component, and similarly, the second component may be named the first component, within the scope of the right.

[0092] In the present invention, the term "substantially" can be determined by taking into account process errors, positional deviations, measurement errors, etc. that occur during the manufacturing process. For example, "substantially perpendicular" can include not only a completely perpendicular case, but also a nearly perpendicular case. Furthermore, "substantially coplanar" can include not only a completely coplanar case, but also a nearly coplanar case.

[0093] In the present invention, the same material can mean not only the completely same material, but also the same type of material. Thus, although the composition of the materials is substantially the same, the specific composition ratios thereof may differ slightly.

[0094] The term "one example" used in the present invention does not mean the same embodiment, but is provided to emphasize and describe unique features that are different from each other. However, the above-mentioned one example does not exclude that it is realized in combination with the features of another example. For example, even if the matter described in a specific example is not described in another example, it can be understood as a description related to the other example, unless there is a description in the other example that is opposite or contradictory to the matter.

[0095] The terms used in the present invention are merely used to describe an example and are not intended to limit the present invention. In this case, a singular expression includes a plural expression unless the context clearly indicates otherwise. [Explanation of symbols]

[0096] 100: Wiring section 110: Insulating layer 111: First insulating layer 112: Second insulating layer 120: Wiring layer 121: 1st wiring layer 122: 2nd wiring layer 130: Via layer 131: First via layer 132: Second via layer 141: First pad 142: 2nd pad 150: Metal post 161: First surface treatment layer 162: Second surface treatment layer 171: First solder resist layer 171O: 1st opening 172: Second solder resist layer 172O: 2nd opening 180: Barrier layer 200: Linked structure 201: Connection part 210: Adhesive layer 301, 302: Semiconductor chips 400: Connecting member 1000:Electronic equipment 1010: Main board 1020: Chip related parts 1030: Network related parts 1040:Other parts 1050: Camera module 1060: Antenna module 1070:Display 1080: Battery 1090: Signal line 1100: Smartphone 1110: Main board inside a smartphone 1120: Electronic components inside smartphones 1121: Antenna module inside a smartphone 1130: Camera module inside a smartphone 1140: Speaker inside smartphone

Claims

1. a wiring section including one or more insulating layers, one or more wiring layers respectively disposed on or within the one or more insulating layers, a first pad disposed on a lowermost insulating layer of the one or more insulating layers, and a second pad disposed on an uppermost insulating layer of the one or more insulating layers; a first solder resist layer disposed below the wiring portion, covering at least a portion of the first pad, and having a first opening above the first pad; a second solder resist layer disposed on the wiring portion and covering at least a portion of the second pad; a first surface treatment layer disposed on at least a portion of the first pad; a barrier layer disposed on the first solder resist layer; The thickness of the barrier layer is less than the thickness of the first pad.

2. The printed circuit board of claim 1 , wherein the barrier layer is disposed on a lower surface of the first solder resist layer.

3. The printed circuit board of claim 2 , wherein the barrier layer is disposed along an inner wall of the first opening and at least a portion of the first surface treatment layer.

4. The printed circuit board of claim 1 , wherein the first solder resist layer covers at least a portion of an upper surface of the first pad.

5. The printed circuit board of claim 1 , wherein the second solder resist layer includes a second opening formed over the second pad.

6. The printed circuit board of claim 5 further comprising a metal post disposed in the second opening and overlying at least a portion of the second pad.

7. The printed circuit board of claim 6 , further comprising a second surface treatment layer disposed on the metal posts.

8. a first semiconductor chip disposed on the metal post; The printed circuit board of claim 6 , further comprising: a connecting member connecting the metal post and the first semiconductor chip to each other.

9. The printed circuit board according to claim 1 , wherein the barrier layer has a thickness less than a thickness of the first surface treatment layer.

10. 10. The printed circuit board of claim 9, wherein the barrier layer has a thickness of less than 100 nm.

11. a wiring section including one or more insulating layers, one or more wiring layers respectively disposed on or within the one or more insulating layers, a first pad disposed on a lowermost insulating layer of the one or more insulating layers, and a second pad disposed on an uppermost insulating layer of the one or more insulating layers; a first solder resist layer disposed below the wiring portion, covering at least a portion of the first pad, and having a first opening above the first pad; a second solder resist layer disposed on the wiring portion and covering at least a portion of the second pad; a first surface treatment layer disposed on at least a portion of the first pad; a barrier layer disposed on the first solder resist layer; The barrier layer comprises an inorganic oxide film.

12. The barrier layer is made of Al ２ O ３ , TiO ２ , ZnO, and SiO ２ The printed circuit board of claim 11, comprising at least one of:

13. The printed circuit board of claim 11 , wherein the barrier layer is disposed on a lower surface of the first solder resist layer.

14. The printed circuit board of claim 13 , wherein the barrier layer is disposed along an inner wall of the first opening and at least a portion of the first surface treatment layer.

15. The printed circuit board of claim 12 further comprising a metal post disposed on at least a portion of the second pad.

16. The printed circuit board of claim 11 , wherein the thickness of the barrier layer is less than the thickness of the first pad.

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