Synchronous serial interface circuit

Abstract

To provide a synchronous serial interface circuit which can reduce processing load without storing dummy data.SOLUTION: A synchronous serial interface circuit 10 includes: a sending buffer 12 for storing data to send; a receiving buffer 14 for storing data to receive; a control register 22 for setting the number of frames of commands adjusted to a device to communicate with and the directions of sending or receiving of each frame; and a frame number control circuit 24 for controlling sending or receiving operations and controlling the sending buffer and the receiving buffer according to the set content set by the control register 22.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a synchronous serial interface circuit. [Background technology]

[0002] Patent document 1 discloses a serial interface transfer device that uses a buffer capacity approximation means to estimate the required buffer capacity from the number of data frames stored in the buffer or the type of transfer data volume between the time the transfer data is stored in a buffer and the time the transfer data is received by an input / output processing device, and then allocates the required buffer capacity using a buffer capacity allocation means.

[0003] In addition, the technique of Patent Document 1 proposes a serial interface circuit having one buffer, but there is also a synchronous serial interface circuit 11 having a transmission buffer 12 and a reception buffer 14 as shown in FIG.

[0004] The synchronous serial interface circuit 11 in Fig. 4 is composed of a transmission buffer 12, a reception buffer 14, a serial / parallel conversion circuit 16, an interrupt control circuit 18, a control circuit 20, and a control register 22. As shown in Fig. 5, a microcomputer 30 is connected to a device 40 via a serial interface terminal 28 (an input terminal 28A, an output terminal 28B, and a clock terminal 28C). As shown in Fig. 6, an input signal MI input to the input terminal 28A and an output signal MO output from the output terminal 28B may have a pull-up 42.

[0005] The connected device 40 is controlled by commands defined in the respective specifications, and generally has a control register, which often consists of an address and data.

[0006] A master such as CPU 32 or DMAC (Direct Memory Controller) 34 on the microcomputer 30 sets the transfer size of one frame, the number of buffer stages, interrupt timing, and terminal state during idle time in the control register 22 and writes them to the transmit buffer 12, whereby a clock signal SCK is output from the serial interface terminal 28, and data written serially to the transmit buffer 12 in synchronization with the clock signal SCK is output from the output terminal 28B as an output signal MO. Also, data is taken in as an input signal MI from the input terminal 28A in synchronization with the clock signal SCK, and stored in the receive buffer 14.

[0007] The master on the microcomputer 30 generates an interrupt depending on the vacancy state of the transmission buffer 12 and writes the next transmission data, or generates an interrupt depending on the vacancy state of the reception buffer 14 and reads data from the reception buffer. [Prior art documents] [Patent documents]

[0008] [Patent Document 1] JP 2009-73389 A Summary of the Invention [Problem to be solved by the invention]

[0009] In a configuration with a transmit buffer 12 and a receive buffer 14, data must be written to the transmit buffer 12 even when receiving. When controlling the device 40, as shown in Fig. 7, for writing, it is sufficient to write an address and data to the transmit buffer 12. However, when reading, as shown in Fig. 8, if an address and dummy data are written to the transmit buffer 12, the dummy data at the time of address transmission and the data to be read are stored in the receive buffer 14. Therefore, the master microcomputer 30 had to process the dummy data for transmission and reception.

[0010] The present invention has been made in consideration of the above circumstances, and has an object to provide a synchronous serial interface circuit capable of reducing the processing load without storing dummy data. [Means for solving the problem]

[0011] The synchronous serial interface circuit according to the first aspect includes a transmit buffer for storing data to be transmitted, a receive buffer for storing received data, a setting unit for setting the number of command frames and the transmission and reception direction of each frame according to the device to be communicated with, and a control unit for controlling transmission and reception operations and controlling the transmit buffer and the receive buffer in accordance with the settings of the setting unit. Effect of the Invention

[0012] As described above, according to the present invention, it is possible to provide a synchronous serial interface circuit capable of reducing the processing load without storing dummy data. [Brief description of the drawings]

[0013] [Figure 1] 1 is a diagram illustrating a synchronous serial interface circuit according to an embodiment of the present invention. [Diagram 2] 1 is a diagram showing an image of access to a device having an address+data configuration when writing data in the synchronous serial interface circuit according to the present embodiment. FIG. [Diagram 3] 1 is a diagram showing an image of access to a device having an address+data configuration when reading data in the synchronous serial interface circuit according to the present embodiment. FIG. [Figure 4] FIG. 1 is a diagram showing an example of a conventional synchronous serial interface circuit including a transmission buffer and a reception buffer. [Diagram 5] FIG. 2 is a diagram illustrating an example of a connection between a microcontroller and a device. [Figure 6] FIG. 11 is a diagram illustrating another example of the connection between the microcontroller and the device. [Figure 7]FIG. 1 is a diagram showing an image of access to a device having an address+data configuration when writing data in a conventional synchronous serial interface circuit. [Figure 8] FIG. 1 is a diagram showing an image of access to a device having an address+data configuration when reading data in a conventional synchronous serial interface circuit. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] An example of an embodiment of the present invention will now be described in detail with reference to the drawings. Fig. 1 is a diagram showing a synchronous serial interface circuit according to this embodiment.

[0015] As shown in FIG. 1, the synchronous serial interface circuit 10 of this embodiment includes, as in the conventional case, a transmit buffer 12, a receive buffer 14, a serial-parallel conversion circuit 16, an interrupt control circuit 18, a control circuit 20, and a control register 22 as an example of a setting section.

[0016] Moreover, the synchronous serial interface circuit 10 according to this embodiment further includes a frame number control circuit 24 as an example of a control unit, in addition to the conventional configuration described above.

[0017] As shown in FIGS. 5 and 6, the microcomputer 30 is connected to a device 40 via serial interface terminals 28 (input terminal 28A, output terminal 28B, clock terminal 28C) in the same manner as in the conventional case.

[0018] The synchronous serial interface circuit 10 is connected to a CPU 32 or a DMAC 34 on a microcomputer 30 via a BUS-MUX 36 (bus multiplexer) connected to a data bus 38 .

[0019] The transmission buffer 12 is connected to the control register 22 and the serial-parallel conversion circuit 16. In the transmission buffer 12, data to be transmitted from the microcomputer 30 to the device 40 is stored via the control register 22.

[0020] The receive buffer 14 is connected to the control register 22 and the serial-to-parallel conversion circuit 16. In the receive buffer 14, data received from the device 40 is stored via the serial-to-parallel conversion circuit 16.

[0021] The serial-parallel conversion circuit 16 is, for example, a shift register and is provided between the transmission buffer 12 and the reception buffer 14 and the input terminal 28A and the output terminal 28B, and converts a serial signal into a parallel signal and converts a parallel signal into a serial signal.

[0022] The interrupt control circuit 18 generates a transmission interrupt for writing data to the transmission buffer 12 according to the free space state of the transmission buffer 12. Also, the interrupt control circuit 18 generates a reception interrupt for reading data from the reception buffer 14 according to the free space state of the reception buffer 14.

[0023] The control circuit 20 is connected to the control register 22 and to a clock terminal 28 C, and generates and outputs a clock signal SCK, and controls the operation of the control register 22 .

[0024] The control register 22 is connected to the BUS-MUX 36 and functions as a bus interface (BUS I / F) accessible from the CPU 32. The control register sets the transfer size of one frame, the number of buffer stages, interrupt timing, and the terminal state during idle time. It also sets the number of command frames and the transmission / reception direction of each frame in accordance with the device 40 to be communicated.

[0025] The frame number control circuit 24 includes a counter 26 that counts the number of frames, and performs transmission and reception operations and controls the receive buffer 14 and the transmit buffer 12 in accordance with the settings of the control register 22 based on the count value of the counter 26. That is, the frame number control circuit 24 controls the transmission and reception operations and controls the transmit buffer 12 and the receive buffer 14 so that data for the set number of frames is stored in the buffer corresponding to the transmission and reception direction set by the control register 22 out of the transmit buffer 12 and the receive buffer 14. In this embodiment, data is not stored in the buffer corresponding to the transmission and reception direction not set by the control register 22, and data for the set number of frames is stored in the buffer corresponding to the set transmission and reception direction.

[0026] Next, an example of the operation of the synchronous serial interface circuit 10 according to the present embodiment configured as described above will be described. Fig. 2 is a diagram showing an image of access to the device 40 having an address + data configuration when writing data, and Fig. 3 is a diagram showing an image of access to the device 40 having an address + data configuration when reading data.

[0027] As in the past, a master such as the CPU 32 or DMAC 34 on the microcomputer 30 sets the transfer size of one frame, the number of buffer stages, the interrupt timing, and the terminal state during idle time in the control register 22. In this embodiment, the number of command frames and the transmission / reception direction of each frame are set according to the device 40 to be communicated.

[0028] For example, in the case of writing, as shown in FIG. 2, the number of command frames, consisting of two address frames and two data frames, is set to 4, and frames 1 to 4 are all set to the transmission direction (TX) in the control register 22.

[0029] By writing data to the transmission buffer 12 according to the settings made in the control register 22 under the control of the frame number control circuit 24, the clock signal SCK is output from the serial interface terminal 28, and the data written serially to the transmission buffer 12 in synchronization with the clock signal SCK is output as the output signal MO from the output terminal MO. At this time, reception is completely ignored and no dummy data is stored in the reception buffer 14, thereby reducing the master processing load on the microcomputer 30.

[0030] For example, in the case of reading, as shown in FIG. 3, the number of command frames (2 address frames + 2 data frames) is set to 4, and frames 1 and 2 are set in the transmission direction (TX), and frames 3 and 4 are set in the reception direction (RX) in the control register 22.

[0031] Under the control of the frame number control circuit 24, data is written to the transmission buffer 12 according to the settings made in the control register 22, and a clock signal SCK is output from the serial interface terminal 28, and the data written serially to the transmission buffer 12 in synchronization with the clock signal SCK is output from the output terminal 28B as an output signal MO. At this time, no data is received between frames 1 and 2, and data is not stored in the reception buffer 14. Also, when the transmission of frame 2 is completed and there is space in the reception buffer 14, the clock signal SCK is output without writing dummy data to the transmission buffer 12, and data is taken in as an input signal MI from the input terminal MI and the taken in data is stored in the reception buffer 14. Then, when data corresponding to frames 3 and 4 is taken in and stored in the reception buffer 14, the process returns to waiting for frame 1 to be processed.

[0032] In this way, in the synchronous serial interface circuit 10 according to this embodiment, by setting the transmission / reception direction for each frame in advance, data is written and read without storing dummy transmission data and reception data in the transmission buffer 12 and reception buffer 14, thereby reducing the processing load of the master of the microcomputer 30. In particular, in the DMAC 34, the amount of RAM (Random Access Memory) used can be reduced.

[0033] In the above embodiment, an example of an image of access to device 40 when writing data and reading data is described using Figures 2 and 3. However, the number of frames, the transmission / reception direction, the contents to be stored, etc. are merely examples and are not limited to Figures 2 and 3.

[0034] Furthermore, the present invention is not limited to the above, and it goes without saying that various modifications can be made without departing from the spirit and scope of the present invention. [Explanation of symbols]

[0035] 10 Synchronous serial interface circuit 12 Send Buffer 14 Receive Buffer 20 Control circuit 22 Control Registers 24 Frame number control circuit 26 Counter

Claims

1. a transmit buffer for storing data to be transmitted; a receive buffer for storing received data; a setting unit that sets the number of command frames and the transmission / reception direction of each frame in accordance with a device to be communicated; a control unit that controls transmission and reception operations and controls the transmission buffer and the reception buffer in accordance with the settings of the setting unit; a synchronous serial interface circuit including:

2. 2. The synchronous serial interface circuit of claim 1, wherein the control unit includes a counter that counts the number of frames, and controls transmission and reception operations and the transmission buffer and the reception buffer based on the count value of the counter and in accordance with the settings of the setting unit.

3. 3. A synchronous serial interface circuit as described in claim 1 or claim 2, wherein the control unit controls transmission and reception operations and controls the transmission buffer and the reception buffer so as to store data of the set number of frames in the buffer corresponding to the transmission and reception direction set by the setting unit, out of the transmission buffer and the reception buffer.

4. 3. A synchronous serial interface circuit as described in claim 1 or claim 2, wherein the control unit controls transmission and reception operations and controls the transmission buffer and the reception buffer so that data is not stored in the transmission buffer and the reception buffer corresponding to the transmission and reception direction not set by the setting unit, and data for the set number of frames is stored in the buffer corresponding to the transmission and reception direction set by the setting unit.

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