Transistor including two-dimensional material, and manufacturing method for the same

Abstract

To provide a highly reliable transistor including a two-dimensional material in an active layer, and a manufacturing method for the transistor.SOLUTION: A transistor 100 is provided on a substrate 102 directly or through an undercoat, and includes a gate electrode 104, a gate insulating layer 106, a first conductivity type control layer 108 overlapping with the gate electrode, an active layer 110 in contact with the first conductivity type control layer and containing graphene or transition metal dichalcogenide, and a pair of terminals 112 and 114 electrically connected to the active layer. The first conductivity type control layer is held between the gate electrode and the active layer, and includes a two-dimensional layer nanosheet of metal oxide. The two-dimensional layer nanosheet may be single crystal.SELECTED DRAWING: Figure 1A

Description

[Technical field]

[0001] One embodiment of the present invention relates to a transistor including a two-dimensional material in an active layer and a method for manufacturing the same. [Background technology]

[0002] Two-dimensional materials such as graphene and transition metal dichalcogenides have attracted much attention due to their unique electrical properties resulting from their unique structures. For example, graphene and its laminated films are expected to be used not only as materials for forming transparent conductive films and wiring, but also as key materials for electronic devices such as high-frequency devices, sensors, and transistors (see Patent Documents 1 and 2). In addition, transition metal dichalcogenides function as semiconductors capable of emitting light due to their relatively large band gaps, and are therefore expected to be applied not only to transistors but also to light-emitting devices. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Application Publication No. 2014 / 0158988 [Patent Document 2] US Patent Application Publication No. 2021 / 0234015 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of one embodiment of the present invention is to provide a transistor having a novel structure including a two-dimensional material and a manufacturing method thereof. Alternatively, an object of one embodiment of the present invention is to provide a highly reliable transistor including a two-dimensional material in an active layer and a manufacturing method thereof. Alternatively, an object of one embodiment of the present invention is to provide a method for controlling the conductivity type of a thin film including a two-dimensional material and the conductivity type of a transistor including a two-dimensional material in an active layer. [Means for solving the problem]

[0005] One embodiment of the present invention is a transistor. The transistor includes a gate electrode, a first conductivity type control layer overlapping the gate electrode, a gate insulating layer sandwiched between the gate electrode and the first conductivity type control layer and in contact with the gate electrode and the first conductivity type control layer, an active layer in contact with the first conductivity type control layer and including graphene or a transition metal dichalcogenide, and a pair of terminals in direct contact with the active layer. The gate insulating layer and the first conductivity type control layer are sandwiched between the gate electrode and the active layer. The first conductivity type control layer includes a two-dimensional layered nanosheet of a metal oxide.

[0006] One embodiment of the present invention is a method for manufacturing a transistor. The method includes forming a gate electrode on a substrate, forming a gate insulating layer on the substrate, forming a first conductivity type control layer on the gate insulating layer, forming an active layer on the first conductivity type control layer, the active layer including graphene or a transition metal dichalcogenide and in contact with the first conductivity type control layer, and forming a pair of terminals in direct contact with the active layer. The first conductivity type control layer includes a two-dimensional layered nanosheet of a metal oxide.

[0007] One embodiment of the present invention is a method for manufacturing a transistor. The method includes forming an active layer including graphene or a transition metal dichalcogenide on a substrate, forming a first conductivity type control layer on the active layer in contact with the active layer, forming a gate insulating layer on the active layer, forming a gate electrode on the gate insulating layer, and forming a pair of terminals in direct contact with the active layer. The first conductivity type control layer includes a two-dimensional layered nanosheet of a metal oxide. [Brief description of the drawings]

[0008] [Figure 1A] FIG. 1 is a schematic end view of a transistor according to an embodiment of the present invention. [Figure 1B] FIG. 1 is a schematic end view of a transistor according to an embodiment of the present invention. [Figure 1C] FIG. 1 is a schematic end view of a transistor according to an embodiment of the present invention. [Figure 2A] FIG. 1 is a schematic end view of a transistor according to an embodiment of the present invention. [Figure 2B] FIG. 1 is a schematic end view of a transistor according to an embodiment of the present invention. [Figure 3A] FIG. 1 is a schematic end view of a transistor according to an embodiment of the present invention. [Figure 3B] FIG. 1 is a schematic end view of a transistor according to an embodiment of the present invention. [Figure 3C] FIG. 1 is a schematic end view of a transistor according to an embodiment of the present invention. [Figure 4A] 1A to 1C are schematic end views illustrating a method for manufacturing a transistor according to an embodiment of the present invention. [Figure 4B] 1A to 1C are schematic end views illustrating a method for manufacturing a transistor according to an embodiment of the present invention. [Figure 5A] 1A to 1C are schematic end views illustrating a method for manufacturing a transistor according to an embodiment of the present invention. [Figure 5B] 1A to 1C are schematic end views illustrating a method for manufacturing a transistor according to an embodiment of the present invention. [Figure 5C] 1A to 1C are schematic end views illustrating a method for manufacturing a transistor according to an embodiment of the present invention. [Figure 6] 1A to 1C are schematic end views illustrating a method for manufacturing a transistor according to an embodiment of the present invention. [Figure 7A] 4 shows Raman spectra of the laminates of Example 1 and Comparative Example 1. [Figure 7B] 1 shows X-ray photoelectron spectroscopy (XPS) spectra of the laminates of Example 1 and Comparative Example 1. [Figure 8A] 5A to 5C are schematic end views illustrating a method for manufacturing a transistor according to Example 2. [Figure 8B] 5A to 5C are schematic end views illustrating a method for manufacturing a transistor according to Example 2. [Figure 8C] FIG. 4 is a schematic end view of a transistor according to Comparative Example 2. [Figure 9A] 13 is a Vgs-sheet resistance plot for the transistor of Example 2. [Figure 9B] 13 is a Vgs-sheet resistance plot for the transistor of Comparative Example 2. [Figure 10] 4 shows Raman spectra of the laminates of Example 3 and Comparative Example 3. [Figure 11A] FIG. 2 is a schematic top view of a sample used in measuring a surface potential in Example 1. [Figure 11B] FIG. 2 is a schematic end view of a sample used for measuring a surface potential in Example 1. [Figure 12A] 1 is an atomic force microscope (AFM) image of a sample used in measuring the surface potential in Example 1. [Figure 12B] 4 is a surface profile obtained by AFM measurement of the sample used in the surface potential measurement in Example 1. [Figure 12C] 4 is a measurement result of the surface potential in Example 1. [Figure 13] 13 is a plot of Vgs-sheet resistance of the transistors of Example 4 and Comparative Example 4. [Figure 14A] 4 shows Raman spectra of samples of Example 5 and Comparative Example 5. [Figure 14B] 13 is a graph showing the change in carrier density of the laminate of Example 5, estimated from the Raman shift. [Figure 15A] FIG. 13 is a schematic end view of a transistor according to a sixth embodiment. [Figure 15B] FIG. 13 is a schematic end view of a transistor according to Comparative Example 6. [Figure 16] 13 is a Vgs-Ids plot of the transistors of Example 6 and Comparative Example 6. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, the embodiments of the invention disclosed in this application will be described. The present invention can be implemented in various forms without departing from the gist of the invention, and should not be construed as being limited to the description of the embodiments exemplified below. Even if the effects and advantages brought about by the following embodiments are different from those brought about by the following embodiments, those that are clear from the description in this specification or that can be easily predicted by a person skilled in the art are naturally understood to be brought about by the present invention.

[0010] In order to clarify the description, the drawings may show the width, thickness, shape, etc. of each part in a schematic manner compared to the actual embodiment, but these are merely examples and do not limit the interpretation of the present invention. In this specification and each drawing, elements having the same functions as those described in the previous drawings may be given the same reference numerals, and duplicated descriptions may be omitted.

[0011] In this specification and the claims, when describing an aspect in which a structure is placed on top of another structure, the term "on top" is used, unless otherwise specified, to include both a case in which another structure is placed directly on top of a structure so as to be in contact with the structure, and a case in which another structure is placed above a structure via yet another structure.

[0012] 1. Structure of transistor FIG. 1A shows a schematic end view of a transistor 100 including a two-dimensional material in an active layer according to one embodiment of the present invention. As shown in FIG. 1A, the transistor 100 is provided directly on a substrate 102 or via an undercoat (not shown), and includes a gate electrode 104, a gate insulating layer 106, a conductivity type control layer 108, an active layer 110, and a pair of terminals 112 and 114. The gate insulating layer 106 and the conductivity type control layer 108 are sandwiched between the gate electrode 104 and the active layer 110. There are no restrictions on the material included in the substrate 102, and the substrate 102 may be appropriately made of, for example, glass, quartz, single crystal silicon, single crystal germanium, sapphire, or the like. Although not shown, an insulating film or the like for protecting the transistor 100 may be provided on the transistor 100.

[0013] (1) Gate electrode The gate electrode 104 is an electrode that controls the density of electrons or holes in the active layer 110 via the gate insulating layer 106, and includes, for example, a metal such as molybdenum, tantalum, tungsten, titanium, copper, nickel, chromium, or gold, or an alloy containing a metal selected from these metals. Alternatively, the gate electrode 104 may include silicon. In this case, low-resistance silicon doped with a dopant such as boron or aluminum at a relatively high concentration can be used as the gate electrode 104. There is no restriction on the thickness of the gate electrode 104, and it may be appropriately selected from the range of 5 nm to 1000 nm. The gate electrode 104 may be formed by applying, for example, a sputtering method, a chemical vapor deposition (CVD) method including a metal-organic chemical vapor deposition (MOCVD) method, a deposition method (vacuum deposition method, electron beam deposition method), or the like.

[0014] (2) Gate insulation layer The gate insulating layer 106 is provided on the gate electrode 104 so as to be in contact with the gate electrode 104. The gate insulating layer 106 is provided so as to cover the gate electrode 104. The gate insulating layer 106 can be composed of one or more layers containing a silicon-containing inorganic compound such as silicon oxide or silicon nitride. The gate insulating layer 106 may be made of a silicon-containing inorganic compound and may not contain a metal oxide. Alternatively, the gate insulating layer 106 may be formed using a so-called high dielectric constant material such as hafnium silicate, zirconium silicate, hafnium oxide, or zirconium oxide. The gate insulating layer 106 may be formed to a thickness of, for example, 5 nm to 30 nm by using a sputtering method or a CVD method.

[0015] (3) Conductivity control layer The conductivity type control layer 108 is provided on the gate insulating layer 106 so as to overlap the gate electrode 104 and be in contact with the gate insulating layer 106. The conductivity type control layer 108 controls the conductivity type (n-type or p-type) of the active layer 110 including a two-dimensional material provided thereon. Specifically, by appropriately selecting the material contained in the conductivity type control layer 108, charge transfer occurs between the conductivity type control layer 108 and the active layer 110, and as a result, the active layer 110 is given a conductivity type of p-type or n-type. As shown in the examples, for example, titanium oxide or niobium oxide (Nb 3 O 8 ), titanium niobium oxide (TiNbO 5 ), the active layer 110 can be doped with electrons, thereby imparting n-type conductivity to the two-dimensional material or increasing the n-type conductivity. In the following description, the composition of the inorganic compound does not necessarily have to match the stoichiometry calculated by treating the valence of the metal as an integer. In other words, the composition ratio of the elements in the inorganic compound does not necessarily have to match the integers in the chemical formula. Thus, for example, in the case of titanium oxide, TiO 2 Even when written as TiO, the atomic ratio of Ti and O does not have to be strictly 1:2. Titanium oxide with a composition that deviates from 1:2 is also called TiO 2 This falls within the category of compounds described as follows:

[0016] The conductivity type control layer 108 includes a two-dimensional layered nanosheet of metal oxide. Metals contained in the metal oxide include titanium, ruthenium, molybdenum, cobalt, tantalum, manganese, niobium, bismuth, lanthanum, calcium, and strontium. Specific metal oxides include titanium oxide, ruthenium oxide, molybdenum oxide, cobalt oxide, niobium oxide, and tantalum oxide. Alternatively, a metal oxide containing multiple metals may be used. For example, TiNbO 5 Metal oxides containing titanium and niobium such as titanium and bismuth, metal oxides containing lanthanum and niobium, metal oxides containing calcium and niobium, metal oxides containing strontium and tantalum, and metal oxides containing bismuth, strontium, and tantalum may also be used.

[0017] A two-dimensional layered nanosheet of a metal oxide is the smallest basic unit constituting a layered compound, that is, a single layer of a metal oxide. Although the thickness is extremely small, about 1 nm, it is a highly anisotropic two-dimensional single crystal having a lateral dimension of several hundreds of nm to several tens of μm. For this reason, it exhibits properties that are significantly different from those of metal oxides having an amorphous structure. The conductive control layer 108 is composed of a single or multiple layers of a two-dimensional layered nanosheet of a metal oxide. There is no restriction on the thickness of the conductive control layer 108, and it is appropriately selected, for example, from the range of 1 nm to 100 nm. The conductive control layer 108 can be formed, for example, by using a spin coating method or a Langmuir-Blodgett method (LB method). Specifically, first, a layered compound (precursor) containing a metal oxide is treated with an acid such as hydrochloric acid or nitric acid to replace metal ions (for example, alkali metal ions such as sodium, cesium, and potassium, or alkaline earth ions such as calcium) contained between the layers of the precursor with protons. Then, the protons are exchanged with organic ions to obtain a solution or dispersion in which the two-dimensional layered nanosheets of the metal oxide are dispersed in a colloidal state. Then, the two-dimensional layered nanosheets of the metal oxide formed at the gas-liquid interface can be formed into one or more layers on the gate insulating layer 106 by the LB method.

[0018] (4)Active layer The active layer 110 includes a two-dimensional material and is disposed on the conductivity type control layer 108 such that the active layer 110 is in contact with the conductivity type control layer 108. The channel of the transistor 100 is formed in the region where the active layer 110 overlaps the gate electrode 104. As will be described below, the active layer 110 is formed on the conductivity type control layer 108 using a transfer method.

[0019] Two-dimensional materials include graphene and transition metal dichalcogenides. Graphene is a material that has a structure similar to that of sp 2It refers to a sheet-like material in which carbon atoms are arranged in a two-dimensional honeycomb lattice and have a thickness of one atomic layer (about 0.3 nm). Graphene is one of the layers that make up the layered structure of graphite, and is also called single-layer graphene. A transition metal dichalcogenide is a single-layer material or a laminate thereof having a structure in which a single transition metal layer is sandwiched between atomic layers of sulfur, selenium, or tellurium, which are chalcogen atoms, and the thickness is about 0.6 nm to 3 nm. In particular, transition metal dichalcogenides having a single-layer structure are preferable. The transition metal can be selected from molybdenum, tungsten, niobium, tantalum, zirconium, platinum, and hafnium, and a representative transition metal dichalcogenide is molybdenum disulfide (MoS 2 ) and tungsten disulfide (WS 2 ), molybdenum diselenide (MoSe 2 ), tungsten diselenide (WSe 2 ) etc.

[0020] (5) Terminal The pair of terminals 112, 114 are both provided to contact the active layer 110 and to be directly and electrically connected to the active layer 110. One of the pair of terminals 112, 114 functions as a source electrode, and the other functions as a drain electrode. The pair of terminals 112, 114 may contain a metal or alloy that can be used in a gate electrode, and may be formed by appropriately using a sputtering method, a CVD method, a deposition method, or the like. The pair of terminals 112, 114 may be provided in contact with the conductive type control layer 108 exposed from the active layer 110, as shown in FIG. 1A. Alternatively, although not shown, the active layer 110 may be provided in an area overlapping the pair of terminals 112, 114, and the transistor 100 may be configured so that the pair of terminals 112, 114 are not in contact with the conductive type control layer 108.

[0021] 2. Variations The configuration of the transistor 100 is not limited to the above-mentioned configuration. For example, as shown in FIG. 1B, when the conductive control layer 108 has sufficient insulating properties, the gate insulating layer 106 is not provided, and the conductive control layer 108 may function alone as a gate insulating layer. In this case, the conductive control layer 108 contacts the gate electrode 104 and the active layer 110. In this configuration, the gate insulating layer 106 containing a silicon-containing inorganic compound or the like is not required, so that the transistor 100 can be manufactured at a lower cost. Note that FIG. 1B illustrates a configuration in which the conductive control layer 108 and the active layer 110 are partially etched, but the conductive control layer 108 and / or the active layer 110 may not be etched and may cover the whole or part of the substrate 102. In this case, as shown in FIG. 1C, the conductive control layer 108 and / or the active layer 110 are exposed from the terminals 112 and 114.

[0022] The transistor 100 shown in FIGS. 1A to 1C is a so-called bottom gate transistor, but the structure of the transistor 100 is not limited thereto, and the transistor 100 may be a so-called top gate transistor. Specifically, as shown in FIG. 2A, an active layer 110, a conductivity type control layer 108 on the active layer 110, a gate insulating layer 106 on the conductivity type control layer 108, and a gate electrode 104 on the gate insulating layer 106 may be provided from the substrate 102 side. When the transistor 100 has a top gate structure, it is preferable to provide an undercoat 116 for preventing the intrusion of impurities from the substrate 102. In addition, an interlayer insulating film 118 covering the gate electrode 104 and the gate insulating layer 106 is provided on the gate electrode 104, and the pair of terminals 112 and 114 are electrically connected to the active layer 110 through openings provided in the interlayer insulating film 118, the gate insulating layer 106, and the conductivity type control layer 108. The undercoat 116 and the interlayer insulating film 118 may be formed of one or more layers containing a silicon-containing inorganic compound. The undercoat 116 and the interlayer insulating film 118 may also be formed by appropriately applying a sputtering method or a CVD method. Although not shown, a second gate electrode may be further provided on the interlayer insulating film 118. In this case, the second gate electrode may be electrically connected to the gate electrode 104.

[0023] Even when the transistor 100 is a top-gate transistor, the conductivity type control layer 108 may function solely as a gate insulating layer. In this case, the conductivity type control layer 108 contacts the gate electrode 104 and the active layer 110, as shown in FIG. 2B.

[0024] Furthermore, the transistor 100 may have a plurality of conductivity type control layers 108 sandwiching the active layer 110. Specifically, as shown in FIG. 3A, the transistor 100 may have a first conductivity type control layer 108-1 and a second conductivity type control layer 108-2 in contact with the active layer 110 and sandwiching the active layer 110. In this case, an opening exposing the active layer 110 is provided in the conductivity type control layer (here, the second conductivity type control layer 108-2) provided on the active layer 110, and a pair of terminals 112, 114 are electrically connected to the active layer 110 through the opening. As shown in FIG. 3B, even when the transistor 100 has a plurality of conductivity type control layers 108, a gate insulating layer 106 in contact with one of the conductivity type control layers (here, the first conductivity type control layer 108-1) may be provided between the gate electrode 104 and the first conductivity type control layer 108-1.

[0025] This laminated structure of the multiple conductivity type control layers 108 and the active layer 110 can also be used in the top-gate transistor 100. For example, as shown in FIG. 3C, the first conductivity type control layer 108-1 / active layer 110 / second conductivity type control layer 108-2 may be provided directly on the substrate 102 or via an undercoat 116, and the terminals 112, 114 may be electrically connected to the active layer 110 via an opening provided in the second conductivity type control layer 108-2 on the active layer 110. Although not shown, even in this case, the gate insulating layer 106 may not be provided, and the second conductivity type control layer 108-2 may function alone as a gate insulating layer.

[0026] 3. Transistor manufacturing method A method for manufacturing the bottom-gate transistor 100 shown in FIG. 1A will now be described.

[0027] First, a gate electrode 104 and a gate insulating layer 106 are formed on a substrate 102 (FIG. 4A). The steps up to this point are widely known, so we will not go into detail here.

[0028] Then, the conductive control layer 108 is formed on the gate insulating layer 106 (FIG. 4B). Specifically, first, a precursor of a two-dimensional layered nanosheet of oxide is prepared. In the case of titanium oxide, for example, a mixture of cesium carbonate and titanium (IV) oxide is baked at a high temperature of about 800° C. to obtain Cs x Ti y O 4 A precursor having the composition of can be obtained. Although it depends on the mixture ratio of cesium carbonate and titanium oxide (IV) and the baking conditions, x is usually 0.6 to 0.7, and y is 1.80 to 1.85. In this precursor, a single layer of titanium oxide and a layer of cesium ions are alternately laminated. Then, the precursor is treated with hydrochloric acid, nitric acid, or the like to replace the cesium ions with protons. Furthermore, it is treated with a solution containing a water-soluble organic cation such as tetrabutylammonium hydroxide. The organic cation is preferably a large cation such as a quaternary ammonium cation. The treatment with the organic cation increases the interlayer distance of the titanium oxide. In this state, by applying a mechanical stimulus such as shaking or ultrasonic irradiation, the single layer of titanium oxide is peeled off, and a solution or dispersion in which the single layer of titanium oxide is dispersed in a colloidal state can be obtained. By using a spin coating method using this solution or dispersion, a two-dimensional layered nanosheet of titanium oxide can be laminated on the substrate 102 on which the gate electrode 104 and the gate insulating layer 106 are formed. There is no restriction on the number of layers, and it may be appropriately selected from the range of, for example, 1 to 100 or 10 to 50. When the oxide is titanium oxide, the composition Ti of the conductivity type control layer 108 is z O 2 z in ranges from 0.87 to 0.91.

[0029] The method for producing the conductivity-type control layer 108 is not limited to spin coating, and various wet film formation methods such as the LB method, dip coating, electrophoresis, layer-by-layer (LBL) method, and alternate adsorption / deposition may be used. The thickness of the conductivity-type control layer 108 can be controlled by appropriately adjusting various parameters such as the concentration of the solution or dispersion in which the two-dimensional layered nanosheets of metal oxide are dispersed, the drop amount and rotation speed in the spin coating method, the pull-up speed in the dip coating method, and the applied voltage and migration time in the electrophoresis.

[0030] Subsequently, the active layer 110 is formed on the conductivity type control layer 108. However, as an optional configuration, the conductivity type control layer 108 may be irradiated with ultraviolet light before the formation of the active layer 110. The wavelength of the ultraviolet light may be selected, for example, from the range of 280 nm to 400 nm. The ultraviolet light irradiation can improve the hydrophilicity of the surface of the conductivity type control layer 108, thereby increasing the bonding strength with the active layer 110.

[0031] In forming the active layer 110 including the two-dimensional material, a transfer method of the two-dimensional material synthesized on a synthetic substrate can be used. When the two-dimensional material is graphene, a synthetic substrate 120 such as copper is placed in a chamber, and the active layer 110 is formed by growing graphene on the synthetic substrate 120 by applying a thermal CVD method (FIG. 5A). As reactant gases in the thermal CVD method, raw material gases such as methane, ethane, acetylene, ethanol, and benzene, and reducing gases such as hydrogen are used. The temperature at which graphene is grown is, for example, 600° C. or higher and 1200° C. or lower, and under these conditions, an active layer 110 having a single atomic layer of graphene is obtained.

[0032] The synthetic substrate 120 has at least a metal having catalytic activity for growing graphene on the surface. Therefore, the synthetic substrate 120 may be a metal plate or metal foil containing a metal having catalytic activity, such as gold, silver, copper, nickel, molybdenum, chromium, iridium, or platinum, or an alloy such as stainless steel or nickel-chromium. Alternatively, the synthetic substrate 120 may be an insulating substrate or a semiconductor substrate on which a metal layer containing the above-mentioned metal or alloy is formed. Examples of the insulating substrate include a glass substrate, a quartz substrate, and a sapphire substrate, and examples of the semiconductor substrate include a single crystal silicon substrate. Typically, a glass substrate, a quartz substrate, a sapphire substrate, or a silicon substrate, and a copper thin film, a copper foil, or a copper plate provided thereon are provided as the synthetic substrate 120.

[0033] The transfer method can also be used when transition metal dichalcogenides are used as two-dimensional materials. For example, molybdenum disulfide (MoS 2 When using MoS, first, a thermal CVD method is used to deposit MoS on a synthetic substrate 120. 2 The active layer 110 is formed by growing the above-mentioned. Specifically, a synthetic substrate 120 is placed in a chamber. Examples of the synthetic substrate 120 include a mica substrate, a silicon substrate, a germanium substrate, a gallium arsenide substrate, a gallium nitride substrate, a sapphire substrate, a quartz substrate, a graphite substrate, a hexagonal boron nitride substrate, a glass substrate, a gold substrate, and a strontium titanate (SrTiO 3 ) single crystal substrates are used. The mica substrate may be a natural mica substrate or an artificial mica substrate such as a fluorine-containing mica substrate. When a substrate containing a semiconductor such as silicon, germanium, or a compound semiconductor is used, an oxide may be formed on the surface.

[0034] After that, the raw materials, carrier gas, and, if necessary, a growth promoter are introduced into the chamber in which the synthetic substrate 120 is placed, and the raw materials are reacted by heating, and MoS is formed on the synthetic substrate 120. 2 The raw material is molybdenum oxide (MoO 2 Or MoO 3) and solid sulfur (S). The carrier gas may be a rare gas such as argon or helium, or nitrogen. Hydrogen may also be added to the carrier gas. The growth promoter may be an alkali metal salt. The alkali metal may be selected from lithium, potassium, sodium, and cesium. There is no restriction on the anion constituting the salt. For example, the salt may be selected from halides, oxides, hydroxides, sulfides, carbonates, hydrogen carbonates, nitrates, sulfates, phosphates, carboxylates such as citric acid, acetic acid, and ethylenediaminetetraacetic acid. Preferably, the salt has a melting point higher than the heating temperature in thermal CVD, and typically sodium chloride or potassium chloride can be used. The alkali metal salt may be filled in the form of powder into a container such as quartz and placed in the chamber. MoS 2 The temperature at which the MoS layer is grown is, for example, 500°C to 1100°C. 2 An active layer 110 having the following structure is obtained.

[0035] Subsequently, a resin layer 122 is formed on the active layer 110 (FIG. 5A). Examples of the resin layer 122 include, but are not limited to, acrylic resins such as polymethyl methacrylate, aliphatic polyimides such as poly(methyl glutarimide), epoxy resins, and water-soluble polymers such as polyvinyl alcohol. Materials that are soluble in organic solvents or water, which will be described later, can be used as the resin layer 122. Examples of methods for forming the resin layer 122 include spin coating, inkjet, dip coating, and printing. Instead of the resin layer, a heat-release tape or an ultraviolet-release tape can also be used.

[0036] Next, the synthetic substrate 120 is removed. For example, the synthetic substrate 120 is removed by using an etchant that dissolves a metal that functions as a catalyst for growing graphene. For example, when copper is used as the synthetic substrate, an etchant such as an aqueous solution of ferric chloride, an aqueous solution of ammonium persulfate, or an aqueous solution of an inorganic acid such as nitric acid is used. Alternatively, an etchant that dissolves the surface of the synthetic substrate 120 may be used. Also, the active layer 110 may be mechanically peeled off from the synthetic substrate 120 without using an etchant.

[0037] In addition, for example, a single crystal silicon substrate with silicon oxide was used as a synthesis substrate to produce MoS 2 In the case where the active layer 110 is synthesized, an inorganic alkaline aqueous solution such as potassium hydroxide is used. In addition, pure water may be used. Also, the active layer 110 may be mechanically peeled off from the synthesis substrate 120 without using an etchant.

[0038] After that, the resin layer 122 and the substrate 102 are bonded (FIGS. 5B and 5C). The bonding is performed so that the active layer 110 and the conductive control layer 108 are sandwiched between the resin layer 122 and the substrate 102. At this time, unevenness may be present on the upper surface of the conductive control layer 108 due to the gate electrode 104, etc., but by using the flexible resin layer 122, the active layer 110 can be arranged so as to fit the shape of the upper surface of the conductive control layer 108. After that, the active layer 110 can be laminated on the conductive control layer 108 by removing the resin layer 122. The resin layer 122 can be removed by immersing the substrate 102 on which the resin layer 122 is formed in a solvent that dissolves the resin layer 122. The solvent may be water, ketones such as acetone and methyl ethyl ketone, aromatic solvents such as toluene, xylene, and anisole, halogen-based solvents such as methylene chloride and chloroform, and ether-based solvents such as tetrahydrofuran and dioxane. Alternatively, the resin layer 122 may be mechanically peeled off without using a solvent. As an optional step, after removing the resin layer 122, a small amount of the remaining resin layer 122 may be removed by heat treatment. For example, the remaining resin layer 122 may be removed by heat treatment at a temperature of 300° C. or more and 500° C. or less in a mixed gas of an inert gas such as argon or nitrogen and hydrogen gas, or in a vacuum atmosphere. When a thermal release sheet or an ultraviolet release sheet is used instead of the resin layer 122, the thermal release sheet or the ultraviolet release sheet can be removed by heating or ultraviolet irradiation.

[0039] Although not shown, a further conductivity type control layer 108 may be provided on the active layer 110 using a method similar to the method for forming the conductivity type control layer 108 provided below the active layer 110. In this case, the conductivity type control layer 108 on the active layer 110 may be further etched to form openings for connecting the terminals 112 and 114.

[0040] The active layer 110 may be appropriately etched to expose a part of the conductivity type control layer 108 from the active layer 110 (FIG. 6). Etching may be performed by, for example, electron beam irradiation, water molecule cluster ion beam irradiation, oxygen plasma irradiation, hydrogen plasma irradiation, halogen compound plasma irradiation, helium ion irradiation, or the like. Alternatively, etching may be performed using an etchant such as a chlorine-based oxoacid or its salt, such as hypochlorous acid, chlorous acid, or chloric acid, a metal permanganate such as potassium permanganate, a metal chromate such as potassium chromate or potassium dichromate, ozone, hydrogen peroxide, or a halogen, such as chlorine, iodine, or bromine.

[0041] Thereafter, a pair of terminals 112, 114 are formed. The pair of terminals 112, 114 can be formed by forming a film containing the above-mentioned metal or alloy over almost the entire surface of the substrate 102 using a sputtering method, a vacuum deposition method, an electron beam deposition method, or the like, and then patterning the film by lithography. In this manner, the transistor 100 can be manufactured.

[0042] In a transistor 100 according to one embodiment of the present invention, a conductivity type control layer 108 including a two-dimensional layered nanosheet of metal oxide is provided in contact with an active layer 110 including a two-dimensional material such as graphene or transition metal dichalcogenide. Therefore, charge is transferred between the active layer 110 and the conductivity type control layer 108, and by appropriately selecting the type of metal oxide included in the conductivity type control layer 108, the conductivity type of the active layer 110 can be arbitrarily controlled to n-type or p-type. For example, titanium oxide, niobium oxide, TiNbO 5 By using such a two-dimensional layered nanosheet in the conductivity type control layer 108, an n-type active layer 110 can be formed, and as a result, an n-type transistor can be provided.

[0043] In addition, in the transistor 100, the two-dimensional layered nanosheet of metal oxide contained in the conductivity type control layer 108 is a highly anisotropic two-dimensional single crystal. Therefore, unlike metal oxides with an amorphous structure, it has high thermal stability. Therefore, even under the conditions of a semiconductor process that requires a relatively high temperature, no structural change occurs, and deterioration and characteristic changes of the transistor 100 caused by structural change can be prevented. This means that providing the active layer 110 containing the two-dimensional material in contact with the conductivity type control layer 108 contributes to the provision of highly reliable transistors and various electronic devices including the same. EXAMPLES

[0044] 1. Example 1: Characteristics of graphene layers on two-dimensional layered nanosheets of titanium oxide In the transistor 100, an active layer 110 including a two-dimensional material is formed on a conductivity type control layer 108 including a two-dimensional layered nanosheet of a metal oxide. In this example, titanium oxide and graphene are used as the metal oxide and the two-dimensional material, respectively, and the results of evaluating the properties of the graphene layer on the two-dimensional layered nanosheet are described.

[0045] (1) Sample preparation First, cesium carbonate and titanium (IV) oxide were mixed so that the molar ratio of cesium to titanium (Cs / Ti) was 0.8 / 1.8, and the mixture was ground in a mortar. The resulting powder was placed in an alumina crucible and heated at 800°C in air for 20 hours to produce the precursor Cs 0.6 Ti 1.8 O 4 This precursor was treated with 1M hydrochloric acid at room temperature for three days. Specifically, the mixture of precursor and hydrochloric acid was shaken and centrifuged (4000 rpm, 10 min) to remove the supernatant every 24 hours. Water was then added to disperse the mixture in water, and a washing procedure was carried out six times, including the removal of the supernatant by centrifugation (4000 rpm, 10 min). This resulted in the formation of H, in which cesium had been replaced by protons. + Layered titanium dioxide H 0.6 Ti 1.8 O 4 nH 2I got an O.

[0046] After that, H + A 0.025 M aqueous solution of tetrabutylammonium hydroxide (TBAOH) was added to the layered titanium oxide so that the molar ratio of protons / TBAOH was 1:8, and ultrasonic irradiation (240 W) was performed for 9 hours to obtain an aqueous solution of two-dimensional layered titanium oxide nanosheets.

[0047] Using the spin coating method, the two-dimensional layered nanosheet of titanium oxide in the above aqueous solution was laminated on a single crystal silicon substrate (1.6 cm × 1.6 cm, 0.5 mm thick) on whose surface a thermally oxidized film of silicon oxide had been formed. After each lamination, the single crystal silicon substrate was dried on a hot plate set at 80°C. The lamination process was carried out 20 times, after which the single crystal silicon substrate was treated in an oven at 200°C for 1 hour. Through the above operations, a Si / SiO 2 / TiO 2 A laminate of TiO 2 The thickness was about 20 nm.

[0048] Subsequently, a graphene layer was formed on the laminate. Specifically, a single-layer graphene film (manufactured by Graphenea) formed on a copper foil by thermal CVD was used, and a resin layer was formed by applying a 2 wt% anisole solution of polymethyl methacrylate (PMMA) on the single-layer graphene film. The obtained copper foil / graphene layer / PMMA laminate was treated with an aqueous ferric chloride solution (20%) for 30 minutes to dissolve the copper foil, thereby obtaining a graphene layer / PMMA laminate. Thereafter, the graphene layer / PMMA laminate and Si / SiO 2 / TiO 2 The laminate was bonded, and the PMMA-containing resin layer was then removed using toluene and acetone to transfer the graphene layer. 2 / TiO 2 A stack of graphene layers was obtained.

[0049] As Comparative Example 1, a single crystal silicon substrate with silicon oxide (Si / SiO 2) and the graphene layer / PMMA laminate, followed by removal of the PMMA, were used to prepare a Si / SiO 2 A stack of graphene layers was obtained.

[0050] (2) Characterization Using a Renishaw Raman spectrometer (model number in Via, the same applies below), the Raman spectra (excitation wavelength 488 nm, spot diameter 1 μm) of the obtained samples of Example 1 and Comparative Example 1 were measured. 2 / TiO 2 The G-band peak of the laminate of the graphene layer is the Si / SiO 2 This suggests that the carrier density of the graphene layer in Example 1 is higher than that of the graphene layer in Comparative Example 1.

[0051] XPS spectra of the samples of Example 1 and Comparative Example 1 were obtained using an X-ray photoelectron spectrometer manufactured by PHI and a light source of AlKα radiation. The measurement range was 400 μm. The results are shown in FIG. 7B. The C1s binding energies of the graphene layers in the samples of Example 1 and Comparative Example 1 were 284.55 eV and 284.40 eV, respectively, and it can be seen that the former is shifted to the higher energy side by 0.15 eV compared to the latter. From this, it can be said that the work function of the graphene layer in the sample of Example 1 is smaller than that of Comparative Example 1. This result shows that the electron density of the graphene layer in the sample of Example 1 is higher than that of Comparative Example 1, suggesting that the graphene layer takes on an n-type conductivity type due to the occurrence of electron transfer from the two-dimensional layered nanosheet of titanium oxide to the graphene layer.

[0052] In addition, the surface potential of the graphene layer was measured using KFM. 2 TiO on the substrate 2 After deposition, the mask is removed to leave TiO on part of the substrate surface. 2 No SiO 2 An exposed portion was formed. Furthermore, TiO2 A graphene layer was formed on the entire surface including the area where no graphene was deposited, by using the above-mentioned transfer method. As a result, as shown in Figs. 11A and 11B, a graphene layer was formed on the entire surface including the area where no graphene was deposited, and the graphene layer was formed on the entire surface including the area where no graphene was deposited. As a result, as shown in Figs. 2 and the other part constitutes the conductive control layer 108. i O 2 An active layer 110 (i.e., a graphene layer) was formed in contact with TiO 2 FIG. 12A shows an AFM image of an observation region centered on end 108a of the substrate, and FIG. 12B shows a surface profile obtained using an AFM on the dotted line shown in FIG. 12A. As shown in FIG. 12A, two regions with different shading are observed in this observation region. The surface height was measured using an AFM on the dotted line that intersects with the boundary between these two regions. As a result, as shown in FIG. 12B, it was found that the height is almost constant up to a distance of about 45,000 nm from the left end of the observation region, but that the height gradually increases when the distance exceeds 45,000 nm. This suggests that TiO 2 The graphene layer is SiO 2 In the right area, TiO 2 It can be seen that a graphene layer is present on top.

[0053] The results of surface potential measurement in the same observation area are shown in FIG. 12C. From the results in FIG. 12C, it is clear that the surface potential of the TiO 2 It can be seen that the surface potential increases from the vicinity of the end 108a of the TiO 2 The average surface potentials in the left and right regions from the end 108a of the TiO 2 The work function of the top graphene layer is SiO 2 These results also suggest that the work function of the TiO 2 This shows that the graphene layer is doped with electrons and becomes n-type.

[0054] 2. Example 2: Transistor Including a Stack of a Titanium Oxide Conductivity Control Layer and a Graphene Layer In this example, a transistor was fabricated including a conductive control layer including a two-dimensional layered nanosheet of titanium oxide and a stack of a graphene layer, which is a layer of a two-dimensional material, and the characteristics of the transistor were evaluated. The results are described below.

[0055] 8A and 8B are schematic end views showing a method for producing a transistor according to the present embodiment 2. First, a two-dimensional layered nanosheet of titanium oxide was formed as a conductive type control layer 108 on a p-type silicon substrate (1.6 cm×1.6 cm, 0.5 mm thick) 130 on which a thermally oxidized film 132 of silicon oxide was formed by spin coating, as in the case of the embodiment 1. Here, the p-type silicon substrate 130 and the thermally oxidized film 132 function as a gate electrode and a gate insulating layer of the transistor, respectively. Then, as in the case of the embodiment 1, an active layer 110 containing graphene was formed on the conductive type control layer 108 by a transfer method (FIG. 8A). After that, four samples (element 1 to element 4) of bottom gate type transistors having four terminals according to the embodiment 2 were produced by forming terminals 112, 113, 114, and 115 as a laminate of titanium (10 nm) and gold (90 nm) by electron beam deposition (FIG. 8B). The channel length of the fabricated transistor was 50 μm, and the channel width was 10 μm or 40 μm. For comparison, a transistor not having the conductivity type control layer 108 was fabricated as Comparative Example 2 (FIG. 8C).

[0056] For the transistors of Example 2 and Comparative Example 2, a source-drain voltage (V gs ) was applied, and the sheet resistance of the active layer 110 was measured using the potential difference generated between the two terminals 113 and 115. gs The dependence of the V is shown in Figures 9A and 9B, respectively. As shown in Figure 9A, although there is variation between the samples, all four samples in Example 2 have a V gs It was confirmed that the sheet resistance is maximum when V is negative. That is, the Dirac point is negative V gsThis shows that the active layer 110 has n-type conductivity, and all the transistors of Example 2 are n-type transistors. On the other hand, in the transistor of Comparative Example 2 that does not have the conductivity type control layer 108, the Dirac point is V gs was positive (FIG. 9B). This confirmed that the active layer 110 provided in contact with silicon oxide had p-type conductivity, and the transistor of Comparative Example 2 was a p-type transistor.

[0057] The above results indicate that the conductivity type of the active layer 110 and the transistor 100 including it can be controlled by providing the conductivity type control layer 108 between the gate insulating layer 106 and the active layer 110. This suggests that the conductivity type of the active layer including graphene can be controlled by using a two-dimensional layered nanosheet including a metal oxide.

[0058] 3. Example 3: TiNbO 5 Properties of graphene layers on two-dimensional layered nanosheets of In this example, TiNbO is used as the metal oxide and the two-dimensional material. 5 and graphene, 5 We describe the characterization of the graphene layers on two-dimensional layered nanosheets of graphene.

[0059] (1) Sample preparation First, potassium carbonate, titanium (IV) oxide, and niobium (V) oxide were mixed so that the molar ratio of potassium, titanium, and niobium (K / Ti / Nb) was 1.35 / 1 / 1, and the mixture was ground in a mortar. The resulting powder was placed in a tungsten carbide crucible and heated at 1100 °C in air for 24 hours to obtain the precursor KTiNbO 5 This precursor was treated with 2M nitric acid at room temperature for 5 days. Specifically, the mixture of the precursor and nitric acid was shaken and centrifuged (4000 rpm, 10 min) to remove the supernatant every 24 hours. After that, water was added to disperse the mixture in water, and a washing procedure including removing the supernatant by centrifugation (4000 rpm, 10 min) was performed six times. This resulted in the formation of H, in which potassium was replaced by protons.+ Layered titanium niobium oxide HTiNbO 5 nH 2 I got an O.

[0060] After that, H + A 0.025 M aqueous solution of tetrabutylammonium hydroxide (TBAOH) was added to the layered titanium niobium oxide so that the molar ratio of protons / TBAOH was 1:8, and ultrasonic irradiation (240 W) was performed for 9 hours to obtain an aqueous solution of two-dimensional layered nanosheets of titanium niobium oxide.

[0061] Using the LB method, TiNbO adsorbed on the gas-liquid interface of the above aqueous solution was 5 The two-dimensional layered nanosheet of was laminated on a single crystal silicon substrate (1.6 cm × 1.6 cm, 0.5 mm thick) on which a thermally oxidized film of silicon oxide was formed on the surface. After each lamination, the single crystal silicon substrate was dried on a hot plate set at 80 °C. The lamination was performed 20 times, and then the single crystal silicon substrate was treated in an oven at 200 °C for 1 hour. Through the above operations, a Si / SiO 2 / TiNbO 5 A laminate of TiNbO 5 The thickness was about 20 nm.

[0062] Subsequently, the same method as in Example 1 was applied to Si / SiO 2 / TiNbO 5 A laminate of TiNbO / graphene layer was obtained as a sample of Example 3. 5 The two-dimensional layered nanosheets are not formed, i.e., Si / SiO 2 A laminate of the graphene layer and the graphene layer was obtained as a sample of Comparative Example 3.

[0063] (2) Characterization The Raman spectrum (excitation wavelength 488 nm, spot diameter 1 μm) was measured using a Renishaw Raman spectrometer. 2 / TiNbO 5 The G-band peak of the laminate of the graphene layer is the Si / SiO 2This suggests that the carrier density of the graphene layer in Example 3 is higher than that of the graphene layer in Comparative Example 3.

[0064] 4. Example 4: TiNbO 5 A transistor including a stack of a conductive control layer and a graphene layer. In this embodiment, TiNbO 5 A transistor was fabricated that includes a conductive control layer that includes a two-dimensional layered nanosheet of TiNbO 3 and a stack of graphene layers that are layers of two-dimensional material, and the results of evaluating the characteristics of the transistor are described below. The fabrication method of the transistor is the same as in Example 2, except that instead of the two-dimensional layered nanosheet of titanium oxide, TiNbO 3 described in Example 3 was used. 5 A transistor was produced by using the two-dimensional layered nanosheet. Two samples (Examples 4-1 and 4-2) were produced as the transistor of Example 4. For comparison, a transistor not having the conductivity type control layer 108 was produced as Comparative Example 4.

[0065] The sheet resistance of the active layer 110 of the transistors of Example 4 and Comparative Example 4 was measured in the same manner as in Example 2, and the results are shown in Fig. 13. As shown in Fig. 13, the transistor of Comparative Example 4 has a maximum sheet resistance at V gs is positive and V gs When V is close to 0V, gs As the applied V increases, the sheet resistance increases. This shows that the transistor of Comparative Example 4 is a p-type transistor. gs Although no maximum value of sheet resistance was observed in the range of V gs When V is close to 0V, gs 13, the sheet resistance decreases as the density increases. Moreover, the sheet resistance is significantly decreased compared to Comparative Example 4. From this, it can be said that the electron carrier density is significantly increased in the active layer 110 of the transistor of Example 4 compared to Comparative Example 4.

[0066] These results also confirmed that the conductivity of a two-dimensional material layer can be changed to n-type by forming a two-dimensional material layer in contact with a conductivity type control layer.

[0067] 5. Example 5: Properties of Molybdenum Sulfide Layers on Various Conductivity Type Control Layers In this embodiment, titanium oxide and TiNbO shown in Examples 1 and 3 are 5 In addition, niobium oxide (Nb 3 O 8 We report the results of evaluating the properties of transition metal dichalcogenides formed on a conductive control layer containing two-dimensional layered nanosheets of molybdenum disulfide (MoS). 2 ) was used. Titanium oxide and TiNbO 5 The method for producing the conductivity type control layer is as described in the first and third embodiments.

[0068] (1)Nb 3 O 8 Fabrication of the conductivity control layer Potassium carbonate and niobium oxide (V) were mixed so that the molar ratio of potassium to niobium (K / Nb) was 1.2 / 3, and the mixture was ground in a mortar. The resulting powder was placed in a tungsten carbide crucible and heated at 900°C for 10 hours in air to obtain KNb as a precursor. 3 O 8 This precursor was treated with 2M nitric acid at room temperature for 5 days. Specifically, the mixture of the precursor and nitric acid was shaken and centrifuged (4000 rpm, 10 min) to remove the supernatant every 24 hours. After that, water was added to disperse the mixture in water, and a washing procedure including removing the supernatant by centrifugation (4000 rpm, 10 min) was performed six times. This resulted in the formation of H, in which potassium was replaced by protons. + Layered titanium oxide niobium HNb 3 O 8 nH 2 I got an O.

[0069] After that, H +A 0.025M aqueous solution of tetrabutylammonium hydroxide (TBAOH) was added to the layered titanium oxide niobium so that the molar ratio of protons / TBAOH was 1:8, and ultrasonic irradiation (240 W) was performed for 9 hours to obtain an aqueous solution of two-dimensional layered nanosheets of niobium oxide. Then, centrifugation was performed at 15,000 rpm for 30 minutes, and the supernatant liquid was removed. Ethanol was added to the obtained gel-like precipitate, and it was dispersed by ultrasonic irradiation (240 W). One drop of this ethanol dispersion was dropped onto a single crystal silicon substrate (1.6 cm x 1.6 cm, thickness 0.5 mm) on which a thermally oxidized film of silicon oxide was formed on the surface, spin-coated at 5,000 rpm, and the single crystal silicon substrate was then heat-treated at 200 °C for 1 hour. By the above operations, Si / SiO 2 / Nb 3 O 8 A laminate of the above formula was obtained.

[0070] (2) Sample preparation Molybdenum dioxide (MoO 2 Using 1.5 cm × 1.5 cm, 0.5 mm thick, and 1.5% NaCl as the raw materials, and potassium bromide as the growth promoter, MoS was grown at a synthesis temperature of 830 °C on a single crystal silicon substrate (1.5 cm × 1.5 cm, 0.5 mm thick) with silicon oxide formed on the surface as the synthesis substrate by thermal CVD. 2 The resulting sample (Si / SiO 2 / MoS 2 A resin layer was formed by applying an 11% by weight PMMA anisole solution to the Si / SiO 2 / MoS 2 The MoS / PMMA laminate was treated with a potassium hydroxide solution (2M) for several hours to form the MoS 2 / PMMA laminated to Si / SiO 2 After that, the MoS 2 / PMMA laminate and Si / SiO 2 / Nb 3 O 8 The laminate was then bonded together, and the PMMA-containing resin layer was subsequently removed using acetone to obtain MoS. 2 Transfer layer: Si / SiO 2 / Nb 3 O 8 / MoS 2A laminate (Example 5-1) was obtained.

[0071] Similarly, titanium oxide and TiNbO 5 The laminates (Examples 5-2 and 5-3) containing as a conductivity type control layer were prepared by using the Si / SiO 2 / TiO 2 and Si / SiO 2 / TiNbO 5 On top of the stack of MoS 2 As Comparative Example 5, a Si / SiO 2 / MoS 2 The sample of Comparative Example 5 was a single crystal silicon substrate (Si / SiO 2 ) and Si / SiO 2 / MoS 2 The laminate was bonded together and the PMMA was subsequently removed.

[0072] (3) Characterization The Raman spectra (excitation wavelength 532 nm, spot diameter 0.7 μm) of the samples of Example 5 and Comparative Example 5 were measured using a Renishaw Raman spectrometer. As shown in FIG. 14A, the A′ 1 It can be seen that all of the mode peaks are shifted to lower wave numbers compared to those of the laminate of Comparative Example 5. In addition, the peak position changes depending on the conductivity type control layer used, and the peak positions are as follows, from lowest to highest: Examples 5-1, 5-3, and 5-2 (i.e., MoS 2 / Nb 3 O 8 , MoS 2 / TiNbO 5 , MoS 2 / TiO 2 ) The change in carrier density Δn (unit: cm ) based on the comparative example was calculated using the following formula: -2 ) is shown in FIG. E´ and Δω A´1 are the E' mode peak and A' mode peak between Example 5 and Comparative Example 5, respectively. 1 The difference in the Raman shift of the mode peak is shown in Fig. 1. The order of carrier density is MoS 2 / Nb3 O 8 , MoS 2 / TiNbO 5 , MoS 2 / TiO 2 From the above results, it was found that the two-dimensional material MoO 2 This suggests that electrons are doped in the

[0073]

number

[0074] 5. Example 6: Transistors Comprising Stacks of Various Conductivity Type Control Layers and Molybdenum Sulfide Layers In this embodiment, the Nb 3 O 8 , TiO 2 , and TiNbO 5 as a conductivity type control layer, and MoS 2 As a comparative example 6, a transistor containing MoS as an active layer of a two-dimensional material was fabricated (Examples 6-1, 6-2, and 6-3, respectively), and the results of evaluating its characteristics are described. 2 As an active layer, a transistor was used that did not include a conductive type control layer. The structures of the transistors of Example 6 and Comparative Example 6 are shown in Fig. 15A and Fig. 15B, respectively. The transistors shown in Fig. 15A and Fig. 15B are bottom-gate type transistors having two terminals, unlike the transistors of Example 2 and Comparative Example 2 (see Fig. 8B and Fig. 8C). However, since the manufacturing method is the same as that of the transistors of Example 2 and Comparative Example 2, the description of the structure and manufacturing method will be omitted.

[0075] For the transistors of Example 6 and Comparative Example 6, a gate-source voltage (V gs ) was applied, and a source-drain potential of 0.5 V was applied between the two terminals 113 and 115, and the current flowing through the active layer 110 was measured (see FIG. 15). gsThe dependency is shown in FIG. 16. As shown in FIG. 16, the transistors of Example 6 and Comparative Example 6 both exhibited a V gs This shows that the active layer 110 has n-type conductivity, and both the transistors of Example 6 and Comparative Example 6 are n-type transistors.

[0076] Here, in the transistor of Comparative Example 6 that does not have the conductivity type control layer 108, V gs In the transistor of Example 6 having the conductivity type control layer 108, the current decreased sharply in the negative region. gs is negative but still 10 -7 A or more of current flows, and it is confirmed that the active layer 110 has a high carrier density compared to the transistor of Comparative Example 6. In addition, the amount of current flowing was gs In the range of SiO 2 / Nb 3 O 8 / MoS 2 ), Example 6-3 (SiO 2 / TiNbO 5 / MoS 2 ), Example 6-2 (SiO 2 / TiO 2 / MoS 2 ), Comparative Example 6 (SiO 2 / MoS 2 ). Therefore, together with the results of Raman spectroscopy in Example 5, the order of carrier density was from highest to lowest in Example 6-1 (SiO 2 / Nb 3 O 8 / MoS 2 ), Example 6-3 (SiO 2 / TiNbO 5 / MoS 2 ), Example 6-2 (SiO 2 / TiO 2 / MoS 2 These results indicate that the conductivity control layer strongly shifts the active layer, which contains a two-dimensional material, transition metal dichalcogenide, to n-type.

[0077] The above-described embodiments of the present invention may be combined as appropriate as long as they are not mutually inconsistent. In addition, those in which a person skilled in the art appropriately adds or removes components or modifies the design of each embodiment, or adds or omits steps or modifies conditions, are also included in the scope of the present invention as long as they include the gist of the present invention.

[0078] Even if there are other effects and advantages different from those brought about by the aspects of each of the above-mentioned embodiments, those that are clear from the description in this specification or that can be easily predicted by a person skilled in the art are naturally understood to be brought about by the present invention. [Explanation of symbols]

[0079] 100: transistor, 102: substrate, 104: gate electrode, 106: gate insulating layer, 108: conductivity type control layer, 108-1: first conductivity type control layer, 108-2: second conductivity type control layer, 108a: end portion, 110: active layer, 112: terminal, 113: terminal, 114: terminal, 115: terminal, 116: undercoat, 118: interlayer insulating film, 120: synthetic substrate, 122: resin layer, 130: p-type silicon substrate, 132: thermal oxide film

Claims

1. A gate electrode, a first conductivity type control layer overlapping the gate electrode; a gate insulating layer sandwiched between the gate electrode and the first conductivity type control layer and in contact with the gate electrode and the first conductivity type control layer; an active layer in contact with the first conductivity type control layer and including graphene or a transition metal dichalcogenide; and A pair of terminals in direct contact with the active layer, the gate insulating layer and the first conductivity type control layer are sandwiched between the gate electrode and the active layer; The first conductivity type control layer comprises a two-dimensional layered nanosheet of a metal oxide.

2. The transistor of claim 1 , wherein the active layer is located above the first conductivity type control layer.

3. The transistor according to claim 1 , wherein the first conductivity type control layer is insulating.

4. A second conductivity type control layer is further provided in contact with the active layer, The transistor of claim 1 , wherein the active layer is sandwiched between the first conductivity type control layer and the second conductivity type control layer.

5. the gate electrode is located on a substrate; The transistor of claim 1 , wherein the gate electrode is sandwiched between the substrate and the active layer.

6. The transistor of claim 1 , wherein the two-dimensional layered nanosheet is single crystalline.

7. 2. The transistor of claim 1, wherein the metal oxide comprises one or more selected from titanium, ruthenium, molybdenum, cobalt, tantalum, manganese, niobium, bismuth, lanthanum, calcium, and strontium.

8. 2. The transistor of claim 1, wherein the transition metal dichalcogenide is selected from sulfides, selenides, and tellurides of molybdenum, tungsten, niobium, tantalum, zirconium, rhenium, palladium, platinum, and hafnium.

9. forming a gate electrode on a substrate; forming a gate insulating layer on the substrate; forming a first conductivity type control layer on the gate insulating layer; forming an active layer on the first conductivity type control layer, the active layer including graphene or a transition metal dichalcogenide and in contact with the first conductivity type control layer; forming a pair of terminals in direct contact with the active layer; The first conductivity type control layer comprises a two-dimensional layered nanosheet of a metal oxide.

10. forming an active layer comprising graphene or a transition metal dichalcogenide on a substrate; forming a first conductivity type control layer on the active layer in contact with the active layer; forming a gate insulating layer on the active layer; forming a gate electrode on the gate insulating layer; and forming a pair of terminals in direct contact with the active layer; The first conductivity type control layer comprises a two-dimensional layered nanosheet of a metal oxide.

11. The method according to claim 9 , wherein the first conductivity type control layer has insulating properties.

12. forming a second conductivity type control layer; The method according to claim 9 or 10, wherein the active layer is sandwiched between the first conductivity type control layer and the second conductivity type control layer.

13. The method of claim 9 , further comprising irradiating the first conductivity type control layer with ultraviolet light.

14. 11. The method according to claim 9, wherein the first conductivity type control layer is formed by a Langmuir-Blodgett method or a spin coating method.

15. The method according to claim 12 , wherein the second conductivity type control layer is formed by a Langmuir-Blodgett method or a spin coating method.

16. The method according to claim 9 or 10, wherein the active layer is formed by a transfer method.

17. The method according to claim 9 or 10, wherein the two-dimensional layered nanosheet is a single crystal.

18. The method according to claim 9 or 10, wherein the metal oxide comprises one or more selected from the group consisting of titanium, ruthenium, molybdenum, cobalt, tantalum, manganese, niobium, bismuth, lanthanum, calcium, and strontium.

19. 11. The method according to claim 9 or 10, wherein the transition metal dichalcogenide is selected from sulfides, selenides and tellurides of molybdenum, tungsten, niobium, tantalum, zirconium and hafnium.

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