Control circuit, isolation type DC / DC converter, invertor system and motor system

Abstract

To suppress erroneous detection of a feedback voltage caused by common-mode noise.SOLUTION: A control circuit (101), which is a control circuit for an isolation type DC / DC converter (11) configured to supply a power supply voltage to a gate drive circuit (1) configured to drive a power device (Q1), includes: a sampling circuit (102) configured to sample a feedback voltage according to an output voltage of the isolation type DC / DC converter; a selection circuit (103) configured to select one of the feedback voltage sampled at the N-th time by the sampling circuit and the feedback voltage sampled at the (N-1)-th time by the sampling circuit; and a switching control circuit (105) configured to perform switching control for a switching element on the basis of the feedback voltage selected by the selection circuit.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The invention disclosed in this specification relates to a control circuit, an isolated DC / DC converter, an inverter system, and a motor system. [Background technology]

[0002] 2. Description of the Related Art Various motor systems have been developed in the past, each of which includes an inverter circuit including a high-side transistor and a low-side transistor, and a motor that receives a voltage output from the inverter circuit (see, for example, Patent Document 1).

[0003] An isolated DC / DC converter is used as a power supply device for a high-side gate drive circuit that drives the gate of a high-side transistor. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent Publication No. 2021-52508

[0005] [overview] Mainly, when the high-side transistor turns off, large common-mode noise is generated in the ground of the high-side gate drive circuit. This large common-mode noise passes through the capacitance of the isolation transformer provided in the isolated DC / DC converter and fluctuates the potential of the feedback system of the isolated DC / DC converter, which may cause erroneous detection of the feedback voltage.

[0006] Recently, high-side transistors are being replaced by compound semiconductor power devices such as SiC and GaN from IGBTs (Insulated Gate Bipolar Transistors). In general, the switching slew rate of compound semiconductor power devices such as SiC and GaN is set higher than that of IGBTs. A high slew rate increases common-mode noise. In other words, when compound semiconductor power devices such as SiC and GaN are used as high-side transistors, there is a high possibility that the feedback voltage will be erroneously detected in an isolated DC / DC converter.

[0007] The control circuit disclosed in this specification is a control circuit for an isolated DC / DC converter configured to supply a power supply voltage to a gate drive circuit configured to drive a power device, and includes a sampling circuit configured to sample a feedback voltage corresponding to an output voltage of the isolated DC / DC converter, a selection circuit configured to select either the feedback voltage sampled the Nth time by the sampling circuit or the feedback voltage sampled the N-1th time by the sampling circuit, and a switching control circuit configured to control the switching of a switching element based on the feedback voltage selected by the selection circuit.

[0008] The isolated DC / DC converter disclosed in this specification includes a control circuit having the above configuration and the switching element.

[0009] The inverter system disclosed in this specification includes an isolated DC / DC converter having the above-described configuration, the gate drive circuit, and an inverter circuit including the power device.

[0010] The motor system disclosed in this specification includes an inverter system having the above-described configuration, and a motor configured to receive a voltage output from the inverter system. [Brief description of the drawings]

[0011] [Figure 1] FIG. 1 is a diagram showing a configuration of a motor system according to an embodiment. [Diagram 2] FIG. 2 is a diagram showing the configuration of an isolated DC / DC converter. [Diagram 3] FIG. 3 is a perspective view of the appearance of the semiconductor integrated circuit device. [Figure 4] FIG. 4 is a diagram showing a configuration of a semiconductor integrated circuit device. [Diagram 5] FIG. 5 is a diagram showing an example of the configuration of the sampling circuit and the selection circuit. [Figure 6] FIG. 6 is a flowchart showing the operations of the sampling circuit, the selection circuit, and the capacitor. [Figure 7] FIG. 7 is a timing chart for explaining normal operations of the sampling circuit and the selection circuit. [Figure 8] FIG. 8 is a timing chart for explaining the operation of the sampling circuit and the selection circuit when the common mode noise is large.

[0012] [Detailed Description] In this specification, MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) refers to a field effect transistor whose gate structure is composed of at least three layers: "a layer made of a conductor or a semiconductor such as polysilicon with a low resistance value," "an insulating layer," and "a P-type, N-type, or intrinsic semiconductor layer." In other words, the gate structure of a MOSFET is not limited to a three-layer structure of metal, oxide, and semiconductor. Hereinafter, a P-channel type MOSFET will be referred to as a PMOS transistor, and an N-channel type MOSFET will be referred to as an NMOS transistor.

[0013] <Motor system> Fig. 1 is a diagram showing the configuration of a motor system according to one embodiment. The motor system SYS1 shown in Fig. 1 includes an inverter system SYS2 and a three-phase brushless DC motor M1. The inverter system SYS2 drives the brushless DC motor M1.

[0014] The inverter system SYS2 includes a capacitor C1, an inverter circuit IV1, high-side gate drive circuits 1 to 3, low-side gate drive circuits 4 to 6, isolated DC / DC converters 11 to 13, and a control circuit 20.

[0015] The capacitor C1 smoothes the DC voltage VDC and supplies it to the inverter circuit IV1. The inverter circuit IV1 converts the DC power output from the capacitor C1 into AC power.

[0016] The inverter circuit IV includes a U-phase half bridge, a V-phase half bridge, and a W-phase half bridge. The U-phase half bridge is configured by a series connection of an NMOS transistor Q1, which is a high-side transistor, and an NMOS transistor Q4, which is a low-side transistor. The V-phase half bridge is configured by a series connection of an NMOS transistor Q2, which is a high-side transistor, and an NMOS transistor Q5, which is a low-side transistor. The W-phase half bridge is configured by a series connection of an NMOS transistor Q3, which is a high-side transistor, and an NMOS transistor Q6, which is a low-side transistor.

[0017] A node NU where the NMOS transistor Q1 and the NMOS transistor Q4 are connected is connected to a U-phase coil of the brushless DC motor M1. A node NV where the NMOS transistor Q2 and the NMOS transistor Q5 are connected is connected to a V-phase coil of the brushless DC motor M1. A node NW where the NMOS transistor Q3 and the NMOS transistor Q6 are connected is connected to a V-phase coil of the brushless DC motor M1.

[0018] The control circuit 20 controls the switching of the NMOS transistors Q1 to Q6. The high-side gate drive circuits 1 to 3 drive the gates of the NMOS transistors Q1 to Q3, respectively, under the control of the control circuit 20. The low-side gate drive circuits 4 to 6 drive the gates of the NMOS transistors Q4 to Q6, respectively, under the control of the control circuit 20.

[0019] The high-side gate drive circuits 1 to 3 use, as a power supply voltage, the output voltages of the insulating DC / DC converters 11 to 13. The low-side gate drive circuits 4 to 6 use, as a power supply voltage, the DC voltage VCC.

[0020] <Isolated DC / DC converter> Fig. 2 is a diagram showing the configuration of an isolated DC / DC converter 11. Isolated DC / DC converters 12 and 13 have the same configuration as the isolated DC / DC converter 11. The isolated DC / DC converter 11 shown in Fig. 2 includes a capacitor C2, a semiconductor integrated circuit device 100, a transformer TR1, a Schottky diode D1, a capacitor C3, and resistors R1 to R3.

[0021] The isolated DC / DC converter 11 is a flyback power supply that converts an input voltage VIN, which is a DC voltage supplied to the primary circuit system, into an output voltage (a voltage obtained by subtracting voltage VOUT- from voltage VOUT+) which is also a DC voltage and supplies it to the secondary circuit system while electrically insulating the primary circuit system from the secondary circuit system.

[0022] The capacitor C2 smoothes the input voltage V IN. The voltage output from the capacitor C2 is supplied to the terminal T1 of the semiconductor integrated circuit device 100 and to a first end of the primary winding of the transformer TR1.

[0023] The semiconductor integrated circuit device 100 is a so-called power supply control IC (Integrated Circuit), and is provided in the primary circuit system to mainly control the isolated DC / DC converter 11. The semiconductor integrated circuit device 100 is connected to terminals T1 to T5. The terminal T2 is connected to a first end of the primary winding of the transformer TR1 and a first end of the resistor R1. The terminal T3 is connected to a second end of the resistor R1. The terminal T4 is connected to a first end of the resistor R2. The second end of the resistor R2 and the terminal T5 are connected to ground.

[0024] The transformer TR1 includes a primary winding and a secondary winding that are magnetically coupled to each other while electrically insulating the primary circuit system from the secondary circuit system. A first end of the secondary winding of the transformer TR1 is connected to the anode of the Schottky diode D1. A cathode of the Schottky diode D1 is connected to a first end of the capacitor C3 and a first end of the resistor R3. A second end of the secondary winding of the transformer TR1 is connected to a second end of the capacitor C3 and a second end of the resistor R3. A rectifying and smoothing circuit formed by the Schottky diode D1 and the capacitor C3 rectifies and smoothes an induced voltage appearing in the secondary winding of the transformer TR1 to generate an output voltage (a voltage obtained by subtracting the voltage VOUT- from the voltage VOUT+).

[0025] <Semiconductor integrated circuit device> Fig. 3 is an external perspective view of semiconductor integrated circuit device 100. Semiconductor integrated circuit device 100 is an electronic component formed by encapsulating a semiconductor integrated circuit chip in a housing (package) made of resin. A plurality of external terminals are provided and exposed on the housing of semiconductor integrated circuit device 100, and the plurality of external terminals include terminals T1 to T5 shown in Fig. 2. Note that the number of external terminals of semiconductor integrated circuit device 100 and the external appearance of semiconductor integrated circuit device 100 shown in Fig. 3 are merely examples.

[0026] Fig. 4 is a diagram showing a configuration of a semiconductor integrated circuit device 100. The semiconductor integrated circuit device 100 shown in Fig. 4 includes a control circuit 101 and an NMOS transistor Q7, which is a switching element configured to be controlled by the control circuit 101. The control circuit 101 includes a sampling circuit 102, a selection circuit 103, a comparison circuit 104, and a switching control circuit 105.

[0027] The sampling circuit 102 is configured to sample the feedback voltage VFB corresponding to the output voltage of the isolated DC / DC converter 11 (the voltage obtained by subtracting the voltage VOUT− from the voltage VOUT+).

[0028] The selection circuit 103 is configured to select either the feedback voltage VFB sampled the Nth time by the sampling circuit 102 or the feedback voltage VFB sampled the (N-1)th time by the sampling circuit 102. Here, N is any natural number.

[0029] The comparison circuit 104 compares the feedback voltage selected by the selection circuit 103 with the periodically changing voltage, and outputs the comparison result. The periodically changing voltage used in the comparison circuit 104 is, for example, a triangular waveform voltage, a sawtooth waveform voltage, or the like. The frequency of the periodically changing voltage used in the comparison circuit 104 is the switching frequency of the NMOS transistor Q7. The switching frequency of the NMOS transistor Q7 is about 65 kHz to 2 MHz. On the other hand, the driving frequency of the NMOS transistors Q1 to Q6 of the inverter circuit IV1 is about 10 kHz to 20 kHz in order to suppress the switching loss of the NMOS transistors Q1 to Q6. It is preferable that the switching frequency of the NMOS transistor Q7 is at least twice the driving frequency of the NMOS transistors Q1 to Q6. As a result, the isolated DC / DC converter 11 can determine whether or not to perform a process to mask common mode noise every time the NMOS transistor Q1 is turned off, and can perform a process to mask common mode noise as necessary.

[0030] The switching control circuit 105 is configured to control the switching of the NMOS transistor Q7 based on the feedback voltage VFB selected by the selection circuit 103. More specifically, the switching control circuit 105 is configured to control the switching of the NMOS transistor Q7 based on the output of the comparison circuit 104.

[0031] <Sampling circuit and selection circuit> FIG. 5 is a diagram showing an example of the configuration of the sampling circuit 102 and the selection circuit 103. As shown in FIG.

[0032] The sampling circuit 102 shown in FIG. 5 includes resistors R4 and R5, an NPN bipolar transistor Q8, PMOS transistors Q9 and Q10, a constant current source CS1, analog switches ASW1 to ASW3, and a logic circuit L1. The circuit formed by the resistor R4, the NPN bipolar transistor Q8, the PMOS transistors Q9 and Q10, and the constant current source CS1 generates a voltage (a voltage equivalent to a flyback voltage) obtained by subtracting the input voltage VIN applied to the terminal T1 from the voltage applied to the terminal T3. The resistor R5 converts the voltage equivalent to the flyback voltage into a current. The current output from the resistor R5 is converted into a feedback voltage VFB by the resistor R2 (see FIG. 2) externally connected to the terminal T4. When the analog switch ASW1 is turned on, the feedback voltage VFB is sampled and held in the capacitor C4. When the analog switch ASW2 is turned on, the feedback voltage VFB is sampled and held in the capacitor C5. When the analog switch ASW3 is turned on, the feedback voltage VFB is sampled and held in the capacitor C6. The logic circuit L1 is synchronized with a voltage used in the comparison circuit 104 that changes periodically to control the analog switches ASW1 to ASW3.

[0033] 5 includes analog switches ASW4 to ASW12, window comparators W1 to W3, and a logic circuit L1. The sampling circuit 102 and the selection circuit 103 share the logic circuit L1.

[0034] When the analog switch ASW4 is turned on, the feedback voltage VFB (signal Sig1) held by the capacitor C4 becomes the output voltage VSEL of the selection circuit 103 and is supplied to the comparison circuit 104 (see FIG. 4). When the analog switch ASW5 is turned on, the feedback voltage VFB (signal Sig2) held by the capacitor C5 becomes the output voltage VSEL of the selection circuit 103 and is supplied to the comparison circuit 104 (see FIG. 4). When the analog switch ASW6 is turned on, the feedback voltage VFB (signal Sig3) held by the capacitor C6 becomes the output voltage VSEL of the selection circuit 103 and is supplied to the comparison circuit 104 (see FIG. 4). The logic circuit L1 controls the analog switches ASW4 to ASW12 in synchronization with the periodically changing voltage used in the comparison circuit 104. The logic circuit L1 controls the analog switches ASW4 to ASW6 based on the outputs of the window comparators W1 to W3.

[0035] The window comparator W1 determines whether the signal Sig3 is within the range of the signal Sig2 ±0.1 V when the analog switch ASW7 is on and the analog switch ASW8 is off. The window comparator W1 determines whether the signal Sig3 is within the range of the signal Sig1 ±0.1 V when the analog switch ASW7 is off and the analog switch ASW8 is on.

[0036] The window comparator W2 determines whether the signal Sig2 is within the range of the signal Sig3 ±0.1 V when the analog switch ASW9 is on and the analog switch ASW10 is off. The window comparator W2 determines whether the signal Sig2 is within the range of the signal Sig1 ±0.1 V when the analog switch ASW9 is off and the analog switch ASW10 is on.

[0037] The window comparator W3 determines whether the signal Sig1 is within the range of the signal Sig2 ±0.1 V when the analog switch ASW11 is on and the analog switch ASW12 is off. The window comparator W3 determines whether the signal Sig1 is within the range of the signal Sig3 ±0.1 V when the analog switch ASW11 is off and the analog switch ASW12 is on.

[0038] In the window comparators W1 to W3, the absolute value of the plus side offset (+0.1 V) and the absolute value of the minus side offset (-0.1 V) are the same, but may be different from each other.

[0039] The selection circuit 103 shown in Fig. 5 is configured to perform a selection process based on the value of the feedback voltage VFB sampled the Nth time, the value of the feedback voltage VFB sampled the N-1th time, and the value of the feedback voltage VFB sampled the N-2th time. More specifically, the selection circuit 103 shown in Fig. 5 is configured to perform a selection process based on the difference between the value of the feedback voltage VFB sampled the Nth time and the value of the feedback voltage VFB sampled the N-1th time, and the difference between the value of the feedback voltage VFB sampled the Nth time and the value of the feedback voltage VFB sampled the N-2th time.

[0040] In more detail, the selection circuit 103 shown in FIG. 5 is configured to perform selection processing based on whether or not the difference between the value of the feedback voltage VFB sampled the Nth time and the value of the feedback voltage VFB sampled the N-1th time is within a predetermined range (within ±0.1 V), and whether or not the difference between the value of the feedback voltage VFB sampled the Nth time and the value of the feedback voltage VFB sampled the N-2th time is within a predetermined range (within ±0.1 V).

[0041] In further detail, the selection circuit 103 shown in FIG. 5 selects a feedback voltage VFB sampled at the Nth time when the difference between the feedback voltage VFB sampled at the N-1th time and the feedback voltage VFB sampled at the N-1th time is outside a predetermined range (>+0.1V, <-0.1V), when the difference between the feedback voltage VFB sampled at the Nth time and the feedback voltage VFB sampled at the N-2th time is outside a predetermined range (>+0.1V, <-0.1V), and when the feedback voltage VFB sampled at the Nth time is smaller than the feedback voltage VFB sampled at the N-1th time and the feedback voltage VFB sampled at the N-2th time, or when the feedback voltage VFB sampled at the Nth time is smaller than the feedback voltage VFB sampled at the N-1th time and the feedback voltage VFB sampled at the N-2th time. The feedback voltage VFB sampled at the N-1th time is selected when the difference between the value of the sampled feedback voltage VFB and the (N-1)th sampled feedback voltage VFB is outside a predetermined range (>+0.1V, <-0.1V), the difference between the value of the Nth sampled feedback voltage VFB and the value of the (N-2)th sampled feedback voltage VFB is outside a predetermined range (>+0.1V, <-0.1V), and the value of the Nth sampled feedback voltage VFB is greater than the (N-1)th sampled feedback voltage VFB and the (N-2)th sampled feedback voltage VFB.

[0042] FIG. 6 is a flowchart showing the operations of the sampling circuit 102, the selection circuit 103, and the capacitors C4 to C6.

[0043] The initial value of N is 1, and the initial values ​​of the signals Sig1 to Sig3 held by the capacitors C4 to C6 are all 0V.

[0044] In step S1, the sampling circuit 102 samples the feedback voltage VFB for the Nth time.

[0045] In step S2 following step S1, any one of the capacitors C4 to C6 holds the N-th feedback voltage VFB sampled in step S1.

[0046] In step S3 following step S2, the window comparators W1 to W3 calculate comparison results C1A, C1B, C2A, and C2B. The comparison result C1A is a comparison result obtained by subtracting the Nth feedback voltage VFB from the N-1th feedback voltage VFB+0.1V. The comparison result C1B is a comparison result obtained by subtracting the N-1th feedback voltage VFB-0.1V from the Nth feedback voltage VFB. The comparison result C2A is a comparison result obtained by subtracting the Nth feedback voltage VFB from the N-2th feedback voltage VFB+0.1V. The comparison result C2B is a comparison result obtained by subtracting the N-2th feedback voltage VFB-0.1V from the Nth feedback voltage VFB.

[0047] If the condition that the comparison results C1A, C1B, C2A, and C2B are all at a LOW level is not satisfied, and the condition that the comparison results C1A, C1B, C2A, and C2B are all at a HIGH level is also not satisfied, the Nth feedback voltage VFB is not significantly different from the N-1th feedback voltage VFB and the N-2th feedback voltage VFB, and is not considered to be significantly affected by common mode noise, so the selection circuit 103 selects the Nth feedback voltage VFB (step S4).

[0048] On the other hand, when the condition that the comparison results C1A, C1B, C2A, and C2B are all at a LOW level or the condition that the comparison results C1A, C1B, C2A, and C2B are all at a HIGH level is satisfied, the Nth feedback voltage VFB is significantly different from the N-1th feedback voltage VFB and also significantly different from the N-2th feedback voltage VFB, and is considered to be significantly affected by common mode noise, so the selection circuit 103 selects the N-1th feedback voltage VFB (step S5). In other words, the selection circuit 103 masks the feedback voltage VFB that is considered to be significantly affected by common mode noise.

[0049] When the process of step S4 or step S5 is completed, a value obtained by adding 1 to N is set as a new value of N in the logic circuit L1 (step S6).

[0050] When the process of step S6 is completed, the process returns to step S1, and the above-mentioned operations are repeated.

[0051] FIG. 7 is a timing chart for explaining normal operation of the sampling circuit 102 and the selection circuit 103. FIG. 8 is a timing chart for explaining operation of the sampling circuit 102 and the selection circuit 103 when common mode noise is large. In FIG. 7 and FIG. 8, GATE indicates a gate signal supplied to the gate of the NMOS transistor Q7, and SW indicates the drain voltage of the NMOS transistor Q7. In FIG. 7 and FIG. 8, ASW1 to ASW6 indicate the states of the analog switches ASW1 to ASW6, and Sig1 to Sig3 are waveforms of the signals Sig1 to Sig3. In FIG. 7 and FIG. 8, COMP1+ and COMP1- indicate the output of the window comparator W1, COMP2+ and COMP2- indicate the output of the window comparator W2, and COMP3+ and COMP3- indicate the output of the window comparator W3. In FIG. 7 and FIG. 8, COMP DET is generated inside the logic circuit L1 and is used to determine the timing at which the logic circuit L1 detects the outputs of the window comparators W1 to W3.

[0052] In Fig. 7, since there is no need to mask common mode noise, the analog switches ASW6, ASW4, ASW5, and ASW6 are turned on in this order. On the other hand, in Fig. 8, since there is a need to mask common mode noise, the analog switches ASW6, ASW4, ASW5, and ASW5 are turned on in this order, and the signal Sig3 held in the capacitor C6 in the latter half of the timing chart shown in Fig. 8 is masked.

[0053] <Other> In addition to the above-described embodiment, various modifications can be made to the configuration of the invention without departing from the spirit of the invention. The above-described embodiment should be considered to be illustrative in all respects and not restrictive, and the technical scope of the present invention is indicated by the claims, not the description of the above-described embodiment, and should be understood to include all modifications that fall within the meaning and scope of the claims.

[0054] For example, in the above-described embodiment, the input voltage VIN supplied to the isolated DC / DC converter 11 may be a voltage output from a DC power supply, or may be a voltage output from a rectifying and smoothing circuit that receives an AC voltage output from an AC power supply.

[0055] <Additional Notes> Regarding the present disclosure, specific configuration examples of which have been shown in the above-mentioned embodiments, additional notes will be provided.

[0056] A control circuit (101) according to the present disclosure is a control circuit for an isolated DC / DC converter (11) configured to supply a power supply voltage to a gate drive circuit (1) configured to drive a power device (Q1), and has a configuration (first configuration) including: a sampling circuit (102) configured to sample a feedback voltage corresponding to an output voltage of the isolated DC / DC converter; a selection circuit (103) configured to select either the feedback voltage sampled the Nth time by the sampling circuit or the feedback voltage sampled the N-1th time by the sampling circuit; and a switching control circuit (105) configured to control the switching of a switching element based on the feedback voltage selected by the selection circuit.

[0057] According to the control circuit of the first configuration, it is possible to mask the common mode noise generated when the power device is turned off, thereby making it possible to suppress erroneous detection of the feedback voltage caused by the common mode noise.

[0058] In the control circuit of the above first configuration, the selection circuit may be configured to perform selection processing based on the value of the feedback voltage sampled the Nth time, the value of the feedback voltage sampled the N-1th time, and the value of the feedback voltage sampled the N-2th time (second configuration).

[0059] In the control circuit of the above second configuration, the selection circuit may be configured to perform the selection process based on the difference between the value of the feedback voltage sampled the Nth time and the value of the feedback voltage sampled the N-1th time, and the difference between the value of the feedback voltage sampled the Nth time and the value of the feedback voltage sampled the N-2th time (third configuration).

[0060] In the control circuit of the above third configuration, the selection circuit may be configured (fourth configuration) to perform the selection process based on whether or not a difference between the value of the feedback voltage sampled the Nth time and the value of the feedback voltage sampled the N-1th time is within a predetermined range, and whether or not a difference between the value of the feedback voltage sampled the Nth time and the value of the feedback voltage sampled the N-2th time is within the predetermined range.

[0061] In the control circuit of the fourth configuration, the selection circuit may be configured to select the feedback voltage sampled the N-1th time when a difference between the value of the feedback voltage sampled the Nth time and the feedback voltage sampled the N-1th time is outside the predetermined range, a difference between the value of the feedback voltage sampled the Nth time and the value of the feedback voltage sampled the N-2th time is outside the predetermined range, and the value of the feedback voltage sampled the Nth time is smaller than the feedback voltage sampled the N-1th time and the feedback voltage sampled the N-2th time, or when a difference between the value of the feedback voltage sampled the Nth time and the feedback voltage sampled the N-1th time is outside the predetermined range, a difference between the value of the feedback voltage sampled the Nth time and the feedback voltage sampled the N-2th time is outside the predetermined range, and the value of the feedback voltage sampled the Nth time is larger than the feedback voltage sampled the N-1th time and the feedback voltage sampled the N-2th time, respectively (fifth configuration).

[0062] In the control circuit of any one of the above first to fifth configurations, a switching frequency of the switching element may be configured to be at least twice the drive frequency of the power device (sixth configuration).

[0063] An isolated DC / DC converter (11 to 13) of the present disclosure has a configuration (seventh configuration) including a control circuit having any one of the first to sixth configurations and the switching element.

[0064] The inverter system (SYS2) of the present disclosure has a configuration (eighth configuration) including the isolated DC / DC converter of the seventh configuration, the gate drive circuit, and an inverter circuit including the power device.

[0065] A motor system (SYS1) of the present disclosure has a configuration (ninth configuration) including the inverter system of the eighth configuration described above, and a motor (M1) configured to receive a voltage output from the inverter system. [Explanation of symbols]

[0066] 1~3 High side gate drive circuit 4~6 Low side gate drive circuit 11~13 Isolated DC / DC Converter 20, 101 Control circuit 100 Semiconductor integrated circuit device 102 Sampling circuit 103 Selection circuit 104 Comparison circuit 105 Switching control circuit ASW1~ASW12 Analog Switches C1~C6 capacitors CS1 current source D1 Schottky diode IV1 Inverter circuit L1 Logic circuit M1 Brushless DC Motor NU, NV, and NW nodes Q1~Q7 NMOS transistors Q8 NPN bipolar transistor Q9, Q10 PMOS transistors R1~R5 Resistors SYS1 Motor system SYS2 Inverter System T1~T5 terminals TR1 transformer W1~W3 Window Comparator

Claims

1. 1. A control circuit for an isolated DC / DC converter configured to provide a power supply voltage to a gate drive circuit configured to drive a power device, comprising: a sampling circuit configured to sample a feedback voltage corresponding to an output voltage of the isolated DC / DC converter; a selection circuit configured to select one of the feedback voltage sampled by the sampling circuit for an N-th time and the feedback voltage sampled by the sampling circuit for an (N-1)-th time; a switching control circuit configured to control switching of a switching element based on the feedback voltage selected by the selection circuit; A control circuit comprising:

2. 2. The control circuit according to claim 1, wherein the selection circuit is configured to perform a selection process based on a value of the feedback voltage sampled an Nth time, a value of the feedback voltage sampled an N-1th time, and a value of the feedback voltage sampled an N-2th time.

3. 3. The control circuit according to claim 2, wherein the selection circuit is configured to perform the selection process based on a difference between the feedback voltage value sampled at an Nth time and the feedback voltage sampled at an (N-1)th time, and a difference between the feedback voltage value sampled at an Nth time and the feedback voltage value sampled at an (N-2)th time.

4. 4. The control circuit according to claim 3, wherein the selection circuit is configured to perform the selection process based on whether a difference between the feedback voltage value sampled the Nth time and the feedback voltage sampled the N-1th time is within a predetermined range, and whether a difference between the feedback voltage value sampled the Nth time and the feedback voltage value sampled the N-2th time is within the predetermined range.

5. The selection circuit includes: When a difference between the feedback voltage value sampled at the Nth time and the feedback voltage sampled at the (N-1)th time is outside the predetermined range, a difference between the feedback voltage value sampled at the Nth time and the feedback voltage value sampled at the (N-2)th time is outside the predetermined range, and the feedback voltage value sampled at the Nth time is smaller than the feedback voltage sampled at the (N-1)th time and the feedback voltage sampled at the (N-2)th time, or When a difference between the value of the feedback voltage sampled the Nth time and the value of the feedback voltage sampled the N-1th time is outside the predetermined range, a difference between the value of the feedback voltage sampled the Nth time and the value of the feedback voltage sampled the N-2th time is outside the predetermined range, and the value of the feedback voltage sampled the Nth time is greater than the feedback voltage sampled the N-1th time and the feedback voltage sampled the N-2th time, The control circuit of claim 4 configured to select the N-1th sampled feedback voltage.

6. The control circuit according to claim 1 , wherein a switching frequency of the switching element is equal to or greater than twice a drive frequency of the power device.

7. A control circuit according to any one of claims 1 to 6; An isolated DC / DC converter comprising the switching element.

8. An isolated DC / DC converter according to claim 7; The gate drive circuit; and an inverter circuit including the power device.

9. An inverter system according to claim 8; a motor configured to receive a voltage output from the inverter system.

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