Integration process using boron-doped silicon material

Abstract

To provide a method for deposition, etching and removal of materials containing boron or boron and silicon materials in a semiconductor integration process.SOLUTION: An integrated process includes depositing a boron-containing material or silicon and boron-containing materials onto a substrate disposed in a processing region of a semiconductor processing chamber, etching portions of the boron-containing material or silicon and boron-containing materials with a chlorine-containing precursor to form one or more features in the substrate, and removing remaining portions of the boron-containing material or silicon and boron-containing materials from the substrate using a fluorine-containing precursor.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to U.S. patent application Ser. No. 63 / 053,693, filed July 19, 2020, entitled "INTEGRATION PROCESSES UTILIZING BORON-DOPED SILICON MATERIALS," which is incorporated by reference in its entirety for all purposes.

[0002]

[0002] The present technology relates to semiconductor integration processes. More specifically, the present technology relates to methods of deposition, etching, and removal of materials that include boron or boron and silicon materials. [Background technology]

[0003]

[0003] Integrated circuits are made possible by processes that produce intricately patterned layers of material on a substrate surface. Creating patterned materials on a substrate requires controlled methods of forming and removing exposed materials. As devices become smaller, the uniformity of the materials can affect subsequent operation. For example, many process steps utilize masking or sacrificial materials to facilitate pattern transfer or structure formation within or between layers of a semiconductor substrate. As the number of different materials used in processing increases and the critical dimensions of the feature sizes decrease, the use of masks with increased selectivity to the various exposed materials becomes more important.

[0004]

[0004] Thus, there is a need for improved systems and methods that can be used to manufacture high quality devices and structures. The present technology addresses these and other needs. Summary of the Invention

[0005]

[0005] An exemplary processing method may include depositing a boron-containing material or a silicon and boron-containing material on a substrate disposed in a processing region of a semiconductor processing chamber. The method may include etching a portion of the boron-containing material or the silicon and boron-containing material with a chlorine-containing precursor to form one or more features in the substrate. The method may also include removing a remaining portion of the boron-containing material or the silicon and boron-containing material from the substrate using a fluorine-containing precursor.

[0006]

[0006] In some embodiments, the boron-containing material can be a silicon- and boron-containing material. Depositing the boron-containing material can include providing a silicon-containing precursor and a boron-containing precursor to a processing region of a semiconductor processing chamber. Depositing the boron-containing material can include providing a hydrogen-containing precursor together with the silicon-containing precursor and the boron-containing precursor. A flow rate ratio of the hydrogen-containing precursor to either the silicon-containing precursor or the boron-containing precursor can be about 2:1 or greater. Depositing the boron-containing material can include forming a plasma of all precursors in the processing region of the semiconductor processing chamber. The silicon-containing precursor can be or include silane. The boron-containing precursor can be or include diborane. Removing can be performed at a rate of about 35 nm / min or greater. The boron-containing material can be characterized by a film thickness of about 20 nm or greater.

[0007]

[0007] The substrate temperature may be maintained at about 400°C or higher during deposition of the boron-containing material on the substrate. The substrate temperature may be maintained at about 200°C or higher during removal. The etching may include forming a plasma of a bromine-containing precursor. The etching may include contacting the boron-containing material with plasma effluents of the bromine-containing precursor. The etching may include stopping the supply of the bromine-containing precursor. The etching may include forming a plasma of a chlorine-containing precursor. The etching may include contacting the boron-containing material with plasma effluents of the chlorine-containing precursor. The etching may include forming a plasma of an etchant mixture including a chlorine-containing precursor and an oxygen-containing precursor. The etching may include contacting the boron-containing material with plasma effluents of the etchant mixture while forming a plasma at a first plasma power. The etching may include increasing the first plasma power to a second plasma power after the first period of time. The etching can include transferring a pattern from an overlying mask material through the boron-containing material. The etching can include applying a bias power for a first period of time. The etching can include terminating the bias power after the first period of time. The removing can include forming a remote plasma of an etchant mixture including a fluorine-containing precursor and a hydrogen-containing precursor. The removing can include contacting the boron-containing material with plasma effluents of the etchant mixture. The removing can include removing the boron-containing material with a selectivity of about 20:1 or greater over other exposed materials on the substrate. The remote plasma can be formed with a plasma power of about 2.0 kW or greater.

[0008]

[0008] Some embodiments of the present technology may include a processing method. The method may include depositing a silicon- and boron-containing material on a substrate disposed in a processing region of a semiconductor processing chamber. The method may include etching a portion of the silicon- and boron-containing material to form one or more features in the substrate. The etching may include forming a plasma of an etchant mixture including a chlorine-containing precursor and an oxygen-containing precursor. The etching may include contacting the silicon- and boron-containing material with plasma effluents of the etchant mixture while forming a plasma at a first plasma power. The etching may include increasing the first plasma power to a second plasma power after the first period of time. The method may include removing a remaining portion of the silicon- and boron-containing material from the substrate using a fluorine-containing precursor.

[0009]

[0009] In some embodiments, the silicon and boron-containing material may be characterized by a boron concentration of about 40 atomic % or more. The etchant mixture may include a fluorine-containing precursor. A flow ratio of the fluorine-containing precursor to the oxygen-containing precursor to the chlorine-containing precursor may be about 1:5:10 or more. The method may include applying a bias power during a first period of time. The method may include terminating the bias power after the first period of time. The plasma may be formed at a pulsing frequency of about 500 Hz or more. A duty cycle of the bias power during plasma formation may be about 40% or less.

[0010]

[0010] Some embodiments of the present technology may include a processing method. The method may include depositing a silicon- and boron-containing material on a substrate disposed in a processing region of a semiconductor processing chamber. The method may include etching a portion of the silicon- and boron-containing material with a chlorine-containing precursor to form one or more features in the substrate. The method may include removing a remaining portion of the silicon- and boron-containing material from the substrate. The removing may include forming a remote plasma of an etchant mixture including a fluorine-containing precursor and a hydrogen-containing precursor. The removing may include contacting the silicon- and boron-containing material with plasma effluents of the etchant mixture. The method may include removing the silicon- and boron-containing material at a rate of about 35 nm / min or greater. In some embodiments, the temperature of the substrate during the removing may be maintained at about 200° C. or greater, and the remote plasma may be formed with a plasma power of about 2.0 kW or greater. The substrate may include an exposed region of titanium nitride, and the etchant mixture may include ammonia.

[0011]

[0011] Such techniques may provide many benefits over conventional systems and techniques. For example, materials according to embodiments of the present technology may improve selectivity for various materials to be etched. This may allow thinner layers to be used for patterning, reducing risks associated with pattern transfer, including distortion of structures due to etchant impingement and loss of critical dimensions due to timing of etching. Additionally, the present technology may improve etching removal of mask material, increasing semiconductor processing throughput. These and other embodiments, along with their many advantages and features, are described in more detail below in conjunction with the following description and accompanying drawings.

[0012]

[0012] A further understanding of the nature and advantages of the disclosed technology may be realized by reference to the remaining portions of the specification and the drawings. [Brief description of the drawings]

[0013] [Figure 1]1 shows a schematic cross-sectional view of an exemplary processing chamber in accordance with some embodiments of the present technique. [Diagram 2] 1 shows a schematic cross-sectional view of an exemplary processing chamber in accordance with some embodiments of the present technique. [Diagram 3] 1 shows a schematic cross-sectional view of an exemplary processing chamber in accordance with some embodiments of the present technique. [Figure 4] 1 illustrates exemplary steps of an integration method according to some embodiments of the present technique. [Figure 5A] 1 shows a schematic isometric partial view of a substrate during a pattern transfer process in accordance with some embodiments of the present technique; [Figure 5B] 1 shows a schematic isometric partial view of a substrate during a pattern transfer process in accordance with some embodiments of the present technique; [Figure 6] 1 illustrates exemplary steps that may be included in methods according to some embodiments of the present technology. [Figure 7] 1 illustrates exemplary steps that may be included in methods according to some embodiments of the present technology. [Figure 8] 1 illustrates exemplary steps that may be included in methods according to some embodiments of the present technology. [Figure 9] 1 illustrates exemplary steps that may be included in methods according to some embodiments of the present technology. [Figure 10A] 1A-1D show schematic cross-sectional partial views of a substrate during a removal process in accordance with some embodiments of the present technique; [Figure 10B] 1A-1D show schematic cross-sectional partial views of a substrate during a removal process in accordance with some embodiments of the present technique; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014]

[0023] Some figures are included as schematic diagrams. It should be understood that the figures are for illustrative purposes and should not be considered to scale unless expressly stated to be to scale. Furthermore, as schematic diagrams, the figures are provided to aid in understanding and may not include all aspects or information compared to realistic depictions and may include material that is emphasized for illustrative purposes.

[0015]

[0024] In the accompanying drawings, similar components and / or features may have the same reference numbers. Furthermore, various components of the same type may be distinguished according to the reference numbers, with a letter distinguishing between the similar components. If only a first reference number is used in this specification, the description is applicable to any of the similar components having the same first reference number, regardless of the letter.

[0016]

[0025] During semiconductor manufacturing, several structures may be fabricated on a substrate using various deposition and etching processes. Mask materials may be used to etch materials partially or to etch to create features across the substrate. As devices become smaller and the selectivity between materials improves and structures may be easier to form, improved hard masks may facilitate fabrication. For example, compared to thermally generated amorphous silicon hard masks, silicon films incorporating boron may be characterized by improved hardness and other material properties, facilitating the use of the films as mask materials. Increasing the hardness may improve the use of mask materials for any number of processes. For example, many memory structures may include the formation of high aspect ratio openings. In DRAM structures, capacitor contactors may be formed, and in 3D NAND, memory holes or contact openings may be formed. Storage node contacts may also be formed. Using harder films as masks may help maintain uniformity of local critical dimensions across the substrate, allowing thinner films to be used. However, the increased hardness may make etching and removal of masks and sacrificial layers more difficult.

[0017]

[0026] The present technology may overcome these limitations by utilizing tunable boron-containing and silicon- and boron-containing films in semiconductor processing. In addition, by utilizing improved processes for etching and removal, throughput may not be adversely affected. In addition, removal rates according to some embodiments of the present technology may be improved by adjusting the chamber structure and configuration to facilitate improved etch rates with high selectivity. This may facilitate rapid removal of residual materials while substantially or completely preserving other materials exposed during removal. After describing the general aspects of the chamber according to some embodiments of the present technology in which the plasma processing steps described below may be performed, specific methodologies may be described. It is understood that the technology described is not intended to be limited to the specific films, chambers, or processes described, as the described technology may be used to improve numerous film formation processes and may be applicable to a variety of processing chambers and steps.

[0018]

[0027] FIG. 1 illustrates a cross-sectional view of an exemplary processing chamber 100 according to some embodiments of the present technique. The diagram may provide an overview of a system incorporating one or more aspects of the present technique and / or that may perform one or more deposition or other processing steps according to embodiments of the present technique. Additional details of the chamber 100 or the method performed may be further described below. Although the chamber 100 may be utilized to form a film layer according to some embodiments of the present technique, it should be understood that the method may similarly be performed in any chamber in which film formation may occur. The processing chamber 100 may include a chamber body 102, a substrate support 104 disposed within the chamber body 102, and a lid assembly 106 coupled to the chamber body 102 and confining the substrate support 104 within a processing space 120. A substrate 103 may be provided to the processing space 120 through an opening 126, which may be conventionally sealed for processing using a slit valve or door. The substrate 103 may be located on a surface 105 of the substrate support during processing. The substrate support 104 may be rotatable, as indicated by arrow 145, along an axis 147 about which the shaft 144 of the substrate support 104 may lie. Alternatively, the substrate support 104 may be elevated for rotation as needed during the deposition process.

[0019]

[0028] A plasma profile modulator 111 may be disposed in the process chamber 100 to control plasma distribution across the substrate 103 disposed on the substrate support 104. The plasma profile modulator 111 includes a first electrode 108 that may be disposed adjacent to the chamber body 102 and may separate the chamber body 102 from other components of the lid assembly 106. The first electrode 108 may be part of the lid assembly 106 or may be a separate sidewall electrode. The first electrode 108 may be an annular or ring-shaped member and may be a ring electrode. The first electrode 108 may be a continuous loop along the periphery of the process chamber 100 surrounding the process space 120 or may be discontinuous at selected locations as desired. The first electrode 108 may also be a perforated electrode, such as a perforated ring or mesh electrode, or may be a plate electrode, such as a secondary gas distributor, for example.

[0020]

[0029] The one or more isolators 110a, 110b may be a dielectric material such as ceramic or a metal oxide, e.g., aluminum oxide and / or aluminum nitride, and may contact the first electrode 108 and electrically and thermally isolate the first electrode 108 from the gas distributor 112 and the chamber body 102. The gas distributor 112 may define an aperture 118 for distributing the process precursors into the processing space 120. The gas distributor 112 may be connected to a first power source 142, such as an RF generator, an RF power source, a DC power source, a pulsed DC power source, a pulsed RF power source, or any other power source that may be connected to a processing chamber. In some embodiments, the first power source 142 may be an RF power source.

[0021]

[0030] The gas distributor 112 may be a conductive gas distributor or a non-conductive gas distributor. The gas distributor 112 may also be formed from conductive and non-conductive components. For example, the body of the gas distributor 112 may be conductive, but the face plate of the gas distributor 112 may be non-conductive. The gas distributor 112 may be powered, such as by a first power source 142 as shown in FIG. 1, or the gas distributor 112 may be connected to ground in some embodiments.

[0022]

[0031] The first electrode 108 may be connected to a first tuned circuit 128 that may control a ground path of the process chamber 100. The first tuned circuit 128 may include a first electronic sensor 130 and a first electronic controller 134. The first electronic controller 134 may be or may include a variable capacitor or other circuit element. The first tuned circuit 128 may be or may include one or more inductors 132. The first tuned circuit 128 may be any circuit that allows for a variable or controllable impedance under plasma conditions present in the process space 120 during processing. In some illustrated embodiments, the first tuned circuit 128 may include a first circuit leg and a second circuit leg connected in parallel between ground and the first electronic sensor 130. The first circuit leg may include a first inductor 132A. The second circuit leg may include a second inductor 132B connected in series with the first electronic controller 134. The second inductor 132B can be disposed between the first electronic controller 134 and a node coupling both the first and second circuit legs to the first electronic sensor 130. The first electronic sensor 130 can be a voltage sensor or a current sensor and can be connected to the first electronic controller 134 to allow some closed-loop control of the plasma conditions inside the process space 120.

[0023]

[0032] The second electrode 122 may be connected to the substrate support 104. The second electrode 122 may be incorporated into the substrate support 104 or may be connected to a surface of the substrate support 104. The second electrode 122 may be a plate, a perforated plate, a mesh, a wire screen, or any other distributed configuration of conductive elements. The second electrode 122 may be a tuning electrode and may be connected to a second tuning circuit 136, for example, by a conduit 146 (e.g., a cable having a selected resistance, such as 50 ohms) disposed in a shaft 144 of the substrate support 104. The second tuning circuit 136 may have a second electronic sensor 138, a second electronic controller 140, which may be a second variable capacitor. The second electronic sensor 138 may be a voltage sensor or a current sensor and may be connected to the second electronic controller 140 to provide further control over the plasma conditions in the process space 120.

[0024]

[0033] A third electrode 124, which may be a bias electrode and / or an electrostatic chucking electrode, may be coupled to the substrate support 104. The third electrode is connected to a second power source 150 through a filter 148, which may be an impedance matching circuit. The second power source 150 may be DC power, pulsed DC power, RF bias power, a pulsed RF source or bias power, or a combination of these or other sources. In some embodiments, the second power source 150 may be an RF bias power.

[0025]

[0034] The lid assembly 106 and substrate support 104 of FIG. 1 may be used with any processing chamber for plasma or thermal processing. In operation, the processing chamber 100 may perform real-time control of plasma conditions within the processing space 120. The substrate 103 may be placed on the substrate support 104, and process gases may flow through the lid assembly 106 using the inlet 114 according to any desired flow scheme. The gases may be exhausted from the processing chamber 100 through the outlet 152. Power may be connected to the gas distributor 112 to establish a plasma within the processing space 120. In some embodiments, the substrate may be subjected to an electrical bias using the third electrode 124.

[0026]

[0035] Upon exciting a plasma in the process space 120, a potential difference may be established between the plasma and the first electrode 108. A potential difference may also be established between the plasma and the second electrode 122. The electronic controllers 134 and 140 may then be used to adjust the flow characteristics of the ground paths represented by the two tuned circuits 128 and 136. Set points may be provided to the first tuned circuit 128 and the second tuned circuit 136 to provide independent control of the deposition rate and center-to-edge plasma density uniformity. In an embodiment in which both electronic controllers may be variable capacitors, the electronic sensors may independently adjust the variable capacitors to maximize the deposition rate and minimize the thickness non-uniformity.

[0027]

[0036] Each of the tuning circuits 128 and 136 may have a variable impedance that may be adjusted using the respective electronic controllers 134 and 140. If the electronic controllers 134, 140 are variable capacitors, the capacitance range of each of the variable capacitors and the inductance of the first inductor 132A and the second inductor 132B may be selected to provide an impedance range. This range may depend on the frequency and voltage characteristics of the plasma and may have a minimum value for the capacitance range of each variable capacitor. Thus, when the capacitance of the first electronic controller 134 is at a minimum or maximum, the impedance of the first tuning circuit 128 may be high. This results in a plasma shape that has a minimum aerial or lateral coverage above the substrate support. When the capacitance of the first electronic controller 134 reaches a value that minimizes the impedance of the first tuning circuit 128, the aerial coverage of the plasma may grow to a maximum, thus effectively covering the entire working area of ​​the substrate support 104. If the capacitance of the first electronic controller 134 deviates from the minimum impedance setting, the plasma shape may shrink from the chamber walls, reducing the aerial coverage of the substrate support. The second electronic controller 140 may have a similar effect, so that as the capacitance of the second electronic controller 140 changes, the aerial coverage of the plasma above the substrate support increases or decreases.

[0028]

[0037] Electronic sensors 130 and 138 may be used to tune the respective circuits 128, 136 in a closed loop. Depending on the type of sensor used, a set point for current or voltage may be attached to each sensor. The sensors may be provided with control software that determines adjustments to the respective electronic controllers 134, 140 to minimize deviations from the set point. As a result, the shape of the plasma may be selected and dynamically controlled during processing. Although the above description is based on the electronic controllers 134, 140 being variable capacitors, it should be understood that any electronic components having adjustable characteristics may be used to provide the tuning circuits 128 and 136 with adjustable impedance.

[0029]

[0038] FIG. 2 shows a schematic cross-sectional view of an exemplary processing chamber 200 suitable for patterning a layer of material disposed on a substrate 202 in the processing chamber 200. For example, the chamber 200 may be an exemplary etch chamber that may be configured to facilitate pattern transfer or etching of materials according to the present technique, including boron-containing materials and boron and silicon-containing materials. Although the exemplary processing chamber 200 may be suitable for performing a patterning process, it will be understood that aspects of the present technique may be performed in any number of chambers configured to perform operations according to embodiments of the present technique. The plasma processing chamber 200 may include a chamber body 205 that defines a processing region 201 in which a substrate may be processed. The chamber body 205 may have sidewalls 212 and a bottom 218, which are connected to a ground 226. The sidewalls 212 may have a liner 215 to protect the sidewalls 212 and extend the time between maintenance cycles of the plasma processing chamber 200. The dimensions of the chamber body 205 and associated components of the plasma processing chamber 200 are not limiting and can generally be proportionally larger than the size of the substrate 202 to be processed therein. Example substrate sizes include 200 mm, 250 mm, 300 mm, 450 mm diameters, as well as display substrates and solar cell substrates, among others.

[0030]

[0039] The chamber body 205 may support a chamber lid assembly 210 to enclose the processing region 201. The chamber body 205 may be fabricated from aluminum or other suitable materials. A substrate access port 213 may be formed through a sidewall 212 of the chamber body 205 to facilitate transfer of the substrate 202 into and out of the plasma processing chamber 200. The access port 213 may be connected to a transfer chamber and / or other chambers of a substrate processing system, as previously described. A pumping port 245 may be formed through the sidewall 212 of the chamber body 205 and coupled to the processing region 201. A pumping device may be connected to the processing region 201 through the pumping port 245 to evacuate the interior space and control the pressure therein. The pumping device may include one or more pumps and a throttle valve.

[0031]

[0040] A gas panel 260 is connected to the chamber body 205 by gas lines 267 to supply process gases into the processing region 201. The gas panel 260 includes one or more process gas sources 261, 262, 263, 264 and may additionally include inert, non-reactive, and reactive gases that may be utilized for any number of processes. Examples of process gases that may be provided by the gas panel 260 include, but are not limited to, hydrocarbon-containing gases including methane, sulfur hexafluoride, silicon chloride, carbon tetrafluoride, hydrogen bromide, argon, chlorine, nitrogen, helium, or oxygen, as well as any number of additional materials. In addition, the process gas may include any number of nitrogen-, chlorine-, fluorine-, oxygen-, and hydrogen-containing gases, such as BCl3, C2F4, C4F8, C4F6, CHF3, CH2F2, CH3F, NF3, NH3, CO2, SO2, CO, N2, NO2, N2O, and H2, among any number of additional precursors.

[0032]

[0041] A valve 266 controls the flow of process gas from the sources 261, 262, 263, 264 from the gas panel 260 and may be managed by a controller 265. The flow of gas supplied to the chamber body 205 from the gas panel 260 may include a combination of gases from one or more sources. The lid assembly 210 may include a nozzle 214. The nozzle 214 may be one or more ports for introducing process gases from the sources 261, 262, 263, 264 of the gas panel 260 into the processing region 201. After the process gases are introduced into the plasma processing chamber 200, the gases may be excited to form a plasma. An antenna 248, such as one or more inductor coils, may be provided adjacent to the plasma processing chamber 200. The antenna power supply 242 may feed the antenna 248 through a matching network 241 to inductively couple energy (e.g., RF energy) to the process gas and maintain a plasma formed from the process gas in the processing region 201 of the plasma processing chamber 200. Alternatively, or in addition to the antenna power supply 242, a process electrode below the substrate 202 and / or above the substrate 202 may be used to capacitively couple RF power to the process gas and maintain a plasma in the processing region 201. The operation of the power supply 242 may be controlled by a controller (e.g., controller 265), which also controls the operation of other components in the plasma processing chamber 200.

[0033]

[0042] A substrate support pedestal 235 may be disposed within the processing region 201 to support the substrate 202 during processing. The substrate support pedestal 235 may include an electrostatic chuck 222 for holding the substrate 202 during processing. The electrostatic chuck ("ESC") 222 may use electrostatic attraction to hold the substrate 202 against the substrate support pedestal 235. The ESC 222 may be powered by an RF power supply 225 integrated with a matching network 224. The ESC 222 may include an electrode 221 embedded within a dielectric body 251. The electrode 221 may be connected to the RF power supply 225 and provide a bias. The bias attracts plasma ions formed by process gases in the processing region 201 to the ESC 222 located on the pedestal and the substrate 202. The RF power supply 225 may cycle on and off, or pulse during processing of the substrate 202. The ESC 222 may have an isolator 228 to make the sidewalls of the ESC 222 less attractive to the plasma in order to extend the maintenance life of the ESC 222. Additionally, the substrate support pedestal 235 may have a cathode liner 236 to protect the sidewalls of the substrate support pedestal 235 from the plasma gases and extend the maintenance interval of the plasma processing chamber 200.

[0034]

[0043] The electrode 221 may be connected to a power supply 250. The power supply 250 may provide a chucking voltage of about 200 volts to about 2000 volts to the electrode 221. The power supply 250 may also include a system controller for controlling the operation of the electrode 221 by directing a DC current to the electrode 221 for chucking and dechucking the substrate 202. The ESC 222 may include a heater disposed in the pedestal and coupled to the power supply for heating the substrate. Meanwhile, the cooling base 229 supporting the ESC 222 may include conduits for circulating a heat transfer fluid to maintain the temperature of the ESC 222 and the substrate 202 disposed thereon. The ESC 222 may be configured to operate within a temperature range required by the thermal budget of a device fabricated on the substrate 202. For example, the ESC 222 may be configured to maintain the substrate 202 at a temperature of about −150° C. or less to about 500° C. or more, depending on the process being performed.

[0035]

[0044] A cooling base 229 may be provided to assist in temperature control of the substrate 202. To mitigate process drift and time, the temperature of the substrate 202 may be maintained approximately constant by the cooling base 229 throughout the time the substrate 202 is in the cleaning chamber. In some embodiments, the temperature of the substrate 202 may be maintained at a temperature between about −150° C. and about 500° C. throughout the subsequent cleaning process, although any temperature may be utilized. A cover ring 230 may be mounted on the ESC 222 along the periphery of the substrate support pedestal 235. The cover ring 230 may be configured to contain the etching gas to a desired portion of the exposed upper surface of the substrate 202 while shielding the upper surface of the substrate support pedestal 235 from the plasma environment inside the plasma processing chamber 200. As described above, lift pins are selectively translated through the substrate support pedestal 235 to lift the substrate 202 above the substrate support pedestal 235 to facilitate access to the substrate 202 by a transfer robot or other suitable transfer mechanism.

[0036]

[0045] The controller 265 may be utilized to control processing sequences and regulate gas flows and other process parameters from the gas panel 260 to the plasma processing chamber 200. The software routines, when executed by the CPU, transform the CPU into a special purpose computer, such as a controller, that controls the plasma processing chamber 200, such that processes are performed in accordance with the present disclosure. The software routines may also be stored and / or executed by a second controller that may be associated with the plasma processing chamber 200.

[0037]

[0046] 3 shows a schematic cross-sectional view of an exemplary processing chamber 300 in accordance with some embodiments of the present technique. The processing chamber 300 may be suitable for performing material removal on a substrate 302 therein. For example, the chamber 300 may be an exemplary etch or removal chamber that may be configured to facilitate removal of materials in accordance with the present technique, including boron-containing materials and boron and silicon-containing materials.

[0038]

[0047] FIG. 3 may illustrate components located on a chamber body 301, such as on a lid plate 305, that may define multiple process regions for a tandem chamber, a stand-alone chamber, or any other configuration that may benefit from one or more of the stack components. The lid stack may include a spacer 310 located on the lid plate. This may radially define a processing region 304 where a pedestal or other substrate support may extend with a substrate, as previously described. A pedestal 303 or other substrate support may extend through the chamber body 301 and support a substrate 302. The substrate may include a boron-containing material or a boron and silicon-containing material, as described throughout the present technique. Defining the processing region from above may be a showerhead 315 located on the spacer 310. Although the showerhead 315 is shown as a single channel showerhead, it will be understood that a dual channel showerhead may be used as well. The showerhead 315 can include a resistive element 317 that can be used to heat the showerhead during operation.

[0039]

[0048] Above the showerhead 315 may be an electrode 320 located on the showerhead, although in some embodiments a thermal spacer may at least partially separate the two components, for example the showerhead may be heated while the electrode may be cooled. The electrode may define or include a channel 322 extending around the plate and through which a temperature controlled fluid may be flowed. Above the electrode may be an isolator 325, and above the isolator may be a faceplate 330. The faceplate may include a channel 332 defined therein for the temperature controlled fluid to flow. The electrode, faceplate, and isolator define a remote plasma region 327 between the components in which a capacitively coupled plasma may be formed. The isolator electrically isolates the faceplate from the electrode, thereby allowing the components to be charged or grounded to form a plasma of the precursors flowed into the remote plasma region. In some embodiments the hot electrode, which may be the faceplate for example, may be powered with higher power, thereby increasing the ion density to increase the etch rate.

[0040]

[0049] Some embodiments of the present technology may provide high etching rates of masks or other materials. Thus, the capacitively coupled plasma that can be formed between the faceplate and the electrode may be generated with increased plasma power to increase plasma density in the space and increase plasma effluent generation to increase etching of the substrate material in the processing region. In some embodiments, the plasma is generated with a plasma power of about 2.0 kW or more, and may be generated with a plasma power of about 2.5 kW or more, about 3.0 kW or more, about 3.5 kW or more, about 4.0 kW or more, about 4.5 kW or more, about 5.0 kW or more, about 5.5 kW or more, about 6.0 kW or more, or higher. However, this increase in plasma power may increase the impact of the plasma in the chamber.

[0041]

[0050] For example, many of the surfaces or components may be coated with a protective coating to ameliorate the erosion and / or corrosion effects in the remote plasma region. For example, an oxide coating may be formed on the components, which may be aluminum or any other material used in semiconductor chambers. One such oxide coating may be yttrium oxide. As the plasma power increases in the remote plasma region, the plasma energy may increase the temperature of the electrode and adjacent components as well. This may increase the bombardment of the coated surfaces and increase the plasma effects on corners and other materials. Also, coatings such as yttrium oxide may begin to decompose when temperatures exceed 150° C. Thus, to limit degradation of this coating, a fluid may be flowed through the channels 322 formed in the electrode 320 to maintain a temperature of about 150° C. or less, about 125° C. or less, about 100° C. or less, about 90° C. or less, about 80° C. or less, about 70° C. or less, about 60° C. or less, about 50° C. or less, or less during processing.

[0042]

[0051] In addition, the aperture profile of the apertures formed within the faceplate and electrode may be tailored to further mitigate damage. For example, in some prior art, one or more apertures in the faceplate and electrode may be characterized by a conical or tapered section that extends to the surface facing the remote plasma region. These regions are more difficult to coat with protective materials, such as yttrium oxide or other oxide coatings, and the thickness of the coating may decrease further toward the conical portion. In addition, the conical portion may limit the amount of flat surface between adjacent cones. This may increase charge accumulation in these regions, further increasing defects in the coating, all of which may increase the likelihood of arcing in the region. The conical portion may also promote a hollow cathode effect within the cone, drawing the plasma further into the conical portion and further increasing damage to the thinner coating within the conical portion. Some prior art may tolerate arcing or damage to the coating when lower plasma power is used, such as less than 2.5 kW or less than 1.0 kW, but the risk of arcing may be less and the damage that occurs may be lower. At high plasma powers, such as those that may be used in some embodiments of the present technology, these materials can further damage components and increase particle displacement to the substrate. The present technology may modify one or more aspects to limit or prevent arcing during formation of high power plasmas.

[0043]

[0052] For example, in some embodiments, the apertures formed through the faceplate and electrode may be characterized by a counterbore or countersunk profile extending in a direction toward the remote plasma region as shown, where the apertures may be characterized by a reduced diameter extending to the surface facing the remote plasma region and a larger diameter or taper extending to the opposite surface. This may facilitate the coating process on the plasma-facing surface, improve component protection from energetic plasma species, and limit sharp angles or pronounced edges that may be prone to arc paths.

[0044]

[0053] The blocker plate 335 is located in a recess in the face plate and may be bolted to a gas box 340 that is connected to the face plate at an outer edge. An outlet manifold 345 is connected to the gas box, which may include an internal plenum that allows gases to mix before being delivered to the chamber. The electrode 320 is an ion suppressor that allows ions formed in the capacitively coupled plasma to be filtered from the plasma effluent, which may allow etching to be performed substantially or exclusively by radical species, protecting structures and improving selectivity. The electrode 320 may operate as one of two electrodes for generating a remote plasma in the process chamber, as described above. The electrode 320 may be an integral component in some embodiments, as shown, and may include a channel 322 defined in the electrode that may extend around the electrode. As described above, the channel may allow temperature control of the electrode 320 during processing in some embodiments. The electrode 320 is characterized by a first surface that faces the remote plasma region and a second surface opposite the first surface, which may face the showerhead, for example. As shown, recesses may be formed in the second surface of the electrode, which may increase mixing and distribution of fluids within the chamber.

[0045]

[0054] Conventionally utilized electrodes may also include recesses defined in the first surface of the electrode, which may partially define a plasma envelope in the remote plasma region. As shown similar to the recesses formed along the second surface of the electrode, the recesses may create a corner profile around the recess. This setup may work well during some conventional capacitively coupled plasma processes where the plasma power may be less than 1,000 watts. On the other hand, in some embodiments of the present technology where the plasma power may be several thousand watts, these corner profiles may cause several problems. For example, the corner profiles may be more difficult to plasma coat with a protective layer, similar to those described above, and thus the coating may be thinner or contain gaps in these regions, increasing the opportunity for damage. Additionally, the plasma profile in the remote plasma region may include increased edge density and electric field concentration, which may further damage the coating in this region. If the coating is not complete or is thin, it may be more susceptible to damage. Additionally, increased charge density may accumulate on the upper ridge of the recess, increasing the likelihood of arcing and material damage, as well as increasing particles on the substrate being processed.

[0046]

[0055] As a result, electrodes according to some embodiments of the present technology may be characterized by a substantially planar profile in the active area of ​​the processing chamber. The electrode 320 may include a substantially flat surface across the surface of the electrode facing the faceplate, which may extend past the inner annular edge of the isolator 325 to the area where an O-ring or elastomeric element may be located between the components. This facilitates surface coating of the electrode, and the faceplate may likewise be characterized by a substantially planar surface, which may also be coated with a protective material as described above. The apertures defined through the faceplate and the electrode may be characterized by counterbore or countersunk profiles facing each other, as discussed above. Here, the portion characterized by a reduced diameter may extend to the surface of the component facing or defining the remote plasma region. The surface of the component facing the remote plasma region does not include a conical or tapered portion, which may pose coating challenges and increase the possibility of arcing, as described above.

[0047]

[0056] Because recesses in the surfaces of components facing the remote plasma region may partially define the plasma region, and to maintain similar plasma profile characteristics where the faceplate and electrodes may be characterized by a substantially planar profile along their surfaces, the isolator may be modified to maintain the remote plasma region characteristics. For example, in some embodiments, recess distances may be incorporated into the isolator to maintain electrode spacing in the remote plasma region. Thus, in some embodiments, the isolator may be characterized by a thickness or height of at least about 5 mm, and may be characterized by a height of about 6 mm or more, about 7 mm or more, about 8 mm or more, about 9 mm or more, about 10 mm or more, about 11 mm or more, about 12 mm or more, about 13 mm or more, about 14 mm or more, about 15 mm or more, or more, to maintain the characteristics of the plasma between the electrodes.

[0048]

[0057] In addition, remote plasma regions are characterized by increased plasma density at edge regions of the plasma envelope, potentially increasing the likelihood of problems in these regions. To control the plasma envelope in the remote plasma region, the apertures through the components may not extend radially outwardly along the plate. For example, in some embodiments, one or more of the components may be aperture-free a distance from an edge of the remote plasma region. For example, as shown, in some embodiments, the electrode may not include apertures in a region that extends a distance to the inner annular radius of the isolator. For example, apertures through the electrode may not be formed at a radial distance of about 2 mm or more from the inner annular edge of the isolator, and may not be formed at a distance of about 3 mm or more, about 4 mm or more, about 5 mm or more, about 6 mm or more, about 7 mm or more, about 8 mm or more, about 9 mm or more, about 10 mm or more, about 11 mm or more, about 12 mm or more, about 13 mm or more, about 14 mm or more, about 15 mm or more, or more. This may further suppress plasma effects in the remote plasma region.

[0049]

[0058] The exemplary chambers described above may be utilized in some embodiments of an integrated process that may include forming, etching, and removing materials as described above. It should be understood that the described chambers should not be considered limiting and any chamber that may be configured to perform the operations as described may be used as well. The chambers may be combined in a single mainframe or may be separated across a mainframe for processing. FIG. 4 illustrates exemplary steps of an integrated method 400 according to some embodiments of the present technology. The method may be performed in a variety of processing chambers, including any of the processing chambers 100, 200, or 300 described above, and one or more mainframes or tools. The method 400 may include several optional steps. These steps may or may not be specifically associated with some embodiments of the method according to the present technology. For example, many of the steps are described to provide a broader scope of structure formation, but may be performed by alternative methodologies that are not critical to the present technology or will be readily understood. The method 400 may describe steps shown generally in FIGS. 5A-5B, examples of which will be described in conjunction with the steps of the method 400. It should be understood that the figures are only partially schematic and that the substrate may include any number of additional materials and features having various properties and aspects as shown in the figures.

[0050]

[0059] Method 400 may include additional steps prior to the initiation of the recited steps. For example, the additional processing steps may include forming structures on the semiconductor substrate, which may include both the formation and removal of materials. For example, transistor structures, memory structures, or any other structures may be formed. The prior processing steps may be performed in the chamber in which method 400 may be performed, or processing may be performed in one or more other processing chambers prior to providing a substrate to one or more semiconductor processing chambers in which method 400 may be performed. Nevertheless, method 400 may optionally include providing a semiconductor substrate to a processing region of a semiconductor processing chamber, such as processing chamber 100 described above, or other chambers that may include components as described above. The substrate may be deposited on a substrate support, which may be a pedestal, such as substrate support 104, and may be present in a processing region of a chamber, such as processing space 120 described above.

[0051]

[0060] A substrate upon which several steps have been performed becomes a substrate 505 or structure 500, which may represent one or more underlying structures. It should be understood that structure 500 may represent only some of the top layers in processing to illustrate aspects of the present technology. However, it should be understood that any number of layers, materials, or structures may be formed beneath the illustrated material. For example, substrate 505 may represent a material upon which one or more features may be formed, and may represent additional masking or structural layers. Substrate 505 may illustrate an oxide material 506 and an overlying etch stop layer, such as silicon nitride 508. Although these materials may be discussed throughout, it should be understood that other underlying and substrate materials may be or include silicon, germanium, dielectric materials including silicon oxide or silicon nitride, metallic materials, or any number of combinations of these materials, which may be substrate 505, or materials formed upon substrate 505.

[0052]

[0061] In step 405, a boron-containing material or a boron and silicon-containing material 510 may be deposited on a substrate 505. Exemplary deposition method aspects encompassed by the present technology may be further described below, such as with FIG. 6. After deposition of the mask material, additional processing may be performed before additional steps of the method. For example, the pattern to be transferred to the boron and silicon-containing material 510 may be applied in any number of ways. In one non-limiting example, an additional mask 512 may be formed on the boron and silicon-containing material, and a structure or pattern 514 may be formed through the mask and then transferred to the boron and silicon-containing material 510. The mask 512 may be any sacrificial material, such as an oxide or nitride, and a photolithography or other lithography step may be performed to generate the pattern 514. Pattern 514 is illustrated as a set of equal openings formed through a mask, such as might be used to form a cell capacitor for DRAM or a memory hole for 3D NAND, although it should be understood that any pattern may be produced and the illustration is not intended to limit the present technology.

[0053]

[0062] In step 410, a pattern may be transferred through the boron and silicon containing material 510 to the underlying structure 508. Etching may remove portions of the material 510, such as to create a pattern through the material. FIG. 5B shows the pattern 514 transferred to the underlying boron and silicon containing material as pattern 520. As described above, compared to amorphous silicon mask materials, boron doped mask materials, i.e., boron masks, may provide improved hardness and material strength. As a result, masks of reduced thickness may be used. Benefits of reduced thickness may include reduced deposition time, but additional benefits may be realized during pattern transfer. When performing pattern transfer, such as aperture opening, the thickness of the material may affect the etching process. For example, the further into the structure that etching is performed, the more likely it is that the ions and radicals of the etchant will affect the sidewalls as they move. This may result in an amount of wrinkling or twisting in the structure that may affect the material properties of what is subsequently deposited in the aperture. Furthermore, longer etching processes can affect the critical dimension of the apertures by increasing the residence time of the etchant, which in turn increases the time that the top regions can be exposed to the etchant. This can increase the loss of critical dimension, which can be more pronounced at the edge regions. In this case, additional chamber effects can cause redirection of the etchant within the chamber, again increasing the isotropic aspect of removal. Thus, films produced according to the present technique can beneficially affect many processing aspects.

[0054]

[0063] Although some embodiments of the present technology may provide reduced thickness masking, the technology may produce material thicknesses over a large range. For example, deposition processes according to embodiments of the present technology may produce boron-containing materials or boron and silicon-containing materials that are conformal in some embodiments and may be characterized by material thicknesses of about 10 nm or more, about 20 nm or more, about 30 nm or more, about 50 nm or more, about 75 nm or more, about 100 nm or more, about 200 nm or more, about 300 nm or more, about 400 nm or more, about 500 nm or more, about 600 nm or more, about 700 nm or more, about 800 nm or more, about 900 nm or more, about 1,000 nm or more, or more.

[0055]

[0064] After the pattern transfer step, in some embodiments, an additional etching step may be performed, which may further transfer the pattern to the underlying structure, such as to contacts or other interconnect materials. After the final pattern transfer or etch is performed, the boron and silicon-containing materials may be removed from the structure in step 415. As described above, the incorporation of boron may improve film hardness and etch resistance. Conventional etches may be limited by slow etch rates or poor selectivity to other exposed materials. Thus, the removal step of the present technique may rapidly remove material from the underlying structure while maintaining high selectivity to exposed materials. Better removal may be achieved by using a chamber configured to generate a plasma with higher plasma power without arcing or damage to the chamber.

[0056]

[0065] The individual deposition, etching, and removal steps of the present technique may include any number of additional aspects, steps, or features described below. It should be understood that any aspect of any individual process may be incorporated into an integrated method according to an embodiment of the present technique. FIG. 6 illustrates exemplary steps of a deposition method 600 that may be included in an integrated method according to some embodiments of the present technique. The method may be performed in a variety of processing chambers, including the processing chamber 100 described above. The method 600 may include several optional steps. These steps may or may not be specifically associated with some embodiments of the method according to the present technique. Furthermore, any aspect of the method 600 may be considered optional within a broader integrated method in which any number of aspects of the method 600 may be incorporated. For example, many of the steps are described to provide a broader scope of structure formation, but may be performed by alternative methodologies that are not critical to the present technique or will be readily understood.

[0057]

[0066] Method 600 may include additional steps prior to the initiation of the recited steps. For example, additional processing steps may include forming structures on a semiconductor substrate, which may include both the formation and removal of materials. The prior processing steps may be performed in the chamber in which method 600 may be performed, or processing may be performed in one or more other processing chambers prior to providing a substrate to a semiconductor processing chamber in which method 600 may be performed. Nevertheless, method 600 may optionally include providing a semiconductor substrate to a processing region of a semiconductor processing chamber, such as processing chamber 100 described above, or other chambers that may include components as described above. The substrate may be deposited on a substrate support, which may be a pedestal, such as substrate support 104, and may be present in a processing region of a chamber, such as processing space 120 described above.

[0058]

[0067] The substrate may be any number of materials onto which materials such as those described above may be deposited. In some embodiments, optional processing steps such as pretreatment may be performed to prepare the surface of the substrate for deposition. For example, pretreatment may be performed to provide specific ligand terminations on the surface of the substrate to facilitate nucleation of the film to be deposited. For example, other molecular terminations including, by way of non-limiting example, hydrogen, oxygen, carbon, nitrogen, or any combination of these atoms or radicals, such as amidogen or other functional groups, may be adsorbed, reacted, or formed on the surface of the substrate. In addition, material removal may be performed, such as reduction of native oxides or etching of materials, or any other steps that may prepare one or more exposed surfaces of the substrate for deposition.

[0059]

[0068] In step 605, one or more precursors may be delivered to the processing region of the chamber. For example, in an exemplary embodiment where a boron-incorporated silicon film may be formed, a silicon-containing precursor and a boron-containing precursor may be delivered to the processing region of the processing chamber. In some embodiments of the present technique, plasma-enhanced deposition may be performed to promote the reaction and deposition of materials. Some embodiments of the present technique may include the formation or deposition of silicon and boron materials, which may be conventionally characterized by increased surface roughness, for example, compared to thermally produced silicon films. Nucleation of these silicon and boron materials may form islands on the substrate in some embodiments. These islands may form three-dimensionally to different heights during initial film formation and may be maintained during film growth.

[0060]

[0069] Some embodiments of the present technique may include, in optional step 610, additionally providing a hydrogen-containing precursor, which is provided along with the silicon-containing precursor and the boron-containing precursor. The provided precursors may all be used to form a plasma in a processing region of the semiconductor processing chamber in step 615. In step 620, silicon and boron materials may be deposited on the substrate. In some embodiments, the incorporation of a hydrogen-containing precursor may reduce or limit islands formed during nucleation.

[0061]

[0070] By incorporating an additional hydrogen source, film modification or etching of a profile can be performed simultaneously with the deposition of the material. For example, through reaction and / or physical interaction with features formed of silicon and boron materials, hydrogen radicals can trim island formation while creating a more uniform formation profile. As a result, the islands may not extend as far as in conventional processes. To provide sufficient hydrogen radicals in the process, the hydrogen-containing precursor can be included at a higher flow rate than either or both of the silicon-containing precursor or the boron-containing precursor. For example, in some embodiments, the flow ratio of the hydrogen-containing precursor to either or both of the silicon-containing precursor and / or the boron-containing precursor is about 1:1 or greater, and in some embodiments can be about 2:1 or greater, about 3:1 or greater, about 4:1 or greater, about 5:1 or greater, about 6:1 or greater, about 8:1 or greater, about 10:1 or greater, about 15:1 or greater, about 20:1 or greater, about 25:1 or greater, about 30:1 or greater, about 35:1 or greater, about 40:1 or greater, about 45:1 or greater, about 50:1 or greater, or more. As further described below, in some embodiments, the ratio of hydrogen to silicon and / or boron precursor is about 100:1 or greater, and further dilution can be performed that can be about 500:1 or greater, about 1,000:1 or greater, about 1,500:1 or greater, about 2,000:1 or greater, about 2,500:1 or greater, or more.

[0062]

[0071] For example, depending on the precursor used, silicon-containing precursors may be provided at a flow rate of about 500 sccm or less, about 400 sccm or less, about 300 sccm or less, about 200 sccm or less, about 100 sccm or less, about 90 sccm or less, about 80 sccm or less, about 70 sccm or less, about 60 sccm or less, about 50 sccm or less, or less. Similarly, boron-containing precursors may be provided at a flow rate of about 1000 sccm or less, about 800 sccm or less, about 600 sccm or less, about 500 sccm or less, about 450 sccm or less, about 400 sccm or less, about 350 sccm or less, about 300 sccm or less, about 250 sccm or less, about 200 sccm or less, or less. Any additional ranges within these ranges or combinations of stated or unstated numbers may also be used.

[0063]

[0072] The hydrogen-containing precursor is delivered at about 1,000 sccm or greater, and may be delivered at a flow rate of about 1,200 sccm or greater, about 1,400 sccm or greater, about 1,600 sccm or greater, about 1,800 sccm or greater, about 2,000 sccm or greater, about 2,200 sccm or greater, about 2,400 sccm or greater, about 2,600 sccm or greater, about 2,800 sccm or greater, about 3,000 sccm or greater, or greater. Increasing the hydrogen-containing precursor can further smooth the surface of the deposited film, but may also result in more hydrogen being incorporated into the deposited film. Thus, in some embodiments, the hydrogen-containing precursor is provided at a flow rate of about 4,000 sccm or less, and may be provided at a flow rate of about 3,800 sccm or less, about 3,600 sccm or less, about 3,400 sccm or less, about 3,200 sccm or less, about 3,000 sccm or less, about 2,800 sccm or less, about 2,600 sccm or less, or less than this. Additionally, in some embodiments where higher dilution may be performed, the hydrogen-containing precursor is provided at a flow rate of about 5,000 sccm or more, and may be provided at a flow rate of about 10,000 sccm or more, about 15,000 sccm or more, about 20,000 sccm or more, about 25,000 sccm or more, or more. In some embodiments, the flow rate of the silicon or boron precursor may be further reduced to 200 sccm or less, and may be reduced to about 150 sccm or less, about 100 sccm or less, about 50 sccm or less, about 30 sccm or less, about 20 sccm or less, about 10 sccm or less, or even less.

[0064]

[0073] The film may be deposited on the substrate to any thickness. The surface roughness of the produced film may not be limited to the problems during film nucleation mentioned above. For example, film growth and plasma termination may also affect the surface roughness in some aspects of the present technology. For example, once sufficient film growth has occurred, the process may be stopped by extinguishing the plasma in the processing chamber, for example by turning off the power to the electrode where the plasma is generated. Plasma termination may also increase the surface roughness by causing an amount of physical interaction of ions remaining after deposition is completed. It may be assumed that both the nucleation effect and the plasma termination effect are constant regardless of the thickness of the film formed. However, tests have shown that the roughness of the deposited film increases as the film thickness increases. As a result, roughness effects occur during film growth as well, and as the film thickness increases, the roughness of the film may also increase further. Thus, the produced film may be characterized by an increase in roughness that may affect the uniformity of the subsequent etch.

[0065]

[0074] For example, thermally produced silicon, such as polysilicon or other silicon materials, may be characterized by a relatively low average roughness, such as less than about 0.5 nm or less than about 0.2 nm. The films may also be characterized by a relatively low roughness range, such as the difference between the highest and lowest peaks on the formed film. For example, the roughness range may be about 1.5 nm or less, or about 1 nm or less. However, for silicon and boron films produced without one or more aspects of the present technology, the average roughness may be about 2 nm or more, about 3 nm or more, or more for films of similar thickness, but as mentioned above, the roughness may increase with increasing film thickness. Furthermore, the roughness range for produced silicon and boron materials may be about 10 nm or more, and about 15 nm or more, again depending on the film thickness. In subsequent etching operations, such large imbalances between films may cause challenges to the uniformity of the etching operation and may require additional operations to be performed, such as additional chemical mechanical polishing operations.

[0066]

[0075] However, the present technique may reduce or significantly reduce both the average roughness and the roughness range of the produced silicon and boron films by utilizing additional hydrogen-containing precursors to perform a substantially simultaneous etch or by making one or more additional adjustments as further described below. The produced films may be characterized by an average thickness of about 2 nm or less and an average roughness of about 1.5 nm or less, about 1.0 nm or less, about 0.9 nm or less, about 0.8 nm or less, about 0.7 nm or less, about 0.6 nm or less, about 0.5 nm or less, about 0.4 nm or less, about 0.3 nm or less, about 0.2 nm or less, or less. Additionally, in some embodiments, the roughness may be substantially controlled regardless of the film thickness. This may allow for the avoidance of an additional chemical mechanical polishing step, since the as-deposited film may be characterized by any of the average roughness ranges shown. Additionally, the roughness range across the deposited film is about 10 nm or less, and can be about 9 nm or less, about 8 nm or less, about 7 nm or less, about 6 nm or less, about 5 nm or less, about 4 nm or less, about 3 nm or less, about 2 nm or less, about 1 nm or less, or less. As a result, improved materials can be produced that provide film and mask advantages over conventional materials and processes, as well as potentially reduce manufacturing steps by limiting or reducing the number of polishing sequences.

[0067]

[0076] With regard to silicon-containing precursors and boron-containing precursors, any number of precursors may be used in the present technology. For example, silicon-containing precursors may include any silicon-containing material, such as organosilanes, which may include silanes, disilanes, and other materials including higher silanes. Additional silicon-containing materials may include silicon, carbon, oxygen, or nitrogen, such as trisilylamine. Boron-containing materials may include boranes, such as borane, diborane, or other multi-center bonded boron materials, as well as any other boron-containing materials that may be used to produce silicon and boron-containing materials. For example, boron-containing materials may include dimethylamine borane, trimethylborane, triethylborane, or any other boron-containing material or combination of boron-containing materials. The incorporation of boron in silicon films may be based on any percentage incorporation. For example, films produced include about 5 atomic % or greater incorporation of boron, and in some embodiments, about 10 atomic % or greater incorporation of boron, about 15 atomic % or greater incorporation of boron, about 20 atomic % or greater incorporation of boron, about 25 atomic % or greater incorporation of boron, about 30 atomic % or greater incorporation of boron, about 35 atomic % or greater incorporation of boron, about 40 atomic % or greater incorporation of boron, about 45 atomic % or greater incorporation of boron, about 50 atomic % or greater incorporation of boron, about 55 atomic % or greater incorporation of boron. The boron incorporation may include greater than or equal to 100 atomic % boron incorporation, such as a boron film that is silicon-free and essentially pure boron film, or a film of boron and hydrogen, including greater than or equal to about 60 atomic % boron incorporation, greater than or equal to about 65 atomic % boron incorporation, greater than or equal to about 70 atomic % boron incorporation, greater than or equal to about 75 atomic % boron incorporation, greater than or equal to about 80 atomic % boron incorporation, greater than or equal to about 85 atomic % boron incorporation, greater than or equal to about 90 atomic % boron incorporation, greater than or equal to about 95 atomic % boron incorporation, and may include greater than or equal to 100 atomic % boron incorporation, such as a boron film that is silicon-free and essentially pure boron film, or a film of boron and hydrogen.

[0068]

[0077] One or more additional aspects of the deposition may also be adjusted to improve the aspect of the deposition being performed. For example, plasma power may affect the degree of hydrogen dissociation. Any number of hydrogen-containing precursors may be used, and in some embodiments, diatomic hydrogen may be included. For some silicon- and boron-containing materials, the material is sufficiently reactive at the deposition temperature that minimal plasma enhancement may be included. For example, some conventional techniques utilize plasma powers of about 200 watts or less. The present technique utilizes higher or much higher plasma powers, which may promote hydrogen dissociation, increase hydrogen radicals, and reduce roughness as previously described.

[0069]

[0078] For example, in some embodiments, the plasma power may be maintained at about 1,000 or more, about 1,200 watts or more, about 1,400 watts or more, about 1,600 watts or more, about 1,800 watts or more, about 2,000 watts or more, about 2,200 watts or more, about 2,400 watts or more, about 2,600 watts or more, about 2,800 watts or more, about 3,000 watts or more, or more. This increase in plasma power may also improve dissociation and activation of other precursors, which may increase the deposition rate as well. As a result, the deposition rate of the film may be comparable, if not improved, compared to conventional deposition, despite the material being simultaneously etched during deposition. The deposition and simultaneous etching may then be maintained continuously or sequentially for profile modification until the target film thickness is produced. Depending on the plasma process being performed, the plasma power density may also be maintained, allowing for modulation of frequency and power. For example, in some embodiments, the plasma power density may be about 0.25 W / cm 2 The power density is maintained at about 0.5 W / cm 2 Above, approximately 1.0W / cm 2 Above, approximately 1.5W / cm 2 Above, approximately 2.0W / cm 2 Above, approximately 2.5W / cm 2 It may be maintained at or above this level.

[0070]

[0079] The temperature of the substrate may further affect the deposition. For example, in some embodiments, the substrate may be maintained at a temperature of about 400° C. or higher, about 420° C. or higher, about 440° C. or higher, about 460° C. or higher, about 480° C. or higher, about 500° C. or higher, or higher. To reduce roughness of the film formed by performing deposition according to some embodiments of the present technique, hydrogen etching may be performed during deposition. However, the amount of hydrogen radicals generated by the enhanced plasma and hydrogen supply, etc., may also increase the amount of hydrogen incorporated in the film that is generated. This may increase the compressive stress in the film. For example, the as-deposited film may be characterized by a compressive stress of about −800 MPa or higher, which may be due in part to the incorporation of hydrogen. As a result, in some embodiments, the method 600 may include a step of reducing the incorporation of hydrogen in the film.

[0071]

[0080] For example, in some embodiments, the method 600 may include, in optional step 625, thermally annealing the formed silicon and boron-containing material. The deposition may be performed at a first temperature, while the thermal anneal may be performed at a second temperature that is higher than the first temperature. For example, the thermal anneal may be performed at a temperature of about 480° C. or greater. The thermal anneal may be performed at a temperature of about 500° C. or greater, about 510° C. or greater, about 520° C. or greater, about 530° C. or greater, about 540° C. or greater, about 550° C. or greater, about 560° C. or greater, about 570° C. or greater, about 580° C. or greater, about 590° C. or greater, about 600° C. or greater, or greater. The thermal anneal may be performed for a period of about 0.5 minutes or greater, about 1 minute or greater, about 2 minutes or greater, about 3 minutes or greater, about 4 minutes or greater, about 5 minutes or greater, about 6 minutes or greater, or greater.

[0072]

[0081] Thermal annealing can remove the amount of hydrogen incorporated in the film and relieve the compressive stress. For example, in some embodiments, after thermal annealing, the compressive stress in the film can be maintained at about -700 MPa or less, about -650 MPa or less, about -600 MPa or less, about -550 MPa or less, about -500 MPa or less, about -450 MPa or less, about -400 MPa or less, about -350 MPa or less, about -300 MPa or less, about -250 MPa or less, about -200 MPa or less, about -150 MPa or less, about -100 MPa or less, or less.

[0073]

[0082] The pressure in the processing region can affect the amount of ionization and physical interaction that occurs during deposition. Lowering the process pressure can result in greater ion interaction. Thus, in some embodiments, the process pressure during deposition is maintained at about 50 Torr or less, and can be maintained at about 40 Torr or less, about 30 Torr or less, about 20 Torr or less, about 15 Torr or less, about 10 Torr or less, about 9 Torr or less, about 8 Torr or less, about 7 Torr or less, about 6 Torr or less, about 5 Torr or less, about 4 Torr or less, about 3 Torr or less, about 2 Torr or less, or less.

[0074]

[0083] Tests have shown that incorporating argon can increase roughness, and therefore limiting or excluding argon can improve film roughness. However, tests have shown that excluding argon from the process precursor can increase film peeling. Thus, in some embodiments, argon can nevertheless be included with silicon-containing precursor and boron-containing precursor. To limit the impact on roughness, the flow ratio of argon precursor to hydrogen-containing precursor is maintained at about 2:1 or less, and can be maintained at about 1:1 or less, about 0.8:1 or less, about 0.7:1 or less, about 0.6:1 or less, about 0.5:1 or less, about 0.4:1 or less, about 0.3:1 or less, about 0.2:1 or less, about 0.1:1 or less, or less.

[0075]

[0084] Combinations or further adjustments of process parameters may also affect and improve additional aspects of the produced film. Incorporating boron into the hardmask film may improve selectivity to many films. Since the film stack contains more material involved in both the hardmask release step and the subsequent film etching step, improving selectivity may reduce the number of additional steps that are performed. Also, increasing the crystallinity of the film may improve etch selectivity, but in prior art techniques increasing the crystallinity of the film reduces or worsens line edge roughness and line width roughness. As a result, many techniques attempt to keep the film as amorphous silicon. The techniques may at least partially increase the crystallinity of the formed film, thereby increasing the etch selectivity, but by limiting the crystallinity, the techniques may maintain the line edge roughness and line width roughness.

[0076]

[0085] When an increase in hydrogen flow rate according to embodiments of the present technology is utilized for silicon and boron precursors, crystallinity may increase. However, by utilizing process parameters as previously described, crystallinity may be maintained at about 50 Å or less, and may be maintained at about 40 Å or less, about 30 Å or less, about 20 Å or less, about 15 Å or less, about 10 Å or less, about 7 Å or less, about 5 Å or less, about 3 Å or less, or less, but an increase in crystallinity of about 2 Å or more may provide improved etch selectivity.

[0077]

[0086] However, increasing the hydrogen content in the plasma may also increase the incorporation of hydrogen into the film. This may affect the film stress as previously discussed, as well as other film properties. For example, hardmask films are characterized by extinction coefficients for different wavelengths of light, which may affect the lithography process. Amorphous silicon materials are characterized by an extinction coefficient of about 0.2 for certain parameters, which may allow lithography at film thicknesses up to about 800 nm based on lower reflectivity, but which may affect visibility through the mask. Silicon and boron films are characterized by increased extinction coefficients for similar parameters, but the extinction coefficient may at least partially decrease with increasing hydrogen incorporation. For example, with increasing boron incorporation, the extinction coefficient may increase to about 0.3 or more, about 0.35 or more, about 0.4 or more, about 0.45 or more, or even more.

[0078]

[0087] The effect of the higher extinction coefficient of light may be that lithography becomes a challenge and additional processing may be required. For example, these increased extinction coefficients may limit the lithography field of view to film thicknesses of about 400 nm or less, about 300 nm or less, or less. However, by increasing the incorporation of hydrogen, and using increased plasma density, the extinction coefficient may be reduced to about 0.35 or less, to about 0.33 or less, to about 0.30 or less, to about 0.28 or less, to about 0.25 or less, or less. This may allow lithography to be extended to thicknesses of about 400 nm or more, about 450 nm or more, about 500 nm or more, or more, without performing additional alignment key opening operations. By increasing the temperature and plasma properties, film structures may be formed that improve properties such as extinction coefficient and etch selectivity, even with increased incorporation of hydrogen. Hydrogen incorporation may also be increased by processing at lower temperatures, such as below 400° C. or below about 350° C., but differences in film properties of such films produced may cause further hydrogen outgassing in subsequent processing, as discussed above. By performing the process at higher temperatures, the increased hydrogen incorporation films formed as described above may improve thermal stability. In addition, deposition according to embodiments of the present technique may reduce roughness of silicon and boron-containing films, improving the effectiveness of the hard mask. During the subsequent etching in optional step 630, as will be further described below, the etch critical dimensions may remain more uniform with the present technique than if the present technique were not performed. Reducing the surface roughness may result in improved etching and structure development.

[0079]

[0088] Once the silicon and boron material is formed above the substrate, one or more additional steps may be performed to pattern the material. For example, an etching process may be performed to form one or more features through the silicon and boron-containing material. FIG. 7 illustrates exemplary steps of an etching method 700 that may be included in an integrated method according to some embodiments of the present technique. The method may be performed in a variety of processing chambers, including the processing chamber 200 described above. The method 700 may include several optional steps. These steps may or may not be specifically associated with some embodiments of the method according to the present technique. Furthermore, any aspect of the method 700 may be considered optional within a broader integrated method in which any number of aspects of the method 700 may be incorporated. For example, many of the steps are described to provide a broader scope of structure formation, but may be performed by alternative methodologies that are not critical to the present technique or will be readily understood.

[0080]

[0089] Method 700 may include additional steps prior to the initiation of the recited steps. For example, additional processing steps may include forming structures on a semiconductor substrate, which may include boron and silicon-containing materials, which may include both the formation and removal of materials. The prior processing steps may be performed in the chamber in which method 700 may be performed, or processing may be performed in one or more other processing chambers prior to providing a substrate to a semiconductor processing chamber in which method 700 may be performed. Nevertheless, method 700 may optionally include providing a semiconductor substrate to a processing region of a semiconductor processing chamber, such as processing chamber 200 described above, or other chambers that may include components as described above. The substrate may be deposited on a substrate support, which may be a chuck, such as electrostatic chuck 222, and which is present in a processing region of a chamber, such as processing region 201 described above.

[0081]

[0090] The substrate may be any number of materials on which materials may be deposited as described above, including boron and silicon-containing materials, such as may be deposited by one or more steps of method 600 described above. In some embodiments, one or more additional steps may be performed before the start of method 700. For example, additional masking material may be deposited or formed over the boron and silicon-containing material to initiate pattern transfer. For example, an oxide or other mask layer may be formed over the boron and silicon-containing material, as described above. Photolithography or other patterning may be performed to generate a pattern through the mask down to the level of the boron and silicon-containing material.

[0082]

[0091] Method 700 may include one or more steps to etch through boron and silicon-containing materials. A bromine-containing precursor may be delivered to the processing region in step 705. A plasma may be formed with the precursor in step 710, and the plasma effluent may etch through the boron and silicon-containing material in step 715. The bromine precursor may be any bromine-containing material, and in some embodiments may be or include hydrogen bromide. The radical bromine-based material may interact to provide a clean and straight etch profile through the boron and silicon-containing material. In addition, the bromine radicals may maintain a flat etch front profile in the material. However, the etch rate may be relatively slower than other etchant precursors. As a result, in some embodiments, method 700 may include additional steps utilizing one or more additional precursors. For example, after etching a first amount of material with a bromine-containing precursor, a second etching process may be performed.

[0083]

[0092] For example, after an etch utilizing a certain amount of bromine, the chamber may be purged or the flow of bromine may be stopped. In step 720, a chlorine-containing precursor may be provided to the processing region, such as diatomic chlorine or any other chlorine-containing precursor previously described. In step 725, a plasma may be formed from the precursor, and in step 730, a second etch may be performed using a radical chlorine species. Radical chlorine may etch faster than bromine, but chlorine may create a pinched taper at the etch front, which may affect the critical dimension of the overall material. This method or steps may be repeated to alternate between two etching processes, which may be characterized by a higher etch rate based on the chlorine etch step, while maintaining a flatter etch front based on the bromine etch step. The process may be looped any number of times, depending on the thickness of the boron and silicon-containing materials, and may be looped about 2 times or more, about 10 times or more, about 25 times or more, about 50 times or more, about 100 times or more, about 200 times or more, or more. A greater number of loops can create a cleaner pattern through the material, but the greater the number of loops, the longer it may take to perform the method. In some embodiments, the etching method may begin and end with the bromine portion of the etching process. This may ensure that the critical dimensions of the bottom features are better maintained.

[0084]

[0093] In some embodiments, by performing the loop process as described, the critical dimensions of the pattern, such as apertures, may be maintained more uniformly both from a top-down perspective and across the substrate. For example, in some embodiments, the critical dimensions at the top of the feature or at the bottom of the feature may be maintained across the substrate between the center and edge regions, and the diameter of the aperture formed at the edge region may be at least about 80% of the diameter of the aperture formed at the center of the substrate, at least about 85% of the diameter of the aperture formed at the center of the substrate, at least about 90% of the diameter of the aperture formed at the center of the substrate, at least about 95% of the diameter of the aperture formed at the center of the substrate, at least about 98% of the diameter of the aperture formed at the center of the substrate, or more.

[0085]

[0094] A loop process may necessarily increase the etching time of the process by adding time between precursor switching steps. Thus, some embodiments of the present technology may also utilize a continuous process using a single etchant mixture. FIG. 8 illustrates exemplary steps of an etching method 800 that may be included in an integrated method according to some embodiments of the present technology. The method may be performed in a variety of processing chambers, including the processing chamber 200 described above. The method 800 may include several optional steps. These steps may or may not be specifically associated with some embodiments of the method according to the present technology. Furthermore, any aspect of the method 800 may be considered optional within a broader integrated method in which any number of aspects of the method 800 may be incorporated. For example, many of the steps are described to provide a broader scope of structure formation, but may be performed by alternative methodologies that are not critical to the present technology or will be readily understood.

[0086]

[0095] Method 800 may include additional steps prior to the initiation of the recited steps. For example, similar to those described above for method 700, additional processing steps may include forming structures on the semiconductor substrate including boron and silicon-containing materials, which may include both material formation and removal. The prior processing steps may be performed in the chamber in which method 800 may be performed, or processing may be performed in one or more other processing chambers prior to providing the substrate to the semiconductor processing chamber in which method 800 may be performed. Nevertheless, method 800 may optionally include providing a semiconductor substrate to a processing region of a semiconductor processing chamber, such as processing chamber 200 described above, or other chambers that may include components as described above. The substrate may be a chuck, such as electrostatic chuck 222, and may be deposited on a substrate support present in a processing region of a chamber, such as processing region 201 described above. The substrate may include any of the materials as described above, including boron and silicon-containing materials, and a previously patterned overlying mask structure.

[0087]

[0096] The method 800 may include providing an etchant mixture in a processing region of the processing chamber in step 805. The etchant mixture may include one or more precursors that may function together to protect sidewall features during an etching process. In some embodiments, the etchant mixture may include a chlorine-containing precursor and an oxygen-containing precursor. The chlorine-containing precursor may include diatomic chlorine, as well as any other chlorine-containing precursors described above. The oxygen-containing precursors used in any process as described throughout the present technique may include O2, N2O, NO2, O3, H2O, as well as any other oxygen-containing precursor. In some embodiments, the etchant mixture may also include a fluorine-containing precursor. This precursor may be or include any precursor described elsewhere in this disclosure.

[0088]

[0097] In step 810, a plasma may be formed of the etchant mixture, as well as any carrier or inert precursors provided as well. The plasma may be formed at a first plasma power. A bias power may be applied in optional step 815 during application of the plasma power. A plasma may be formed from a plasma source as described above and at a first plasma power. This may dissociate the etchant precursors to generate plasma effluents. The bias power may draw the plasma effluents into the structure to generate an anisotropic etch profile and maintain the pattern through the structure. The etching may be performed for a period of time that may correspond to a duty cycle of the bias power, as described further below. At the end of the first period of time, in step 820, the first plasma power may be increased to a second plasma power. The precursors may be continuously flowed while the plasma power is being changed. In some embodiments, the bias power may be stopped during the second period of time in optional step 825. Again, the second period may be the remaining portion of the duty cycle applied to the bias power, and the first and second periods may correspond to the periods of the pulse frequency applied to the plasma power. Over the course of time and successive periods of the process, the plasma effluent contacts the boron and silicon containing material, which is etched in step 830. This may transfer a pattern into the material, as previously described.

[0089]

[0098] As explained above, the applied bias may draw the etchant to the substrate, resulting in a more anisotropic etching process. Due to the reactivity of the etchant material, the plasma effluent may remove other exposed materials, such as oxides on the sidewalls of the overlying material. This may increase the critical dimensions of the features and reduce control of the process uniformity. Incorporation of oxygen-containing precursors may be used to promote redeposition of oxide materials removed during the process to passivate exposed surfaces and maintain the critical dimensions. However, the etchant may be more reactive than the passivation process and continue to erode the critical dimensions. Therefore, the present etching process may be performed with level-to-level plasma generation as described above to promote passivation while controlling the etching process.

[0090]

[0099] When the bias power is turned off, the etch front may slow down as the chlorine etching continues. In addition, increasing the source plasma power may increase the plasma density, generate more oxygen radicals, and increase passivation. Similarly, turning off the bias power may cause isotropic interaction with the sidewalls of the structure to be protected, which may result in additional passivation. By controlling the delivery rate of the constituent precursors, the process may be performed continuously, both etching and passivating during the constituent period of the pulse frequency. In some embodiments, the pulse frequency applied to one or both power sources is at a frequency of about 100 Hz or more, and may be about 250 Hz or more, about 500 Hz or more, about 1,000 Hz or more, about 2,000 Hz or more, or more.

[0091]

[0100] During the pulse frequency, the source power may be maintained continuously while a duty cycle may be applied to the bias power to control the etching. For example, the bias power may be switched off according to the duty cycle while increasing the first plasma power after a set time for the duty cycle of the bias power. As one non-limiting example, the source power may be applied at the first plasma power at time T0 and the bias power may be applied at the first power at time T0. This may increase the etching until the duty cycle switches the bias power off at time T1. At the same time that the bias power is switched off, the first plasma power may be switched from the first power to the second power at time T1. This may occur until time T2, which corresponds to the next T0 of the next period of the pulse at any of the frequencies, as described above. Thus, the time between time T0 and time T2 may be one period at the pulse frequency, and time T1 may be the duty cycle application at the corresponding pulse frequency.

[0092]

[0101] The bias power may be applied at any power, and may be applied at about 2,000 W or less, about 1,500 W or less, about 1,400 W or less, about 1,300 W or less, about 1,200 W or less, about 1,100 W or less, about 1,000 W or less, about 900 W or less, about 800 W or less, or less. The duty cycle is about 50% or less, and in some embodiments may be about 45% or less, about 40% or less, about 35% or less, about 30% or less, about 25% or less, about 20% or less, about 15% or less, or less. The plasma power of the plasma source may be different between the first time period and the second time period. For example, in a first period, the plasma source power is about 1,000 W or more, and can be about 1,100 W or more, about 1,200 W or more, about 1,300 W or more, about 1,400 W or more, about 1,500 W or more, or more. In some embodiments, the source power and bias power during the first period can be the same. In a second period, the source power can be increased to about 2,000 W or more, and a second power that can be about 2,200 W or more, about 2,400 W or more, about 2,600 W or more, about 2,800 W or more, about 3,000 W or more, or more. The process can then be run continuously until the etch is complete.

[0093]

[0102] In some embodiments, the substrate is maintained at a temperature of about 200° C. or higher, and may be maintained at temperatures of about 225° C. or higher, about 250° C. or higher, about 275° C. or higher, about 300° C. or higher, or higher during the method. By maintaining a higher temperature, the volatile by-products may be more easily removed as volatiles and more easily become gases. Although the critical dimension may be influenced by the particular structure being formed, in some embodiments, the apertures formed may be characterized by a diameter of about 50 nm or less, and may be characterized by a diameter of 40 nm or less, about 30 nm or less, about 20 nm or less, about 10 nm or less, or less. Due to the rate at which etching may be performed, in some embodiments, the by-products produced may increase. By including a fluorine-containing precursor, mask clogging may be reduced, as the additional etchant further decomposes the by-product materials and they flow more easily from the pattern being produced. Additionally, the pressure within the processing chamber is maintained at about 500 mTorr or less, and may be maintained at about 100 mTorr or less, about 50 mTorr or less, about 20 mTorr or less, or less.

[0094]

[0103] The etchant precursors may be provided in a ratio in some embodiments of the present technology. For example, the mixture may include a first amount of a fluorine-containing precursor, a second amount of an oxygen-containing precursor, and a third amount of a chlorine-containing precursor. In some embodiments, the oxygen-containing precursor is provided at a flow rate of about 2 times or more than the flow rate of the fluorine-containing precursor, and may be about 3 times or more than the flow rate, about 4 times or more than the flow rate, about 5 times or more than the flow rate, about 6 times or more than the flow rate, about 7 times or more than the flow rate, about 8 times or more than the flow rate, about 9 times or more than the flow rate, about 10 times or more than the flow rate, or more than that. For example, in some embodiments, the oxygen-containing precursor is flowed at a rate of about 25 sccm or more, and may be flowed at a rate of about 50 sccm or more, about 75 sccm or more, about 100 sccm or more, or more than that. The chlorine-containing precursor is provided at a rate that is about 2 times or more than the rate of the oxygen-containing precursor, and can be about 4 times or more, about 6 times or more, about 8 times or more, about 10 times or more, about 12 times or more, about 14 times or more, about 16 times or more, about 20 times or more, or more. For example, in some embodiments, the oxygen-containing precursor is flowed at a rate of about 250 sccm or more, about 500 sccm or more, about 750 sccm or more, about 1,000 sccm or more, or more.

[0095]

[0104] After the pattern transfer is completed, the boron and silicon-containing material may be removed from the substrate. FIG. 9 illustrates exemplary steps of a removal method 900 that may be included in an integrated method according to some embodiments of the present technology. The method may be performed in a variety of processing chambers, including the processing chamber 300 described above. The method 900 may include several optional steps. These steps may or may not be specifically associated with some embodiments of the method according to the present technology. Furthermore, any aspect of the method 900 may be considered optional within a broader integrated method in which any number of aspects of the method 900 may be incorporated. For example, many of the steps are described to provide a broader scope of structure formation, but may be performed by alternative methodologies that are not critical to the present technology or will be readily understood. The method 900 may describe the steps shown generally in FIGS. 10A-10B. These figures will be described in conjunction with the steps of the method 900. It should be understood that only partial schematic views are shown in the figures, and the substrate may include any number of additional materials and features having various properties and aspects as shown in the figures.

[0096]

[0105] Method 900 may include additional steps prior to the initiation of the recited steps. For example, additional processing steps may include additional removal steps or processing through boron and silicon-containing materials, and may include both formation and removal of materials. The prior processing steps may be performed in the chamber in which method 900 may be performed, or processing may be performed in one or more other processing chambers prior to providing a substrate to a semiconductor processing chamber in which method 900 may be performed. Nevertheless, method 900 may optionally include providing a semiconductor substrate to a processing region of a semiconductor processing chamber, such as processing chamber 300 described above, or other chambers that may include components as described above. The substrate may be deposited on a substrate support, which may be a chuck, such as pedestal 303, and may be present in processing region 304 of the chamber described above.

[0097]

[0106] The substrate on which several steps have been performed becomes a substrate 1005 or structure 1000, which may represent one or more substructures. It should be understood that structure 1000 may not represent all layers, materials, or structures that may be formed under the material shown. For example, substrate 1005 represents a material on which one or more features may be formed and may represent additional masking or structural layers. Substrate 1005 may represent a boron and silicon-containing material 1006 that is removed after patterning. FIG. 10A represents a first structure that may be provided and FIG. 10B represents a second structure that may be processed. In a structure as illustrated in FIG. 10A, patterning may expose contact structure 1008a. The trench, opening, or feature may be filled with a protective material 1010 as illustrated. In a structure as illustrated in FIG. 10B, patterning may keep contact structure 1008b exposed during the removal step.

[0098]

[0107] In step 905, one or more etchant precursors may be delivered to the processing chamber, such as in the remote plasma region 327, as previously described. A plasma may be formed in this region in step 910, which may be flowed into the processing region to contact the boron and silicon containing material in step 915 and remove it from the otherwise exposed structures. As shown, one or more materials may be exposed during the etching process, but etching of these exposed materials may be minimized. However, in some embodiments, the boron and silicon containing materials may be formed in a manner that extends the exposure to the material. For example, in some embodiments as shown, edge regions that may not be patterned may be characterized by a greater thickness of mask material than the center region. As a result, the removal process may still remove material in the edge regions while the center patterned material may be fully exposed. Thus, in some embodiments, the removal process may be adjusted to ensure that the etch selectivity to each exposed material is high enough to limit damage to the structures, as well as to increase the etch rate to limit the time required to remove material from the substrate.

[0099]

[0108] The precursors used in the present technology may include fluorine-containing precursors as well as additional precursors as described below. An exemplary fluorine-containing precursor is nitrogen trifluoride, which may be flowed into a remote plasma region. The remote plasma region may be separated from the processing region but fluidly connected to the processing region. Other sources of fluorine may be used along with or instead of nitrogen trifluoride. In general, a fluorine-containing precursor is flowed into the remote plasma region, and the fluorine-containing precursor may include at least one precursor selected from the group consisting of atomic fluorine, diatomic fluorine, nitrogen trifluoride, carbon tetrafluoride, hydrogen fluoride, xenon difluoride, fluorinated organic molecules or hydrocarbons such as fluoromethane or difluoromethane, and various other fluorine-containing precursors used or useful in semiconductor processing.

[0100]

[0109] In some embodiments of the present technology, additional precursors may also be provided along with the fluorine-containing precursor. For example, a hydrogen-containing precursor may be provided, and one or more other precursors may be provided, such as argon, nitrogen, helium, or other precursors. Hydrogen is easily ionizable, which in some embodiments may facilitate processing and increase ion density in the processing region to increase etchant production. The hydrogen-containing precursor may be or include hydrogen, a hydrocarbon, or any hydrogen-containing precursor.

[0101]

[0110] Pressure and temperature can affect the process and etch rate. The pressure in the processing chamber is maintained at about 20 mTorr or less, and can be maintained at about 10 Torr or less, about 5 Torr or less, about 1 Torr or less, or less. The temperature of the substrate support is maintained at a temperature of about 100° C. or more, which in some embodiments can increase the removal rate, and the temperature can be maintained at about 150° C. or more, about 175° C. or more, about 200° C. or more, about 225° C. or more, about 250° C. or more, or more. Plasma power can also affect the etch rate. In some embodiments, the removal step is performed with a capacitively coupled plasma power of about 2.0 kW or more, and can be performed with a plasma power of about 2.5 kW or more, about 3.0 kW or more, about 3.5 kW or more, about 4.0 kW or more, or more.

[0102]

[0111] Materials that may be exposed during removal may include several materials, including metals for contact landing, such as tungsten. The materials may include several dielectric materials, including silicon oxide, silicon nitride, and silicon carbonitride. In addition, in some embodiments, such as illustrated in FIG. 10A, the material provided to the trench, hole, or feature may be or include, for example, titanium nitride, or some other transition metal nitride. To limit the etching of the transition metal nitride, an additional precursor, such as a nitrogen-containing precursor, may be provided with the etchant precursor. The nitrogen-containing precursor may include ammonia, or any other nitrogen-containing material, to suppress the etching of the transition metal nitride while performing the removal of boron and silicon-containing materials with other etchant materials.

[0103]

[0112] By carrying out the process as described above, the etch selectivity of boron and boron and silicon materials to silicon oxide, silicon nitride, silicon carbonitride, and tungsten or other metals can be maintained at about 100:1 or more, and can produce selectivities of about 200:1 or more, about 400:1 or more, about 600:1 or more, about 800:1 or more, about 1,000:1 or more, or higher. In some embodiments, one or more of these materials may remain substantially unetched during the removal of boron or boron and silicon-containing materials. In addition, the etch selectivity of boron and boron and silicon materials to titanium nitride can be maintained at about 20:1 or more, and can produce selectivities of about 40:1 or more, about 80:1 or more, about 100:1 or more, about 150:1 or more, about 200:1 or more, or higher.

[0104]

[0113] Generating the plasma effluent in a remote plasma region may allow for filtering of ions from the plasma effluent while it is flowing through the electrodes as described above. This may increase the etch rate by reducing the bombardment component of the etch. Additionally, utilizing a remote plasma region in the chamber instead of a remote plasma source unit external to the chamber may limit recombination and complete ionization of the constituent etchant materials. High plasma power etching may allow removal of boron and silicon containing materials at etch rates of about 30 nm / min or greater, and may provide etch rates of about 35 nm / min or greater, about 40 nm / min or greater, about 45 nm / min or greater, about 50 nm / min or greater, about 55 nm / min or greater, about 60 nm / min or greater, about 65 nm / min or greater, about 70 nm / min or greater, about 75 nm / min or greater, about 80 nm / min or greater, or higher. This may limit interaction with other exposed materials and reduce the overall removal time during processing, improving throughput. By implementing processes according to some embodiments of the present technique, process integration may reduce throughput and produce higher quality devices than prior art techniques.

[0105]

[0114] In the preceding description, for purposes of explanation, numerous details have been set forth in order to provide an understanding of various embodiments of the present technology. However, it will be apparent to one of ordinary skill in the art that certain embodiments may be practiced without some of these details, or with additional details.

[0106]

[0115] Although several embodiments have been disclosed, those skilled in the art will recognize that various modifications, alternative structures, and equivalents can be used without departing from the spirit of the embodiments. Additionally, some well-known processes and elements have not been described to avoid unnecessarily obscuring the present technology. Thus, the above description should not be construed as limiting the scope of the present technology. Furthermore, although a method or process may be described sequentially or stepwise, it should be understood that the steps may be performed simultaneously or in a different order than that listed.

[0107]

[0116] Where a range of values ​​is given, each intervening value between the upper and lower limit of that range is specifically disclosed to the smallest unit of the lower limit, unless the context clearly indicates otherwise. Any smaller ranges between any stated or unstated intervening value in a stated range, as well as any other stated or intervening value in that stated range, are also included. The upper and lower limits of such narrower ranges may be individually included or excluded from the range. Each range in which either or both limits are included in the narrower range, or neither is included in the narrower range, is also encompassed by this technology and covers any specifically excluded limit in the stated range. When a stated range includes one or both of the limits, ranges excluding either or both of those included limits are also included.

[0108]

[0117] As used in the specification and claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. Thus, for example, reference to "a precursor" includes a plurality of such precursors, reference to "the layer" includes reference to one or more layers and equivalents known to those skilled in the art, and so forth.

[0109]

[0118] Additionally, the terms "comprise(s)", "comprising", "contain(s)", "containing", "include(s)", and "including", when used in this specification and claims, are intended to specify the presence of stated features, integers, components, or steps, but do not exclude the presence or addition of one or more other features, integers, components, steps, operations, or groups.

Claims

1. depositing a boron-containing material onto a substrate disposed in a processing region of a semiconductor processing chamber; Etching portions of the boron-containing material with a chlorine-containing precursor to form one or more features in the substrate; removing remaining portions of the boron-containing material from the substrate using a fluorine-containing precursor; A processing method comprising:

2. The boron-containing material is a silicon and boron-containing material, and depositing the boron-containing material comprises: delivering a silicon-containing precursor and a boron-containing precursor to a processing region of a semiconductor processing chamber; providing a hydrogen-containing precursor along with the silicon-containing precursor and the boron-containing precursor, wherein a flow ratio of the hydrogen-containing precursor to either the silicon-containing precursor or the boron-containing precursor is about 2:1 or greater; forming a plasma of all precursors in the processing region of the semiconductor processing chamber; The method of claim 1 , comprising:

3. 3. The process of claim 2, wherein the silicon-containing precursor comprises silane and the boron-containing precursor comprises diborane.

4. 10. The process of claim 1, wherein said removing occurs at a rate of about 35 nm / min or greater and said boron-containing material is characterized by a film thickness of about 20 nm or greater.

5. 10. The method of claim 1, wherein a substrate temperature is maintained at or above about 400° C. during depositing the boron-containing material on the substrate, and wherein the substrate temperature is maintained at or above about 200° C. during the removing.

6. The etching step comprises: forming a plasma of a bromine-containing precursor; contacting the boron-containing material with a plasma effluent of the bromine-containing precursor; stopping the supply of the bromine-containing precursor; forming a plasma of a chlorine-containing precursor; contacting said boron-containing material with plasma effluent of said chlorine-containing precursor; The method of claim 1 , comprising:

7. The etching step comprises: forming a plasma of an etchant mixture comprising the chlorine-containing precursor and the oxygen-containing precursor; contacting the boron-containing material with plasma effluent of the etchant mixture while forming the plasma at a first plasma power; increasing the first plasma power to a second plasma power after the first period of time; The method of claim 1 , comprising:

8. The etching step comprises: transferring a pattern through said boron-containing material from an overlying mask material; The method of claim 7, comprising:

9. The etching step comprises: applying a bias power during the first period of time; terminating the bias power after the first period of time. The method of claim 7, comprising:

10. The removing comprises: forming a remote plasma of an etchant mixture comprising the fluorine-containing precursor and a hydrogen-containing precursor; contacting the boron-containing material with a plasma effluent of the etchant mixture; removing the boron-containing material with a selectivity of about 20:1 or greater relative to other exposed materials on the substrate; The method of claim 1 , comprising:

11. 11. The method of claim 10, wherein the remote plasma is formed at a plasma power of about 2.0 kW or greater.

12. forming a plasma of an etchant mixture comprising a chlorine-containing precursor and an oxygen-containing precursor; contacting a silicon and boron containing material on a substrate disposed in a processing region of a semiconductor processing chamber with plasma effluents of the etchant mixture while forming the plasma at a first plasma power; increasing the first plasma power to a second plasma power after a first period of time to form one or more features in the substrate; An etching method comprising:

13. 13. The etching method of claim 12, wherein the silicon and boron containing material is characterized by a boron concentration of about 40 atomic percent or greater.

14. The etchant mixture comprises: Fluorine-Containing Precursors 13. The etching method of claim 12, further comprising: a flow ratio of the fluorine-containing precursor to the oxygen-containing precursor to the chlorine-containing precursor is about 1:5:10 or greater.

15. applying a bias power during the first period of time; terminating the bias power after the first period of time. The etching method of claim 12 further comprising:

16. 16. The etching method of claim 15, wherein the plasma is formed at a pulse frequency of about 500 Hz or greater.

17. 17. The etching method of claim 16, wherein the duty cycle of the bias power during plasma formation is about 40% or less.

18. forming a remote plasma of an etchant mixture comprising a fluorine-containing precursor and a hydrogen-containing precursor; contacting a silicon- and boron-containing material on a substrate disposed in a processing region of a semiconductor processing chamber with plasma effluents of the etchant mixture, the silicon- and boron-containing material defining one or more features in the substrate; removing said silicon and boron containing material at a rate of about 35 nm / min or greater; The removal method includes:

19. 20. The method of claim 18, wherein the temperature of the substrate during the removal is maintained at or above about 200° C. and the remote plasma is formed with a plasma power of at or above about 2.0 kW.

20. 20. The method of claim 18, wherein the substrate further comprises exposed regions of titanium nitride and the etchant mixture further comprises ammonia.

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