Direct-bonded stack structure for improved reliability and yield in microelectronics

Abstract

To provide a direct bond stack structure that improves reliability and increases yield in microelectronics.SOLUTION: A memory module 400 reduces warpage stress between a thicker top die 106 and a direct bonded die 102 below. An etched surface on the top die relieves warpage stress. A vertical stack 402 includes a compliant layer 404 between the dies. Another stack configuration replaces the top die with a layer of molding material to avoid warpage stress. An array of cavities on the bonding surface relieves stress. One or more stress balancing layers on the sides of the top die or between other dies reduce or eliminate warpage. Rounded edges can prevent stress and compressive forces from destructively transmitting through the die and substrate layers. These means can be applied together or in various combinations within a single package.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] (CROSS REFERENCE TO RELATED APPLICATIONS) This application claims the benefit of priority to U.S. Application No. 16 / 911,360, filed June 24, 2020, and the benefit of U.S. Provisional Application No. 62 / 866,965, filed June 26, 2019, to Uzoh et al., the entire contents of which are incorporated herein by reference.

[0002] (Technical field) The present disclosure relates to direct bond stack structures in microelectronics. [Background technology]

[0003] The stack of integrated circuit microchips ("die") joined together during the fabrication of traditional 3DIC microelectronic packages such as high bandwidth memory modules (HBM, HBM2, HBM3) are vulnerable to certain types of defects due to their vertical stacking, and these defects affect the overall manufacturing yield. For example, for HBM2 modules, the memory specifications may dictate some physical dimensions for the assembled modules, such as a height requirement of 700μm.

[0004] As shown in FIG. 1, the high bandwidth of an exemplary conventional HBM2 memory module 100 is achieved by bonding multiple memory dies 102 into a vertical stack 103 on a substrate 104. Each individual die 102 can have a particular vertical thickness, such as 55 μm. At the top of the vertical stack, an additional top die 106 is often made thicker than the other dies 102 to reach a height specification of 700 μm (or other). For example, the top die 106 may be 90-400 μm thick, while each die 102 below it is 55 μm thick. In some cases, this top die 106 may be a dummy or spacer die. The module 100 may be completed by filling it with side filler 108, underfill, or molding compound. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] U.S. Patent Application No. 16 / 911,360 [Patent Document 2] U.S. Provisional Patent Application No. 62 / 866965 Summary of the Invention [Problem to be solved by the invention]

[0006] A thicker top die 106 can cause structural problems for the dies 102 stacked underneath it during fabrication, reducing the average reliability and overall manufacturing yield. For various reasons, the thin dies 102 forming the vertical memory stack 103 underneath the top die 106 can exhibit negative warpage, resulting in a concave side down condition 110. A thicker top die 106 will often have a positive warpage, resulting in a concave side up condition 112. If a concave side up top die 106 is pressed against a stack of concave side down dies 102 underneath it during bonding to the vertical stack 103, a certain number of destructive defects can occur, such as cracks 114 in the directly bonded dies 102, delamination of the bond between the dies 116, or cracks and chips 118 in the substrate 104 underlying the vertical stack at the points of increased pressure, reducing the overall yield. Cracks 114 in the thin die 102 can occur near the edges of the die 102 when there are small differences in footprint size between the dies 102, creating small overhangs where compression forces can be concentrated. [Means for solving the problem]

[0007] Provide a direct bonded stack structure for improved reliability and yield in microelectronics. Provide structural features and stack configurations for memory modules and 3DIC to reduce both critical and minor defects in vertically stacked dies. Exemplary processes reduce warpage stress between a thicker top die and a directly bonded die below. In one approach, an etched surface on the top die can reduce warpage stress. In another approach, an exemplary stack can include a compliant layer between the top die and the die below. Another exemplary stack configuration replaces the top die with a layer of molding material to avoid warpage stress. An array of cavities on the bonding surface of the top die can also reduce stress. Alternatively, one or more stress balancing layers can be provided on the top or back surface of the top die or between the thin dies to reduce the stress and warpage of the stack. Rounded edges can also prevent stress and compressive forces from destructively transmitting through the die and substrate layers. These various approaches and structures are not mutually exclusive and can be used together or in various combinations within the package.

[0008] This Summary is not intended to identify key or essential features of the claimed subject matter, nor is it intended to be used as an aid in limiting the scope of the claimed subject matter. [Brief description of the drawings]

[0009] [Figure 1] FIG. 1 is a diagram of a prior art vertical die stack in which various stresses and die warpage introduce various structural problems, including bond delamination, cracking, and failure, resulting in unreliability and reduced manufacturing yields. [Diagram 2] FIG. 1 illustrates an example module with grinding / etching features to reduce warpage stress in a vertical stack of dies. [Diagram 3] 3 is a flow diagram of an exemplary process for making the structure of FIG. 2. [Figure 4]FIG. 1 illustrates an example module with a vertical die stack including compliant layer features to reduce warpage stress in the vertical stack. [Diagram 5] 5 is a flow diagram of an example process for fabricating the example module of FIG. 4. [Figure 6] FIG. 1 illustrates an example module with a die stack including molding features to reduce warping stresses in the vertical stack. [Figure 7] 7 is a flow diagram of an example process for fabricating the example module of FIG. 6. [Figure 8] FIG. 1 illustrates an example module with a vertical die stack including relief cavity features to reduce warpage stress in the vertical stack. [Figure 9] 9 is a flow diagram of an example process for fabricating the example module of FIG. 8. [Figure 10] FIG. 1 illustrates an example module with a die stack including a stress balancing layer feature to reduce warpage stress in the vertical stack. [Figure 11] 11 is a flow diagram of an example process for fabricating the example module of FIG. 10. [Figure 12] FIG. 1 illustrates an example module of a vertically stacked die with at least some rounded corners or edges to prevent stress concentrations at the corners. [Figure 13] 4 is a flow diagram of an exemplary process for preventing damaging force concentrations in fabricating a vertical stack of dies. [Figure 14] FIG. 1 illustrates an exemplary module in which multiple thin dies take the place of a larger die to reduce stress warpage of the die stack. [Figure 15] FIG. 13 illustrates an exemplary structure including side supports to eliminate warpage issues and improve yield in the fabrication of modules with vertical die stacks. [Figure 16] FIG. 13 is a diagram of an example configuration without the top die spacer and with side support structures and moldings to reduce internal stresses. [Figure 17] 1A-1C are diagrams of example structures formed in a process that uses temperature differentials to reduce warpage stresses during fabrication of a vertical stack of dies. [Figure 18] FIG. 1 illustrates an exemplary structure and associated process for fabricating an exemplary module of stacked dies by combining multiple prefabricated die stacks while reducing warpage due to internal stresses. [Figure 19] FIG. 1 illustrates an example structure with features to reduce warping stress in a die stack, including rounded die corners supported by encapsulant fillets or wedges. [Figure 20] FIG. 1 illustrates an exemplary structure for assembling larger modules having multiple stacked dies without introducing problems due to stress warping. [Figure 21] FIG. 1 illustrates an example structure including a thin layer of dielectric material and features for reducing internal stress. [Figure 22] FIG. 13 is another view of a possible example structure including features for reducing internal stress. [Figure 23] FIG. 1 illustrates an exemplary structure including one or more direct bonded die stacks incorporating stress relief, a processor, and an optional heat sink. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Overview This disclosure describes a direct bond stack structure for improved reliability and yield in microelectronics. Structural features and stack configurations for memory modules, stacked passives, interposers, and 3DICs are provided to reduce both hard and soft defects in vertically stacked dies. Exemplary processes and structures reduce stresses, such as warpage stresses, between a thicker top die and a directly bonded die below it, or between a thinner top die and a thicker directly bonded die below it.

[0011] In one embodiment, a ground or etched surface on the top die can relieve stresses, such as warpage stresses, of the die stack. In the same or another embodiment, the exemplary stack can include a compliant layer between the top die and the die below it to relieve warpage stresses. Another exemplary stack configuration replaces the top die with a layer of molding material to avoid warpage stresses. In another embodiment, an arrangement of cavities on the mating surface or elsewhere of the top die can relieve stresses. Furthermore, a stress balancing layer can be provided on the top or back surface of the top die, or one or more stress balancing layers can be interposed between other dies in the die stack to relieve warpage stresses of the stack. In another exemplary approach and related structure, right-angle corners of some dies in the stack are rounded to prevent concentrated compressive forces on the square corners of the die during stack fabrication from being transferred to the relatively fragile die or substrate layers above and below, causing them to crack and chip.

[0012] Exemplary Processes and Systems Exemplary processes fabricate stack structures with structural features and configurations that reduce critical and minor defects that can occur in vertical stacks of directly bonded die. Memory modules are described below as representative examples, including, but not limited to, 3DS®, HMC Hybrid Memory Cube, HBM, HBM2, and HBM3, although the described techniques may be applied to any microelectronic package with vertically stacked die, particularly directly bonded die, and the structures and approaches described herein are not limited to memory modules.

[0013] It should be noted that the embodiments described below may, in some cases, be combined into a single embodiment that includes features of each of the embodiments described below. The embodiments described below are not intended to be mutually exclusive and may be combined together where possible.

[0014] FIG. 2 illustrates an exemplary memory module 200 with a die stack 202 including features for mitigating warpage stress in the vertical stack 202. The top die 106 of the stack 202 has a surface that is treated by grinding 204 and then either wet or dry etching 206 to relieve the warpage 112 or internal stresses of the top die 106, in some cases reducing or eliminating the concavity 112 thereof. The etching 206 relieves the stress trapped in the grinding operation 204. This in turn helps to relieve stress-induced defects that may develop between the top die 106 and the die 102 below it. As described above, the substrate 104 can be an organic or inorganic structure such as a circuit board, packaging substrate, die, wafer, carrier, etc., and can be electrically coupled to the stack 202, including at least partially via direct bonding and / or hybrid bonding, eutectic bonding, etc.

[0015] Figure 3 illustrates an exemplary process 300 for making the structure 200 of Figure 2. In Figure 3, the operations of the exemplary process are shown in discrete blocks.

[0016] In block 302 , the exemplary process includes directly bonding dies 102 to form a portion of a vertical stack 202 .

[0017] At block 304 , a top die 106 is prepared for joining on top of the other dies 102 to form a vertical stack 202 .

[0018] In block 306, the backside of the top die 106 is ground.

[0019] In block 308, the backside of the top die 106 is then wet etched 206 or dry etched for stress relief.

[0020] In block 310, the top die 106 is then bonded to the bottom die 102 to produce a vertically stacked die 102&106 microelectronic package 200 with reduced internal stresses and improved reliability, thereby reducing warpage stresses between the top die 106 and the dies 102 in the vertical stack below the top die 106.

[0021] 4 illustrates an exemplary memory module 400 with a die stack 402 that includes features to mitigate warpage stress in the vertical stack 402. The vertical stack 402 is fabricated with a compliant layer 404 interposed between the top die 106 and the dies 102 that are directly bonded to one another below the top die 106. The top die can have different vertical and / or horizontal dimensions than at least one other die in the direct bonded die stack 400.

[0022] The compliant layer 404 is intended to mitigate uneven forces during bonding of the top die 106 to the vertical stack 402 and to counteract or eliminate ongoing unevenness in stress and warpage forces between the top die 106 and the die 102 below it. The thickness of the compliant material or compliant layer 404 can range from 0.5 to 55.0 μm, preferably 3.0 to 30.0 μm. The compliant layer 404 can be bonded or glued between the dies and can provide a single solution to warpage when the top die 106 is a dummy die to fill the headspace of the package 400. The compliant layer 404 can be bonded or glued between the dies and can provide a single solution to warpage when the top die 106 is a dummy die to fill the headspace of the package 400. The Young's modulus of the compliant layer 404 is preferably less than 4 GPa.

[0023] In some embodiments, such as stack 400, the width of the top die 106 is similar to the width of one of the bottom dies 102. In other embodiments, such as stack 400', the width of the top die 106' may be different from the width of the other dies in the vertical stack 400', e.g., wider than the bottom die 102.

[0024] Figure 5 shows an example process 500 for fabricating the example module 400 of Figure 4. The operations of the example process 500 are shown in individual blocks.

[0025] At block 502 , the exemplary process 500 includes directly bonding the dies 102 to form a portion of the vertical stack 402 .

[0026] At block 504 , a top die 106 is provided for bonding on top of the directly bonded die 102 .

[0027] In block 506 , a compliant layer 404 is applied, for example, to interpose between the top die 106 and the other dies 102 in the vertical stack 402 .

[0028] At block 508, the top die 106 is then bonded to the compliant layer 404. The compliant layer can be, for example, a thin film die attach adhesive or another compliant material, a printed or stenciled die attach material, or other adhesive. The microelectronic package 400 with the vertically stacked dies 102&106 and the compliant layer 404 provides reduced warpage stress between the top die 106 and the die 102 in the vertical stack 402, providing reduced internal stress and improved reliability. The compliant layer 404 can be a flowable material that hardens. The dispensed material flows and accommodates the warpage very well. In thin film die attach embodiments, flow is achieved at high temperatures, and the flowed material accommodates the height difference between the warped dies to reduce warpage. The width of the top die 106 can be similar or different to the width of the bottom die 102, as in FIG. 4.

[0029] FIG. 6 illustrates an exemplary memory module 600 with a die stack 602 including filler features to mitigate warpage stresses in the vertical stack 602. In this exemplary microelectronic package 600, a volume of molding compound 604, filler, underfill material, etc., takes the place of the top die 106, which is deleted in this embodiment. Since there is no warpage stress competition between the positive warpage of the non-existent top die and the dies 102 of the stack 602 that may have negative warpage, the actual dies 102 of the vertical stack 602 remain with a slight but acceptable negative warpage, and the microelectronic package 600 is filled with molding compound 604 to complete the microelectronic package 600. Residual negative warpage of the direct bonded dies 102 can also be addressed and mitigated using stress balancing layers, as described with respect to FIGS. 10-11. One or more stress balancing layers (not shown in FIG. 6) can be applied on or within the stack 602 to balance and offset the net warpage of the entire stack 602. That is, such a stress balancing layer may be aligned with each individual die 102 that is bonded into the stack 602 .

[0030] Each stress balancing layer is designed to counter the camber of the warped die or stack with its own opposite camber before the stress balancing layer and the warped die or stack are mated together, at which point the cambers cancel each other out, resulting in a flat stack 602 with zero net overall warpage. Also, in the microelectronic package 600, the lateral width of the molding material 604 on either side of the stacked dies 602 is less than the width of the die 102, preferably less than 10% of the width of the die 102. In some embodiments, the vertical thickness of the molding material abutting the top die 102 is less than the thickness of the die stack 602, preferably less than 50% of the vertical thickness of the die stack 602.

[0031] Figure 7 shows an example process 700 for fabricating the example module 600 of Figure 6. The operations of the example process 700 are shown in individual blocks.

[0032] At block 702 , the exemplary process 700 includes directly bonding the dies 102 to create a vertical stack 602 .

[0033] At block 704, molding material 604 is at least partially filled around the vertical stack 602 to replace the volume of the missing top die 106 and complete the physical outer dimensions of the memory module 600 to specification. The thickness of the molding material 604 at the top of the vertical stack 602 can be a multiple of the thickness of the individual dies 102 in the vertical stack 602. For example, the thickness of the molding material 604 can be three times the thickness of the dies 102 in the vertical stack 602. One or more stress balancing layers can be added anywhere in or around the stack 602.

[0034] FIG. 8 illustrates an exemplary memory module 800 with a die stack 802 including relief cavity features to mitigate warpage stresses in the vertical stack 802. In this exemplary module 800, relief cavities 804 (not to scale) are created in the bonding surface of the top die 106 to mitigate bonding forces between the top die 106 and at least the next die 102'' below the top die 106. The series of relief cavities 804 can be placed where there are bonding forces known or determined to be detrimental to the stability of the microelectronic package 800. If the top die 106 is an active die and part of the electronic circuitry of the memory module 800 (not just a dummy die), there may be metal interconnects, such as directly bonded interconnects, between the top die 106 and the next die 102'' below it. Even if the metal interconnects are rigid, the series of relief cavities 804 can still reduce and mitigate the bonding forces between the top die 106 and the vertical stack 802 to reduce the effects of warpage forces in the microelectronic package 800.

[0035] Exemplary relief cavities 804 are typically formed in portions of the dielectric regions between adjacent interconnects. In other applications, the relief cavities 804 may be formed between the interconnects and the edge or singulation lanes of the die. The relief cavities 804 may also be continuous or discontinuous, and the geometrical contour of the relief cavities 804 may be triangular, rectangular, or curvilinear. The depth of the relief cavities 804 may range from a few nanometers to a few microns. In an embodiment, it is important that in the region immediately adjacent the relief cavities 804, the bonding surface of the top die 106 is discontinuous from the surface of the die 102 below.

[0036] Figure 9 shows an example process 900 for fabricating the example module 800 of Figure 8. The operations of the example process 900 are shown in individual blocks.

[0037] At block 902 , the exemplary process 900 includes directly bonding the dies 102 to create a vertical stack 802 .

[0038] At block 904 , a top die 106 is prepared for direct bonding to the vertical stack 802 .

[0039] At block 906 , a relief cavity 804 is created in the top die 106 .

[0040] In block 908, the top die 106 is bonded or directly bonded to the vertical stack 802 to create a microelectronic package 800 with reduced warpage stress between the top die 106 and the dies 102 in the vertical stack 802, providing a more reliable package with reduced risk of serious defects.

[0041] FIG. 10 illustrates an exemplary memory module 1000 with a die stack 1002 that includes features for reducing warpage stress in the vertical stack 1002. In an exemplary embodiment, a stress balancing layer 1004 is fabricated on the backside of the top die 106 (or on the top side of the vertical stack 1002 if the vertical stack 1002 includes a top die 106). The stress balancing layer 1004 can be fabricated of a hard or rigid material applied, for example, by physical vapor deposition (PVD) or by other application techniques, to prevent warpage in the first place. The stress balancing layer 1004 can also be one or more rigid materials to inhibit or counteract die or stack warpage due to assembly of the package 1000 or due to subsequent thermal changes during operation. The stress balancing layer 1004 can also have a unique warp or camber, designed to counteract and counter the warpage or stress of the die or stack to which it is bonded or joined. The stress balancing layer 1004 can also redistribute stress in some configurations, balancing local stresses by horizontally redistributing localized warpage and stress points with other localized areas of opposing warpage or stress to achieve a net zero overall warpage.

[0042] In some applications and structures 1000', a stress balancing layer 1004 may be coated on the underside of the top die 106. In this arrangement, the stress balancing layer 1004 is disposed between the top die 106 and the mating die directly below the top die 106 in the stack 1002', such as die 4 102''' in the structure 1000' of FIG.

[0043] In the structure 1000'', one or more stress balancing layers 1004 may be disposed between the thin dies 102 in the die stack 1002'', or anywhere within the stack 1002''.

[0044] Such stress balancing layers can also be matched to each individual die 102 that is to be joined into the stack 1002''. Each stress balancing layer 1004 is designed to counter the camber of the warped die 102 or stack 1002 with its own opposite camber. Thus, the stress balancing layer 1004 can apply a slight leaf spring action to the die or stack to eliminate the warp. The opposite cambers cancel each other out when each stress balancing layer 1004 is mated with its warped die or stack, ideally resulting in a flat stack 1002 with zero net overall warp, or a flatter stack 1002.

[0045] In another embodiment, the stress balancing structure can include the stress balancing layer 1004 and a bonding layer (not shown), such as a separate dielectric layer, disposed between the stress balancing layer 1004 and a bonding die directly below it, such as die 4 102″ in FIG. 10. In some applications, the dielectric bonding layer can be a thin bonding layer, the thickness of which is substantially less than the thickness of the bonding die 102.

[0046] In one embodiment, the exemplary stress-balancing layer 1004 can be made of one or more conductive layers, for example, the exemplary stress-balancing layer 1004 can be made of titanium nitride and / or tantalum (TiN / Ta), or Ta and Al as co-evaporated or co-sputtered layers, or these metals can be deposited on top of each other in sequence. However, the exemplary stress-balancing layer 1004 is not limited to these compounds and elements. Multiple stress-balancing layers 1004 can be applied, and they can have different coefficients of thermal expansion (CTE) to provide different balancing force differentials at different temperatures. Furthermore, a bonding layer, such as an oxide, nitride, or similar material, can be formed on the stress-balancing layer to enable direct or hybrid bonding to another surface. If the stress-balancing layer 1004 is a non-conductor, the stress-balancing layer 1004 could accommodate vertical conductors, such as TSVs and / or metal interconnects, passing through the thickness of the stress-balancing layer 1004.

[0047] In one embodiment, the stress-balancing layer 1004 can be made of a photopatternable polymer that assembles or tends to assemble into a curved shape. For example, a differentially photocrosslinked SU-8 photoresist film can bend during photolithographic patterning. In another embodiment, a curved or leaf-spring style stress-balancing layer 1004 is bonded to a warped die by a thin polymer film with non-uniform mechanical properties.

[0048] Figure 11 illustrates an example process 1100 for fabricating the example module 1000 of Figure 10, including one or more stress-balancing layers 1004. The operations of the example process 1100 are illustrated in discrete blocks.

[0049] At block 1102 , the example process 1100 includes directly bonding the dies 102 to create a vertical stack 1102 of the dies 102 .

[0050] At block 1104 , a top die 106 is prepared for direct bonding with the vertical stack 1002 .

[0051] At block 1106, the top die 106 is associated with the stress balancing layer 1004. In one exemplary process, the top die 106 is pre-coated with the stress balancing layer 1004 prior to attachment to the vertical stack 1002. After the attachment step, the new stack may be further processed, for example, subjected to a thermal annealing or forming operation.

[0052] At block 1108 , the top die 106 and the stress balancing layer 1004 are bonded to the die 102 in the vertical stack 1002 .

[0053] In a variation of the exemplary process 1100, one or more stress balancing layers 1004 are placed anywhere within the stack to balance stress or offset warpage of the die, group of dies, or entire stack of dies.

[0054] FIG. 12 illustrates a memory module 1200 of directly bonded vertically stacked dies 102. Right angle corners 1204 of some dies 102 in the stack 1202 can be rounded in the x, y, and / or z directions to prevent stress concentration (concentration of compressive forces at the traditionally squared corners 1204 of the dies 102 during stack fabrication). The compressive forces 1205 can traditionally cause cracking and chipping of the brittle die or substrate 104 below the 90 degree corners. Rounding, chamfering, or otherwise softening the normally sharp 90 degree corners or edges between the z and x / y planes can prevent or distribute the concentrated compressive forces 1205 from being transferred to the relatively weak and fragile die or substrate. In one embodiment, the edges of the bonded dies 102 in the stack 1202 are rounded to prevent point stresses at the corners 1204. In another application, the edges of the top die 106 can also be rounded.

[0055] 13 illustrates an exemplary process 1300 for preventing damaging force concentrations in fabricating a vertical stack of dies. The operations of the exemplary process 1300 are illustrated in discrete blocks.

[0056] In block 1302, the exemplary process 1300 includes rounding right-angled corners of dies selected for the vertical stack 1202 of dies. Corner rounding can be achieved, for example, by applying a high-pressure dielectric etch during a plasma etching operation. The etching operation can include etching the substrate 104 and the coated dielectric layer. In other cases, the edges of the dielectric at the joining surface need to be rounded before the joining operation. In some applications, the joining surface can be shielded with a protective agent, and selected edges can be rounded with a wet etching method, or with a moderate abrasive powder blasting operation, or with a laser jet method, or a combination thereof. The dies 102 to be used in the stack 1202 are then aligned according to a vertical plane. The dies 102 with at least some rounded corners 1204 are directly joined into the stack 1202, which prevents the pressing forces from concentrating at the corners 1204 and from transferring these forces to the next die or the substrate 104 below, causing breakage, cracking, or chipping.

[0057] 14 illustrates another exemplary module 1400, memory module, or other stacked device assembled according to one or more techniques for reducing stress warpage in the die stack 1402 that makes up the module 1400. In this embodiment, instead of using one large monolithic die on top of the die stack 1402, two or more thinner dies 1404 are bonded to the top of a stack 1402 of smaller dies 102. These top thinner dies 1404 can conform to the stack 1402 below or impose a counter warpage to the warpage of the stack 1402 below. In some arrangements, a molding material 1406 laterally surrounds the bonded die stack 1402.

[0058] FIG. 15 illustrates another exemplary structure 1500 for eliminating warpage problems and yield loss in the fabrication of modules, such as memory modules, and other devices with stacked dies.

[0059] The stack of dies 102 is provided with side supports 1502, such as side buttresses made of underfill material or another rigid solid or particulate composite layer. The individual dies 102 may be very thin, such as 55 μm thick, or even thinner, and therefore may be prone to warping. Before bonding the thick top die 1504 to the stack, the side supports 1502 are constructed for the sides of the stack. These one or more side die support structures 1502 can be formed by various dispensing methods, including printing or molding methods. During direct bonding of the top dummy die 1504 (or active die) to the stack of dies 102, for example, the side supports 1502 hold the edges of the die and stabilize the stack of dies 102 as a whole. The side support structures 1502 also reduce the occurrence of damage to the bonded dies due to routine handling operations. As a result, in the completed module, the various dies 102 and 1504 are less likely to chip or crack due to the solid stabilization of the side supports 1502. Side moldings 1506 can also be added to further stabilize the stack 102&1504 to complete the package. It should be noted that the side support structures 1502 abut the outer periphery of the bonding die 102 and not the outer periphery of the top die 1504. Also, while the side moldings 1506 are positioned around the bonding die 102 and the top die 1504, the side moldings 1506 are not in direct contact with the lower die 102 of the stacked bonding die, e.g., die 1 102 and die 2 102'. In this manner, the side moldings 1506 directly abut only a portion of the bonding dies of the bonding die stack.

[0060] 16 shows an example of a structure 1600 similar to structure 1500 of FIG. 15, but the exemplary module 1600 does not use a top extra die 1504. In this case, side moldings 1602 can be used after the side supports 1502 are placed to complete a shorter package 1600. As previously mentioned, the side moldings 1602 directly abut a portion of the top die(s) and do not abut other bonding dies in the bonding die stack. In one embodiment, the side moldings 1602 do not directly contact the stacked bonding dies.

[0061] 17 shows additional example structures 1700 and 1702 for creating modules with stacked dies 102 while reducing stress warpage when the dies 102 are directly bonded in a stack. This example approach also applies when an extra dummy die 1704 is directly bonded to the top of each stack with a warpage recess that may be different from that of the stack of dies 102 below it.

[0062] First, in an exemplary process, the thin dies 102 are directly bonded at a first temperature, for example, in the approximate range of 140-350° C. Then, an extra dummy die 1704, which is the top die, is bonded to the stack of dies 102 at a second temperature, preferably lower than the first temperature. In one embodiment, for example, the thin dies 102 can be bonded at a temperature high enough to form a metal bond between mating metal electrical contacts between the closely mated dies. For example, the mating temperature for the opposing electrical and non-electrical contacts can be in the range of 150-300° C., preferably 180-250° C., for durations ranging from 45 minutes to 2-4 hours or even longer. The bonding temperature depends on the nature of the mating metal layers. In practice, the higher the bonding temperature, the shorter the bonding time, and vice versa.

[0063] The stack of dies 102 can be cooled to a lower bonding temperature for additional processing, if necessary, before attaching the top extra dummy die 1704 to the top surface of the final die in the stack of dies 102. The attached dummy die 1704 is then bonded at a temperature preferably lower than the metal engagement temperature of the bonded stacked dies. In one embodiment, the dummy die 1704 is bonded at a temperature ranging from below room temperature to below 130° C., preferably below 100° C. Lowering the bonding temperature of the top die 1704 reduces stress transferred from the die 1704 to the bonded dies below, such as in the exemplary stack 602 ( FIG. 6 ), stack 1402 ( FIG. 14 ), and stack 1801 ( FIG. 18 ).

[0064] In one embodiment, the warped state of a stack of die 102 that is directly bonded at a high temperature and then cooled to a low temperature is remembered and "set" in place by adding underfill or other solid material side supports 1502 to stabilize the stack. In another embodiment, molding material 1706 is used on the sides as needed to stabilize and / or complete the package.

[0065] 18 illustrates an example structure and associated process for making an example module 1800 of stacked dies with reduced internal stress warpage and / or higher manufacturing yield due to less damage due to warpage during fabrication. A first stack of dies 1801 is assembled by directly bonding thin dies 102 together or by other bonding means. Underfill or other solid material is used to create lateral supports 1502 for the stack of dies 102, thereby stabilizing the stack of dies 102 without warpage.

[0066] Another stack 1810 of dies 1802&1804&1806&1808 is fabricated separately, applying one or more of the warpage countermeasures as described herein, and then this prefabricated stack 1810 of additional dies is bonded or directly bonded to the initial stack of dies 102, rather than simply continuing the initial single stack 102 by adding each additional die 1802&1804&1806&1808 one by one, propagating and further accentuating the negative warpage of the initial stack of dies 102.

[0067] In one embodiment, the top layer 1812 of the initial stack of dies 102, which in a conventional module would be an extra dummy die filling the void in the package, is made of active dies 1802 & 1804 in this embodiment of the assembled microelectronic device or module 1800, which are not dummy dies. The module 1800, which now contains two stacks of directly bonded dies 102 & 1810, can be filled with molding compound 1814 to complete it.

[0068] It should be noted that in one embodiment, the side supports 1502, made for example of underfill material, represent a first encapsulation that touches, supports and stabilizes only the first stack of dies 102, while the later added molding material 1814 represents a second encapsulation that touches, supports and stabilizes only the dies in the second stack 1810. In this way, all the dies in the two stacks 102 and 1810 are stabilized in a warp-free configuration by the encapsulant, but in a different way for each stack when assembling the module 1800. The first stack of dies 102 receives the side support 1502 from the buttress underfill material, while the next stack of dies 1810 receives the warp-free stabilization from the side moldings 1814 that complete the package.

[0069] 19 shows another exemplary structure 1900 and method for mitigating warpage stress in a stack of dies and microchips, especially when the dies are very thin. An exemplary module 1900 with a stack 1902 of dies 102 is built on a substrate 104, such as a semiconductor wafer, carrier, panel, or interposer.

[0070] In one embodiment, a top die 1904 is added to the stack of dies 102 to bring the package to height specifications. The top die 1904 may be a dummy die, but may also be one or more active dies. In one embodiment, the top die 1904 is thicker than the individual dies 102 that make up the stack 1902 below it, and is therefore prone to warping on its own. The bonding surface of the top die 1904 may be formed by photolithography and selective material methods. In one example, the bonding surface of the die 1904 may be selectively protected, for example with an organic or inorganic resist protection layer. The unprotected portions of the bonding surface may be etched by dry or wet methods to remove enough material to prevent the etched areas from contacting the top bonding surface of the die 102 directly below during and after the bonding operation.

[0071] After the die 1904 material removal step, the protective layer is peeled off and the bottom bonding surface of the top die is cleaned and prepared for bonding to the top surface of the die 102. The top die 1904 can be actively given rounded edges on its bonding side. The top die 1904 is directly bonded at its central region to the underlying die stack, forming a peripheral gap beyond the bonding area. In this configuration, the prepared bonding surface of the top die 1904 is smaller than the bonding surface of the underlying die 102. Reducing the bonding area between the top die 1904 and the underlying die, e.g., die 4 102''', reduces the forces transferred to the underlying bonded die. In one embodiment, an encapsulant wedge or fillet 1906 can be applied to fill the peripheral gap beyond the bonding area of ​​the die 1904. The encapsulant fillet 1906 can comprise or incorporate particulate material to reduce the thermal expansion of the encapsulant. In another embodiment, an underfill material or molding material 1908 can be applied to encapsulate the mating die, such as die 102, and the die 1904, filling the fillet 1906 between the top die 1904 and the die 102''' underneath.

[0072] The encapsulation material 1908 provides a strong bond between the bonded die stack 102 and top die 1904 to form a unitary solid structure and also acts as a protective layer to prevent stress cracking and delamination between the stack of dies 102 and the top die 1904. Additionally, the compliant material fillet 1906 can be of the same material as the molding 1908 around the sides of the stack 102 & 1904 to complete the package 1900.

[0073] 20 illustrates another exemplary scheme for assembling a larger module 2000 with multiple stacked dies without introducing yield-reducing problems due to stress warpage during fabrication. In this embodiment, a compliant layer 2001 is added between groups of dies at intervals, such as between a first group 102 of dies 102, a second group 2010 of dies 2002&2004&2006&2008, and a third group 2012 of active or dummy dies. In one embodiment, the compliant layer 2001 comprises one or more conductive vias to electrically connect conductive features on the backside of die 4 102′″ to conductive features of die 5 2002. In some applications, the layer 2001 may comprise one or more low melting point conductive materials (e.g., solder) to connect desired portions of die 4 102′″ to similar portions of die 5 2002.

[0074] In one embodiment, the dies 102 and compliant layer 2001 are individually stacked, such as by direct bonding or direct hybrid bonding, one die 102 or layer 2001 at a time. In another embodiment, a group of dies 102&2010&2012 are assembled separately and the group of dies is added to the overall stack as a grouped unit.

[0075] Once the entire stack of dies 102 & 2010 & 2012 is complete, the stack can be encapsulated with molding 2014 or the same compliant material used in compliant layer 2001.

[0076] FIG. 21 shows thin dies 2102 directly hybrid bonded into stacks 2104. Each stack 2104 is built on a common wafer substrate 2106, or carrier, panel, etc. A thin layer 2108 of dielectric and metal (direct hybrid bond layer 2108) on the die 2102 and substrate 2106 enables the direct hybrid bond. That is, the bond layer 2108 can be composed of multiple layers and / or can be composed of a combination of dielectric material(s) and metal(s). The dielectric can be composed of a multi-layer dielectric including, but not limited to, diffusion barrier layers and dielectric layers for bonding of Si, O, N, and C. Additionally, the layer 2108 can include metal materials as conductive pads, in which case direct bonding occurs between the metal bond pads, vias, and interconnects of the die 2102 after the direct bonding occurs on the dielectric surface, in an annealing step of the same overall direct bonding operation. One or more extra dummy dies on top of each stack 2104 may be bonded directly to each respective stack 2104 with direct oxide-to-oxide bonding.

[0077] A singulation operation 2110 dices the individual stacks 2104 into individual modular units 2112, such as individual high bandwidth memory modules.

[0078] FIG. 22 shows thin dies 2202 that are directly hybrid bonded into a stack 2204 and encapsulated with molding compound 2205. Each stack 2204 is built on a common wafer substrate 2206, for example, or a carrier, panel, etc. The direct hybrid bonding layer 2208 is composed of a very thin layer 2208 of dielectric on the die 2202 and substrate 2206 to enable direct hybrid bonding. The thin layer 2208 of dielectric and metal (direct hybrid bonding layer 2108) on the die 2202 and substrate 2206 enables direct hybrid bonding. The bonding layer 2208 can be composed of multiple layers and / or can be composed of a combination of dielectric material(s) and metal(s). The dielectric can be composed of a multi-layer dielectric, including but not limited to diffusion barrier layers and dielectric layers for bonding of Si, O, N, and C. Additionally, layer 2208 can include metal material as conductive pads, in which case direct bonding occurs at the dielectric surface followed by an annealing step in the same overall direct bonding operation between the metal bond pads, vias, and interconnects of die 2202. One or more extra dummy die on top of each stack 2204 can be directly bonded to each respective stack 2204, for example, with an oxide-to-oxide direct bond.

[0079] A singulation operation 2210 dices the individual stacks 2204 into individual modular units 2212 .

[0080] FIG. 23 illustrates an exemplary module 2300 with one or more directly bonded die stacks 2302 on a substrate 2304 or board and a microprocessor 2306 and / or a graphics processor or microcontroller mounted on the same substrate 2304 or board. Each of the one or more directly bonded die stacks 2302 incorporates one of the stress or warpage relief or stress-warpage prevention devices described in FIGS. 2-22. The microprocessor 2306 or other logic unit or processor is communicatively coupled to the one or more directly bonded die stacks 2302. A thin layer 2303 of dielectric and metal (direct hybrid bonding layer 2303) on the die 2305 and substrate 2304 enables the direct hybrid bonding. The bonding layer 2303 can be composed of multiple layers and / or can be composed of a combination of dielectric material(s) and metal(s). The dielectric can be comprised of a multi-layer dielectric including, but not limited to, diffusion barrier layers and dielectric layers for bonding consisting of Si, O, N, and C. Additionally, layer 2303 can include metal materials as conductive pads, in which case direct bonding occurs between the metal bond pads, vias, and interconnects of die 2305 in an annealing step in the same overall direct bonding operation after direct bonding occurs at the dielectric surface.

[0081] In one embodiment, module 2300 includes at least one heat sink 2308 , and in one embodiment, one or more die stacks 2302 and microprocessor 2306 are in contact with a common heat sink 2308 . In the above description and the accompanying drawings, specific terms and drawing symbols have been set forth to provide a thorough understanding of the disclosed embodiments. In some cases, these terms and symbols may imply specific details that are not required to practice those embodiments. For example, specific dimensions, quantities, types of materials, fabrication steps, etc., may all be different from those described above in alternative embodiments. In this specification, the term "coupled" is used to describe a direct connection as well as a connection through one or more intervening circuits or structures. The terms "example," "embodiment," and "implementation" are used to describe an example, not a preference or requirement. Additionally, the terms "may" and "can" are used interchangeably to indicate any (permissible) subject matter. The absence of either term should not be interpreted to mean that a given feature or technique is required.

[0082] Various modifications and changes can be made to the embodiments presented herein without departing from the broader spirit and scope of the present disclosure. For example, any feature or aspect of the embodiments can be applied in combination with any other of the embodiments or in place of a corresponding feature or aspect thereof. Accordingly, the specification and drawings should be regarded in an illustrative sense, and not in a restrictive sense.

[0083] While the present disclosure has been disclosed with respect to a limited number of embodiments, those skilled in the art having the benefit of this disclosure will recognize numerous modifications and variations possible in light of the description, and it is intended that the appended claims cover such modifications and variations as fall within the true spirit and scope of the present disclosure. [Explanation of symbols]

[0084] 102 Memory Die 1 102' Memory Die 2 102'' Memory Die 3 102'' Memory Die 4 104 Substrate 106 Top Die 112 Dent 200 Memory Modules 202 Die Stack 204 Back grinding 206 Backside wet or dry etching

Claims

1. An apparatus comprising: A substrate; a direct bonded die stack formed on the substrate; a first die comprising a top die of the direct bonded die stack; Equipped with a first die comprising the top die has different physical dimensions than a second die comprising any of the remaining dies of the direct bonded die stack; An apparatus comprising:

2. The apparatus of claim 1 , wherein the top die has a greater vertical thickness than the second die.

3. The apparatus of claim 1 , wherein the top die is attached to an adjacent die in the die stack by one of a compliant adhesive, an underfill, an electrical connection, or a solder joint.

4. The apparatus of claim 1 , wherein the top die has at least one horizontal dimension that is greater than a corresponding horizontal dimension of the second die.

5. The apparatus of claim 4 , wherein the top die has two horizontal dimensions that are greater than corresponding horizontal dimensions of the second die.

6. The apparatus of claim 1 , further comprising an underfill or molding compound on the substrate and surrounding at least a portion of the die stack.

7. The apparatus of claim 1 , wherein the top die comprises a dummy die.

8. 2. The apparatus of claim 1, wherein the top die has a surface with a central region that contacts an adjacent die in the die stack, and a peripheral region that comprises at least a portion of the surface does not contact an adjacent die in the die stack.

9. The apparatus of claim 1 further comprising an array of cavities on a bonding surface of the top die.

10. The apparatus of claim 1 , wherein at least one of the dies in the direct bond die stack comprises a memory die.

11. The apparatus of claim 1 , wherein at least one of the dies in the direct bond die stack has rounded edges.

12. An apparatus comprising: A substrate; a direct bonded die stack formed on the substrate; a non-die layer in the direct bonded die stack; An apparatus comprising:

13. 13. The apparatus of claim 12, wherein the non-die layer comprises one of a molding material, an underfill material, an electrical interconnect, an electrical interconnect embedded in a molding material, or an electrical interconnect embedded in an underfill material.

14. The apparatus of claim 13 , wherein the molding material, the underfill material, or the electrical interconnects extend at least partially between a top die and an adjacent die in the die stack.

15. The apparatus of claim 12 , wherein the non-die layer comprises at least one compliant layer in the direct bond die stack.

16. 16. The apparatus of claim 15, wherein the at least one compliant layer is interposed between a top die and a second die adjacent to the top die.

17. 15. The apparatus of claim 14, wherein the at least one compliant layer has a Young's modulus of less than 4 GPa.

18. 13. The apparatus of claim 12, wherein the non-die layer comprises one of a titanium-tantalum nitride (TiN / Ta) layer, an aluminum layer, a tantalum layer, or a combination of an aluminum layer and a tantalum layer.

19. The apparatus of claim 12 , wherein the non-die layer comprises a curved surface.

20. The apparatus of claim 12 , further comprising a die support structure in contact with at least a portion of the die in the die stack, the non-die layer not in contact with the die support structure.

21. The apparatus of claim 12 , wherein a functional die in the die stack is vertically thinner than a top die in the die stack.

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