Solid-state imaging element and imaging device

Abstract

To provide a solid-state imaging element and an imaging device, which can be designed easily.SOLUTION: A solid-state imaging element according to the present disclosure includes a light-receiving substrate, a circuit board, a plurality of first connections, and a plurality of third connections. The light-receiving substrate includes a plurality of light-receiving circuits provided with photoelectric conversion elements. The circuit board is directly bonded to the light-receiving substrate and includes a plurality of address event detection circuits that detects individual changes in voltages output from the photoelectric conversion elements of the plurality of light-receiving circuits. The plurality of first connections is provided at a joint between the light-receiving substrate and the circuit board to electrically connect the light-receiving circuits and the address event detection circuits corresponding to each other. The third connections are provided at the joint between the light-receiving substrate and the circuit board to connect the photoelectric conversion elements and a power supply voltage. At least one of the third connections is shared by the photoelectric conversion elements.SELECTED DRAWING: Figure 25

Description

[Technical field]

[0001] The present disclosure relates to a solid-state imaging element and an imaging device. [Background technology]

[0002] In recent years, asynchronous solid-state imaging devices have been proposed in which an address event detection circuit is provided for each pixel, which detects in real time, for each pixel address, that the amount of light at that pixel exceeds a threshold value as an address event (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Special Publication No. 2016-533140 Summary of the Invention [Problem to be solved by the invention]

[0004] However, in the above-mentioned conventional techniques, there is still room for improvement in terms of ease of designing the solid-state imaging device.

[0005] Therefore, the present disclosure proposes a solid-state imaging element and an imaging device that can be easily designed. [Means for solving the problem]

[0006] According to the present disclosure, a solid-state imaging element is provided. The solid-state imaging element includes a light-receiving substrate, a circuit substrate, a plurality of first connection parts, and a plurality of third connection parts. The light-receiving substrate has a plurality of light-receiving circuits in which photoelectric conversion elements are provided. The circuit substrate is directly bonded to the light-receiving substrate and has a plurality of address event detection circuits that respectively detect voltage changes output from the photoelectric conversion elements of the plurality of light-receiving circuits. The plurality of first connection parts are provided at a joint between the light-receiving substrate and the circuit substrate, and electrically connect the corresponding light-receiving circuits to the address event detection circuits. The plurality of third connection parts are provided at a joint between the light-receiving substrate and the circuit substrate, and connect the photoelectric conversion elements to a power supply voltage. At least one of the plurality of third connection parts is shared by a plurality of the photoelectric conversion elements. [Brief description of the drawings]

[0007] [Figure 1] 1 is a block diagram illustrating an example of a configuration of an imaging device according to an embodiment of the present disclosure. [Diagram 2] 2A to 2C are diagrams for explaining a layered structure of a solid-state imaging element according to an embodiment of the present disclosure. [Diagram 3] 2A and 2B are diagrams for explaining a planar configuration of a light-receiving substrate according to an embodiment of the present disclosure. [Figure 4] FIG. 2 is a diagram for explaining a planar configuration of a circuit board according to an embodiment of the present disclosure. [Diagram 5] FIG. 2 is a diagram for explaining a configuration of an effective pixel according to an embodiment of the present disclosure. [Figure 6] FIG. 2 is a diagram showing a circuit configuration of an effective pixel according to an embodiment of the present disclosure. [Figure 7] FIG. 2 is a diagram for explaining a configuration of an effective pixel according to an embodiment of the present disclosure. [Figure 8] 1 is a diagram showing a cross-sectional configuration of a solid-state imaging element according to an embodiment of the present disclosure. [Figure 9] 1 is a diagram showing a planar configuration of a solid-state imaging element according to an embodiment of the present disclosure. [Figure 10] 4 is a plan view showing an example of the arrangement of first connection parts within an effective pixel according to an embodiment of the present disclosure. FIG. [Figure 11] 11 is a plan view showing another example of the arrangement of the first connection portion in the effective pixel according to the embodiment of the present disclosure. FIG. [Figure 12] 11 is a plan view showing another example of the arrangement of the first connection portion in the effective pixel according to the embodiment of the present disclosure. FIG. [Figure 13] 4A to 4C are plan views illustrating examples of via arrangement with respect to a first connection portion according to an embodiment of the present disclosure. [Figure 14] 13 is a plan view illustrating an example of an arrangement of vias with respect to another first connection portion according to an embodiment of the present disclosure. FIG. [Figure 15] 13 is a plan view illustrating an example of an arrangement of vias with respect to another first connection portion according to an embodiment of the present disclosure. FIG. [Figure 16] 13 is a plan view illustrating an example of an arrangement of vias with respect to another first connection portion according to an embodiment of the present disclosure. FIG. [Figure 17] 11 is a plan view illustrating another example of the arrangement of vias with respect to a first connection portion according to an embodiment of the present disclosure. FIG. [Figure 18] 11 is a plan view illustrating another example of the arrangement of vias with respect to a first connection portion according to an embodiment of the present disclosure. FIG. [Figure 19] 11 is a plan view illustrating another example of the arrangement of vias with respect to a first connection portion according to an embodiment of the present disclosure. FIG. [Figure 20] 11 is a plan view illustrating another example of the arrangement of vias with respect to a first connection portion according to an embodiment of the present disclosure. FIG. [Figure 21] FIG. 13 is a diagram showing a circuit configuration of an effective pixel according to a first modified example of the embodiment of the present disclosure. [Figure 22] 11 is a plan view showing an example of the arrangement of first connection portions and second connection portions within an effective pixel according to a first modified example of the embodiment of the present disclosure. FIG. [Diagram 23] 11 is a plan view showing another example of the arrangement of the first connection portion and the second connection portion within an effective pixel according to the first modification of the embodiment of the present disclosure. FIG. [Figure 24] 11 is a plan view showing another example of the arrangement of the first connection portion and the second connection portion within an effective pixel according to the first modification of the embodiment of the present disclosure. FIG. [Diagram 25] FIG. 11 is a diagram showing a circuit configuration of an effective pixel according to a second modified example of the embodiment of the present disclosure. [Figure 26]FIG. 11 is a diagram showing a circuit configuration of an effective pixel according to a third modified example of the embodiment of the present disclosure. [Figure 27] FIG. 13 is a block diagram showing a second exemplary configuration of the address event detection unit. [Figure 28] FIG. 11 is a block diagram showing an example of the configuration of an imaging device according to a second configuration example, that is, a scanning type imaging device, which is used as an imaging device in an imaging system to which the technology according to the present disclosure is applied. [Figure 29] FIG. 1 is a schematic diagram illustrating an example of a configuration of a distance measuring system according to an embodiment of the present disclosure. [Diagram 30] FIG. 2 is a block diagram showing an example of a circuit configuration. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] Hereinafter, each embodiment of the present disclosure will be described in detail with reference to the drawings. In the following embodiments, the same components are designated by the same reference numerals, and duplicated descriptions will be omitted.

[0009] Conventionally, synchronous solid-state imaging devices that capture image data (frames) in synchronization with a synchronous signal such as a vertical synchronous signal have been used in imaging devices, etc. This general synchronous solid-state imaging device can only capture image data at synchronous signal intervals (e.g., 1 / 60 seconds), making it difficult to meet the demand for faster processing in fields related to traffic, robots, etc.

[0010] In response to this, an asynchronous solid-state imaging device has been proposed in which an address event detection circuit is provided for each pixel, which detects in real time, for each pixel address, the fact that the amount of light at that pixel exceeds a threshold value as an address event. In this solid-state imaging device, a photodiode and multiple transistors for detecting address events are provided for each pixel.

[0011] However, in the above-mentioned conventional technology, each pixel is electrically connected to the address event detection circuit via a TSV (through silicon via) formed around the pixel array, so the area of ​​the TSV region increases as the number of pixels increases.

[0012] In other words, if one attempts to improve the resolution of a solid-state imaging element by increasing the number of pixels in the pixel array section, the area of ​​the TSV region within the element also increases, reducing the area in which the pixel array section can be arranged, making it difficult to improve the resolution of the solid-state imaging element.

[0013] Therefore, there is a need for a technology that can overcome the above-mentioned problems and improve the resolution of solid-state imaging devices.

[0014] [Configuration of imaging device] First, a configuration of an imaging device 100 according to an embodiment will be described with reference to Fig. 1. Fig. 1 is a block diagram showing an example of a configuration of the imaging device 100 according to an embodiment of the present disclosure.

[0015] The imaging device 100 according to the embodiment includes a lens 110, a solid-state imaging element 200, a recording unit 120, and a control unit 130. The imaging device 100 is assumed to be a camera mounted on a wearable device, an in-vehicle camera, or the like.

[0016] The lens 110 takes in incident light from a subject and forms an image on the imaging surface of the solid-state imaging device 200 .

[0017] The solid-state imaging device 200 is also called a DVS (Dynamic Vision Sensor), and detects, as an address event, that the absolute value of the amount of change in luminance of each of a plurality of pixels has exceeded a threshold value. The address event includes, for example, an ON event indicating that the amount of increase in luminance has exceeded an upper threshold value, and an OFF event indicating that the amount of decrease in luminance has fallen below a lower threshold value that is less than the upper threshold value.

[0018] The solid-state imaging device 200 generates a detection signal indicating the detection result of the address event for each pixel. Each detection signal is an on-event detection signal V CH (See Figure 6) and the off-event detection signal V CL (See FIG. 6).

[0019] The solid-state imaging element 200 performs predetermined signal processing such as image recognition processing on image data consisting of detection signals in a signal processing unit (not shown), and outputs the processed data to the recording unit 120 via a signal line 209.

[0020] The recording unit 120 records the data from the solid-state imaging element 200. The control unit 130 controls the solid-state imaging element 200 to cause the solid-state imaging element 200 to capture image data.

[0021] [Structure of solid-state imaging element] Next, the configuration of the solid-state imaging element 200 according to the embodiment will be described with reference to Fig. 2 to Fig. 20. Fig. 2 is a diagram for explaining the layered structure of the solid-state imaging element 200 according to the embodiment of the present disclosure.

[0022] A solid-state imaging element 200 according to the embodiment includes a circuit board 202 and a light receiving board 201 laminated on the circuit board 202. The light receiving board 201 and the circuit board 202 are electrically connected to each other through connecting parts such as vias, Cu-Cu joints, and bumps.

[0023] 3 is a diagram for explaining a planar configuration of the light-receiving substrate 201 according to the embodiment of the present disclosure. As shown in FIG. 3, the light-receiving substrate 201 has a light-receiving portion 210, a via arrangement portion 221, and a via arrangement portion 222.

[0024] In the light receiving section 210, a plurality of light receiving circuits 211 are arranged in a two-dimensional lattice. The light receiving circuits 211 perform photoelectric conversion of incident light to generate a photocurrent, and perform current-voltage conversion of the photocurrent to output a voltage signal. Each of the light receiving circuits 211 is assigned a pixel address consisting of a row address and a column address.

[0025] In the via arrangement portion 221 and the via arrangement portion 222, vias to be connected to the circuit board 202 (see FIG. 4) are arranged.

[0026] 4 is a diagram for explaining a planar configuration of the circuit board 202 according to the embodiment of the present disclosure. As shown in FIG. 4, the circuit board 202 includes an address event detection unit 230, a signal processing circuit 240, a row driving circuit 251, a column driving circuit 252, a via arrangement unit 261, and a via arrangement unit 262.

[0027] A plurality of address event detection circuits 231 are arranged in a two-dimensional lattice in the address event detection section 230. The address event detection circuit 231 quantizes the voltage signal from the light receiving circuit 211, and outputs the quantized voltage signal as a detection signal.

[0028] A pixel address is assigned to each of the address event detection circuits 231, and the address event detection circuits 231 are electrically connected to the light receiving circuits 211 at the same address. In the embodiment, the light receiving circuits 211 and the address event detection circuits 231 at the same address are disposed at the same position in a plan view.

[0029] The signal processing circuit 240 performs a predetermined signal processing on the detection signal from the address event detection unit 230. For example, the signal processing circuit 240 arranges the detection signal as a pixel signal in a two-dimensional lattice shape, and acquires image data having 2 bits of information for each pixel. Then, the signal processing circuit 240 performs signal processing such as image recognition processing on the acquired image data.

[0030] The row driving circuit 251 selects a row address, and outputs a detection signal corresponding to the selected row address to the address event detection unit 230. The column driving circuit 252 selects a column address, and outputs a detection signal corresponding to the selected column address to the address event detection unit 230. In the via arrangement unit 261 and the via arrangement unit 262, vias to be connected to the light receiving substrate 201 (see FIG. 3) are arranged.

[0031] 5 is a diagram for explaining the configuration of an effective pixel 310 according to an embodiment of the present disclosure. As shown in Fig. 5, each effective pixel 310 is composed of a light receiving circuit 211 in a light receiving substrate 201 and an address event detection circuit 231 in a circuit substrate 202, both of which are assigned the same pixel address.

[0032] As described above, a plurality of light receiving circuits 211 and a plurality of address event detection circuits 231 are arranged in a two-dimensional lattice pattern on the light receiving board 201 and the circuit board 202. Furthermore, the light receiving circuits 211 and the address event detection circuits 231 at the same address are disposed at the same position in a plan view.

[0033] That is, in the solid-state imaging device 200 according to the embodiment, effective pixels 310 each consisting of a pair of a light receiving circuit 211 and an address event detection circuit 231 are arranged in a two-dimensional lattice pattern.

[0034] A pair of the light receiving circuit 211 and the address event detection circuit 231 is electrically connected via a first connection portion 270 provided at a joint portion 203 between the light receiving substrate 201 and the circuit substrate 202 .

[0035] 6 is a diagram showing a circuit configuration of an effective pixel 310 according to an embodiment of the present disclosure. As shown in FIG. 6, the effective pixel 310 includes a photodiode 311, a current-voltage conversion circuit 320, a buffer 330, a subtractor 340, a quantizer 350, and a transfer circuit 360.

[0036] In the embodiment of the present disclosure, among the components of the effective pixel 310, the photodiode 311 and the N-type transistors 321 and 322 of the current-voltage conversion circuit 320 are included in the light receiving circuit 211. Also, among the components of the effective pixel 310, the buffer 330, the subtractor 340, the quantizer 350, and the transfer circuit 360 are included in the address event detection circuit 231.

[0037] That is, in the embodiment of the present disclosure, the effective pixel 310 includes a photodiode 311 , a current-voltage conversion circuit 320 , and an address event detection circuit 231 .

[0038] The photodiode 311 performs photoelectric conversion on the incident light to generate a photocurrent. The photodiode 311 then supplies the generated photocurrent to the current-voltage conversion circuit 320.

[0039] The current-voltage conversion circuit 320 converts the photocurrent from the photodiode 311 into a logarithmic voltage signal. Then, the current-voltage conversion circuit 320 supplies the converted voltage signal to the buffer 330.

[0040] The buffer 330 corrects the voltage signal sent from the current-voltage conversion circuit 320, and outputs the corrected signal to the subtractor 340. In the effective pixel 310 according to the embodiment, the buffer 330 can improve the driving force for driving the subsequent stage, and can ensure isolation of noise associated with the switching operation of the subsequent stage.

[0041] The subtractor 340 performs subtraction processing to determine the amount of change in the correction signal sent from the buffer 330. The subtractor 340 then supplies the determined amount of change to the quantizer 350 as a differential signal.

[0042] The quantizer 350 converts (i.e., quantizes) the analog differential signal into a digital detection signal by comparing the differential signal with a predetermined threshold. The quantizer 350 according to the embodiment compares the differential signal with each of the upper and lower thresholds, and supplies the comparison results to the transfer circuit 360 as a 2-bit detection signal.

[0043] The transfer circuit 360 transfers the detection signal to the signal processing circuit 240 in accordance with the column driving signal from the column driving circuit 252 .

[0044] A specific circuit configuration of each part will be described below. Current-voltage conversion circuit 320 has N-type transistor 321, N-type transistor 322, and P-type transistor 323. N-type transistor 321, N-type transistor 322, and P-type transistor 323 may be, for example, MOS (Metal-Oxide-Semiconductor) transistors.

[0045] The source of N-type transistor 321 is connected to the cathode of photodiode 311, and the drain is connected to the terminal of power supply voltage VDD. The anode of photodiode 311 is connected to the terminal of ground potential. P-type transistor 323 and N-type transistor 322 are connected in series in this order between the terminal of power supply voltage VDD and the terminal of ground potential.

[0046] The connection point between the P-type transistor 323 and the N-type transistor 322 is connected to the gate of the N-type transistor 321 and the input terminal of the buffer 330. The connection point between the N-type transistor 321 and the photodiode 311 is connected to the gate of the N-type transistor 322. A predetermined bias voltage V blog is applied.

[0047] Then, N-type transistor 321 converts the photocurrent generated by photodiode 311 into a voltage between its gate and source, and N-type transistor 322 amplifies the voltage between its gate, which has a potential corresponding to the photocurrent, and its source, which has a ground potential, and outputs it from its drain.

[0048] In addition, the P-type transistor 323 is connected to the bias voltage V blog to N-type transistor 322. With this configuration, current-voltage conversion circuit 320 converts the photocurrent from photodiode 311 into a voltage signal.

[0049] In the solid-state imaging element 200 according to the embodiment, the photodiode 311, the N-type transistor 321, and the N-type transistor 322 are disposed on the light receiving substrate 201, and the P-type transistor 323 and subsequent circuits are disposed on the circuit substrate 202.

[0050] 7 is a diagram for explaining the configuration of an effective pixel 310 according to an embodiment of the present disclosure. As shown in Fig. 7, a photodiode 311 is embedded in a P-well region of a light receiving substrate 201, and a backgate of an N-type transistor 321 and a backgate of an N-type transistor 322 are formed.

[0051] A power supply voltage VDD is supplied to the drain of N-type transistor 321, and the potential of the P-well region (i.e., the anode of photodiode 311) and the potential of the source of N-type transistor 322 are ground potential. Furthermore, the P-well regions of adjacent effective pixels 310 are separated by pixel separation section 410 (see FIG. 8) formed in the portion indicated by the dashed dotted line.

[0052] Returning to the description of Fig. 6, buffer 330 has P-type transistor 331 and P-type transistor 332. P-type transistor 331 and P-type transistor 332 may be, for example, MOS transistors.

[0053] P-type transistor 331 and P-type transistor 332 are connected in series, in this order, between a terminal of a power supply voltage VDD and a terminal of a ground potential. A predetermined bias voltage V bsf The gate of P-type transistor 332 is connected to the output terminal of current-voltage conversion circuit 320.

[0054] With this configuration, buffer 330 outputs the corrected voltage signal from the connection point between P-type transistor 331 and P-type transistor 332 to subtractor 340 .

[0055] Subtractor 340 has a capacitor 341, a P-type transistor 342, a capacitor 343, a P-type transistor 344, and an N-type transistor 345. P-type transistor 342, P-type transistor 344, and N-type transistor 345 are, for example, MOS transistors.

[0056] The P-type transistor 344 and the N-type transistor 345 are connected in series in this order between a terminal of the power supply voltage VDD and a terminal of the reference potential. A predetermined bias voltage V ba is applied.

[0057] P-type transistor 344 and N-type transistor 345 function as an inverter that inverts and outputs an input signal, when the gate of P-type transistor 344 is an input terminal and the connection point between P-type transistor 344 and N-type transistor 345 is an output terminal.

[0058] One end of capacitor 341 is connected to the output terminal of buffer 330, and the other end is connected to the input terminal of the inverter (i.e., the gate of P-type transistor 344). One end of capacitor 343 is connected to the input terminal of the inverter, and the other end is connected to the output terminal of the inverter (i.e., the connection point between P-type transistor 344 and N-type transistor 345).

[0059] The P-type transistor 342 opens and closes the path connecting both ends of the capacitor 343 in accordance with a row drive signal output from the row drive circuit 251 .

[0060] When the P-type transistor 342 is turned on, a voltage signal V initis input, and the opposite side becomes a virtual ground terminal. For convenience, the potential of this virtual ground terminal is set to zero.

[0061] At this time, the charge Q stored in the capacitor 341 init If the capacitance of capacitor 341 is C1, then this is expressed by the following equation (1): On the other hand, both ends of capacitor 343 are short-circuited, so that the stored charge therein is zero. Q init =C1×V init (1)

[0062] Next, P-type transistor 342 is turned off, and the voltage on the buffer 330 side of capacitor 341 changes to V after If we consider the case where the charge Q stored in the capacitor 341 becomes after is expressed by the following equation (2). Q after =C1×V after (2)

[0063] On the other hand, the charge Q2 stored in the capacitor 343 increases the capacitance of the capacitor 343 to C2 and the output voltage to V out Then, it is expressed by the following equation (3). Q2=-C2×V out (3)

[0064] In this case, since the total charge amount of the capacitors 341 and 343 does not change, the following equation (4) holds. Q init =Q after +Q2 ··(4)

[0065] Then, by substituting equations (1) to (3) into the above equation (4) and transforming it, the following equation (5) is obtained. V out =-(C1 / C2)×(V after -V init ) ··(5)

[0066] The above equation (5) represents the subtraction operation of a voltage signal, and the gain of the subtraction result is C1 / C2. Since it is usually desired to maximize the gain, it is preferable to design the capacitance C1 to be large and the capacitance C2 to be small. On the other hand, if the capacitance C2 is too small, the kTC noise increases and the noise characteristics may deteriorate, so the reduction in the capacitance C2 is limited to a range where noise can be tolerated.

[0067] Furthermore, since the subtractor 340 is mounted for each effective pixel 310, there are area restrictions on the capacitance C1 and capacitance C2. Taking these into consideration, for example, the capacitance C1 is set to a value of 20 to 200 femtofarads (fF), and the capacitance C2 is set to a value of 1 to 20 femtofarads (fF).

[0068] Quantizer 350 has a P-type transistor 351, an N-type transistor 352, a P-type transistor 353, and an N-type transistor 354. P-type transistor 351, N-type transistor 352, P-type transistor 353, and N-type transistor 354 are, for example, MOS transistors.

[0069] P-type transistor 351 and N-type transistor 352 are connected in series in this order between a terminal of power supply voltage VDD and a terminal of ground potential. P-type transistor 353 and N-type transistor 354 are connected in series in this order between a terminal of power supply voltage VDD and a terminal of reference potential.

[0070] The gates of P-type transistors 351 and 353 are connected to the output terminal of subtractor 340. A bias voltage V bon is applied to the gate of the N-type transistor 354, and a bias voltage V boff is applied.

[0071] The connection point of the P-type transistor 351 and the N-type transistor 352 is connected to the transfer circuit 360. In the quantizer 350, the voltage at this connection point is converted into the on-event detection signal VCH to the transfer circuit 360.

[0072] The connection point of the P-type transistor 353 and the N-type transistor 354 is connected to the transfer circuit 360. In the quantizer 350, the voltage at this connection point is converted into the off-event detection signal V CL will be output as:

[0073] With this configuration, the quantizer 350 outputs a high-level on-event detection signal V CH When the differential signal falls below the lower threshold, a low-level off-event detection signal V CL That is, the solid-state imaging device 200 according to the embodiment can simultaneously detect the presence or absence of both an ON event and an OFF event.

[0074] Fig. 8 is a diagram showing a cross-sectional configuration of a solid-state imaging element 200 according to an embodiment of the present disclosure, and mainly shows a cross-sectional structure of a peripheral portion of the solid-state imaging element 200. As shown in Fig. 8, the solid-state imaging element 200 has an effective pixel region R1, a dummy pixel region R2, a power supply region R3, and a pad region R4.

[0075] The effective pixel region R1 is a region in which the laminated light receiving section 210 and address event detection section 230 are provided. In the effective pixel region R1, a plurality of effective pixels 310 are arranged in a two-dimensional lattice pattern.

[0076] As shown in Fig. 9, the dummy pixel region R2 is a region provided so as to surround the effective pixel region R1. Fig. 9 is a diagram showing a planar configuration of a solid-state imaging element 200 according to an embodiment of the present disclosure.

[0077] 8, a plurality of dummy pixels 310A are arranged side by side in the dummy pixel region R2. The dummy pixels 310A have the same basic configuration as the effective pixels 310, but do not output a signal to the outside.

[0078] In the solid-state imaging device 200 according to the embodiment, the dummy pixel region R2 is formed so as to surround the effective pixel region R1, thereby ensuring the regularity of the process from the center to the edge of the effective pixel region R1. Therefore, according to the embodiment, the manufacturing yield of the solid-state imaging device 200 can be improved.

[0079] 9, the power supply region R3 is a region provided so as to surround the dummy pixel region R2. The power supply region R3 includes a ground wiring 421 to which a ground potential is applied from the outside, a power wiring 422 to which a power supply voltage VDD is applied from the outside, and a substrate voltage V SUB and a power supply wiring 423 to which a voltage is applied. The ground wiring 421 and the power supply wirings 422, 423 are formed, for example, in a ring shape around the dummy pixel region R2.

[0080] The ground wiring 421 supplies a ground potential to the effective pixels 310, etc. The power supply wiring 422 supplies a power supply voltage VDD to the effective pixels 310, etc. The power supply wiring 423 supplies a substrate voltage V, which has the same potential as the power supply voltage VDD, to the portions of the solid-state imaging device 200 other than the effective pixel region R1 and the dummy pixel region R2. SUB supplies.

[0081] In the solid-state imaging device 200 according to the embodiment, a power supply wiring 423 is provided in addition to the power supply wiring 422, so that even if the power supply voltage VDD fluctuates when the effective pixels 310 are in operation, a stable substrate voltage V SUB can be supplied to the peripheral portion of the solid-state imaging element 200. Therefore, according to the embodiment, the solid-state imaging element 200 can be operated stably.

[0082] Returning to the explanation of Fig. 8, the pad region R4 is a region provided around the power supply region R3, and has a contact hole 424 and a bonding pad 425. The contact hole 424 is formed along the thickness direction of the light receiving substrate 201 and the circuit substrate 202 from the light incident side surface of the light receiving substrate 201 to the middle of the circuit substrate 202.

[0083] The bonding pad 425 is provided at the bottom of the contact hole 424. In the embodiment, a bonding wire or the like is joined to the bonding pad 425 through the contact hole 424, thereby electrically connecting the recording unit 120 (see FIG. 1) or the control unit 130 (see FIG. 1) to each unit of the solid-state imaging element 200.

[0084] The configuration of the effective pixels 310 arranged in the effective pixel region R1 will be further described with reference to Fig. 8. The solid-state imaging element 200 is configured by laminating a light receiving substrate 201 and a circuit substrate 202, and a bonding portion 203 is provided at the interface between the light receiving substrate 201 and the circuit substrate 202.

[0085] The light receiving substrate 201 has a semiconductor layer 201a and an insulating layer 201b. The semiconductor layer 201a is made of a semiconductor material such as silicon. In the semiconductor layer 201a, a photodiode 311, an N-type transistor 321 (see FIG. 7), an N-type transistor 322 (see FIG. 7), and the like are formed for each of the effective pixels 310 and the dummy pixels 310A.

[0086] Furthermore, in the semiconductor layer 201a, a pixel separator 410 is formed so as to separate adjacent effective pixels 310 and dummy pixels 310A from each other. The pixel separator 410 electrically and optically separates adjacent effective pixels 310 and dummy pixels 310A from each other.

[0087] The pixel separation sections 410 are formed, for example, so as to surround the effective pixels 310 and the dummy pixels 310A individually and to penetrate the semiconductor layer 201a.

[0088] A planarization film 411 is formed on the light incident surface of the semiconductor layer 201a, and an on-chip lens 412 is formed on the light incident surface of the planarization film 411. The planarization film 411 planarizes the surface on which the on-chip lens 412 is mounted.

[0089] The on-chip lenses 412 are provided, for example, individually for the effective pixels 310 and the dummy pixels 310A, and collect incident light and guide it to the effective pixels 310 and the dummy pixels 310A.

[0090] The insulating layer 201b is made of silicon oxide (SiO x The insulating layer 202 is made of an insulating material such as silicon nitride (SiN) or silicon oxynitride (SiON), and is provided on the surface of the semiconductor layer 201a opposite to the light incident side.

[0091] Further, in the insulating layer 201b, a wiring section 401 composed of a wiring layer, vias, etc. The wiring section 401 is electrically connected to the photodiode 311, the N-type transistor 321, and the N-type transistor 322 provided in the semiconductor layer 201a by the wiring configuration shown in FIG.

[0092] The wiring portion 401 is electrically connected to the first pad 403 through the via 402. The first pad 403 is exposed on the surface of the light receiving substrate 201 opposite to the light incident surface (i.e., the interface with the circuit substrate 202), and is made of copper or a copper alloy.

[0093] The circuit board 202 has an insulating layer 202a on the interface side with the light-receiving board 201. The insulating layer 202a is made of an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride.

[0094] Furthermore, insulating layer 202a has second pad 404. Second pad 404 is provided exposed on the light incident surface of circuit board 202 (that is, the interface with light receiving board 201), and is made of copper or a copper alloy.

[0095] Second pad 404 is electrically connected to wiring portion 406 through via 405. Wiring portion 406 is electrically connected to the gate of P-type transistor 332 (see FIG. 6) and the source of P-type transistor 323 (see FIG. 6).

[0096] 8, the first pad 403 and the second pad 404 are directly bonded by Cu-Cu bonding. That is, the effective pixel 310 according to the embodiment has a first connection portion 270 configured by the first pad 403 and the second pad 404. In the embodiment, one first connection portion 270 is provided for each effective pixel 310.

[0097] As shown in FIG. 5, the first connection portion 270 is provided at the joint 203 between the light receiving substrate 201 and the circuit substrate 202, and electrically connects the light receiving circuit 211 and the address event detection circuit 231 that belong to the same effective pixel 310.

[0098] As described above, in the embodiment, all of the light receiving circuits 211 and the address event detection circuits 231 are electrically connected by the first connection portions 270 formed by Cu-Cu bonding.

[0099] This makes it possible to reduce the number of wirings that need to be connected in the via arrangement sections 221, 222, 261, and 262 (see FIGS. 3 and 4), and therefore the area of ​​the via arrangement sections 221, 222, 261, and 262 can be reduced.

[0100] Therefore, according to the embodiment, since it becomes possible to arrange the additional effective pixels 310 in the areas where the via arrangement sections 221, 222, 261, and 262 are reduced, the resolution of the solid-state imaging element 200 can be improved.

[0101] In addition, in the embodiment, the light receiving circuit 211 and the address event detection circuit 231 are electrically connected by the first connection portion 270 formed by a Cu-Cu bond, so that the electrical resistance between the light receiving circuit 211 and the address event detection circuit 231 can be reduced.

[0102] This allows a signal relating to a change in luminance of light incident on the photodiode 311 of the light receiving circuit 211 to be transferred at high speed to the address event detection circuit 231. Therefore, according to the embodiment, the asynchronous solid-state imaging device 200 can perform even faster processing.

[0103] 8, the first connection portion 270 may be located between the corresponding light receiving circuit 211 and the address event detection circuit 231. This allows the light receiving circuit 211 and the address event detection circuit 231 to be electrically connected to each other over a short distance via the first connection portion 270.

[0104] That is, in the embodiment, by disposing the first connection portion 270 between the corresponding light receiving circuit 211 and address event detection circuit 231, the electrical resistance between the light receiving circuit 211 and the address event detection circuit 231 can be reduced.

[0105] Therefore, according to the embodiment, the signal detected by the photodiode 311 of the light receiving circuit 211 can be transferred to the address event detection circuit 231 at high speed, thereby enabling even faster processing to be performed in the asynchronous solid-state imaging element 200.

[0106] In the embodiment, the first pad 403 and the second pad 404 constituting the first connection portion 270 may be made of the same material (for example, Cu or a Cu alloy). This allows the first connection portion 270 to be formed by direct bonding such as Cu-Cu bonding, so that a large number of first connection portions 270 in the solid-state imaging element 200 can be formed in a single process.

[0107] Therefore, according to the embodiment, the manufacturing process for the solid-state imaging device 200 can be shortened.

[0108] 10 is a plan view showing an example of the arrangement of the first connection portion 270 in the effective pixel 310 according to the embodiment of the present disclosure. For ease of understanding, the first connection portion 270 is depicted as a circle in FIGS. 10 to 12.

[0109] 10, the pixel separating section 410 is formed so as to separate adjacent effective pixels 310. In the example of Fig. 10, the first connection section 270-1 belonging to the effective pixel 310-1 is arranged so as to overlap the effective pixel 310-1 in a plan view, but not to overlap the pixel separating section 410 adjacent to the effective pixel 310-1.

[0110] Moreover, N-type transistor 321-1 belonging to effective pixel 310-1 is provided at a position where effective pixel 310-1 and first connection unit 270-1 overlap in a plan view. Furthermore, N-type transistor 322-1 belonging to effective pixel 310-1 is provided from the position where effective pixel 310-1 and first connection unit 270-1 overlap in a plan view to a position where only effective pixel 310-1 is disposed.

[0111] Similarly, in the example of FIG. 10, the first connection section 270-2 belonging to the effective pixel 310-2 overlaps the effective pixel 310-2 in a plan view, but is disposed so as not to overlap the pixel separation section 410 that contacts the effective pixel 310-2.

[0112] Moreover, the N-type transistor 321-2 belonging to the effective pixel 310-2 is provided at a position where the effective pixel 310-2 and the first connection unit 270-2 overlap in a planar view. Furthermore, the N-type transistor 322-2 belonging to the effective pixel 310-2 is provided from the position where the effective pixel 310-2 and the first connection unit 270-2 overlap in a planar view to a position where only the effective pixel 310-2 is disposed.

[0113] Furthermore, the first connection section 270-3 belonging to the effective pixel 310-3 overlaps the effective pixel 310-3 in a plan view, but is disposed so as not to overlap the pixel separating section 410 that contacts the effective pixel 310-3.

[0114] Moreover, the N-type transistor 321-3 belonging to the effective pixel 310-3 is provided at a position where the effective pixel 310-3 and the first connection unit 270-3 overlap in a planar view. Furthermore, the N-type transistor 322-3 belonging to the effective pixel 310-3 is provided from the position where the effective pixel 310-3 and the first connection unit 270-3 overlap in a planar view to a position where only the effective pixel 310-3 is disposed.

[0115] Furthermore, the first connection portion 270-4 belonging to the effective pixel 310-4 overlaps the effective pixel 310-4 in a plan view, but is disposed so as not to overlap the pixel separating portion 410 that contacts the effective pixel 310-4.

[0116] Moreover, the N-type transistor 321-4 belonging to the effective pixel 310-4 is provided at a position where the effective pixel 310-4 and the first connection unit 270-4 overlap in a planar view. Furthermore, the N-type transistor 322-4 belonging to the effective pixel 310-4 is provided from the position where the effective pixel 310-4 and the first connection unit 270-4 overlap in a planar view to a position where only the effective pixel 310-4 is disposed.

[0117] The arrangement of the first connection units 270 in the effective pixel 310 is not limited to the example in Fig. 10. Fig. 11 is a plan view showing another example arrangement of the first connection units 270 in the effective pixel 310 according to an embodiment of the present disclosure.

[0118] In the example of Figure 11, the first connection section 270-1 belonging to effective pixel 310-1 is arranged so as to overlap one side of effective pixel 310-1 (the left side in the figure) in a planar view and also overlap the pixel separation section 410 that is in contact with one side of effective pixel 310-1.

[0119] Moreover, N-type transistor 321-1 belonging to effective pixel 310-1 is provided at a position where effective pixel 310-1 and first connection unit 270-1 overlap in a plan view. Furthermore, N-type transistor 322-1 belonging to effective pixel 310-1 is provided from the position where effective pixel 310-1 and first connection unit 270-1 overlap in a plan view to a position where only effective pixel 310-1 is disposed.

[0120] Similarly, in the example of Figure 11, the first connection section 270-2 belonging to effective pixel 310-2 is arranged so as to overlap one side of effective pixel 310-2 (the left side in the figure) in a planar view and also overlap the pixel separation section 410 that is adjacent to one side of effective pixel 310-2.

[0121] Moreover, the N-type transistor 321-2 belonging to the effective pixel 310-2 is provided at a position where the effective pixel 310-2 and the first connection unit 270-2 overlap in a planar view. Furthermore, the N-type transistor 322-2 belonging to the effective pixel 310-2 is provided from the position where the effective pixel 310-2 and the first connection unit 270-2 overlap in a planar view to a position where only the effective pixel 310-2 is disposed.

[0122] In addition, in the example of Figure 11, the first connection section 270-3 belonging to effective pixel 310-3 is arranged so as to overlap one side of effective pixel 310-3 (the left side in the figure) in a planar view and also overlap the pixel separation section 410 that is in contact with one side of effective pixel 310-3.

[0123] Moreover, the N-type transistor 321-3 belonging to the effective pixel 310-3 is provided at a position where the effective pixel 310-3 and the first connection unit 270-3 overlap in a planar view. Furthermore, the N-type transistor 322-3 belonging to the effective pixel 310-3 is provided from the position where the effective pixel 310-3 and the first connection unit 270-3 overlap in a planar view to a position where only the effective pixel 310-3 is disposed.

[0124] In addition, in the example of Figure 11, the first connection section 270-4 belonging to effective pixel 310-4 is arranged so as to overlap one side of effective pixel 310-4 in a planar view (the left side in the figure) and also overlap the pixel separation section 410 that is in contact with one side of effective pixel 310-4.

[0125] Moreover, the N-type transistor 321-4 belonging to the effective pixel 310-4 is provided at a position where the effective pixel 310-4 and the first connection unit 270-4 overlap in a planar view. Furthermore, the N-type transistor 322-4 belonging to the effective pixel 310-4 is provided from the position where the effective pixel 310-4 and the first connection unit 270-4 overlap in a planar view to a position where only the effective pixel 310-4 is disposed.

[0126] Fig. 12 is a plan view showing another example of the arrangement of the first connection unit 270 in the effective pixel 310 according to the embodiment of the present disclosure. In the example of Fig. 12, the first connection unit 270-1 belonging to the effective pixel 310-1 is arranged so as to overlap a corner of the effective pixel 310-1 in plan view (the upper left corner in the figure) and also overlap the pixel separation unit 410 that contacts the corner of the effective pixel 310-1.

[0127] Moreover, N-type transistor 321-1 belonging to effective pixel 310-1 is provided at a position where effective pixel 310-1 and first connection unit 270-1 overlap in a plan view. Furthermore, N-type transistor 322-1 belonging to effective pixel 310-1 is provided from the position where effective pixel 310-1 and first connection unit 270-1 overlap in a plan view to a position where only effective pixel 310-1 is disposed.

[0128] Similarly, in the example of Figure 12, the first connection section 270-2 belonging to effective pixel 310-2 is arranged so as to overlap a corner of effective pixel 310-2 in a planar view (the upper left corner in the figure) and also overlap the pixel separation section 410 that is in contact with the corner of effective pixel 310-2.

[0129] Moreover, the N-type transistor 321-2 belonging to the effective pixel 310-2 is provided at a position where the effective pixel 310-2 and the first connection unit 270-2 overlap in a planar view. Furthermore, the N-type transistor 322-2 belonging to the effective pixel 310-2 is provided from the position where the effective pixel 310-2 and the first connection unit 270-2 overlap in a planar view to a position where only the effective pixel 310-2 is disposed.

[0130] Further, the first connection portion 270-3 belonging to the effective pixel 310-3 overlaps a corner of the effective pixel 310-3 in a plan view (the upper left corner in the figure), and is disposed so as to overlap also with the pixel separation portion 410 that contacts the corner of the effective pixel 310-3.

[0131] Moreover, the N-type transistor 321-3 belonging to the effective pixel 310-3 is provided at a position where the effective pixel 310-3 and the first connection unit 270-3 overlap in a planar view. Furthermore, the N-type transistor 322-3 belonging to the effective pixel 310-3 is provided from the position where the effective pixel 310-3 and the first connection unit 270-3 overlap in a planar view to a position where only the effective pixel 310-3 is disposed.

[0132] Further, the first connection portion 270-4 belonging to the effective pixel 310-4 overlaps a corner of the effective pixel 310-4 in a plan view (the upper left corner in the figure), and is disposed so as to overlap also with the pixel separation portion 410 that contacts the corner of the effective pixel 310-4.

[0133] Moreover, the N-type transistor 321-4 belonging to the effective pixel 310-4 is provided at a position where the effective pixel 310-4 and the first connection unit 270-4 overlap in a planar view. Furthermore, the N-type transistor 322-4 belonging to the effective pixel 310-4 is provided from the position where the effective pixel 310-4 and the first connection unit 270-4 overlap in a planar view to a position where only the effective pixel 310-4 is disposed.

[0134] Fig. 13 is a plan view showing an example of the arrangement of vias 402, 405 with respect to the first connection portion 270 according to the embodiment of the present disclosure. As shown in Fig. 13, the first connection portion 270 according to the embodiment has a rectangular shape in a plan view. In the example of Fig. 13, two vias 402 and two vias 405 are connected to the rectangular first connection portion 270.

[0135] In this way, by connecting two vias 402 and two vias 405 to one first connection portion 270, the electrical resistance between the light receiving circuit 211 and the address event detection circuit 231 can be reduced.

[0136] Therefore, according to the embodiment, the signal detected by the photodiode 311 of the light receiving circuit 211 can be transferred to the address event detection circuit 231 at high speed, thereby enabling even faster processing to be performed in the asynchronous solid-state imaging element 200.

[0137] In the example of FIG. 13, the via 402 and the via 405 are arranged so as to overlap in a planar view, but the via 402 and the via 405 do not have to be arranged so as to overlap in a planar view.

[0138] Furthermore, the planar shape of the first connection portion 270 according to the embodiment is not limited to a rectangular shape. Fig. 14 is a plan view showing an example of the arrangement of vias 402, 405 with respect to another first connection portion 270 according to the embodiment of the present disclosure.

[0139] 14, the first connection portion 270 is circular in plan view. Two vias 402 and two vias 405 are connected to the circular first connection portion 270. In the example of FIG. 14, the planar shape of the first connection portion 270 may be elliptical.

[0140] Fig. 15 is a plan view showing an example of the arrangement of vias 402, 405 with respect to another first connection portion 270 according to an embodiment of the present disclosure. In the example of Fig. 15, the first connection portion 270 has a hexagonal shape in a plan view. Two vias 402 and two vias 405 are connected to the hexagonal first connection portion 270.

[0141] In the example of FIG. 15, by forming the first connection portions 270 in a hexagonal shape, the first connection portions 270 can be arranged in closest packing at the joint 203.

[0142] Fig. 16 is a plan view showing an example of the arrangement of vias 402, 405 with respect to another first connection portion 270 according to an embodiment of the present disclosure. In the example of Fig. 16, the first connection portion 270 has an octagonal shape in a plan view. Two vias 402 and two vias 405 are connected to the octagonal first connection portion 270.

[0143] Furthermore, the number of vias 402 and vias 405 connected to first connection portion 270 according to the embodiment is not limited to 2. Fig. 17 is a plan view showing another example of the arrangement of vias 402, 405 with respect to first connection portion 270 according to the embodiment of the present disclosure.

[0144] 17, the first connection portion 270 has a rectangular shape in a plan view. One via 402 and one via 405 are connected to the rectangular first connection portion 270. In the example of FIG. 17, the planar shape of the first connection portion 270 may be a circle, an ellipse, a hexagon, an octagon, or the like.

[0145] Fig. 18 is a plan view showing another example of the arrangement of the vias 402, 405 with respect to the first connection portion 270 according to the embodiment of the present disclosure. In the example of Fig. 18, the first connection portion 270 has a rectangular shape in a plan view.

[0146] Four vias 402 and four vias 405 are connected to the rectangular first connection portion 270. In the example of Fig. 18, the planar shape of the first connection portion 270 may be a circle, an ellipse, a hexagon, an octagon, or the like.

[0147] Fig. 19 is a plan view showing another example of the arrangement of the vias 402, 405 with respect to the first connection portion 270 according to the embodiment of the present disclosure. In the example of Fig. 19, the first connection portion 270 has a rectangular shape in a plan view.

[0148] Five vias 402 and five vias 405 are connected to the rectangular first connection portion 270. In the example of Fig. 19, the planar shape of the first connection portion 270 may be a circle, an ellipse, a hexagon, an octagon, or the like.

[0149] In the examples of Figures 13 to 19, the same number of vias 402 and vias 405 are connected to one first connection portion 270, but a different number of vias 402 and vias 405 may be connected to one first connection portion 270.

[0150] In addition, in the examples of FIGS. 13 to 19, the planar shapes of the vias 402 and 405 are rectangular, but the planar shapes of the vias 402 and 405 are not limited to rectangular.

[0151] 20 is a plan view showing another example of arrangement of the vias 402, 405 with respect to the first connection portion 270 according to the embodiment of the present disclosure. As shown in FIG 20, the vias 402 and 405 having circular planar shapes may be connected to one first connection portion 270.

[0152] [Various variations] Next, various modified examples of the embodiment will be described with reference to Fig. 21 to Fig. 26. Fig. 21 is a diagram showing a circuit configuration of an effective pixel 310 according to Modification 1 of the embodiment of the present disclosure. Note that in the various modified examples below, illustrations of the components subsequent to the buffer 330 in the address event detection circuit 231 are omitted.

[0153] 21, Modification 1 differs from the embodiment in that a gradation acquisition circuit 370 is provided in the effective pixel 310. The gradation acquisition circuit 370 is connected to the drain of the N-type transistor 321 in the current-voltage conversion circuit 320 via a second connection portion 371.

[0154] In the solid-state imaging element 200 according to the first modification, the gradation acquisition circuit 370 is used to detect the amount of current flowing through the N-type transistor 321, thereby making it possible to acquire the absolute value of the luminance in the effective pixel 310 (i.e., the gradation of the effective pixel 310).

[0155] In other words, in the solid-state imaging element 200 according to the first modification, it is possible to detect, as an address event, that the absolute value of the amount of change in luminance for each of the plurality of pixels exceeds a threshold value, and to acquire the gradation for each of the plurality of pixels.

[0156] Here, in the first modification, the light receiving circuit 211 and the gradation acquisition circuit 370 that belong to the same effective pixel 310 are electrically connected by a second connection portion 371 provided at the joint portion 203 between the light receiving substrate 201 and the circuit substrate 202. The second connection portion 371 is composed of a first pad and a second pad, which are not shown.

[0157] The first pad is exposed on the surface of the light receiving substrate 201 opposite to the light incident surface (i.e., the interface with the circuit substrate 202) and is made of copper or a copper alloy. The second pad is exposed on the surface of the circuit substrate 202 on the light incident surface (i.e., the interface with the light receiving substrate 201) and is made of copper or a copper alloy.

[0158] In the first modification, the first pad and the second pad are directly bonded by Cu-Cu bonding to form the second connection portion 371. In the first modification, one second connection portion 371 is provided for each of the effective pixels 310.

[0159] In this manner, in the first modification, all of the light receiving circuits 211 and the gradation acquisition circuit 370 are electrically connected by the second connection portions 371 formed by Cu-Cu bonding.

[0160] This makes it possible to reduce the number of wirings that need to be connected in the via arrangement sections 221, 222, 261, and 262 (see FIGS. 3 and 4), and therefore the area of ​​the via arrangement sections 221, 222, 261, and 262 can be reduced.

[0161] Therefore, according to the first modification, the additional effective pixels 310 can be arranged in the areas where the via arrangement portions 221, 222, 261, and 262 are reduced, so that the resolution of the solid-state imaging element 200 can be improved.

[0162] In addition, in the first modified example, the light receiving circuit 211 and the gradation acquisition circuit 370 are electrically connected by the second connection portion 371 formed by a Cu-Cu bond, so that the electrical resistance between the light receiving circuit 211 and the gradation acquisition circuit 370 can be reduced.

[0163] This allows a signal related to the luminance of light incident on the photodiode 311 of the light receiving circuit 211 to be transferred at high speed to the gradation acquisition circuit 370. Therefore, according to the first modification, the asynchronous solid-state imaging element 200 can perform even faster processing.

[0164] 22 is a plan view showing an example of the arrangement of the first connection portion 270 and the second connection portion 371 in an effective pixel 310 according to Modification 1 of the embodiment of the present disclosure. For ease of understanding, the first connection portion 270 and the second connection portion 371 are depicted as circles in FIGS. 22 to 24.

[0165] In the example of Figure 22, the first connection section 270-1 belonging to effective pixel 310-1 is arranged so as to overlap one side of effective pixel 310-1 (the left side in the figure) in a planar view and also overlap the pixel separation section 410 that is in contact with that side of effective pixel 310-1.

[0166] In addition, the second connection portion 371-1 belonging to the effective pixel 310-1 is arranged so as to overlap another side of the effective pixel 310-1 (the upper side in the figure) in a planar view and also overlap the pixel separation portion 410 that is in contact with the other side of the effective pixel 310-1.

[0167] Similarly, in the example of Figure 22, the first connection section 270-2 belonging to effective pixel 310-2 is arranged so as to overlap one side of effective pixel 310-2 (the left side in the figure) in a planar view and also overlap the pixel separation section 410 that is in contact with one side of effective pixel 310-2.

[0168] Furthermore, the second connection portion 371-2 belonging to the effective pixel 310-2 is arranged so as to overlap another side of the effective pixel 310-2 (the upper side in the figure) in a planar view and also overlap the pixel separation portion 410 that contacts the other side of the effective pixel 310-2.

[0169] Further, the first connection portion 270-3 belonging to the effective pixel 310-3 overlaps one side of the effective pixel 310-3 in a plan view (the left side in the figure), and is disposed so as to overlap also with the pixel separation portion 410 that contacts the one side of the effective pixel 310-3.

[0170] Furthermore, the second connection portion 371-3 belonging to the effective pixel 310-3 is arranged so as to overlap another side of the effective pixel 310-3 (the upper side in the figure) in a planar view and also overlap the pixel separation portion 410 that contacts the other side of the effective pixel 310-3.

[0171] Further, the first connection portion 270-4 belonging to the effective pixel 310-4 overlaps one side of the effective pixel 310-4 in a plan view (the left side in the figure), and is disposed so as to overlap also with the pixel separation portion 410 that contacts one side of the effective pixel 310-4.

[0172] Furthermore, the second connection portion 371-4 belonging to the effective pixel 310-4 is arranged so as to overlap another side of the effective pixel 310-4 (the upper side in the figure) in a planar view and also overlap the pixel separation portion 410 that contacts the other side of the effective pixel 310-4.

[0173] The arrangement of the first connection portion 270 and the second connection portion 371 in the effective pixel 310 is not limited to the example in Fig. 22. Fig. 23 is a plan view showing another example arrangement of the first connection portion 270 in the effective pixel 310 according to the first modification of the embodiment of the present disclosure.

[0174] In the example of FIG. 23, the first connection portion 270-1 and the second connection portion 371-1 belonging to the effective pixel 310-1 are arranged so as to overlap the effective pixel 310-1 in a plan view but not to overlap the pixel separation portion 410 that contacts the effective pixel 310-1.

[0175] Similarly, in the example of FIG. 23, the first connection portion 270-2 and the second connection portion 371-2 belonging to effective pixel 310-2 are arranged so as to overlap effective pixel 310-2 in a planar view, but not to overlap pixel separation portion 410 that contacts effective pixel 310-2.

[0176] Furthermore, the first connection portion 270-3 and the second connection portion 371-3 belonging to the effective pixel 310-3 overlap the effective pixel 310-3 in a plan view, but are disposed so as not to overlap the pixel separation portion 410 that contacts the effective pixel 310-3.

[0177] Furthermore, the first connection portion 270-4 and the second connection portion 371-4 belonging to the effective pixel 310-4 overlap the effective pixel 310-4 in a plan view, but are disposed so as not to overlap the pixel separation portion 410 that contacts the effective pixel 310-4.

[0178] Fig. 24 is a plan view showing another example arrangement of the first connection portion 270 and the second connection portion 371 in the effective pixel 310 according to the first modification of the embodiment of the present disclosure. In the example of Fig. 24, the first connection portion 270-1 belonging to the effective pixel 310-1 is arranged so as to overlap a corner of the effective pixel 310-1 in plan view (the upper left corner in the figure) and also overlap a pixel separation portion 410 that contacts the corner of the effective pixel 310-1.

[0179] Further, the second connection portion 371-1 belonging to the effective pixel 310-1 overlaps the effective pixel 310-1 in a plan view, but is disposed so as not to overlap the pixel separation portion 410 that contacts the effective pixel 310-1.

[0180] Similarly, in the example of Figure 24, the first connection section 270-2 belonging to effective pixel 310-2 is arranged so as to overlap a corner of effective pixel 310-2 in a planar view (the upper left corner in the figure) and also overlap the pixel separation section 410 that is in contact with the corner of effective pixel 310-2.

[0181] Furthermore, the second connection portion 371-2 belonging to the effective pixel 310-2 overlaps the effective pixel 310-2 in a plan view, but is disposed so as not to overlap the pixel separation portion 410 that contacts the effective pixel 310-2.

[0182] Further, the first connection portion 270-3 belonging to the effective pixel 310-3 overlaps a corner of the effective pixel 310-3 in a plan view (the upper left corner in the figure), and is disposed so as to overlap also with the pixel separation portion 410 that contacts the corner of the effective pixel 310-3.

[0183] Furthermore, the second connection portion 371-3 belonging to the effective pixel 310-3 overlaps the effective pixel 310-3 in a plan view, but is disposed so as not to overlap the pixel separation portion 410 that contacts the effective pixel 310-3.

[0184] Further, the first connection portion 270-4 belonging to the effective pixel 310-4 overlaps a corner of the effective pixel 310-4 in a plan view (the upper left corner in the figure), and is disposed so as to overlap also with the pixel separation portion 410 that contacts the corner of the effective pixel 310-4.

[0185] Furthermore, the second connection portion 371-4 belonging to the effective pixel 310-4 is arranged so as to overlap the effective pixel 310-4 in a plan view but not overlap the pixel separation portion 410 that contacts the effective pixel 310-3.

[0186] In the examples of FIGS. 22 to 24, the first connection portion 270 and the second connection portion 371 belonging to each effective pixel 310 may be arranged in an interchangeable manner.

[0187] Fig. 25 is a diagram showing a circuit configuration of an effective pixel 310 according to Modification 2 of the embodiment of the present disclosure. As shown in Fig. 25, Modification 2 differs from the embodiment in that the drains of the N-type transistors 321 belonging to the multiple effective pixels 310 are connected to a power supply wiring 422 (i.e., a power supply voltage VDD) via the same third connection portion 380.

[0188] The third connection portion 380 is composed of a first pad and a second pad, not shown.

[0189] The first pad is exposed on the surface of the light receiving substrate 201 opposite to the light incident surface (i.e., the interface with the circuit substrate 202) and is made of copper or a copper alloy. The second pad is exposed on the surface of the circuit substrate 202 on the light incident surface (i.e., the interface with the light receiving substrate 201) and is made of copper or a copper alloy.

[0190] In the second modification, the first pad and the second pad are directly bonded by Cu-Cu bonding to form the third connection portion 380. In the second modification, one third connection portion 380 is shared by a plurality of (two in the figure) effective pixels 310.

[0191] In this manner, in the second modification, the drain of N-type transistor 321 and power supply line 422 are electrically connected by third connection portion 380 formed by a Cu—Cu junction.

[0192] This makes it possible to reduce the number of wirings that need to be connected in the via arrangement sections 221, 222, 261, and 262 (see FIGS. 3 and 4), and therefore the area of ​​the via arrangement sections 221, 222, 261, and 262 can be reduced.

[0193] Therefore, according to the second modification, the additional effective pixels 310 can be arranged in the areas where the via arrangement portions 221, 222, 261, and 262 are reduced, so that the resolution of the solid-state imaging element 200 can be improved.

[0194] Moreover, in the second modification, one third connection portion 380 is shared by a plurality of effective pixels 310, thereby making it possible to reduce the number of third connection portions 380 in the solid-state imaging element 200. Therefore, according to the second modification, connection portions (first connection portion 270, second connection portion 371) different from the third connection portion 380 can be easily disposed in the joint portion 203.

[0195] In the example of FIG. 25, one third connection portion 380 is shared by two effective pixels 310, but one third connection portion 380 may be shared by three or more effective pixels 310.

[0196] FIG. 26 is a diagram showing a circuit configuration of an effective pixel 310 according to a third modification of the embodiment of the present disclosure, and shows a quantizer 350 that detects the presence or absence of a selected on-event or off-event.

[0197] Quantizer 350 according to the third modification includes a P-type transistor 351, an N-type transistor 352, and a switch 355. P-type transistor 351 and N-type transistor 352 are connected in series in this order between a terminal for a power supply voltage VDD and a terminal for a ground potential.

[0198] The gate of P-type transistor 351 is connected to the output terminal of subtractor 340. The gate of N-type transistor 352 is connected to switch 355.

[0199] Then, the control unit 130 switches the switch 355 to apply a bias voltage V bon or the bias voltage V that indicates the lower threshold boff A connection point 356 of the P-type transistor 351 and the N-type transistor 352 is connected to a transfer circuit 360.

[0200] A bias voltage V bon is applied, in the quantizer 350 according to the third modification, the voltage at the connection point 356 is the on-event detection signal V CH to the transfer circuit 360.

[0201] On the other hand, a bias voltage V boff is applied, in the quantizer 350 according to the third modification, the voltage at the connection point 356 is equal to the off-event detection signal V CL to the transfer circuit 360.

[0202] With this configuration, the quantizer 350 according to the third modification generates a high-level on-event detection signal V when the differential signal exceeds the upper limit threshold value in a case where an on-event is selected by the control unit 130. CH Output.

[0203] On the other hand, in the quantizer 350 according to the third modification, when an off-event is selected by the control unit 130, if the differential signal falls below the lower limit threshold, the quantizer 350 outputs a low-level off-event detection signal V CL Output.

[0204] For example, in the solid-state imaging device 200 according to the third modification, when a light source (not shown) is turned on by a command from the control unit 130 or the like, the control unit 130 selects an on-event, and generates an on-event detection signal V CH can be output efficiently.

[0205] In the solid-state imaging device 200 according to the third modification, when a light source (not shown) is turned off by a command from the control unit 130 or the like, the control unit 130 selects an off event, so that an off event detection signal V CL can be output efficiently.

[0206] In the third modification described above, the number of transistors constituting the quantizer 350 can be reduced, so that the chip area of ​​the solid-state imaging element 200 can be reduced and the power consumption of the solid-state imaging element 200 can be reduced.

[0207] [effect] The solid-state imaging element 200 according to the embodiment includes a light receiving substrate 201, a circuit substrate 202, and a plurality of first connection parts 270. The light receiving substrate 201 includes a plurality of light receiving circuits 211 in which photoelectric conversion elements (photodiodes 311) are provided. The circuit substrate 202 includes a plurality of address event detection circuits 231 that are directly bonded to the light receiving substrate 201 and detect voltage changes output from the photoelectric conversion elements (photodiodes 311) of the plurality of light receiving circuits 211. The plurality of first connection parts 270 are provided at a bonding portion 203 between the light receiving substrate 201 and the circuit substrate 202, and electrically connect the corresponding light receiving circuits 211 and the address event detection circuits 231.

[0208] This makes it possible to improve the resolution of the solid-state imaging device 200.

[0209] Moreover, in the solid-state imaging device 200 according to the embodiment, the first connection sections 270 are located between the corresponding light receiving circuits 211 and the corresponding address event detection circuits 231 .

[0210] This allows the asynchronous solid-state imaging device 200 to perform even faster processing.

[0211] In the solid-state imaging element 200 according to the embodiment, at least one of the multiple first connection portions 270 has a first pad 403 formed on the bonding surface of the light receiving substrate 201 and a second pad 404 formed on the bonding surface of the circuit substrate 202. The first pad 403 and the second pad 404 are made of the same material.

[0212] This makes it possible to form a large number of first connection sections 270 in the solid-state imaging device 200 in a single process.

[0213] In the solid-state imaging element 200 according to the embodiment, the first pad 403 and the second pad 404 are directly bonded to each other.

[0214] This makes it possible to form a large number of first connection sections 270 in the solid-state imaging device 200 in a single process.

[0215] Moreover, in the solid-state imaging element 200 according to the embodiment, the circuit board 202 has a plurality of gradation acquisition circuits 370 that acquire the gradation of light incident on the photoelectric conversion elements (photodiodes 311) of the plurality of light receiving circuits 211. The solid-state imaging element 200 according to the embodiment includes a plurality of second connection parts 371 that are provided at the joint part 203 between the light receiving board 201 and the circuit board 202 and electrically connect the corresponding light receiving circuits 211 and the gradation acquisition circuits 370.

[0216] This makes it possible to improve the resolution of the solid-state imaging device 200.

[0217] Moreover, the solid-state imaging element 200 according to the embodiment includes a plurality of third connection parts 380 that are provided at the joint 203 between the light receiving substrate 201 and the circuit substrate 202 and connect between the photoelectric conversion elements (photodiodes 311) and the power supply voltage VDD. At least one of the plurality of third connection parts 380 is shared by the plurality of photoelectric conversion elements (photodiodes 311).

[0218] This makes it possible to easily arrange a connection portion (first connection portion 270, second connection portion 371) different from the third connection portion 380 in the joint portion 203.

[0219] [Second configuration example of the address event detector] Fig. 27 is a block diagram showing a second configuration example of the address event detection section 1000. As shown in Fig. 27, the address event detection section 1000 according to this configuration example has a storage section 1336 and a control section 1337 in addition to a current-voltage conversion section 1331, a buffer 1332, a subtractor 1333, a quantizer 1334, and a transfer section 1335.

[0220] The storage unit 1336 is provided between the quantizer 1334 and the transfer unit 1335, and accumulates the output of the quantizer 1334, i.e., the comparison result of the comparator 1334a, based on a sample signal supplied from the control unit 1337. The storage unit 1336 may be a sampling circuit such as a switch, a plastic, or a capacitor, or may be a digital memory circuit such as a latch or a flip-flop.

[0221] The control unit 1337 supplies a predetermined threshold voltage Vth to the inverting (-) input terminal of the comparator 1334a. The threshold voltage Vth supplied from the control unit 1337 to the comparator 1334a may have different voltage values ​​in a time-division manner. For example, the control unit 1337 supplies a threshold voltage Vth1 corresponding to an ON event indicating that the amount of change in the photocurrent has exceeded an upper threshold, and a threshold voltage Vth2 corresponding to an OFF event indicating that the amount of change has fallen below a lower threshold, at different timings, thereby enabling detection of multiple types of address events with one comparator 1334a.

[0222] For example, the storage unit 1336 may accumulate a comparison result of the comparator 1334a using the threshold voltage Vth1 corresponding to an ON event during a period in which the threshold voltage Vth2 corresponding to an OFF event is supplied from the control unit 1337 to the inverting (-) input terminal of the comparator 1334a. The storage unit 1336 may be located inside the pixel 2030 (see FIG. 28) or outside the pixel 2030. The storage unit 1336 is not an essential component of the address event detection unit 1000. That is, the storage unit 1336 may be omitted.

[0223] [Imaging device according to the second configuration example (scanning method)] The imaging device 100 according to the first configuration example described above is an asynchronous imaging device that reads out events by an asynchronous readout method. However, the event readout method is not limited to the asynchronous readout method, and may be a synchronous readout method. An imaging device to which the synchronous readout method is applied is a scanning imaging device, the same as a normal imaging device that captures images at a predetermined frame rate.

[0224] FIG. 28 is a block diagram showing an example of the configuration of an imaging device according to the second configuration example, that is, a scanning type imaging device, used as the imaging device 2000 in an imaging system to which the technology according to the present disclosure is applied.

[0225] As shown in FIG. 28, an imaging device 2000 according to a second configuration example as an imaging device of the present disclosure includes a pixel array section 2021, a driving section 2022, a signal processing section 2025, a readout area selection section 2027, and a signal generation section 2028.

[0226] The pixel array unit 2021 includes a plurality of pixels 2030. The plurality of pixels 2030 output an output signal in response to a selection signal from the readout region selection unit 2027. Each of the plurality of pixels 2030 may be configured to have a quantizer comparator within the pixel. The plurality of pixels 2030 output an output signal corresponding to the amount of change in light intensity. The plurality of pixels 2030 may be two-dimensionally arranged in a matrix as shown in FIG. 28.

[0227] The driving unit 2022 drives each of the multiple pixels 2030 to output a pixel signal generated in each pixel 2030 to the signal processing unit 2025. The driving unit 2022 and the signal processing unit 2025 are circuit units for acquiring gradation information. Therefore, when only event information is acquired, the driving unit 2022 and the signal processing unit 2025 may not be provided.

[0228] The readout region selection unit 2027 selects a part of the multiple pixels 2030 included in the pixel array unit 2021. Specifically, the readout region selection unit 2027 determines the selection region in response to a request from each pixel 2030 of the pixel array unit 2021. For example, the readout region selection unit 2027 selects any one or more rows among the rows included in the two-dimensional matrix structure corresponding to the pixel array unit 2021. The readout region selection unit 2027 sequentially selects one or more rows according to a preset period. The readout region selection unit 2027 may also determine the selection region in response to a request from each pixel 2030 of the pixel array unit 2021.

[0229] The signal generating unit 2028 generates an event signal corresponding to an active pixel that detects an event among the selected pixels, based on the output signal of the pixel selected by the readout region selecting unit 2027. An event is an event in which the intensity of light changes. An active pixel is a pixel in which the amount of change in the intensity of light corresponding to the output signal exceeds or falls below a preset threshold. For example, the signal generating unit 2028 compares the output signal of the pixel with a reference signal, detects an active pixel that outputs an output signal when the output signal is greater or smaller than the reference signal, and generates an event signal corresponding to the active pixel.

[0230] The signal generating unit 2028 may be configured to include, for example, a column selection circuit that arbitrates signals coming into the signal generating unit 2028. The signal generating unit 2028 may be configured to output not only information about active pixels that detect an event, but also information about inactive pixels that do not detect an event.

[0231] Address information and time stamp information (e.g., (X, Y, T)) of an active pixel in which an event is detected are output from the signal generating unit 2028 through an output line 2015. However, the data output from the signal generating unit 2028 may be not only address information and time stamp information but also frame format information (e.g., (0, 0, 1, 0,...)).

[0232] [Range measurement system] The distance measuring system according to the embodiment of the present disclosure is a system for measuring the distance to a subject using a structured light technique. The distance measuring system according to the embodiment of the present disclosure can also be used as a system for acquiring a three-dimensional (3D) image, and in this case, can be called a three-dimensional image acquisition system. In the structured light method, distance measurement is performed by identifying the coordinates of a point image and the light source (so-called point light source) from which the point image is projected by pattern matching.

[0233] FIG. 29 is a schematic diagram showing an example of the configuration of a distance measuring system according to an embodiment of the present disclosure, and FIG. 30 is a block diagram showing an example of a circuit configuration.

[0234] The distance measuring system 3000 according to this embodiment uses a surface emitting semiconductor laser, for example, a vertical cavity surface emitting laser (VCSEL) 3010 as a light source unit, and an event detection sensor 3020 called a DVS as a light receiving unit. The vertical cavity surface emitting laser (VCSEL) 3010 projects a predetermined pattern of light onto a subject. In addition to the vertical cavity surface emitting laser 3010 and the event detection sensor 3020, the distance measuring system 3000 according to this embodiment includes a system control unit 3030, a light source driving unit 3040, a sensor control unit 3050, a light source side optical system 3060, and a camera side optical system 3070.

[0235] The system control unit 3030 is configured by, for example, a processor (CPU), and drives the vertical cavity surface emitting laser 3010 via the light source driving unit 3040, and drives the event detection sensor 3020 via the sensor control unit 3050. More specifically, the system control unit 3030 controls the vertical cavity surface emitting laser 3010 and the event detection sensor 3020 in synchronization with each other.

[0236] In the distance measuring system 3000 according to the present embodiment having the above configuration, light of a predetermined pattern emitted from the vertical cavity surface emitting laser 3010 is projected onto the subject (measurement target) 3100 through the light source side optical system 3060. This projected light is reflected by the subject 3100. Then, the light reflected by the subject 3100 is incident on the event detection sensor 3020 through the camera side optical system 3070. The event detection sensor 3020 receives the light reflected by the subject 3100, and detects that a luminance change of a pixel exceeds a predetermined threshold as an event. Event information detected by the event detection sensor 3020 is supplied to an application processor 3200 outside the distance measuring system 3000. The application processor 3200 performs a predetermined process on the event information detected by the event detection sensor 3020.

[0237] Although the embodiments of the present disclosure have been described above, the technical scope of the present disclosure is not limited to the above-described embodiments, and various modifications are possible without departing from the gist of the present disclosure. In addition, components of different embodiments and modifications may be appropriately combined.

[0238] Furthermore, the effects described in this specification are merely examples and are not limiting, and other effects may also be present.

[0239] The present technology can also be configured as follows. (1) a light-receiving substrate having a plurality of light-receiving circuits on which photoelectric conversion elements are provided; a circuit board directly bonded to the light receiving substrate, the circuit board having a plurality of address event detection circuits each detecting a voltage change output from the photoelectric conversion element of each of the light receiving circuits; a plurality of first connection parts provided at a joint between the light receiving board and the circuit board, electrically connecting the corresponding light receiving circuit and the address event detection circuit; A solid-state imaging element comprising: (2) The first connection parts are located between the corresponding light receiving circuits and the corresponding address event detection circuits. The solid-state imaging device according to (1) above. (3) At least one of the plurality of first connection portions has a first pad formed on a bonding surface of the light receiving substrate and a second pad formed on a bonding surface of the circuit substrate, The first pad and the second pad are made of the same material. The solid-state imaging device according to (1) or (2). (4) The first pad and the second pad are directly bonded to each other. The solid-state imaging device according to (3) above. (5) the circuit board includes a plurality of tone acquisition circuits each configured to acquire a tone of light incident on the photoelectric conversion element of each of the plurality of light receiving circuits; a plurality of second connection parts provided at a joint between the light receiving board and the circuit board, electrically connecting the corresponding light receiving circuit and the corresponding gradation acquisition circuit; The solid-state imaging device according to any one of (1) to (4). (6) a plurality of third connection parts provided at a joint between the light receiving substrate and the circuit substrate, the third connection parts connecting the photoelectric conversion elements and a power supply voltage; At least one of the plurality of third connection parts is shared by a plurality of the photoelectric conversion elements. The solid-state imaging device according to any one of (1) to (5) above. (7) Lenses and A solid-state imaging element; A control unit that controls the solid-state imaging element, The solid-state imaging device includes: a light-receiving substrate having a plurality of light-receiving circuits on which photoelectric conversion elements are provided; a circuit board directly bonded to the light receiving substrate, the circuit board having a plurality of address event detection circuits each detecting a voltage change output from the photoelectric conversion element of each of the light receiving circuits; a plurality of connection parts provided at a joint between the light receiving board and the circuit board, electrically connecting the corresponding light receiving circuits and the address event detection circuits; a signal processing unit that processes an output of the solid-state imaging device; An imaging device having the above configuration. (8) The first connection parts are located between the corresponding light receiving circuits and the corresponding address event detection circuits. The imaging device according to (7) above. (9) At least one of the plurality of first connection portions has a first pad formed on a bonding surface of the light receiving substrate and a second pad formed on a bonding surface of the circuit substrate, The first pad and the second pad are made of the same material. The imaging device according to (7) or (8). (10) The first pad and the second pad are directly bonded to each other. The imaging device according to (9) above. (11) the circuit board includes a plurality of tone acquisition circuits each configured to acquire a tone of light incident on the photoelectric conversion element of each of the plurality of light receiving circuits; a plurality of second connection parts provided at a joint between the light receiving board and the circuit board, electrically connecting the corresponding light receiving circuit and the corresponding gradation acquisition circuit; The imaging device according to any one of (7) to (10) above. (12) a plurality of third connection parts provided at a joint between the light receiving substrate and the circuit substrate, the third connection parts connecting the photoelectric conversion elements and a power supply voltage; At least one of the plurality of third connection parts is shared by a plurality of the photoelectric conversion elements. The imaging device according to any one of (7) to (11) above. [Explanation of symbols]

[0240] 100 Imaging device 110 Lens 130 Control section 200 Solid-state image sensor 201 Light receiving board 202 Circuit Board 203 Joint 211 Photoreceiving circuit 231 Address Event Detector 270, 270-1 to 270-4 First connection part 310 effective pixels 311 Photodiode (an example of a photoelectric conversion element) 371, 371-1 to 371-4 Second connection part 380 Third Connection 403 1st Pad 404 2nd Pad

Claims

1. a light-receiving substrate having a plurality of light-receiving circuits on which photoelectric conversion elements are provided; a circuit board directly bonded to the light receiving substrate, the circuit board having a plurality of address event detection circuits each detecting a voltage change output from the photoelectric conversion element of each of the light receiving circuits; a plurality of first connection parts provided at a joint between the light receiving board and the circuit board, the first connection parts electrically connecting the corresponding light receiving circuits and the address event detection circuits; a plurality of third connection parts provided at a joint between the light receiving substrate and the circuit substrate, the third connection parts connecting the photoelectric conversion elements and a power supply voltage; Equipped with At least one of the plurality of third connection parts is shared by a plurality of the photoelectric conversion elements. Solid-state imaging element.

2. The first connection parts are located between the corresponding light receiving circuits and the corresponding address event detection circuits. The solid-state imaging device according to claim 1 .

3. At least one of the plurality of first connection portions has a first pad formed on a bonding surface of the light receiving substrate and a second pad formed on a bonding surface of the circuit substrate, The first pad and the second pad are made of the same material.

3. The solid-state imaging device according to claim 1.

4. The first pad and the second pad are directly bonded to each other. The solid-state imaging device according to claim 3 .

5. the circuit board includes a plurality of tone acquisition circuits each configured to acquire a tone of light incident on the photoelectric conversion element of each of the plurality of light receiving circuits; a plurality of second connection parts provided at a joint between the light receiving board and the circuit board, electrically connecting the corresponding light receiving circuit and the corresponding gradation acquisition circuit; 5. The solid-state imaging device according to claim 1.

6. Lenses and A solid-state imaging element; A control unit that controls the solid-state imaging element, The solid-state imaging device includes: a light-receiving substrate having a plurality of light-receiving circuits on which photoelectric conversion elements are provided; a circuit board directly bonded to the light receiving substrate, the circuit board having a plurality of address event detection circuits each detecting a voltage change output from the photoelectric conversion element of each of the light receiving circuits; a plurality of first connection parts provided at a joint between the light receiving board and the circuit board, the first connection parts electrically connecting the corresponding light receiving circuits and the address event detection circuits; a plurality of third connection parts provided at a joint between the light receiving substrate and the circuit substrate, the third connection parts connecting the photoelectric conversion elements and a power supply voltage; a signal processing unit that processes an output of the solid-state imaging device; having At least one of the plurality of third connection parts is shared by a plurality of the photoelectric conversion elements. Imaging device.

7. The first connection parts are located between the corresponding light receiving circuits and the corresponding address event detection circuits. The imaging device according to claim 6.

8. At least one of the plurality of first connection portions has a first pad formed on a bonding surface of the light receiving substrate and a second pad formed on a bonding surface of the circuit substrate, The first pad and the second pad are made of the same material.

8. The imaging device according to claim 6 or 7.

9. The first pad and the second pad are directly bonded to each other. The imaging device according to claim 8.

10. the circuit board includes a plurality of tone acquisition circuits each configured to acquire a tone of light incident on the photoelectric conversion element of each of the plurality of light receiving circuits; The solid-state imaging element has a plurality of second connection parts provided at a joint between the light receiving substrate and the circuit substrate, and electrically connecting the corresponding light receiving circuits and the corresponding gradation acquisition circuits. The imaging device according to any one of claims 6 to 9.

Images