Paralleling power switches

Abstract

To provide paralleling of power switches.SOLUTION: A power switching system includes a plurality of power switching units each including a respective power switch 115, a communication system configured to convey a system-wide switching command to the power switching units along a communication channel, and a circuit, included in each of the power switching units, that is configured to delay execution of the system-wide switching command by a delay.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] This specification relates to paralleling power switches. [Background technology]

[0002] A power switch is a switching device designed to switch relatively high voltages and currents. Examples of power switches include insulated gate bipolar transistors (IGBTs), metal-oxide-semiconductor field effect transistors (MOSFETs), high electron mobility transistors (HEMTs), and the like. These power switches are typically made using semiconductor materials, such as silicon, silicon carbide, gallium nitride, or other semiconductor materials. In some instances, an individual power switch includes more than one physical transistor. For example, two transistors in a cascode configuration may form a power switch.

[0003] In practice, each individual power switch is generally associated with special control, communication, and fault protection circuitry, and the provision of drive signals to the power switches is handled by associated circuitry.

[0004] Even when individual power switches have device characteristics tuned to switch relatively high voltages and currents, individual power switches often cannot meet the demands of some applications. To meet such demands, multiple power switches are often paralleled such that each power switch carries only a portion of the total current. Typically, the total current flowing through an assembly of power switches is monitored.

[0005] Additionally, the voltages across the main terminals of the individual power switches (i.e., collector-to-emitter or drain-to-source voltages) may be monitored for various purposes. For example, special fault protection circuits may monitor such voltages for the individual power switches. Summary of the Invention

[0006] Like reference numbers in the various drawings indicate like elements.

[0007] For purposes of illustration, the detailed description is presented in terms of insulated gate bipolar transistor (IGBT) power switches. However, the corresponding teachings may be applied to a variety of different enhancement or depletion type devices involving electron or hole charge carriers, such as bipolar junction transistors (BJTs), metal-oxide-semiconductor field effect transistors (MOSFETs), or high electron mobility transistors (HEMTs), alone or in combination with other transistors. Devices may be realized in silicon, silicon carbide, gallium nitride, or other semiconductor materials. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a schematic diagram of a system in which the switching of different power switches is ganged to switch total currents and voltages. [Figure 2A] 2A-2D illustrate generally different approaches to determining the current transfer behavior of an IGBT based on VCE sensing information during switching transitions. [Figure 2B] 2A-2D illustrate generally different approaches to determining the current transfer behavior of an IGBT based on VCE sensing information during switching transitions. [Figure 2C] 2A-2D illustrate generally different approaches to determining the current transfer behavior of an IGBT based on VCE sensing information during switching transitions. [Figure 2D] 2A-2D illustrate generally different approaches to determining the current transfer behavior of an IGBT based on VCE sensing information during switching transitions. [Diagram 3] FIG. 3 is a schematic diagram of an embodiment of a power switch and associated circuitry. [Figure 4]FIG. 4 is a swim lane diagram illustrating operation in a system where the switching of different power switches is ganged. [Diagram 5] FIG. 5 is a schematic diagram of a bus structure that can be used to implement a communication channel between a master driver and one or more slave drivers in a system in which the switching of different power switches is ganged. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] The switching of multiple power switches may be ganged, which may be used to achieve any of a number of different purposes and advantages.

[0010] For example, in some implementations described herein, the switching of the power switches is coordinated to ensure that the currents carried by the different switches are balanced. In balanced current sharing, the total current is divided relatively equally among the individual switches. The more evenly the current is distributed among the individual power switches, the fewer switches are required to switch a given total current while ensuring safe operation.

[0011] As an example, assume that 3000A is switched using a power switch with a rated or nominal current of 650A. The nominal or nominal current of a power switch may be defined as the maximum continuous DC current that can safely flow through the power switch under specified conditions, e.g., at a specified maximum junction temperature. Returning to the example, if the current sharing is not balanced, there will likely be a relatively large difference between the currents switched by different switches. For example, when attempting to operate all switches at a target current of 600A, a 15% variation in the currents switched by different power switches will result in one power switch conducting 510A and another conducting 690A. It is likely that the current through at least one switch will be greater than the rated collector current. The designer will accommodate this variation by adding more switches so that the target current delivered by any given switch remains below the rated collector current. For example, instead of operating five switches at a target current of 600A, six switches at a target current of 500A may be used.

[0012] Alternatively, five switches can be used with a target current of 600 A where the current is more evenly distributed and the current sharing is better balanced (e.g., for a target current of 600 A, the currents switched by different switches vary by only 5%). Furthermore, a relatively large safety margin relative to the maximum rated current of the switches can be maintained.

[0013] As another example, in some implementations described herein, the switching of the power switches is coordinated to ensure that the currents carried by different switches are not balanced. Unlike balanced current sharing, unbalanced current sharing distributes the total current unevenly among the power switches. Even if the switches nominally have the same power rating (i.e., the same voltage and current capacity) or are of the same type (i.e., the same within manufacturing tolerances), the current may be distributed unevenly.

[0014] In some implementations described herein, the intentional unbalancing of currents may address device-to-device variations. The variations may be inherent in the switches (i.e., in the switches at the time of manufacture) or may occur over time. For example, the temperature of the power switches may change or the structure of the power switches may degrade over time. Regardless of their cause, the variations may be addressed, for example, to adjust the switching capacity to more closely match the requirements of the operating context or in response to conditions that arise during operation.

[0015] As an example, again assume that 3000 A is switched using power switches with rated currents of 650 A. Initially, the current is distributed approximately evenly among the five switches with only a 5% variation in the current switched by the different switches for a target current of, say, 600 A. However, assume that at some point during the operational life of the switches, one of the switches begins to degrade. For example, thermal or mechanical fatigue may degrade the performance of one of the switches.

[0016] The life of this deteriorating switch (and therefore the life of the system of switches) can be extended by reducing the current carried through that switch. For example, the target current through the deteriorating power switch can be reduced to 540A while the target current through the other four switches is increased to 615A. If the current through the other four switches remains properly balanced with only a 5% variation, this will keep them all below their 650A maximum rated current, reducing wear on the deteriorating switch. The overall system life can be extended.

[0017] In some implementations described herein, the switching of the different power switches is actively adjusted every switching cycle, and deviations from the desired balancing / unbalancing can be quickly addressed.

[0018] In some implementations described herein, the switching of different power switches is actively coordinated using previously measured information for other reasons, such as to limit overvoltage transients during turn-off switching events. For example, measurements of the voltage across the main terminals of individual power switches can be used to coordinate the switching of different power switches in the system. In some examples, the voltage across the main terminals can be directly sensed. In others, the voltage across the main terminals can be indirectly sensed, such as by measuring the current flow through an impendence network.

[0019] Figure 1 shows the total current I SW 1 is a schematic diagram of a system 100 in which the switching of different power switches is coordinated to switch a voltage Vcc and a voltage Vdc. The system 100 includes a plurality of independent, individually addressable switching units 110, 111, 112. Each switching unit 110, 111, 112 includes an IGBT power switch 115 and an associated switching controller and driver circuit 120. In operation, the switching of the IGBT power switches 115 in the system 100 is coordinated to achieve a desired distribution of current flowing through the IGBT power switches 115.

[0020] More specifically, the illustrated embodiment of system 100 includes three switching units 110, 111, 112. The first of these units, namely unit 110, acts as a "master" and is configured to coordinate the switching of the switching units 110, 111, 112, with adjustments addressed to the individual power switches. Furthermore, the switching units 110 may be coupled to a system controller 105, which is the component responsible for controlling the timing of power switching in system 100 (using system level commands addressed to the entire system 100). System controller 105 may be realized using a microcontroller or a field programmable gate array (FPGA).

[0021] The system controller 105 is communicatively coupled to the switching units 110 by one or more communication channels 117. The system controller 105 is configured to send signals along the channels 117 to the switching units 110. The signals specify when the IGBT power switches 115 switch from an open, substantially non-conducting OFF state to a closed, current conducting ON state and vice versa. However, the switching commands are not addressed individually to any one of the switching units 110, 111, 112 but to the system 100 as a whole. The switching units 110 are configured to receive those system-wide switching commands and are configured to both use them themselves and relay them to the other switching units 111, 112.

[0022] In addition to these system-wide switching commands, the switching unit 110 transmits to each switching unit 111, 112 timing adjustments to be implemented for these system-wide switching commands. Generally, the switching unit 110 also applies its own timing adjustments to the system-wide switching commands. The adjustments are individually tailored and specific to each switching unit 110, 111, 112 and specify relatively fine adjustments of the timing of the off / on and / or on / off transitions of the IGBT power switches 115 in those switching units, as described in detail below. The adjustments further refine the switching in the switching units 110, 111, 112 with greater precision to achieve a desired distribution of the current flowing through the IGBT power switches 115. Although the duration of the relatively fine adjustments is theoretically unlimited, in practice the duration of the adjustments is generally only a factor of less than one times the inherent rise or fall time of the gates for a given set of operating conditions in the system 100. For example, in some embodiments, the adjustment may be between 0 ns and 1000 ns, such as between 0 ns and 300 ns under typical operating conditions.

[0023] Generally, but not limited to, communication along channel 117 is bidirectional, with the switching unit 110 also communicating information to the system controller 105. Examples of information communicated from the master unit 110 to the system controller 105 may include error / fault information and operational information (e.g., temperature).

[0024] In the illustrated embodiment, the switching controller and driver circuitry 120 in the switching units 110, 111, 112 includes an extra switching unit communication circuitry 122 and an intra-switching unit communication circuitry 125. The extra switching unit communication circuitry 122 is circuitry configured to exchange information with components other than the switching units. For example, in switching unit 110, the extra switching unit communication circuitry 122 is configured to exchange information with the system controller 105 over channel 117. Although each switching unit 110, 111, 112 in the illustrated embodiment includes an extra switching unit communication circuitry 122, this is not necessarily the case and in some embodiments the extra switching unit communication circuitry 122 may be omitted from one or both of the slave switching units 111, 112.

[0025] The inter-switching-unit communication circuitry 125 is circuitry configured to exchange commands and information with other switching units in the system 100 over one or more channels 130. The communication along the channels 130 is bidirectional. As described in more detail below, the exchanged information may include operational details communicated from the slave switching units 111, 112 to the master switching unit 110, as well as signals specifying adjustments to the timing of switching transitions of the IGBT power switches 115 in the switching units 111, 112.

[0026] In addition to communication circuits 122, 125, each switching controller and driver circuit 120 includes circuitry for driving a respective IGBT power switch 115 between on and off states, and circuitry for controlling that driving. The drive function is typically achieved using a totem-pole (pull-up, pull-down) driver, although direct drive and other drivers are possible. The control function is to control the collector-to-emitter voltage V CEEach switching unit 110, 111, 112 may include timing adjustments and fault protection functions (e.g., overcurrent protection, overvoltage protection, etc.) that rely on detecting the collector-to-emitter voltage V of the IGBT power switch 115. CE It is possible to detect V CE Sense line 135. As will be described in more detail below, switching controller and driver circuit 120 - Collector-to-emitter voltage V CE the time required for the voltage to fall and / or rise to one or more threshold voltage levels; - Collector-to-emitter voltage V at one or more specified times CE or - both such time and such value, The method may be configured to identify:

[0027] In many embodiments, the communication circuits 122, 125 are connected to the IGBTs 115 and their associated drive circuitry and V CE The switching controller and driver circuit 120 is galvanically isolated from the sense line 135. In these cases, the switching controller and driver circuit 120 includes internal communication circuits and components (e.g., optocouplers, transformers, capacitors, and associated switching circuitry) for bidirectional communication across the galvanic isolation. Bidirectional communication can be achieved through a bidirectional communication channel or through two (or more) unidirectional communication channels communicating in opposite directions. CE A data signal encoding the detected information is included in the communication.

[0028] In some embodiments, the system 100 uses V collected during a previous switching cycle. CEThe sensing information may be used to operate to adjust the timing of switching transitions of the IGBTs 115 in the switching units 110, 111, 112 for each switching cycle. For example, in operation, the system controller 105 may send switching commands along the channel 117 to the switching units 110. The switching commands generally indicate when the IGBTs 115 are to be switched into and out of a conducting state. The switching controller and driver circuit 120 receives the switching commands at the extra-system communication circuit 122. For the first such switching command (e.g., an initial command after start-up or a reset after an abnormal condition), the switching controller and driver circuit 120 in the switching unit 110 relays the switching command to the switching units 110, 111, 112 using the intra-switching-unit communication circuit 125 and the channel 130. Note that by routing the switching command for switching unit 110 through the same inter-switching-unit communication circuitry 125 and channel 130 which conveys the switching command to switching units 111, 112, all of the switching units 110, 111, 112 are subject to the same propagation delay introduced by placing the switching command on channel 130. In other words, all of the switching units 110, 111, 112 respond to a switching command on channel 130. The propagation delay associated with placing that switching command on channel 130 is the same.

[0029] In either case, the switching units 110, 111, 112 receive switching commands on channel 130 and route the switching commands through their respective switching controller and driver circuits 120 to switch their respective IGBTs 115 into and out of conduction states in response to and in accordance with the relayed switching commands. Because each switching controller and driver circuit 120 in the different switching units 110, 111, 112 is substantially identical, this also reduces differences in propagation delays. In some implementations, additional trimming circuitry may be included to further reduce any differences.

[0030] During switching transitions between conduction states, the switching controller and driver circuit 120 in each switching unit controls the respective V CE V to the corresponding IGBT 115 through the sense line 135 CE Each switching controller and driver circuit 120 receives the detection information. - Collector-to-emitter voltage V CE the time required for the voltage to fall and / or rise to one or more threshold voltage levels; - Collector-to-emitter voltage V at one or more specified times CE or - both such time and such value, The device may be configured to measure:

[0031] Thus, the time or value may be measured during either or both of the on / off or off / on transitions. Furthermore, the time or value characterizes the actual current conduction through the IGBT 115 during such transitions. This is in contrast to schemes in which a parameter such as the gate-to-emitter voltage VGE is detected and assumed to follow the current conduction. In particular, the operational current transfer behavior 115 of the IGBT (reflecting manufacturing variations and temperature effects) is detected. In either case, the identified time or value is transmitted from the switching controller and driver circuit 120 in the switching units 111, 112 to the switching unit 110 through a channel 130 using the intra-switching-unit communication circuit 125.

[0032] In some implementations, the clocks in the different switching units 110, 111, 112 may be synchronized, for example using phase locking. In some implementations, the clocks in both the primary and secondary sides of the switching units 110, 111, 112 may be synchronized. As will be explained in more detail below, the synchronized clocks are calculated using the collector-to-emitter voltage V CE for measuring the time required for crossing the thresholds in the different switching units 110, 111, 112, or for measuring the collector-to-emitter voltage V CE For example, in the junctions of Figures 2A, 2B, 2C, and 2D, a synchronized clock may provide a common reference point for points A and C.

[0033] The switching controller and driver circuit 120 in the switching unit 110 determines the relatively finer and more precise adjustments to be made to the timing of the switching transitions of the IGBT power switches 115 in the switching units 110, 111, 112 in the next switching cycle. In the initial switching cycle, all of the adjustments are delays. However, in subsequent cycles, the delays can be made smaller. In some implementations, the adjustments can be broken down into discrete time steps, e.g., 1 nanosecond to 10 nanosecond increments, and are generally only a percentage of the underlying rise or fall time of the gates for a given set of operating conditions. The adjustments are tailored for each switching unit 110, 111, 112. In some examples, the adjustments to the timing of the switching transitions for the switching unit 110 are different from the adjustments to the timing of the switching transitions for the switching unit 111, which in turn are different from the adjustments to the timing of the switching transitions for the switching unit 112.

[0034] In some implementations, the adjustments are designed to gradually approach the desired current distribution over multiple switching cycles. For example, rather than using a relatively large adjustment in an attempt to immediately achieve the desired current distribution in the next switching cycle, a more gradual adjustment may be applied in the next switching cycle that is expected to result in a less uneven current distribution. Similarly, gradual adjustments may be applied in subsequent switching cycles that do not immediately achieve the desired current distribution. Furthermore, after the adjustments are applied, the collector-to-emitter voltage V CEThe timing / value of may indicate that the desired current distribution has been overshot. In other words, the current conducted by a switching unit may be too small before an adjustment is applied. After an adjustment is applied, the current conducted by that same switching unit may be too large. In such cases, an adjustment in the opposite direction (i.e., a "smaller" or even "negative" adjustment) may be applied in a subsequent switching cycle.

[0035] In either case, signals characterizing the adjustments to the switching units 111, 112 are sent from the switching controller and driver circuit 120 in the switching unit 110 to the switching units 111, 112 over channel 130 using the intra-switching unit communication circuit 125. The adjustments are individually addressed to the corresponding switching units 111, 112. - Zero adjustment or no adjustment, - Adjustments to the timing of the execution of the switch-on command, - Adjustments to the timing of execution of the switch-off command, - Adjustment to the timing of execution of both switch-on and switch-off commands; may include.

[0036] The timing adjustment is upon receipt of a switching command by the switching unit in each individual switching cycle, or - relative to the adjusted timing in the previous (e.g. previous or other) switching cycle It can be represented as:

[0037] In the former case, each timing adjustment can be represented solely as zero (i.e., no adjustment) or as a positive value representing a delay in the transition. In the latter case, the timing adjustment can also be a negative value representing an earlier start of the transition than its start in the previous switching cycle.

[0038] In some implementations, the slowest of the switching units 110, 111, 112 is designated as the reference switching unit. To balance the currents between the switching units 110, 111, 112, a signal with a positive value representing a delay may be sent to the remaining of the switching units 110, 111, 112. The collector-to-emitter voltage V CE indicates that the desired current set point has been overshot, the delay period may be adjusted.

[0039] In the above embodiment, the timing of the switching transitions of the IGBTs 115 in the switching units 110, 111, and 112 is determined based on the V CE The timing of the switching transition is adjusted every switching cycle exclusively using the detection information. This is not necessarily the case. For example, in some implementations, the timing of the switching transition need only be adjusted every N switching cycles, where N is greater than 1, or mathematically, N>1. Thus, the switching adjustment may be applied in the next immediately following switching cycle or in another subsequent switching cycle. Adjusting the timing every N switching cycles may provide sufficient time to complete the calculation of the delay period and communicate the relevant information to the device. As another example, in some implementations, the adjustment to the timing of the switching transition may be adjusted using the V CE The detection information may be taken into account, where M is greater than 1, or mathematically, M>1. For example, V CE An average or weighted average of the detection information may be used. In some examples, both N>1 and M>1.

[0040] Further, in the above described embodiment, the switching controller and driver circuit 120 in the switching unit 110 determines the adjustments made to the timing of the switching transitions of the IGBT power switches 115 in the switching units 110, 111, 112. This is not necessarily the case. Rather, in other embodiments, some or all of the decisions may be made elsewhere. For example, in some embodiments, the system controller 105 may determine the adjustments. As another example, in some embodiments, the system controller 105 may determine some of the adjustments and the switching controller and driver circuit 120 in the switching unit 110 may determine others. For example, the switching controller and driver circuit 120 in the switching unit 110 may be responsible for determining adjustments where the currents are balanced, while the system controller 105 may be responsible for determining adjustments where the currents are not balanced. As yet another example, in some embodiments, a human user may specify the adjustments.

[0041] 2A to 2D show the V CE 2A and 2B show schematic diagrams of different approaches for identifying the current transfer behavior of an IGBT based on sensing information. In particular, Fig. 2A and Fig. 2B show the collector-to-emitter voltages V of three different IGBT switches as a function of time during the transition from the OFF state to the ON state in three different switching units. CE and collector current I C 2C and 2D show the collector-to-emitter voltages V of three different switched IGBTs as a function of time during the transition from an on-state to an off-state. CE and collector current I C 1 shows a schematic diagram of a

[0042] 2A-2B is triggered by a switch-on command 205 occurring at time point A. In the context of system 100 (FIG. 1), the switch-on command 205 may be received from the system controller 105 by the master switching unit 110 over communication channel 117. The switch-on command 205 is relayed from the master switching unit 110 to itself and over communication channel 130 to the slave switching units 111, 112.

[0043] It is understood that even if the switching commands are communicated to the switching units 110, 111, 112 through the same communication channel 130, differences in propagation delays still exist in the system 100. In some embodiments, the propagation delays are measured during an initialization stage. Examples are described below. In some embodiments of the system 100 (FIG. 1), the occurrence of the point in time A in the different switching units 110, 111, 112 is defined (at least temporarily) and recorded in the switching controller and driver circuit 120 in the master switching unit 110. In other embodiments, the clocks in the different switching units 110, 111, 112 are synchronized, and the point in time A at which each switch-on command 205 occurs is assumed to be the same in the different switching units 110, 111, 112.

[0044] The driver circuits in the different switching units respond to the switch-on command 205 by appropriately biasing the gates of the IGBTs in those switching units to effect an OFF-to-ON transition. In response, the respective collector-to-emitter voltages V CE1 , V CE2 , V CE3 is the collector-emitter voltage V during the IGBT off period. CE(off) The collector current I C 1, I C 2. I C3 increases from approximately zero to the level of the current conducted by the switch in the on-state (after generally overshooting the level of the current conducted by the switch in the on-state). CE1 , V CE2 , V CE3 The decrease in V CE The information reflected in the sensing information and related to the current transfer behavior of the IGBT switch is V CE It can be recognized from the detection information.

[0045] For example, in FIG. 2A, a voltage threshold level X210 is defined for all three switches. Collector-to-emitter voltage V CE1 , V CE2 , V CE3 The points in time B1, B2, B3 at which the voltage drops below the voltage threshold level X210 may be measured by each switching unit. In the context of system 100 (FIG. 1), points in time B1, B2, B3 are identified by the switching controller and driver circuit 120 in switching units 110, 111, 112. Data characterizing points in time B1, B2, B3 are transmitted over channel 130 to the switching controller and driver circuit 120 in the master switching unit 110.

[0046] It should be noted that in some implementations, the voltage threshold level X210 (and indeed other voltage threshold levels described herein) may be adjusted over time for each individual switching unit 110, 111, 112. For example, the collector-to-emitter voltage at each switching unit 110, 111, 112 may be measured in the off-state, and the voltage threshold level may be set relative to the off-state measurement. The measurement and setting may be performed repeatedly by the switching units 110, 111, 112 to account for both differences between the switching units 110, 111, 112 and changes to the operating context (e.g., temperature and voltage levels).

[0047] Due to variations between the switching units, the points in time B1, B2, B3 generally differ from one switching unit to another. In an embodiment where the clocks in the different switching units 110, 111, 112 are synchronized, the point in time A at which each switch-on command 205 occurs is substantially common, and the points in time B1, B2, B3 embody information related to the current transfer behavior of the individual IGBT switches. The same information is used to determine the respective switch-on times T ON1_M1 , T ON1_M2 , T ON1_M3 and the on-switching time T ON1_M1 , T ON1_M2 , T ON1_M3 is the duration between the time points B1, B2, B3 and A. The on-switching time T ON1_M1 , T ON1_M2 , T ON1_M3 is the time when the power switch is turned on and the collector-to-emitter voltage V CE1 , V CE2 , V CE3 reaches the voltage threshold level X210.

[0048] In the schematic diagram of Figure 2A, the collector-to-emitter voltage V during the off-to-on transition CE2 The downward slope of the collector-emitter voltage V CE1 , V CE3 The slope is slightly steeper than that of V CE3 The slope of V CE1 , V CE2 The slope of the on-switching time T ON_M2 is the on-switching time T ON_M1 and the on-switching time T ON_M1 is the on-switching time T ON_M3 The time points B1, B2, B3 and the on-switching time T ON1_M1 , T ON1_M2 , T ON1_M3embodies information related to the current transfer behavior of the IGBT switching units during a switching cycle, and, as discussed above, this information can be used to determine relatively fine adjustments to be made to the timing of the switching transitions in the next switching cycle.

[0049] Multiple voltage thresholds are CE The detection information can further be used to recognize the current transfer behavior of the IGBT. For example, in FIG. 2B, a further voltage threshold level Y215 is defined for all three switching units. The collector-to-emitter voltage V CE1 , V CE2 , V CE3 The points in time C1, C2, C3 at which the voltage drops below the voltage threshold level Y215 may be determined in each switching unit. In the context of system 100 (FIG. 1), the points in time C1, C2, C3 are determined by the switching controller and driver circuit 120 in switching units 110, 111, 112. Data characterizing the points in time C1, C2, C3 are transmitted over channel 130 to the switching controller and driver circuit 120 in the master switching unit 110.

[0050] As with B1, B2, B3, the instants C1, C2, C3 generally vary from one switching unit to another. Assuming synchronism as well, the instant A at which each switch-on command 205 occurs is common to the switching units, and the instants B1, B2, B3, C1, C2, C3 embody information related to the current transfer behavior of the individual IGBTs. The same information is used to determine the switch-on time T for the first switching unit. ON1_M1 and T ON2_M1 , T for the second switching unit ON1_M2 and T ON2_M2 , and T for the third switching unit ON1_M3 and T ON2_M3 where the on-switching time T ON1_M1 , T ON1_M2 , T ON1_M3is the duration between time points B1, B2, B3 and time point A, and T ON2_M1 , T ON2_M2 , T ON2_M3 is the duration between time points C1, C2, C3 and time point A. In the context of the system 100 (FIG. 1), the switching controller and driver circuit 120 in the master switching unit 110 or in each slave switching unit 111, 112 uses the times of occurrence of time points B1, B2, B3, C1, C2, C3 and time point A to determine the on-switching time T ON1_M1 , T ON1_M2 , T ON1_M3 , T ON2_M1 , T ON2_M2 , T ON2_M3 can be calculated.

[0051] 2C, 2D, the on / off transitions shown in Fig. 2C, 2D are triggered by an off switch command 220 occurring at a time C. In the context of the system 100 (Fig. 1), the on switch command 205 may be received from the system controller 105 by the master switching unit 110 through the communication channel 117 and relayed to the driver circuit in the switching controller and driver circuit 120. The off switch command 220 may further be received from the master switching unit 110 by the slave switching units 111, 112 through the communication channel 130 and relayed to the driver circuit in the switching controller and driver circuit 120. Assuming clock synchronization, the time C at which each off switch command 220 occurs is the same in the different switching units, regardless of the path of the off switch command 220 to the driver circuit in those switching units. In another embodiment of the system 100 (Fig. 1), the occurrence of the time C is defined and recorded (at least temporarily) in the switching controller and driver circuit 120 in the master switching unit 110.

[0052] The driver circuits in the different switching units respond to the switch-off command 220 by appropriately biasing the gates of the IGBTs in those switching units to effect an on / off transition. In response, the respective collector-to-emitter voltages V CE1 , V CE2 , V CE3 However, the voltage V CE(off) The collector current I C 1, I C 2. I C 3 is reduced from the level of the current conducted by the switching unit in the on-state to nearly zero (i.e., leakage current only). CE1 , V CE2 , V CE3 The rise in V CE The information reflected in the detection information and related to the current transfer behavior of the IGBT is V CE It can be recognized from the detection information.

[0053] For example, in FIG. 2C, a voltage threshold level Z225 is defined for all three switching units. Collector-to-emitter voltage V CE1 , V CE2 , V CE3 The points in time D1, D2, D3 at which rises above the voltage threshold level Z225 may be determined in each switching unit. In the context of system 100 (FIG. 1), points in time D1, D2, D3 are determined by the switching controller and driver circuit 120 in switching units 110, 111, 112. Data characterizing points in time D1, D2, D3 are transmitted over channel 130 to the switching controller and driver circuit 120 in the master switching unit 110.

[0054] For example, due to variations between IGBTs and the path of the switch-off commands 205 to the driver circuits in those switching units, the instants D1, D2, D3 will generally be different for each switching unit. Assuming clock synchronization, the instant C at which each switch-off command 220 occurs is common to the switching units, and the instants D1, D2, D3 embody information related to the current transfer behavior of the individual IGBTs. The same information is used to determine the respective switch-off times T OFF1_M1 , T OFF1_M2 , T OFF1_M3 where the off-switching time T OFF1_M1 , T OFF1_M2 , T OFF1_M3 is the duration between the time points D1, D2, D3 and C. The off-switching time T OFF1_M1 , T OFF1_M2 , T OFF1_M3 is when the power switch is controlled to be off and when the collector-to-emitter voltage V CE1 , V CE2 , and V CE3 reaches the voltage threshold level Z225. In some implementations of the system 100 (FIG. 1), the switching controller and driver circuit 120 in the master switching unit 110 uses the occurrences of time points D1, D2, D3 and C to determine the turn-off time T OFF1_M1 , T OFF1_M2 , T OFF1_M3 can be calculated.

[0055] In the schematic diagram of Figure 2C, the collector-to-emitter voltage V during the on-to-off transition CE2 The slope of the rise is the collector-emitter voltage V CE1 , V CE3 The slope is slightly steeper than that of V CE3 The slope of V CE1 , V CE2 The slope of the off-switching time T OFF1_M2 is the off-switching time T OFF1_M1 and the off-switching time T OFF1_M1 is the off-switching time T OFF1_M3The time points D1, D2, D3 and the off-switching time T OFF1_M1 , T OFF1_M2 , T OFF1_M3 embodies information related to the current transfer behavior of the IGBT during a switching cycle, and, as discussed above, this information can be used to determine relatively fine adjustments to be made to the timing of the switching transitions in the next switching cycle.

[0056] Multiple voltage thresholds are V CE The detection information can be further used to recognize the current transfer behavior of the IGBT. For example, in FIG. 2D, a further voltage threshold level W230 is defined for all three switching units. The collector-to-emitter voltage V CE1 , V CE2 , V CE3 rises above voltage threshold level W230 may be identified in each switching unit. In the context of system 100 (FIG. 1), points in time E1, E2, E3 are identified by switching controller and driver circuit 120 in switching units 110, 111, 112. Data characterizing points in time E1, E2, E3 are transmitted over channel 130 to switching controller and driver circuit 120 in master switching unit 110.

[0057] As with D1, D2, D3, the instants E1, E2, E3 generally differ for each switching unit. Assuming clock synchronization, the instant C at which each switch-off command 220 occurs is common to the switching units, and the instants D1, D2, D3, E1, E2, E3 embody information related to the current transfer behavior of the individual IGBTs. The same information is used to determine the respective switch-off times T OFF1_M1 and T OFF2_M1 , T for the second switching unit OFF1_M2 and T OFF2_M2 , and T for the third switching unit OFF1_M3 and T OFF2_M3 where the off-switching time TOFF1_M1 , T OFF1_M2 , T OFF1_M3 is the duration between time points D1, D2, D3 and time point C, and T OFF2_M1 , T OFF2_M2 , T OFF2_M3 is the duration between time points E1, E2, E3 and time point C. In some implementations of the system 100 (FIG. 1), the switching controller and driver circuit 120 in the master switching unit 110 or in the slave switching units 111, 112 uses the times of occurrence of time points D1, D2, D3, E1, E2, E3 and time point C to determine the off-switching time T OFF1_M1 , T OFF1_M2 , T OFF1_M3 , T OFF2_M1 , T OFF2_M2 , T OFF2_M3 can be calculated.

[0058] 2A to 2D show the collector-emitter voltage V CE is cast exclusively in terms of the time required for the collector-to-emitter voltage V at one or more defined times to fall or rise to one or more threshold voltage levels, but in other embodiments, the collector-to-emitter voltage V at one or more defined times may be cast exclusively in terms of the time required for the collector-to-emitter voltage V at one or more defined times to fall or rise to one or more threshold voltage levels. CE The value of V during the switching transition CE The sensed information can be used to identify the current transfer behavior of the IGBT. For example, the collector-to-emitter voltage V CE may be measured after one or more times defined for the switch-on command 205 or the switch-off command 220. CE1 , V CE2 , V CE3 A rise or fall in the current carrying behavior of the individual IGBTs can be reflected in these voltage measurements and information related to the current carrying behavior of the individual IGBTs can be discerned.

[0059] 3 is a schematic diagram of an embodiment of a switching unit 300. The switching unit 300 may be part of a system in which the switching of different power switches is coordinated, such as switching units 110, 111, 112 in system 100 (FIG. 1). For purposes of simplicity, the switching unit 300 as illustrated functions as a master switching unit that interfaces with a system controller to coordinate the switching of any slave switching units.

[0060] The switching unit 300 includes one or more IGBT power switches 115 and a switching controller and driver circuit 120. The switching controller and driver circuit 120 includes an extra switching unit communication circuit 122 and an intra-switching unit communication circuit 125 that can communicate with the system controller and slave switching units over channels 117, 130.

[0061] In the illustrated embodiment of the switching unit 300, the control and communication interface circuitry 305 is galvanically isolated from the driver circuitry 310. The sections 305, 310 communicate across the galvanic barrier using respective transceivers 315, 320. The transceivers 315, 320 may be implemented to communicate using, for example, optical couplers, transformers, coupled lead frames, capacitors, and associated switching circuitry. Again, bidirectional communication may be implemented using a bidirectional channel and / or multiple unidirectional channels.

[0062] In addition to the transceiver 320, the driver circuitry 310 also includes a V CE It further includes a measurement circuit 325 , a switch driver control circuit 330 , a pull-up transistor 331 , and a pull-down transistor 332 .

[0063] V CE The measurement circuit 325 is V CE is coupled to the sense line 135 and detects the collector-to-emitter voltage VCE The time required for the transistor to reach the threshold, or the collector-to-emitter voltage V after a specified period of time. CE The time measurement may be accomplished using, for example, a voltage or current comparator, and the voltage or current level measurement may be accomplished using, for example, a timer circuit and a collector-to-emitter voltage V across the SENSE line 135 in response to being triggered by the timer circuit. CE or an analog-to-digital converter to sample the corresponding current. Regardless of the implementation details, V CE Measurement circuit 325 is configured to communicate information characterizing the measured time or voltage level to transceiver 320, typically every switching cycle.

[0064] In addition, further control functions (e.g., overcurrent protection, overvoltage protection) are generally CE This is achieved using the information on the detection line 135.

[0065] The switch driver control circuit 330 is configured to control the driving of the IGBT power switch 115 by switching the pull-up transistor 331 and the pull-down transistor 332 into and out of conduction. In the embodiment shown, this is alternatively - coupling a positive voltage (i.e., VPOS) with respect to the emitter voltage of the IGBT power switch 115 to the high output terminal GH and further to a gate resistor coupled to the gate of the IGBT power switch 115; and A negative voltage with respect to the emitter voltage of the IGBT power switch 115 (ie VPNEG) is coupled to the low output terminal GL and is further coupled to a gate resistor coupled to the gate of the IGBT power switch 115.

[0066] Other implementations are possible. For example, in some implementations, the pull-down transistor 332 couples the emitter of the IGBT power switch 115 to the gate of the IGBT power switch 115. As another example, in some implementations, one output terminal and a gate resistor are used. In a further example, a current source gate driver output stage is used. As another example, in some implementations, the timing adjustment is realized by a driver controller.

[0067] The control and communication interface circuitry 305 includes both the extra switching unit communication circuitry 122 and the intra-switching unit communication circuitry 125 , as well as a transceiver 315 .

[0068] The extra switching unit communication circuitry 122 includes a communication interface 335 that may communicate with components other than the switching units using one or more communication protocols. For example, information that the communication interface 335 may receive includes a system switching command 336. The system switching command 336 indicates the desired state of all the IGBT switches 115 in a system, such as the system 100 (FIG. 1).

[0069] The intra-switching-unit communication circuitry 125 includes a communication interface 340 that may communicate with other switching units using one or more communication protocols. For example, in some implementations, the system switching commands 336 received at the communication interface 335 are simply relayed to the other switching units via the communication interface 340. In some implementations, the system switching commands 336 sent to the other switching units are frequency encoded. For example, an AC clock signal with a relatively high frequency may indicate that all of the switching units are to be turned on, whereas an AC clock signal with a identifiable frequency (e.g., 1 / 10 to 1 / 2 or 2 to 10 times the frequency indicating that all of the switching units are to be turned on) may indicate that all of the switching units are to be turned off. Such encoding is robust in the context of power switching. In particular, even if the transition of the system switching commands 336 between frequencies is obscured by noise, the signals that can be interpreted by the communication interface 335 are readily decoded and the communication interface 335 responds accordingly.

[0070] As another example of communication between the communication interface 340 and other switching units, a frame-based communication protocol may be used to monitor the collector-to-emitter voltage V of other power switches during switching transitions, as described in more detail below. CE The SENSE_OFF signal 341 may be used to receive signals 341, 342 characterizing the collector-to-emitter voltage V of the other power switch during a transition from an on state to an off state, and to transmit signals 343, 344 characterizing relatively fine adjustments made to the timing of switching transitions in other power switches in the system. In particular, the SENSE_OFF signal 341 may be used to receive signals 341, 342 characterizing the collector-to-emitter voltage V of the other power switch during a transition from an on state to an off state, and to transmit signals 343, 344 characterizing relatively fine adjustments made to the timing of switching transitions in other power switches in the system. CE , and the SENSE_ON signal 342 characterizes the collector-to-emitter voltage V of the other power switch during the transition from the off state to the on state. CE, ADJ_ON signal 343 characterizes the adjustments made to the timing of the switching transition to the ON state, and ADJ_OFF signal 344 characterizes the adjustments made to the timing of the switching transition to the OFF state.

[0071] In some implementations, the timing adjustments characterized in signals 343, 344 and transmitted to the slave switching units may be cast in terms of a number of cycles of the clock signal encoding the system switching command 336. For example, assume that the system switching command 336 encodes an ON state using a 100 MHz clock signal. Rising and falling edges of the clock signal occur every 5 nanoseconds. Signals 343, 344 may cast a 20 nanosecond timing adjustment as 4 transitions / / 2 clock cycles.

[0072] Finer adjustments made to the timing of switching transitions in switching unit 300 and / or other switching units in the system may be determined by switching unit 300 itself, by external circuitry (e.g., system controller 105 (FIG. 1)), or by both switching unit 300 and external circuitry.

[0073] In embodiments where external circuitry is involved in determining the fine adjustment, the communications interface 335 may also receive the detected collector-to-emitter voltage V of the other power switches during the switching transition. CE The communication interface 335 may further communicate to the external component a sense information signal 337 characterizing the timing of the switching transitions in the other switching units. The communication interface 335 may further receive an adjustment information signal 338 from the external component characterizing the relatively fine adjustments made to the timing of the switching transitions in the other switching units. Thus, the sense information signal 337 may indicate the information content of the SENSE_ON signal 342 and the SENSE_OFF signal 341, as well as the collector-to-emitter voltage V of the IGBT in the switching unit 300 during that transition. CEAdditionally, the adjustment information signal 338 may include at least some of the equivalent information characterizing the information content of the ADJ_ON signal 343 and the ADJ_OFF signal 344, as well as relatively fine adjustments made to the timing of switching transitions in the switching unit 300.

[0074] In embodiments in which the switching unit 300 is responsible for determining fine adjustments, the switching unit 300 includes a timing adjustment decision circuit 345. The timing adjustment decision circuit 345 is a circuit configured to determine relatively fine adjustments to be made, as necessary, to the timing of switching transitions in the switching units of a system that includes the switching unit 300. For example, the timing adjustment decision circuit 345 may be implemented using a digital clock in an ASIC and configured by registers.

[0075] Whether the timing adjustments are determined by the timing adjustment decision circuit 345 or by an external circuit, the timing adjustments may be designed to achieve a desired current distribution in the power switches of the system.

[0076] In some embodiments, the adjustment is designed to gradually approach the desired current distribution over multiple switching cycles. By way of example, Tables 1-3 show the collector-to-emitter voltage V CE FIG. 1 shows an example of a set of timing adjustments designed to achieve balanced current sharing by ensuring that the collector-to-emitter voltage V at a particular time after the transition begins is approximately the same. Equivalent timing adjustments can be made for the transition to the OFF state. Furthermore, equivalent timing adjustments can be made for the collector-to-emitter voltage V at a particular time after the transition begins. CE are approximately the same. In other implementations, multiple voltage threshold levels or multiple points in time after the transition may be used.

[0077] Table 1 shows exemplary data for the first switching cycle. The first switching cycle may be the first cycle after start-up, after a system reset, or otherwise. In this embodiment, there is no default timing adjustment for the first switching cycle, and the accumulated adjustments for all switching units are initially zero. This is not necessarily the case, and in some embodiments, even the first cycle after start-up or a system reset may involve default adjustments.

[0078] In either case, the collector-to-emitter voltage V CE Examples of detected times at which the voltage threshold level is crossed are provided in the column labeled "Crossing Time." In some embodiments, the crossing time may be measured relative to when the system switching command 336 is received by the switching units 110, 111, 112 over the channel 130. In the context of Figures 2A and 2B, the crossing time is measured from index A 205. In the context of Figures 2C and 2D, the crossing time is measured from index C 220. In other embodiments, the crossing time may be measured relative to when the system switching command 336 received by the master switching unit from the system controller indicates that a transition is to occur.

[0079] In Table 1, the units of time are arbitrary, but in some implementations may be in nanoseconds. As shown, the collector-to-emitter voltage V CE There is some variation in the time at which the first slave switching unit crosses the voltage threshold level. For example, the average crossing time is about 10 time units, but the first slave switching unit crosses the voltage threshold level relatively sooner and the third slave switching unit crosses the voltage threshold level later. More current is conducted by the first slave switching unit than the third slave switching unit, and the current distribution may be relatively unbalanced.

[0080] With regard to the timing adjustment itself, the slowest power switch is the one in the third slave switching unit. The third slave switching unit may act as a reference switching unit, and the adjustments to the other switching units are made based on the collector-to-emitter voltages V of the switches in those other switching units. CE crosses the voltage threshold level at the same time as the reference. Further, adjustments to the other switching units are designed to distribute the current more evenly, but with the understanding that the desired current distribution may only be achieved gradually over multiple switching cycles. For example, the timing adjustment to the first slave switching unit is 10 units, but the power switch of the first slave switching unit crossed the voltage threshold level 30 units sooner than the power switch of the third slave switching unit.

[0081] The gradual, multi-cycle approach to the desired current distribution can be achieved in a variety of different ways. For example, in some implementations, the magnitude of the allowable adjustments can be limited within a range. In such cases, multiple switching cycles are required to approach the desired current distribution even when the magnitude of the difference between the switching units is large. As another example, the magnitude of the adjustments can be limited to a percentage of the magnitude of the difference between the switching units. As yet another example, a combination of these and other techniques can be used. In either case, the direction of the adjustments is designed to achieve the desired current distribution when the current sharing is balanced, i.e., to make the current distribution more uniform, or to achieve the desired non-uniform distribution when the current sharing is not balanced. [Table 1]

[0082] Table 2 shows exemplary data for the second switching cycle. In this shown example, the second switching cycle immediately follows the first switching cycle, i.e., the timing adjustment is applied every switching cycle. This is not necessarily the case. For example, in other embodiments, the timing adjustment may be made after multiple cycles have elapsed, or may be made only when there is a threshold level difference between the crossing times.

[0083] Returning to Table 2, the accumulated adjustments for all switching units are those set after the first switching cycle. After those adjustments are applied, the collector-to-emitter voltage V CE The time when V crosses a voltage threshold level is detected. As can be seen, there is not a one-to-one correspondence between the timing adjustment made and the change in crossing time. For example, the timing adjustment to the master switching unit after the first switching cycle was 10 units. However, the change in crossing time was only 5 units (i.e., the crossing time went from 100 units to 105 units). Such discrepancies can occur for many different reasons. For example, CE Noise may be present on the sense line 135 (FIG. 1). The associated devices may have different temperature / voltage / current dependent tolerances. The measurement and regulation resolution may differ. Furthermore, some of the crossing times may be due to factors that have a one-to-one correspondence to the time when the switching transition is initiated, and other parts may be due to factors that do not have a one-to-one correspondence. For example, the transmission delay for switching units that are relatively far from the master switching unit may be compensated one by one by delaying the transitions of switching units that are relatively close to the master switching unit. On the other hand, the collector-to-emitter voltages V CEThe difference in slope or shape of may not be compensated for one by one. In either case, the change in crossing time for a given switching unit may be larger than the timing adjustment (as seen in the second slave switching unit and the fourth slave switching unit) or smaller than the timing adjustment (as seen in the master switching unit, the first slave switching unit, and the fifth slave switching unit).

[0084] With regard to the timing adjustment itself, the third slave switching unit remains the reference switching unit, but the crossing time point of the third slave switching unit is earlier, and both the second slave switching unit and the fourth slave switching unit crossed the voltage threshold level after the third slave switching unit. There may be several reasons for the earlier crossing time point of the third slave switching unit, including, for example, temperature changes or noise that corrupted the third slave switching unit's reception of the system switching command.

[0085] In either case, the new adjustment is still determined with reference to the third slave switching unit. Both the second and fourth slave switching units have negative timing adjustments, whereas the master and first slave switching units have positive timing adjustments. The collector-to-emitter voltage V of the power switch of the fifth slave switching unit CE is the collector-emitter voltage V of the power switch of the reference third slave switching unit CE At the same time the voltage threshold is crossed and no adjustment is applied. [Table 2]

[0086] Table 3 shows exemplary data for the third switching cycle. The accumulated adjustments for all switching units were set after the second switching cycle. After those adjustments were applied, the collector-to-emitter voltage V CE The time when the collector-to-emitter voltage V crosses a voltage threshold level is detected. As shown, CE crossing the voltage threshold level are approximately identical, only the crossing time of the fourth slave switching unit deviates from the reference. A timing adjustment for the next switching cycle can further be determined. [Table 3]

[0087] 4 is a swim lane diagram representing operations in a system in which the switching of different power switches is ganged. The left lane represents operations performed by a master switching unit in such a system. For example, the operations in the left lane may be performed by switching units 110, 300 (FIGS. 1, 3). The right lane represents operations performed by a slave switching unit in such a system. For example, the operations in the right lane may be performed by switching units 111, 112 (FIG. 1). Furthermore, operations performed on the primary side of the switching units are surrounded by relatively thin lines, and operations performed on the secondary side of the switching units are surrounded by relatively thick lines.

[0088] For purposes of illustration, it is assumed that all on-switching adjustments are determined by the master switching unit. However, as noted above, this is not necessarily the case. Furthermore, ongoing operation is depicted rather than, for example, immediately after start-up or reset. In the context of the timing adjustments described in Tables 1-3, the operation in FIG. 4 may represent the second switching cycle (Table 2) or any subsequent switching cycle.

[0089] At 402, a master switching unit receives a system on command, which is a kind of system switching command that indicates that the IGBT switches in the system are to be turned on.

[0090] At 404, the master switching unit sends a system on command to one or more slave switching units in the system. The system on command is then looped back to the master switching unit. In one example, the loopback may compensate for a propagation delay to the one or more slave switching units.

[0091] Additionally, the master switching unit applies its own timing adjustments (e.g., the accumulated timing adjustments in Tables 2 and 3) to the system ON command. In the embodiment shown, the timing adjustments to the master switching unit are applied on the primary side of the master switching unit at 406, and the adjusted ON command is sent across the galvanic isolation barrier to the secondary side of the master switching unit at 408. In other embodiments, an unadjusted ON command is sent across the galvanic isolation barrier, and the timing adjustments to the master switching unit are applied on the secondary side. To ensure this option is recognized, the application of the timing adjustments to the master switching unit is surrounded by a relatively thin dashed line, and the sent ON command is labeled "Adjusted ON Command."

[0092] Following the master switching unit, at 410, the secondary side of the master switching unit receives the regulated ON command and switches on the switch according to the regulated ON command (wherever the regulation is applied). At 412, the associated collector-to-emitter voltage V CE to the threshold voltage level, or the collector-to-emitter voltage V CEAt 414, the measured time or value is transmitted across the isolation barrier from the secondary side to the primary side of the master switching unit.

[0093] At 416, the primary side of the master switching unit receives both the measured time or value from its own secondary side and one or more measured times or values ​​from the slaves in the system.

[0094] At 418, the master switching unit determines any new adjustments to be applied to the on-command and transmits those new adjustments to the slaves in the system at 420. In embodiments where adjustments are applied to secondary, any new adjustments to the master switching unit must be transmitted to the secondary.

[0095] Considering the slave, at 450 the slave switching unit receives the system on command sent by the master switching unit.

[0096] In the embodiment shown, a timing adjustment for the slave switching unit is applied on the primary side of the slave switching unit at 452, and the adjusted ON command is sent across the galvanic isolation barrier to the secondary side of the master switching unit at 454. As with the master switching unit, this is not necessarily the case.

[0097] At 456, the secondary side of the slave switching unit receives the regulated ON command and switches ON the switch according to the regulated ON command (regardless of where the regulation is applied). At 458, the associated collector-to-emitter voltage V CE to the threshold voltage level, or the collector-to-emitter voltage V CEAt 460, the measured time or value is transmitted across the isolation barrier from the secondary side to the primary side of the slave switching unit.

[0098] At 462, the primary side of the slave switching unit receives the measured time or value from the secondary side. At 464, the slave switching unit transmits the measured time or value to the master switching unit.

[0099] At 470, the slave switching unit receives from the master switching unit the new adjustments to be applied to the ON command.

[0100] 5 is a schematic diagram of a bus 500 structure that may be used to implement a communication channel between a master switching unit 505 and one or more slave switching units 510 in a system in which the switching of different power switches is ganged. For example, the bus structure 500 may be used to implement the communication channel 130 (FIG. 1).

[0101] The illustrated embodiment of the bus structure 500 includes a pair of system command lines 515 and a pair of data communication lines 520. The system command lines 515 provide a channel for communication of system commands. The system command lines 515 are implemented as differential transmission lines and are terminated by a termination resistor 518. The termination resistor 518 may include inherent resistances of components in the switching unit 510 (e.g., the input impedance of a receiver in the slave switching unit 510) and fixed or variable resistors coupled to the component resistances to define the termination resistance 518 "seen" by signals propagating on the system command lines 515. In some embodiments, the termination resistor is a variable termination resistor and is programmable based on the wave impedance of the cable used on the system command lines 515.

[0102] At least the master switching unit 505 includes a differential transmitter 525 coupled to the system command line 515 , and each of the slave switching units 510 includes a differential receiver 527 coupled to the system command line 515 .

[0103] Communication line 520 provides a time-division channel for communication of data and commands. The data communicated is the collector-to-emitter voltage V CE , and signals characterizing relatively fine adjustments made to the timing of switching transitions. The communicated commands may include initialization and reset commands, and signals characterizing the collector-to-emitter voltage V of the slave. CE is detected and a time or value derived therefrom is transmitted on communication line 520, and commands to set the value of termination resistor 518 and the values ​​of termination resistors 522, 524 that terminate communication line 520.

[0104] The master switching unit 505 includes a differential transmitter 530 and a receiver 535 coupled to the communication line 520. Each of the slave switching units 510 includes a differential receiver 532 and a receiver 537 coupled to the system command line 520.

[0105] As mentioned above, the number of slave switching units 510 in a system in which the switching of different power switches is ganged can vary. Furthermore, in some applications it is desirable to make relatively fine adjustments to the timing of the switching transitions in individual switches every switching cycle.

[0106] In operation, the bus 500 may provide a high frequency communication channel between a master switching unit 505 and various numbers of slave switching units 510 to coordinate switching. For example, the master switching unit 505 may receive a command from a system controller indicating that switching is to be coordinated, e.g., to achieve a desired balanced or unbalanced current sharing. In response, the master switching unit 505 may broadcast a command on the data communication lines 520 instructing any slave switching units 510 on the data communication lines 520 to reset and respond with a signal identifying their presence. Arbitration between the slaves is not essential at this point, but may be accomplished here or during subsequent exchanges.

[0107] After receiving confirmation that at least one slave switching unit 510 is present, the master switching unit 505 may broadcast an initialization command on communication line 520. The slave switching units 510 present on communication line 520 may respond to the initialization command with identification information. For example, in some embodiments, any slave switching units 510 present may arbitrate for a time slot on communication line 520 and respond with their respective MAC addresses. If necessary, the slave switching units 510 may be assigned and informed of a short form address.

[0108] After the slave switching units 510 are identified, a frame-based communications protocol may be used to address individual slave switching units 510. Each frame may include, for example, the address of the addressed slave switching unit 510, an identification of the command being sent in that frame, and data associated with that command. A start sequence, an error detection and correction sequence (e.g., a cyclic redundancy check block), information describing the size of the frame, and other information may also be included as desired.

[0109] The commands that can be sent from the master switching unit 505 are: The collector-to-emitter voltage V during a switching transition of the slave switching unit 510 (e.g., the SENSE_OFF signal 341 and the SENSE_ON signal 342 (FIG. 3)). CE and a command to initiate transmitting a signal characterizing the - commands that certain timing adjustments are applied, For example, timing adjustment commands may include data characterizing the magnitude of those timing adjustments.

[0110] Additionally, commands that may be sent from the master switching unit 505 include commands to set values ​​of the termination resistors 518, 522, 524. In some implementations, the commands to set the values ​​of the termination resistors 518, 522, 524 are based on information entered by a user about the system. For example, a user may be able to enter information related to the impedance of the cables implementing the lines 515, 520. In some examples, measurements made on the lines 515, 520 may further be used (alone or in combination with user input) to set the values ​​of the termination resistors.

[0111] In some implementations, the measurements performed on lines 515, 520 may include determining which of the slave switching units 510 is the farthest (in terms of propagation delay) from the master switching unit 505. After the farthest switching unit 510 is identified, it may be instructed to set its termination resistance to reduce or eliminate signal reflections and distortions.

[0112] In some implementations, a baseline of reflections may first be measured. For example, one or both of the differential transmitters 525, 530 in the master switching unit 505 may transmit a measurement signal. One or both of the receiver 535 and a receiver in the system command line 515 (not shown) in the master switching unit 505 may measure the reflections caused by each impedance mismatch along the lines 515, 520. This comparison of the transmitted and reflected signals provides a baseline measurement indicative of the impedance mismatch in the absence of any adjustments to the termination resistors 518, 522, 524.

[0113] Before or after the baseline is measured, each of the slave switching units 510 on lines 515, 520 can be addressed individually and in sequence using commands that set the values ​​of the termination resistors 518, 522, 524. The effect of those settings on the same reflected signal can be used to attribute reflections to the respective slave switching units 510.

[0114] In some implementations, the master switching unit 505 may instruct each respective slave switching unit 510 to short-circuit and open-circuit the switching unit's connection to the lines 515, 520. With the connection short-circuited or open-circuited, the master switching unit 505 may measure reflections along the lines 515, 520 and attribute those reflections to the respective slave switching unit 510. The reflection that occurs last in time is attributed to the slave switching unit 510 that is furthest from the master switching unit 505. Illustratively, it is assumed that the slave switching unit 510 on the right in the schematic diagram of FIG. 5 (i.e., the slave switching unit 10 that includes the termination resistors 518, 524) is the slave switching unit 510 that is furthest from the master switching unit 505.

[0115] After the slave switching unit 510 furthest from the master switching unit 505 is identified, a command may be sent to that slave switching unit 510 to set the value of the termination resistors 518, 524. In some embodiments, an empirical process in which the master switching unit 505 performs multiple transmissions and measures multiple reflections may be used to determine the appropriate values ​​for the termination resistors 518, 524. For example, a range of impedances may be scanned, or the impedance may be gradually adjusted until only acceptable reflections are present.

[0116] In some implementations, the termination resistors 518, 524 may only be set to pre-assigned termination values, for example, termination values ​​encompassing common cable wave impedances (e.g., 50Ω, 75Ω, 100Ω, 125Ω, and 150Ω).

[0117] A number of implementations have been described. Nevertheless, it will be understood that various modifications may be made. For example, the communication channels may be realized as wired and / or wireless connections. The communication paths established by these connections may be divided in time, frequency, phase, or otherwise. Lack of switching commands may be avoided in a variety of different ways, even in high power switching applications. For example, optical techniques may be used to transmit the signals. Accordingly, other implementations are within the scope of the following claims.

[0118] The present invention is defined in the claims. However, it should be understood that the invention can alternatively be defined by the following examples.

[0119] Example 1. a plurality of power switching units each including a respective power switch; a communication system configured to communicate system-wide switching commands to the power switching units along a communication channel; a circuit included in each of the power switching units configured to delay execution of a switching command across the system with a delay; A power switching system comprising:

[0120] Example 2. The delay is between 0 and 1000 nanoseconds, The power switching system described in Example 1.

[0121] Example 3. the delay is a factor of less than one of the inherent rise or fall time of the control terminal of each power switch in the power switching system; The power switching system of example 1 or example 2.

[0122] Example 4. the power switching system including circuitry for determining a magnitude of a delay to be applied to execution of a system-wide switching command by at least some of the plurality of power switching units; The power switching system of any one of Examples 1 to 3.

[0123] Example 5. the circuit for determining the magnitude of the delay is configured to determine the magnitude of the delay every switching cycle; The power switching system of Example 4.

[0124] Example 6. each of the power switching units includes a detection circuit configured to detect a voltage across the main terminals; the circuitry for determining the magnitude of the delay comprises circuitry for comparing the times required for detected voltages at the different power switching units to reach or cross a threshold during a switching transition in response to a previous system-wide switching command, or circuitry for comparing values ​​of detected voltages at the different power switching units at a time defined relative to a previous system-wide switching command; The power switching system of Example 4.

[0125] Example 7. each of the plurality of power switching units comprising a synchronizable clock configured to generate a clock signal; Each of the power switching units is configured to reference a synchronized clock signal for the time required for the detected voltage at the different power switching units to reach or cross a threshold value, or for a time defined for a switching command across the previous system; The power switching system of Example 6.

[0126] Example 8. the circuit for determining the magnitude of the delay is configured to determine a delay that reduces the difference between the times required for the detected voltages at the different power switching units to reach or cross a threshold, or reduces the difference between the values ​​of the detected voltages at the times; The power switching system of Example 6.

[0127] Example 9. The switching commands across the system are clock signals with different frequencies, the delay is expressed in the communication between the power switching units in terms of one cycle of the frequency of the clock signal; The power switching system of any one of Examples 1 to 8.

[0128] Example 10. the magnitude of delay by which execution of a system-wide switching command is delayed is different for each of the plurality of power switching units; The power switching system described in Example 1.

[0129] Example 11. 1. A power switching system, comprising: A communication bus; a master power switching unit and a plurality of slave power switching units coupled to a communication bus; Equipped with Each of the master power switching unit and the slave power switching unit A power switch; a detection circuit configured to detect a voltage across the main terminals of the power switch; a communication interface coupled to the communication bus; Including, each of the slave power switching units includes a control circuit configured to transmit, using the communication interface, a signal to the master power switching unit that includes information characterizing the detected voltage; a power switching system including circuitry configured to receive information characterizing a detected voltage at a slave power switching unit and configured to compare the detected voltage at the slave power switching unit with a detected voltage across main terminals of a power switch of the master power switching unit to determine an adjustment to apply to a switching transition during a subsequent switching cycle by a first one of the slave power switching units; and further comprising: a circuit for the master power switching unit to transmit a signal characterizing the adjustment to a first one of the slave power switching units using the communication interface. Power switching system.

[0130] Example 12. The delay is between 0 and 1000 nanoseconds, 12. The power switching system of Example 11.

[0131] Example 13. the delay is a factor of less than one of the inherent rise or fall time of the control terminal of each power switch in the power switching system; The power switching system of example 11 or example 12.

[0132] Example 14. a system controller configured to provide system-wide switching commands indicating a desired on or off state of the master power switching unit and the plurality of slave power switching units; Adjustments are applied to system-wide switching commands; The power switching system of any one of Examples 11 to 13.

[0133] Example 15. a system controller including circuitry configured to receive information characterizing detected voltages at the slave power switching units and configured to compare the detected voltages to determine an adjustment; 15. The power switching system of Example 14.

[0134] Example 16. the adjustment is configured to reduce a delay between a system-wide switching command and an execution of the system-wide switching command by the at least one power switch; 15. The power switching system of Example 14.

[0135] Example 17. Sensing voltages across main terminals of a plurality of power switches in a power switching system; determining a time required for the detected voltage to reach or cross a threshold during a switching transition in response to a switching command across the system, or a value of the detected voltage at a specified time relative to a switching command across the system; determining an adjustment to be applied to execution of switching commands across the system in a subsequent switching cycle for a first power switch of the power switches in the power switching system; applying an adjustment in a driver of the first power switch to a switching performance across the system in a subsequent switching cycle; A method comprising:

[0136] Example 18. The subsequent switching cycle is the next immediately following switching cycle. The method of Example 17.

[0137] Example 19. The adjustment is determined to unbalance the currents carried by the power switches in the power switching system. The method according to Example 17 or Example 18.

[0138] Example 20. the adjustment is configured to reduce a delay between a system-wide switching command and an execution of the system-wide switching command by the at least one power switch; The method according to any one of the seventeenth to nineteenth examples.

[0139] Example 21. The modulation is between 0 nanoseconds and 1000 nanoseconds. The method according to any one of the seventeenth to twentieth examples.

[0140] Example 22. the delay is a factor of less than one of the inherent rise or fall times of the control terminals of each power switch in the power switching system; The method according to any one of the seventeenth to twenty-first examples.

[0141] Example 23. The method is determining a second adjustment to be applied to execution of switching commands across the system in a subsequent switching cycle for a second one of the power switches in the power switching system, the first adjustment being different from the second adjustment; applying an adjustment in a driver of a second power switch to a switching performance across the system in a subsequent switching cycle; The method of any one of the seventeenth to twenty-second examples, further comprising:

[0142] Example 24. The switching commands across the system are clock signals with different frequencies, the adjustment is expressed in terms of one cycle of the frequency of the clock signal; The method according to any one of the seventeenth to twenty-third examples.

[0143] Example 25. The time required for a detected voltage to reach or cross a threshold, or the time specified for a switching command across the system, is referenced to a clock signal that is synchronized with the clock signals of other of the power switches in the power switching system. The method according to any one of the seventeenth to twenty-fourth examples.

[0144] Example 26. A power switch; a detection circuit configured to detect a voltage across the main terminals of the power switch; a communication interface configured to be coupled to a communication bus; a circuit configured to receive information characterizing detected voltages at a plurality of other power switching units and configured to compare the detected voltages at the other power switching units with the detected voltages across the main terminals of the power switch to determine adjustments to be applied to switching transitions during subsequent switching cycles by the other power switching units; a circuit for transmitting a signal characterizing the regulation to other power switching units using a communication interface; A power switching unit comprising:

Claims

1. a plurality of power switching units coupled in parallel, each of the power switching units including a respective power switch and a detection circuit configured to detect a voltage across main terminals of the respective power switch; a communication system configured to communicate system-wide switching commands to the power switching units along a communication channel; a circuit for determining a magnitude of delay to be applied to execution of the system-wide switching command in the plurality of power switching units, each of the delays is adjusted for a respective one of the power switching units; the circuit for determining the magnitude of the delay comprises a circuit for comparing a time required for the detected voltages at different power switching units to reach or cross a threshold during a switching transition in response to a previous system-wide switching command, or a circuit for comparing values ​​of the detected voltages at different power switching units at a time defined relative to a previous system-wide switching command. the circuitry for determining the magnitude of the delay; a circuit in each of the power switching units configured to delay execution of a switching command across the system with the delay adjusted for the power switching unit; A power switching system comprising:

2. the circuit for determining the magnitude of the delay is configured to determine the magnitude of the delay every switching cycle; 10. The power switching system of claim 1.

3. each of the plurality of power switching units comprising a synchronizable clock configured to generate a clock signal; Each of the power switching units: the time required for the detected voltages at the different power switching units to reach or cross a threshold value, or The time specified for the switching command across the previous system, The clock signal is configured to be synchronized with respect to the 10. The power switching system of claim 1.

4. the circuit for determining the magnitude of the delay is configured to determine a delay that reduces the difference between the times required for the detected voltages at different power switching units to reach or cross the threshold, or reduces the difference between the values ​​of the detected voltages at the times.

4. The power switching system of claim 3.

5. the system-wide switching commands being clock signals having different frequencies; the delay being expressed in communication between the power switching units in terms of one cycle of the frequency of the clock signal; 10. The power switching system of claim 1.

6. the magnitude of the delay by which execution of a switching command across the system is delayed is different for each of the plurality of power switching units; 10. The power switching system of claim 1.

7. the communication system comprises a communication bus; the plurality of power switching units including a master power switching unit and a plurality of slave power switching units coupled to the communication bus; Each of the master power switching unit and the slave power switching unit A power switch; a detection circuit configured to detect a voltage across main terminals of the power switch; a communication interface coupled to the communication bus; Including, each of the slave power switching units includes a control circuit configured to transmit, using the communication interface, a signal to the master power switching unit that includes information characterizing the detected voltage; the power switching system including a circuit configured to receive the information characterizing the detected voltage at the slave power switching units and configured to compare the detected voltage at the slave power switching units with the detected voltage across main terminals of the power switch of the master power switching unit to determine an adjustment to be applied to a switching transition during a subsequent switching cycle by a first one of the slave power switching units, the adjustment being adjusted for the first one of the slave power switching units; and further comprising circuitry for the master power switching unit to transmit a signal characterizing the adjustment to the first of the slave power switching units using the communication interface.

10. The power switching system of claim 1.

8. a system controller configured to provide system-wide switching commands indicating a desired on or off state of the master power switching unit and a plurality of the slave power switching units; the adjustment is applied to switching commands across the system.

8. A power switching system according to claim 7.

9. the system controller including circuitry configured to receive the information characterizing the detected voltages at the slave power switching units and configured to compare the detected voltages to determine the adjustment; 9. The power switching system of claim 8.

10. the adjustment is configured to reduce a delay between a switching command across the system and the execution of the switching command across the system by at least one of the power switches.

9. The power switching system of claim 8.

11. Either a) the modulation is between 0 nanoseconds and 1000 nanoseconds, or b) the delay is a factor of less than one of the inherent rise or fall time of a control terminal of each of the power switches in the power switching system; or c) both a) and b); 10. The power switching system of claim 1.

12. Sensing a voltage across main terminals of a plurality of parallel-coupled power switches in a power switching system; determining a time required for the detected voltage to reach or cross a threshold during a switching transition in response to a switching command across the system, or a value of the detected voltage at a time defined relative to a switching command across the system; determining an adjustment to be applied to execution of a switching command across the system in a subsequent switching cycle for a first one of the power switches in the power switching system, the adjustment being adjusted for the first one of the power switches; applying the adjustment in a driver of the first power switch to the performance of switching across the system in the subsequent switching cycle; A method comprising:

13. a) the subsequent switching cycle is the next immediately succeeding switching cycle, or b) the adjustment is determined to unbalance the currents carried by the power switches in the power switching system; or c) both a) and b); The method of claim 12.

14. the adjustment is configured to reduce a delay between a switching command across the system and the execution of the switching command across the system by at least one of the power switches. The method of claim 12.

15. a) the modulation is between 0 nanoseconds and 1000 nanoseconds; or b) the delay is a factor of less than one of the inherent rise or fall time of a control terminal of each of said power switches in said power switching system; or c) both a) and b); The method of claim 12.

16. The method further comprises determining a second adjustment to be applied to execution of switching commands across the system in the subsequent switching cycle for a second one of the power switches in the power switching system, the first adjustment being different from the second adjustment; applying the adjustment in a driver of the second power switch to the performance of switching across the system in the subsequent switching cycle; The method of claim 12 further comprising:

17. the system-wide switching commands being clock signals having different frequencies; the adjustment being expressed in terms of one cycle of the frequency of the clock signal; The method of claim 12.

18. the time required for the detected voltage to reach or cross the threshold, or the time specified for a switching command across the system, is referenced to a clock signal that is synchronized with clock signals of other ones of the power switches in the power switching system. The method of claim 12.

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