PWM controller

Abstract

To make the upper limit of a count value (carrier) to be compared with a comparison value for determining the duty ratio of a PWM signal constant and independent of the carrier period, thereby simplifying a circuit for generating the comparison value.SOLUTION: A PWM controller includes a normalization counter that counts up or down between 0 and 2^N by an average of 2^N / Cmax for each input of a clock signal, where N is a natural number and Cmax is a value that changes according to the carrier period. The PWM controller further includes a comparator that compares the normalized count value of the normalization counter with a comparison value for determining the duty ratio of the PWM signal and outputs the comparison result as a PWM signal.SELECTED DRAWING: Figure 8

Description

[Technical field]

[0001] The present invention relates to a pulse width modulation (PWM) control device that generates a PWM signal for inverter control of a motor. [Background technology]

[0002] In a motor control device that uses a three-phase motor to control the speed and rotation angle (position) of a load, a PWM inverter that drives a three-phase voltage-type inverter with a PWM signal is typically used as the power converter, and a microcontroller with a built-in PWM circuit is used as a control processor as a peripheral device.

[0003] FIG. 9 is a block diagram showing the configuration of a conventional PWM circuit 5a when outputting a so-called triangular wave PWM signal.

[0004] The PWM circuit 5a includes a PWM counter 51, a counter upper limit value storage unit 52, comparison value storage units 53a, 53b, and 53c, comparators 54a, 54b, and 54c, and complementary dead time generation units 55a, 55b, and 55c. The PWM counter 51 counts up and down a clock signal (not shown). The counter upper limit value storage unit 52 stores a count upper limit value for determining a PWM carrier period. The comparison value storage units 53a, 53b, and 53c store comparison values ​​for determining the duty ratios of the PWM signals of the U phase, V phase, and W phase. The comparators 54a, 54b, and 54c compare the value of the PWM counter 51 with the values ​​of the comparison value storage units 53a, 53b, and 53c, respectively, and generate an active PWM signal when the value of the PWM counter 51 falls below the values ​​of the comparison value storage units 53a, 53b, and 53c. The complementary and dead time generating units 55a, 55b, and 55c output a positive-phase PWM signal and a negative-phase PWM signal that are complementary to the PWM signals generated by the comparators 54a, 54b, and 54c, taking into account the dead time. Various means for implementing the complementary and dead time generating units 55a, 55b, and 55c are known, for example, as disclosed in Patent Document 1.

[0005] Fig. 12 is a timing chart showing the U-phase PWM output of the PWM circuit 5a having the configuration shown in Fig. 9. For simplicity, Fig. 12 shows an example in which the dead time is 0.

[0006] The PWM counter 51 counts a clock signal (not shown). A counter upper limit value is input to the PWM counter 51 from a counter upper limit value storage unit 52. The PWM counter 51 outputs a PWM count value that counts up or down between 0 and the counter upper limit value, and an up / down identification signal that indicates the current count direction. The PWM count value is input to an inverting input terminal of a comparator 54a. A comparison value is input to a non-inverting input terminal of the comparator 54a from a comparison value storage unit 53a. The comparator 54a compares the PWM count value with a comparison value, and outputs ON when the PWM count value is equal to or less than the comparison value, outputs OFF when the PWM count value exceeds the comparison value, and outputs ON when the PWM count value falls below the comparison value. The PWM signal output by the comparator 54a is input to a complementary dead time generation unit 55a. The complementary / dead time generating unit 55a outputs the PWM signal output by the comparator 54a as a positive-phase PWM signal, and outputs the inverted signal as a negative-phase PWM signal. In practice, a dead time during which both are OFF is inserted between the positive-phase ON and the negative-phase ON to prevent simultaneous ON due to the switching time of the inverter unit, but this is omitted in FIG. 12. The counter upper limit value storage unit 52 stores and outputs the counter upper limit update value input from outside the PWM circuit as the counter upper limit value at the timing when counting down changes to counting up based on the up / down discrimination signal input from the PWM counter 51. The comparison value storage unit 53a stores and outputs the U-phase comparison value update value input from outside the PWM circuit as the U-phase comparison value at the timing when the count direction changes based on the up / down discrimination signal input from the PWM counter 51. The same applies to the V-phase and W-phase, and the comparison value storage units 53b, 53c, comparators 54b, 54c, and complementary / dead time generation units 55b, 55c for the V-phase and W-phase have the same functions as the comparison value storage unit 53a, comparator 54a, and complementary / dead time generation unit 55a for the U-phase, respectively.

[0007] The carrier period of the PWM signal can be expressed by the period of the clock signal input to the PWM circuit and the counter upper limit value stored in counter upper limit value storage unit 52, as shown in the following equation (1).

[0008] Carrier period = clock period × counter upper limit × 2 (1)

[0009] Moreover, the comparison value for a duty ratio of 50% is 1 / 2 the counter upper limit value. Therefore, even with the same duty ratio, the comparison value differs depending on the counter upper limit value determined from the carrier period and the clock period. FIG. 12 shows a case in which the second carrier period (T2) is made longer than the first carrier period (T1). In this case, the counter upper limit value of T2 is larger than the counter upper limit value of T1. FIG. 12 shows the difference in the comparison value for a 50% duty in the latter half (down-counting section) of the first carrier period (T1) and the first half (up-counting section) of the second carrier period (T2).

[0010] FIG. 10 is a block diagram showing the configuration of a motor system using a microcontroller 1 incorporating a conventional PWM circuit 5a described with reference to FIGS. 9 and 12. The microcontroller 1 functions as a motor control device. The motor system of FIG. 10 will be described below. A command value X is output to the microcontroller 1 from a higher-level control device (not shown). The command value X is the speed and rotation angle of a load. The motor system includes a detector 9 that detects the rotation angle of a motor 7. The rotation angle of the motor 7 is a position detection value of a load 8 that is connected to and driven by the motor 7, and is output as a position detection value θm via a detector interface 13. The motor system also includes a three-phase voltage-type inverter 6 that is driven by a PWM signal output by the microcontroller 1. The three-phase voltage-type inverter 6 supplies power to the motor 7. At least two phases (for example, Iu and Iv) of the three-phase current (Iu, Iv, Iw) flowing through the motor 7 are detected by current detectors 10 and 11, and output as current detection values ​​Iud and Ivd via an A / D converter 12.

[0011] The microcontroller 1 sequentially performs calculations of a position / speed control process 2, a current control process 3a, and a PWM output rate conversion process 4a in accordance with a stored program by the built-in CPU. The position / speed control process 2 receives a command value X and a position detection value θm as inputs, performs feedback processing by a position control loop and a speed control loop, and various feedforward processing, and outputs a torque command value Tc. The current control process 3a receives a torque command value Tc and current detection values ​​Iud and Ivd as inputs, performs feedback processing by a current control loop, and feedforward processing based on, for example, dq-axis control theory, and outputs voltage command values ​​Vuc, Vvc, and Vwc of three phases (U phase, V phase, and W phase). The PWM output rate conversion process 4a converts the voltage command values ​​Vuc, Vvc, and Vwc into comparison values ​​for the PWM circuit 5a and sets them in the PWM circuit 5a. The PWM circuit 5a is a conventional PWM circuit described using FIG. 9 and FIG. 12, and is a logic circuit built into the microcontroller 1 as a peripheral device.

[0012] Normally, the voltage command values ​​Vuc, Vvc, and Vwc are normalized by a power of 2 before being output. That is, in a three-phase voltage-type inverter with a DC voltage Vdc, if Vdc / 2 is defined as an output voltage of 0V, then the output voltage range is -Vdc / 2 to +Vdc / 2. With the voltage command values ​​Vuc, Vvc, and Vwc, the lower limit of the output voltage range, -Vdc / 2, is set as a PWM output rate of -100% (negative phase 100% ON), and the upper limit of the output voltage range, +Vdc / 2, is set as a PWM output rate of +100% (positive phase 100% ON), and the PWM output rate of 100% is normalized by the Nth power of 2 (hereinafter, expressed as 2^N). Here, N is a natural number.

[0013] When the voltage command values ​​Vuc, Vvc, and Vwc are normalized by 2^N', the counter upper limit value is set to Cmax, and the PWM output rate conversion process 4a is the calculation process of the following equations (2) to (4). Here, the division by 2^(N'+1) can be realized by a bit shift operation, so the calculation load can be reduced.

[0014] U-phase comparison value update value = Vuc × Cmax / 2^(N'+1) + Cmax / 2 (2) V-phase comparison value update value = Vvc × Cmax / 2^(N'+1) + Cmax / 2 (3) W-phase comparison value update value = Vwc × Cmax / 2^(N'+1) + Cmax / 2 (4)

[0015] The counter upper limit value Cmax may be a fixed value that is not synchronized with the PWM signal carrier and the position / speed control process 2 and current control process 3a, or it may be variable to synchronize the PWM signal carrier with the position / speed control process 2 and current control process 3a. When the counter upper limit value Cmax is variable, a carrier frequency changer (not shown) measures the timing between the PWM signal carrier and the position / speed control process 2 and current control process 3a, and based on the measured timing, changes and outputs the counter upper limit value Cmax within a certain range (for example, within a range of plus / minus a few percent) of the reference value of the counter upper limit value. [Prior art documents] [Patent documents]

[0016] [Patent Document 1] JP 2016-19276 A Summary of the Invention [Problem to be solved by the invention]

[0017] In a PWM inverter, power semiconductors such as IGBTs are switched at the carrier frequency of the PWM signal, which generates a ripple current that depends on the carrier frequency. From the perspective of reducing ripple current, a higher carrier frequency is preferable, but increasing the carrier frequency poses issues such as an increase in switching loss in the power semiconductors that is proportional to the carrier frequency, and the need to complete current control calculations in a shorter time also poses issues with microcontroller performance.

[0018] In recent years, the application of power semiconductors using wide band gap semiconductors such as SiC, which can perform faster switching than conventional power semiconductors using Si, has expanded, and carrier frequency restrictions caused by switching losses have been improved. In addition, performance improvements and cost reductions of devices with programmable logic circuits such as FPGAs have progressed, and by using FPGAs to implement logic circuits for current control processing, it has become possible to improve carrier frequency restrictions caused by microprocessor performance without developing ASICs.

[0019] Fig. 11 is a block diagram showing the configuration of a motor system including a motor control device using a microcontroller and an FPGA. Below, only the parts that differ from the motor control device explained above using Fig. 10 will be explained.

[0020] The FPGA 14 operates the current control circuit 3b, the PWM output rate conversion circuit A (reference symbol 4b), and the PWM circuit 5a in parallel by a programmed logic circuit. The current control circuit 3b realizes a function equivalent to the current control process 3a realized by the arithmetic processing of the microcontroller in the conventional example of FIG. 10 by using a logic circuit, and receives the torque command value Tc and the current detection values ​​Iud and Ivd as inputs, performs feedback processing by a current control loop, and feedforward processing based on, for example, dq-axis control theory, and outputs voltage command values ​​Vuc, Vvc, and Vwc of three phases (U phase, V phase, and W phase). Similarly, the PWM output rate conversion circuit A (reference symbol 4b) realizes a function equivalent to the PWM output rate conversion process 4a realized by the arithmetic processing of the microcontroller in the conventional example of FIG. 10 by using a logic circuit, and converts the voltage command values ​​Vuc, Vvc, and Vwc into comparison value update values ​​(U phase, V phase, and W phase) for the PWM circuit 5a and outputs them.

[0021] Here, the PWM output rate conversion circuit A (reference symbol 4b) needs to perform the calculations of the above-mentioned equations (2) to (4) using a logic circuit, and therefore requires three multiplication circuits.

[0022] In FPGAs, hardware multipliers that can perform high-speed multiplication processing are a finite resource, and it is desirable to limit the number of multipliers used. It is also possible to realize a multiplication circuit using programmable logic elements (hereinafter referred to as LE), but if a circuit that realizes multiplication in one clock is configured using LEs, the amount of LE usage and operating speed become issues. It is possible to improve the amount of LE usage and operating speed by making the multiplication a circuit that performs calculations in multiple clocks, but this leads to a decrease in throughput, which is a disadvantage to the purpose of using FPGAs, which is to speed up current control processing by implementing it as a logic circuit.

[0023] 11, in which the current control process is accelerated by the FPGA logic circuit, the current detection is oversampled with respect to the carrier frequency, and filtering is performed based on the relationship between the AD conversion timing and the switching timing based on the PWM counter, thereby reducing the ripple components superimposed on the current and improving the accuracy of the current detection. However, since the upper limit value of the PWM counter in the PWM circuit 5a is not normalized, the phase relationship between the PWM counter and the current detection timing cannot be easily determined, which is problematic as it is difficult to use for filtering the current detection. [Means for solving the problem]

[0024] The PWM control device of the present invention is characterized in that it has a normalization counter that counts up or down on average by 2^N / Cmax between 0 and 2^N for each clock signal input, where N is a natural number and Cmax is a value that changes according to a carrier period, and the PWM control device further has a comparator that compares the normalized count value of the normalization counter with a comparison value for determining the duty ratio of the PWM signal and outputs the comparison result as a PWM signal.

[0025] The PWM control device according to the present invention further comprises a PWM counter which counts up or down by one between 0 and Cmax for each input of the clock signal, counter comparison means which aligns and compares a count conversion value, which is the product of the normalized count value and Cmax, with a PWM count value of the PWM counter, and outputs the result as a counter comparison result, and counter increment calculation means, wherein 2^N / Cmax is defined as a counter increment reference value ΔC, and the counter increment calculation means calculates ΔC as a provisional counter increment value when the PWM counter counts up, and The counter may obtain -ΔC when the counter counts down, obtain a value obtained by shifting ΔC to the right by m bits as a counter correction reference value ΔCc, obtain ΔCc as a counter correction value if the PWM counter value is greater than the count conversion value in the counter comparison result, obtain -ΔCc if it is smaller, and obtain 0 if they are equal, obtain a value obtained by adding the counter correction value to the provisional counter increment value as a counter increment value, and the normalization counter adds the count increment value to a current normalized count value at the timing when the clock signal is input to update the normalized count value.

[0026] In the PWM control device of the present invention, the counter comparison means may align and compare the PWM count value of the PWM counter with the PWM count value of the PWM counter, using up to the nth decimal place of the N fixed decimal places of the count conversion value as the significant number of digits, and the n may satisfy the relationship 2^n≧Cd with respect to the number of delay clocks Cd until the normalized count value is reflected in updating the normalized count value via the counter comparison means and the counter increment calculation means.

[0027] In the PWM control device of the present invention, the m, which is the shift amount of the counter correction reference value ΔCc, may satisfy the relationship m0-1≦m≦m0+1, where m is the smallest integer m0 that satisfies 2^m0≧Cd×2^n for the n in the digit alignment of the counter comparison means and the delay clock number Cd.

[0028] In the PWM control device of the present invention, fixed-point bits of m bits or less may be added to the internal count value of the normalization counter and the counter increment reference value of the counter increment calculation means so that ΔC / 2^m does not become 0 with respect to ΔC and m. Effect of the Invention

[0029] According to the present invention, the upper limit of the normalized count value (carrier) compared with the comparison value for determining the duty ratio of the PWM signal can be made constant without depending on the carrier cycle. Therefore, even if the carrier cycle is changed, the comparison value at the same duty ratio becomes constant, and the conventional multiplier for the comparison value (multiplier in the PWM output rate conversion circuit) can be eliminated. Furthermore, by extracting the upper bits of the normalized count value, it is possible to easily obtain the phase relationship in units of 1 / power of 2 with respect to the PWM carrier cycle, which facilitates correction calculations such as filter processing for current detection. [Brief description of the drawings]

[0030] [Figure 1] FIG. 2 is a block diagram showing a normalized PWM circuit according to an embodiment. [Diagram 2] FIG. 1 is a block diagram showing a motor system including a motor control device using a microcontroller and an FPGA according to an embodiment. [Diagram 3] 1 is a block diagram showing a counter comparator according to an embodiment. [Figure 4] FIG. 2 is a block diagram illustrating a counter increment calculator according to an embodiment. [Diagram 5] 4 is a timing chart showing an example of changes in an internal signal in the embodiment. [Figure 6] 10 is an explanatory diagram of the relationship between a PWM count value and a count conversion value (Cd=1) in the embodiment. FIG. [Figure 7] 10 is an explanatory diagram of the relationship between a PWM count value and a count conversion value (Cd=2) in the embodiment. FIG. [Figure 8]4 is a timing chart of the normalized PWM circuit according to the embodiment. [Figure 9] FIG. 1 is a block diagram showing a PWM circuit in the prior art. [Figure 10] FIG. 1 is a block diagram showing a motor system according to a conventional technique. [Figure 11] FIG. 1 is a block diagram showing another motor system in the prior art. [Figure 12] 1 is a timing chart of a PWM circuit in the prior art. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0031] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the following, a case where a so-called triangular wave PWM signal is output will be described. FIG. 1 is a block diagram showing a normalized PWM circuit 5b according to the embodiment. FIG. 2 is a block diagram showing a motor system including a motor control device using a microcontroller and an FPGA according to the embodiment. The motor control device in FIG. 2 uses a PWM output rate conversion circuit B (reference 4c) that does not require multiplication instead of a PWM output rate conversion circuit A (reference 4b) that requires multiplication, and uses a normalized PWM circuit 5b instead of a PWM circuit 5a, in comparison with the motor control device (conventional technology) in FIG. 11. In the following, only the parts that are different from the conventional technology described so far will be described. In addition, in the following, the output of the PWM counter 51 will be referred to as a PWM count value or a PWM counter value. In addition, the output of the counter comparator 58 (see FIG. 1) will be referred to as a count comparison signal, a counter comparison signal, or a counter comparison result.

[0032] The PWM control device includes a normalization PWM circuit 5b. The normalization PWM circuit 5b in FIG. 1 includes a normalization counter 56 that counts up and down from 0 to 2^N in synchronization with the up and down count of the PWM counter 51 from 0 to the counter upper limit value Cmax. In this normalization PWM circuit 5b, instead of the PWM count value of the PWM counter 51, the normalization count value of the normalization counter 56 is output to the non-inverting input terminals of the comparators 54a, 54b, and 54c, thereby outputting a PWM signal using the normalization count value as a carrier. The normalization count value is multiplied by the counter upper limit value Cmax stored in the counter upper limit value storage unit 52 by the multiplier 57, and is output to the counter comparator 58 as a count conversion value. That is, the count conversion value can be expressed by the following formula (5). The count conversion value includes N fixed-point bits. The count conversion value includes N fixed-point bits because the normalized count value is normalized by 2^N with respect to the counter upper limit value Cmax, that is, when considered based on Cmax, the normalized count value includes N fixed-point bits.

[0033] Count conversion value = normalized count value × Cmax (5)

[0034] The counter comparator 58 compares the PWM count value with the count conversion value and outputs a count comparison signal to the counter increment calculator 59. The count comparison signal is output as 1 when the PWM count value is greater than the count conversion value, as -1 when the PWM count value is smaller, and as 0 when the PWM count value is equal to the count conversion value. Note that the above output value examples are determined for the convenience of explaining the function of this embodiment, and do not limit the actual form. The counter increment calculator 59 receives the counter increment reference value stored in the counter increment reference value storage unit 60, the counter comparison signal, and the up / down identification signal output by the PWM counter 51 as inputs, and calculates and outputs a count increment value. The normalization counter 56 adds the count increment value to the normalization count value by inputting a clock signal (not shown).

[0035] 2 calculates the counter increment reference value based on the reference value Cmax0 of the counter upper limit value Cmax and the counter upper limit value 2^N of the normalized counter using the following formula (6), and sets the counter increment reference value storage unit 60 in advance using an initial setting method (not shown). The counter increment reference value is a natural number.

[0036] Counter increment reference value = 2^N / Cmax0 (6)

[0037] FIG. 3 is a block diagram showing a configuration example of the counter comparator 58. The counter comparator 58 has pipeline registers 61a, 61b, and 61c that latch and output the input values ​​of the PWM counter value and count conversion value, which are inputs, and the counter comparison result, which is output, using a clock signal (not shown). The PWM counter value latched by the pipeline register 61a and the count conversion value latched by the pipeline register 61b are subjected to digit alignment processing by shift operators 581a and 581b, and are input to a comparator 582. The comparator 582 outputs 1 when the latched value of the PWM counter value is greater than the latched value of the count conversion value, -1 when it is smaller, and 0 when they are equal. The output of the comparator 582 is latched by a clock signal (not shown) via the pipeline register 61c, and is output as the counter comparison result. Note that if a sufficient operating frequency can be secured without providing a pipeline register, the pipeline registers 61a, 61b, and 61c may not be required. However, the enabled and disabled states of the pipeline registers 61a and 61b must be the same.

[0038] Here, the digit alignment by the shift calculator 581a and the shift calculator 581b will be described. As described above, the count conversion value includes N fixed-point bits for the PWM counter value. In order for the comparator 582 to perform a comparison including the n fixed-point bits, the shift calculator 581a shifts the latched value of the PWM counter left by n bits, i.e., adds n bits of 0 to the lower part of the latched value of the PWM counter below the LSB, and the shift calculator 581b shifts the latched value of the count conversion value right by (Nn) bits, i.e., extracts the nth bit as the LSB. The method of determining n will be described later.

[0039] 4 is a block diagram showing an example of the configuration of the counter increment calculator 59. The count direction selector 591 switches between a counter increment reference value (hereinafter, referred to as ΔC) and −ΔC whose sign is inverted by the sign inverter 592, depending on the up / down identification signal, and outputs the value. That is, when the up / down identification signal is an up-count, ΔC is output, and when it is a down-count, −ΔC is output. The shift calculator 593 shifts ΔC to the right by m bits, that is, takes out the mth bit as the LSB, and outputs a counter correction reference value ΔCc. The counter correction value selector 594 switches between ΔCc, −ΔCc whose sign is inverted by the sign inverter 595, and 0, depending on the counter comparison signal. That is, when the counter comparison signal is 1, ΔCc is output, when the counter comparison signal is -1, -ΔCc is output, and when the counter comparison signal is 0, 0 is output. The adder 596 adds the output of the count direction selector 591 and the output of the counter correction value selector 594, and outputs the result. The output of the adder 596 is latched by a pipeline register 61d with a clock signal (not shown) and output as a counter increment value. If a sufficient operating frequency can be ensured without providing a pipeline register, the pipeline register 61d may be omitted. A method for determining the shift number m of the shift calculator 593 will be described later.

[0040] In the following description, the number of delay clocks in the feedback path until the normalized count value of the normalization counter 56 in Fig. 1 is reflected in updating the normalized count via the multiplier 57, the counter comparator 58, and the counter increment calculator 59 is defined as Cd. The number of delay clocks Cd is Cd=L+1, where L is the number of stages of the pipeline register inserted in the feedback path.

[0041] Fig. 5 is a timing chart showing an example of changes in internal signals. Fig. 5(a) is a timing chart in the case of Cmax=2000, N=14, Cd=1, m=1, n=1. Fig. 5(b) is a timing chart in the case of Cmax=2000, N=14, Cd=2, m=2, n=1. In Figs. 5(a) and 5(b), the PWM count value (after digit alignment) represents the output of the shift calculator 581a in Fig. 3. Also, the count conversion value (after digit alignment) represents the output of the shift calculator 581b in Fig. 3, which is a value with less than the significant digits truncated.

[0042] Here, the counter comparator 58 will be further explained. Fig. 6 is an example of a timing chart of the PWM count value and the count conversion value when the comparison fixed-point bit width n=0 and Cd=1. In this figure, the count conversion value is expressed as a value (plot position) including a fixed-point part. Fig. 6(a) shows a case where the value obtained by rounding off the part of the count conversion value less than the number of significant digits (here, the decimal part because n=0) is compared with the PWM count value. Fig. 6(b) shows a case where the value obtained by truncating the part of the count conversion value less than the number of significant digits (here, the decimal part because n=0) is compared with the PWM count value.

[0043] The counter comparison result, which is the output of counter comparator 58, is normally 0, and when the difference between the PWM count value and the count conversion value after digit alignment exceeds a certain range, the counter comparison result becomes +1 or -1. The range in which the counter comparison result becomes +1 or -1 varies depending on the comparison fixed-point bit width n in Fig. 3 and the comparison method in comparator 582 in Fig. 3. Here, the comparison method means whether to round off or truncate the digits less than the number of significant digits of the count conversion value after digit alignment processing in shift calculator 581b in Fig. 3.

[0044] When the counter comparison result remains at 0, the difference between the PWM count value and the count conversion value monotonically decreases or increases. Figures 6(a) and (b) show the case of monotonically decreasing, and when the count conversion value falls below a predetermined range for the PWM count value (the range between the dashed line and the dashed line in the figure), the counter comparison result becomes 1 and the counter increment value is corrected in the positive direction. As a result, in the next cycle, the count conversion value returns to the predetermined range for the PWM count value again (the counter comparison result becomes 0). Note that when the comparison fixed-point bit width n increases by 1, the range in which the counter comparison result in Figures 6(a) and (b) is 0 narrows by half.

[0045] As shown in FIGS. 6(a) and 6(b), when the number of delay clocks Cd=1, the count increment value is corrected at the next clock after the counter comparison result changes to 1 or −1, and the count comparison result returns to 0.

[0046] Fig. 7 is an example of a timing chart of the PWM count value and the count conversion value when the delay clock count Cd=2. Fig. 7(a) shows the case where the comparison fixed-point bit width n=0. Fig. 7(b) shows the case where the comparison fixed-point bit width n=1. When the delay clock count Cd=2, as shown in Figs. 7(a) and (b), the counter increment value is not corrected in the clock next to when the counter comparison result changes to 1 or -1, so the difference between the PWM count value and the counter conversion value increases compared to when Cd=1.

[0047] Therefore, as shown in Fig. 7(b), the range where the counter comparison result is 0 can be narrowed by half by setting the comparison fixed-point bit width n=1. This makes it faster for the counter comparison result to change to 1 or -1, and therefore the correction of the counter increment value is also faster. As a result, it is possible to suppress the increase in the difference between the PWM count value and the count conversion value that occurs when Cd=2 is set.

[0048] It is preferable that the comparison fixed-point bit width n used for the comparison of the comparator 582 in Fig. 3 is determined according to the number of delayed clocks Cd. The comparison fixed-point bit width n should be set so as to satisfy 2^n ≧ Cd, where Cd is the number of delayed clocks. This makes the response of the comparator 582 faster in response to the delay due to the number of delayed clocks Cd, and makes the feedback to the normalization counter 56 in Fig. 1 faster.

[0049] Here, the setting of the counter correction shift number m of the shift calculator 593 in FIG. 4 will be considered. When the counter comparison signal changes from 0 to 1 or from 0 to -1, the state of 1 or -1 continues at least the number of delay clocks Cd. Therefore, the counter correction value needs to be equal to or less than 1 / Cd of the counter increment reference value. Also, the counter correction value needs to be reduced as the feedback to the normalization counter 56 in FIG. 1 becomes faster with the number of comparison fixed-point bits n. That is, the optimal value of the counter correction shift number m is the smallest integer that satisfies 2^m≧Cd×2^n according to the number of delay clocks Cd and the bit width n of the comparison fixed-point. The counter correction shift number m may be changed by about plus / minus 1 with respect to the optimal value.

[0050] The above-mentioned optimum value of the counter correction shift number m, which is the smallest integer that satisfies 2^m≧Cd×2^n, will be further explained. This is considered by dividing m=m1+m2 into the relationship between m1 and n and the relationship between Cd and m2.

[0051] The relationship between m1 and n is considered when Cd = 1. n is the number of effective bits of the fixed-point part when the PWM counter value and the count conversion value are compared in the counter comparator 58. Therefore, the width of the range in which the counter comparison result = 0 shown in Figures 6 and 7 is 1 / 2^n.

[0052] When Cd=1, the counter increment amount of the normalization counter 56 is corrected at the next clock after the counter comparison result changes to +1 or -1, so that the counter comparison result between the PWM count value and the count conversion value is returned to 0. Therefore, the correction value of the counter increment value is within the range in which the counter comparison result can be corrected to 0 in the unit system of the PWM count value, that is, equivalent to 1 / 2^n. This is what is meant by the above-mentioned "the counter correction value needs to be reduced as the feedback to the normalization counter 56 in FIG. 1 becomes faster with the comparison fixed-point bit count n."

[0053] If the correction amount 1 / 2^n of the counter increment value in the unit system of the PWM count value is changed to the counter correction reference value ΔCc' in the unit system of the normalized count value, the following formula (7) is obtained. Note that this formula uses the above formula (6).

[0054] ΔCc'=1 / 2^n×2^N / Cmax ≒1 / 2^n×2^N / Cmax0 ≒ΔC / 2^n (7)

[0055] From the above equation (7) and the explanation of the shift calculator 593 (see FIG. 4) mentioned above ("ΔC is shifted to the right by m bits, i.e., the mth bit is extracted as the LSB, and the counter correction reference value ΔCc is output"), when m1=n and Cd=1, the counter correction reference value ΔCc' is given by the following equation (8).

[0056] ΔCc'=ΔC / 2^m1=ΔC / 2^n ···(8)

[0057] The relationship between Cd and m2 is based on the above statement that "When the counter comparison signal changes from 0 to 1 or from 0 to -1, the state of 1 or -1 continues for at least the number of delay clocks Cd. Therefore, the counter correction value must be less than or equal to 1 / Cd of the counter increment reference value." The above description is based on the assumption that n=0, so if we replace the above "counter increment reference value" with the counter correction reference value Cc' when Cd=1, we obtain the following equation (9).

[0058] ΔCc' / 2^m2 ≦ΔCc' / Cd ΔC / 2^(m1+m2)≦ΔC / 2^n / Cd ΔC / 2^m ≦ΔC / 2^n / Cd 2^m ≧ Cd×2^n (9)

[0059] From the above formula (9), "the smallest integer that satisfies 2^m≧Cd×2^n," which is the optimal value of the counter correction shift number m, can be obtained. Note that in FIG. 4, when the counter increment reference value ΔC and the counter correction shift number m satisfy the relationship ΔC<2^m, the counter correction reference value ΔCc becomes 0, and the feedback to the normalization counter 56 in FIG. 1 does not function. In other words, if m is too large, the feedback to the normalization counter 56 does not function. To prevent this, the "smallest integer" is used in the above condition (condition for the optimal value of the counter correction shift number m).

[0060] As described above, when the counter increment reference value ΔC and the counter correction shift number m satisfy the relationship ΔC<2^m in Fig. 4, the counter correction reference value ΔCc becomes 0, and the feedback to the normalization counter 56 in Fig. 1 does not function. Therefore, to satisfy ΔCc ≧ 1, fixed-point bits with a bit width of m or less may be added to the internal count value of the normalization counter 56 in Fig. 1 and the count increment reference value set in the counter increment reference value storage unit 60. Even when fixed-point bits are added, the normalization counter 56 outputs only the integer part as the normalized count value.

[0061] 8 is a timing chart of the normalized PWM circuit of this embodiment, showing an example of outputting a PWM signal equivalent to that of FIG. 12. The PWM counter 51 counts up and down between 0 and the counter upper limit value Cmax(n), and the normalized counter 56 counts up and down between 0 and 2^N in synchronization with the PWM counter 51. That is, when the PWM counter 51 counts up from 0 to the counter upper limit value Cmax(n) with a slope of 1, the normalized PWM counter counts up from 0 to 2^N with an average slope of 2^N / Cmax(n), and when the PWM counter 51 counts down from the counter upper limit value Cmax(n) to 0 by -1, the normalized PWM counter counts down from 2^N to 0 with an average slope of 2^N / Cmax(n). The positive phase PWM signal and the negative phase PWM signal are generated by comparing the value of normalization counter 56 with the comparison value, not the value of PWM counter 51. Therefore, unlike the conventional technology of FIG. 12, the comparison value remains constant even if the carrier period is changed.

[0062] By configuring the PWM circuit as normalized PWM circuit 5b, PWM output rate conversion circuit B (reference symbol 4c) in Fig. 2 is simplified compared to PWM output rate conversion circuit A (reference symbol 4b) in Fig. 11. That is, by substituting Cmax=2^N and N=N'+1 into the above equations (2) to (4), the following equations (10) to (12) are obtained, and PWM output rate conversion circuit B (reference symbol 4c) can be configured using only addition processing without a multiplication circuit.

[0063] U phase comparison value update value = Vuc + 2^N' (10) V-phase comparison value update value = Vvc + 2^N' (11) W phase comparison value update value = Vwc + 2^N' (12)

[0064] So far, the present embodiment has been described as an example of a configuration using a so-called triangular wave PWM, which uses a counter that counts up and down as a carrier for a PWM signal, but the scope of the present invention is not limited to triangular wave PWM. For example, the present invention can be easily applied to a so-called sawtooth wave PWM, which clears the counter to 0 after reaching the upper limit value as a carrier for a PWM signal and continues counting up.

[0065] 1, the comparators 54a, 54b, and 54c output PWM signals, and the complementary / dead time generating units 55a, 55b, and 55c generate positive-phase PWM signals and negative-phase PWM signals with dead times, but this does not limit the scope of the present invention. For example, the count value of the normalization counter 56 may be compared with a positive-phase comparison value and a negative-phase comparison value by a comparator, and a positive-phase PWM signal and a negative-phase PWM signal may be output. In this case, the configuration may be combined with various known methods for outputting complementary PWM signals. [Explanation of symbols]

[0066] 1 Microcontroller, 2 Position and speed control processing, 3a Current control processing, 3b Current control circuit, 4a PWM output rate conversion processing, 4b, 4c PWM output rate conversion circuit, 5a PWM circuit, 5b Normalized PWM circuit, 6 Three-phase voltage-type inverter, 7 Motor, 8 Load, 9 Detector, 10, 11 Current detector, 12 A / D converter, 13 Detector interface, 14 FPGA, 51 PWM counter, 52 Counter upper limit value storage unit, 53a, 53b, 53c Comparison value storage unit, 54a, 54b, 54c Comparator, 55a, 55b, 55c Complementary and dead time generation unit, 56 Normalized counter, 57 Multiplier, 58 Counter comparator, 59 Counter increment calculator, 60 Counter increment reference value storage unit, 61a, 61b, 61c, 61d Pipeline register, 581a, 581b, 593 shift operator, 582 comparator, 591 count direction selector, 592, 595 sign inverter, 594 counter correction value selector, 596 adder.

Claims

1. A PWM control device, A normalization counter that counts up or down by an average of 2^N / Cmax between 0 and 2^N for each input of a clock signal is provided; The N is a natural number, The Cmax is a value that changes depending on the carrier period, the PWM control device further includes a comparator that compares the normalized count value of the normalization counter with a comparison value for determining a duty ratio of a PWM signal and outputs the comparison result as a PWM signal. A PWM control device comprising:

2. 2. The PWM control device according to claim 1, a PWM counter that counts up or down by one between 0 and Cmax for each input of the clock signal; a counter comparison means for comparing a count conversion value, which is a product of the normalized count value and the Cmax, with a PWM count value of the PWM counter after digit alignment, and outputting the result as a counter comparison result; A counter increment calculation means, The 2^N / Cmax is defined as a counter increment reference value ΔC, The counter increment calculation means As a provisional counter increment value, ΔC is obtained when the PWM counter counts up, and −ΔC is obtained when the PWM counter counts down; A value obtained by shifting ΔC to the right by m bits is obtained as the counter correction reference value ΔCc. As a counter correction value, ΔCc is obtained when the PWM counter value is larger than the count conversion value in the counter comparison result, −ΔCc is obtained when the PWM counter value is smaller, and 0 is obtained when the PWM counter value and the count conversion value are equal; obtaining a counter increment value by adding the counter correction value to the provisional counter increment value; The normalized counter is adding the count increment value to a current normalized count value at a timing when the clock signal is input, to update the normalized count value; A PWM control device comprising:

3. 3. The PWM control device according to claim 2, the counter comparison means performs a comparison with the PWM count value of the PWM counter by aligning the digits of the count conversion value with respect to the N-digit fixed decimal point, with the nth decimal point being the significant digit number; the n satisfies a relationship of 2^n≧Cd with respect to a delay clock count Cd until the normalized count value is reflected in updating the normalized count value via the counter comparison means and the counter increment calculation means; A PWM control device comprising:

4. 4. The PWM control device according to claim 3, the m, which is the shift amount of the counter correction reference value ΔCc, satisfies a relationship of m0-1≦m≦m0+1, where m0 is a minimum integer that satisfies 2^m0≧Cd×2^n for the n in the digit alignment of the counter comparison means and the number of delay clocks Cd; A PWM control device comprising:

5. 5. The PWM control device according to claim 4, adding m or less fixed-point bits to the internal count value of the normalization counter and the counter increment reference value of the counter increment calculation means so that ΔC / 2^m does not become 0 with respect to ΔC and m; A PWM control device comprising:

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