Electronic power devices integrated with an engineered substrate

Abstract

To provide methods and systems suitable for fabricating power devices using epitaxial growth processes.SOLUTION: A power device 900 includes: a substrate 910 comprising a polycrystalline ceramic core, a first adhesion layer coupled to the polycrystalline ceramic core, a barrier layer coupled to the first adhesion layer, a bonding layer coupled to the barrier layer, and a substantially single crystal layer 912 coupled to the bonding layer; a buffer layer 920 coupled to the substantially single crystal layer; and a channel region 930 coupled to the buffer layer. The channel region comprises a first end 924, a second end 926, and a central portion 928 disposed between the first end and the second end. The channel region includes: a channel region barrier layer (barrier layer 932, cap layer 934) coupled to the buffer layer; a source contact 940 disposed at the first end of the channel region; a drain contact 950 disposed at the second end of the channel region, and a gate contact 960 coupled to the channel region.SELECTED DRAWING: Figure 9

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to U.S. Provisional Patent Application No. 62 / 378,382, filed August 23, 2016, the disclosure of which is incorporated herein by reference in its entirety for all purposes. [Background technology]

[0002]

[0002] Gallium nitride based power devices are typically epitaxially grown on sapphire substrates. The growth of gallium nitride based power devices on sapphire substrates is a heteroepitaxial growth process because the substrate and epitaxial layers are composed of different materials. Due to the heteroepitaxial growth process, the epitaxially grown materials may exhibit various adverse effects, including reduced uniformity and reduced metrics related to the electronic / optical properties of the epitaxial layers. Thus, there is a technical need for improved methods and systems related to epitaxial growth processes and substrate structures. Summary of the Invention [Means for solving the problem]

[0003]

[0003] The present invention generally relates to power devices formed on engineered substrate structures. More specifically, the present invention relates to methods and systems suitable for fabricating power devices using epitaxial growth processes. As described herein, some embodiments of the present invention apply to methods and systems for fabricating power devices and semiconductor diodes by epitaxial growth on substrate structures, the substrate structures being characterized by a coefficient of thermal expansion (CTE) that substantially matches the epitaxial layers that form the power devices. The methods and techniques can be applied to a variety of semiconductor process steps.

[0004] According to one embodiment of the present invention, a power device is provided. The power device includes a substrate including a polycrystalline ceramic core, a first adhesion layer coupled to the polycrystalline ceramic core, a barrier layer coupled to the first adhesion layer, a bonding layer coupled to the barrier layer, and a substantially single crystalline layer coupled to the bonding layer. The power device also includes a buffer layer coupled to the substantially single crystalline layer and a channel region coupled to the buffer layer. The channel region includes a first end, a second end, and a central portion disposed between the first end and the second end. The channel region also includes a channel region barrier layer coupled to the buffer layer. The power device further includes a source contact disposed at the first end of the channel region, a drain contact disposed at the second end of the channel region, and a gate contact coupled to the channel region.

[0005] According to another embodiment of the present invention, there is provided a method of forming a power device. The method includes forming a substrate by providing a polycrystalline ceramic core, encapsulating the polycrystalline ceramic core with a first adhesive shell, encapsulating the first adhesive shell with a barrier layer, forming a bonding layer on the barrier layer, and bonding a substantially single crystalline layer to the bonding layer. The method also includes forming a buffer layer on the substantially single crystalline layer, and forming a channel region on the buffer layer by forming an epitaxial channel region barrier layer on the buffer layer. The channel region has a first end, a second end, and a central portion between the first end and the second end. The method also includes forming a source contact at the first end of the channel region, forming a drain contact at the second end of the channel region, and forming a gate contact on the channel region.

[0006]

[0006] In accordance with certain embodiments of the present invention, a semiconductor diode is provided. The semiconductor diode includes a substrate including a polycrystalline ceramic core, a first adhesion layer bonded to the polycrystalline ceramic core, a barrier layer bonded to the first adhesion layer, a bonding layer bonded to the barrier layer, and a substantially single-crystalline layer bonded to the bonding layer. The semiconductor diode also includes a buffer layer bonded to the substantially single-crystalline layer, a semi-insulating layer bonded to the buffer layer, and a first N-type gallium nitride layer bonded to the semi-insulating layer. The first N-type gallium nitride layer has a first doping concentration. The semiconductor diode further includes a second N-type gallium nitride layer bonded to the first N-type gallium nitride layer. The second N-type gallium nitride layer has a second doping concentration that is lower than the first doping concentration. The semiconductor diode further includes a P-type gallium nitride layer coupled to the second N-type gallium nitride layer, an anode contact coupled to the P-type gallium nitride layer, and a cathode contact coupled to a portion of the first N-type gallium nitride layer.

[0007] According to another specific embodiment of the present invention, a method of forming a semiconductor diode is provided. The method includes forming a substrate by providing a polycrystalline ceramic core, encapsulating the polycrystalline ceramic core with a first adhesive shell, encapsulating the first adhesive shell with a barrier layer, forming a bonding layer on the barrier layer, and bonding a substantially monocrystalline layer to the bonding layer. The method also includes forming a buffer layer on the substantially monocrystalline layer, forming a semi-insulating layer on the buffer layer, and forming a first epitaxial N-type gallium nitride layer on the semi-insulating layer. The first epitaxial N-type gallium nitride layer has a first doping concentration. The method further includes forming a second epitaxial N-type gallium nitride layer on the first epitaxial N-type gallium nitride layer. The second epitaxial N-type gallium nitride layer has a second doping concentration that is lower than the first doping concentration. The method further includes forming an epitaxial P-type gallium nitride layer on the second epitaxial N-type gallium nitride layer; removing a portion of the second epitaxial N-type gallium nitride layer and a portion of the epitaxial P-type gallium nitride layer to expose a portion of the first epitaxial N-type gallium nitride layer; forming an anode contact on a remaining portion of the epitaxial P-type gallium nitride layer; and forming a cathode contact on the exposed portion of the first epitaxial N-type gallium nitride layer.

[0008]

[0008] In accordance with certain embodiments of the present invention, a method for forming a semiconductor diode is provided. The method includes forming a substrate by providing a polycrystalline ceramic core, encapsulating the polycrystalline ceramic core with a first adhesive shell, encapsulating the first adhesive shell with a barrier layer, forming a bonding layer on the barrier layer, and bonding a substantially single-crystalline layer to the bonding layer. The method also includes forming a first epitaxial N-type gallium nitride layer on the substantially single-crystalline layer, and forming a second epitaxial N-type gallium nitride layer on the first epitaxial N-type gallium nitride layer. The first epitaxial N-type gallium nitride layer has a first doping concentration and the second epitaxial N-type gallium nitride layer has a second doping concentration that is less than the first doping concentration. The method further includes forming an epitaxial P-type gallium nitride layer on the second epitaxial N-type gallium nitride layer; removing a portion of the substrate to expose a surface of the first epitaxial N-type gallium nitride layer; forming an anode contact on the epitaxial P-type gallium nitride layer; and forming a cathode contact on the exposed surface of the first epitaxial N-type gallium nitride layer.

[0009]

[0009] According to another specific embodiment of the present invention, a power device is provided. The power device includes a substrate including a polycrystalline ceramic core, a first adhesion layer bonded to the polycrystalline ceramic core, a barrier layer bonded to the first adhesion layer, a bonding layer bonded to the barrier layer, and a substantially single crystalline layer bonded to the bonding layer. The power device also includes a buffer layer bonded to the substantially single crystalline layer and a channel region bonded to the buffer layer. The channel region includes a first end, a second end, and a central portion disposed between the first end and the second end. The channel region includes a channel region barrier layer bonded to the buffer layer and a source contact disposed at the first end of the channel region. The device further includes a drain contact disposed at the second end of the channel region and a gate contact coupled to the channel region. By way of example, the buffer layer may include at least one of III-V semiconductor materials, silicon germanium, aluminum gallium nitride, indium gallium nitride, or indium aluminum gallium nitride.

[0010]

[0010] Many advantages are achieved by the present invention over the prior art. For example, embodiments of the present invention provide power devices and semiconductor diodes formed on engineered substrates having a coefficient of thermal expansion (CTE) that substantially matches the CTE of the epitaxial layers of the devices. Matching the thermal expansion properties of the growth substrate with the epitaxial layers reduces stress in the epitaxial layers and / or engineered substrates. Stress is the source of several types of defects. For example, stress can increase dislocation density in the epitaxial layers, which impairs the electrical and optical properties of the epitaxial layers. Stress can also result in residual strain in the epitaxial layers or substrates, which can lead to further processing concerns in later steps, such as stress cracking, dislocation glide, slippage, bending and warping. Bending and warping of the substrate due to thermal expansion can make the material difficult to handle in automated equipment and limit the ability to perform additional lithography steps required for device fabrication, substrate cracking, and material creep. In addition, stressed materials shorten the performance life of devices. Stress relaxation and stress-induced crack propagation, dislocation glide, and other lattice motions resulting from thermal mismatch can lead to premature failure in modes ranging from degradation of device performance to fracture or delamination of devices and device layers.

[0011]

[0011] These and other embodiments of the present invention, together with many of its advantages and features, are described in more detail in conjunction with the following text and accompanying drawings. [Brief description of the drawings]

[0012] [Figure 1] 1 is a simplified schematic cross-sectional view illustrating an engineered substrate structure according to one embodiment of the present invention. [Figure 2A] 1 is a SIMS profile showing species concentration as a function of depth for an engineered structure according to one embodiment of the present invention. [Figure 2B] 1 is a SIMS profile showing species concentration as a function of depth for an annealed engineered structure in accordance with an embodiment of the present invention. [Figure 2C]4 is a SIMS profile showing species concentration as a function of depth for a processed structure having a silicon nitride layer after annealing, in accordance with one embodiment of the present invention. [Diagram 3] 1 is a simplified schematic cross-sectional view illustrating an engineered substrate structure according to another embodiment of the present invention. [Figure 4] 1 is a simplified schematic cross-sectional view illustrating an engineered substrate structure according to yet another embodiment of the present invention. [Diagram 5] 4 is a simplified flow chart illustrating a method of manufacturing an engineered substrate according to one embodiment of the present invention. [Figure 6] 5 is a simplified flow chart illustrating a method of manufacturing an engineered substrate according to another embodiment of the present invention. [Figure 7] FIG. 2 is a simplified schematic cross-sectional view illustrating an epitaxial / engineered substrate structure for RF and power applications according to one embodiment of the present invention. [Figure 8A] FIG. 2 is a simplified schematic diagram illustrating III-V epitaxial layers on an engineered substrate structure according to one embodiment of the present invention. [Figure 8B] FIG. 2 is a simplified schematic plan view illustrating a via configuration for a semiconductor device formed on an engineered substrate in accordance with another embodiment of the present invention. [Figure 9] 1 is a simplified schematic cross-sectional view illustrating a lateral power device formed on an engineered substrate in accordance with an embodiment of the present invention. [Figure 10] 4 is a simplified flow chart illustrating a method for fabricating a lateral power device on an engineered substrate in accordance with one embodiment of the present invention. [Figure 11A] 1 is a simplified schematic cross-sectional view illustrating a lateral power device formed on an engineered substrate according to another embodiment of the present invention. [Figure 11B] 1 is a simplified schematic cross-sectional view illustrating a lateral power device formed on an engineered substrate according to another embodiment of the present invention. [Figure 11C] FIG. 1 is a simplified schematic cross-sectional view illustrating an exploded view of a P-type gallium nitride structure according to one embodiment of the present invention. [Figure 12]5 is a simplified flow chart illustrating a method for fabricating a lateral power device on an engineered substrate in accordance with another embodiment of the present invention. [Figure 13] 1 is a simplified schematic cross-sectional view illustrating a vertical semiconductor diode formed on an engineered substrate in accordance with one embodiment of the present invention. [Figure 14] 4 is a simplified flow chart illustrating a method of fabricating a vertical semiconductor diode on an engineered substrate in accordance with another embodiment of the present invention. [Figure 15] 2 is a simplified schematic cross-sectional view illustrating a vertical semiconductor diode formed on an engineered substrate in accordance with another embodiment of the present invention. [Figure 16] 4 is a simplified flow chart illustrating a method of fabricating a vertical semiconductor diode on an engineered substrate in accordance with another embodiment of the present invention. [Figure 17] 1 is a simplified schematic cross-sectional view illustrating a semiconductor device formed on an engineered substrate in accordance with one embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013]

[0034] The present invention relates generally to power devices formed on engineered substrate structures. More specifically, the present invention relates to methods and systems suitable for fabricating power devices using epitaxial growth processes. By way of example only, the present invention applies to methods and systems for fabricating power devices on substrate structures by epitaxial growth, the substrate structures being characterized by a coefficient of thermal expansion (CTE) that substantially matches the epitaxial layers that form the power devices. The methods and techniques can be applied to a variety of semiconductor process steps.

[0014]

[0035] FIG 1 is a simplified schematic cross-sectional view illustrating an engineered substrate structure according to one embodiment of the present invention. Engineered substrate 100, shown in FIG 1, is suitable for a variety of electronic and optical applications. Engineered substrate 100 includes a core 110 that can have a coefficient of thermal expansion (CTE) that substantially matches the CTE of an epitaxial material grown on engineered substrate 100. Epitaxial material 130 is not required as an element of engineered substrate 100, but is shown as optional since it is typically grown on engineered substrate 100.

[0015]

[0036] For applications involving the growth of gallium nitride (GaN) based materials (epitaxial layers including GaN based layers), the core 110 may be a polycrystalline ceramic material, for example, polycrystalline aluminum nitride (AlN), which may include a binder material such as yttrium oxide. Other materials may be utilized for the core 110, including polycrystalline gallium nitride (GaN), polycrystalline aluminum gallium nitride (AlGaN), polycrystalline silicon carbide (SiC), polycrystalline zinc oxide (ZnO), polycrystalline gallium trioxide (Ga2O3), and the like.

[0016]

[0037] The thickness of the core may be on the order of 100-1500 μm, for example 725 μm. The core 110 is encapsulated in an adhesion layer 112, which may be referred to as a shell or encapsulation shell. In one embodiment, the adhesion layer 112 comprises a tetraethylorthosilicate (TEOS) oxide layer having a thickness on the order of 1000 A (angstroms). In other embodiments, the thickness of the adhesion layer varies, for example, from 100 A to 2000 A. Although TEOS oxide is utilized for the adhesion layer in some embodiments, other materials that provide adhesion between a subsequently deposited layer and an underlying layer or material (e.g., ceramic, particularly polycrystalline ceramic) may also be utilized in accordance with embodiments of the present invention. For example, SiO2 or other silicon oxides (Si x O y) adheres well to ceramic materials and provides a suitable surface for subsequent deposition of, for example, conductive materials. In some embodiments, adhesion layer 112 completely surrounds core 110, forming a completely encapsulated core. Adhesion layer 112 may be formed using an LPCVD process. The adhesion layer provides a surface onto which subsequent layers adhere to form elements of the engineered substrate 100 structure.

[0017]

[0038] In addition to using LPCVD processes, furnace-based processes, and the like, to form the encapsulating first adhesion layer, other semiconductor processes, including CVD processes or similar deposition processes, can be utilized in accordance with embodiments of the present invention. As an example, a deposition process can be utilized to coat a portion of the core, the core can be turned over, and the deposition process can be repeated to coat an additional portion of the core. Thus, while LPCVD techniques are utilized in some embodiments to provide a fully encapsulated structure, other film formation techniques can be utilized depending on the particular application.

[0018]

[0039] A conductive layer 114 is formed surrounding the adhesion layer 112. In one embodiment, the conductive layer 114 is a shell of polysilicon (i.e., polycrystalline silicon) that is formed surrounding the first adhesion layer 112 because polysilicon has poor adhesion to ceramic materials. In embodiments in which the conductive layer 114 is polysilicon, the thickness of the polysilicon layer may be on the order of 500-5000 A, for example 2500 A. In some embodiments, the polysilicon layer may be formed as a shell to completely surround the first adhesion layer 112 (e.g., a TEOS oxide layer), thereby forming a completely encapsulated first adhesion layer, which may be formed using an LPCVD process. In other embodiments, as described below, the conductive material may be formed on a portion of the adhesion layer, for example, on the bottom half of the substrate structure. In some embodiments, the conductive material may be formed as a completely encapsulated layer and subsequently removed on one side of the substrate structure.

[0019]

[0040] In one embodiment, the conductive layer 114 may be a polysilicon layer doped to provide a highly conductive material, for example a polysilicon layer doped with boron to provide a P-type polysilicon layer. In some embodiments, the doping with boron is on the order of 1×10 to provide high conductivity. 19 cm -3 ~1×10 20 cm -3 The level of other dopants with different dopant concentrations (e.g., 1×10 16 cm -3 ~5×10 18 cm -3 Dopant concentrations ranging from 0.1 to 1000 nm (e.g., phosphorous, arsenic, bismuth, etc.) can be utilized to provide either N-type or P-type semiconductor materials suitable for use in conductive layer 114. One of ordinary skill in the art would recognize many variations, modifications, and alternatives.

[0020]

[0041] The presence of conductive layer 114 is useful during electrostatic chucking of processed substrate 100 to a semiconductor processing tool, such as a tool having an electrostatic discharge (ESD) chuck. Conductive layer 114 allows for rapid dechucking after processing in the semiconductor processing tool. Thus, embodiments of the present invention provide a substrate structure that can be processed in the manner utilized with conventional silicon wafers. One of ordinary skill in the art would recognize many variations, modifications, and alternatives.

[0021]

[0042] A second adhesion layer 116 (e.g., a TEOS oxide layer with a thickness on the order of 1000 A) is formed surrounding the conductive layer 114. In some embodiments, the second adhesion layer 116 completely surrounds the conductive layer 114, forming a completely encapsulated structure. The second adhesion layer 116 can be formed using an LPCVD process, a CVD process, or any other suitable deposition process, including deposition of a spin-on dielectric.

[0022]

[0043] A barrier layer 118, for example a silicon nitride layer, is formed to surround the second adhesive layer 116. In one embodiment, the barrier layer is a silicon nitride layer 118 having a thickness on the order of about 4000A to 5000A. In some embodiments, the barrier layer 118 completely surrounds the second adhesive layer 116, forming a fully encapsulated structure, and can be formed using an LPCVD process. In addition to silicon nitride layers, amorphous materials can be utilized as the barrier layer, including SiCN, SiON, AlN, SiC, and the like. In some implementations, the barrier layer is comprised of several auxiliary layers constructed to form the barrier layer. Thus, the term barrier layer is not intended to mean a single layer or material, but rather to encompass one or more materials stacked together in a composite manner. One skilled in the art would recognize many variations, modifications, and alternatives.

[0023]

[0044] In some embodiments, the barrier layer, e.g., a silicon nitride layer, prevents diffusion and / or outgassing of elements present in the core 110 into the environment of a semiconductor processing chamber in which the engineered substrate 100 may reside, e.g., during a high temperature (e.g., 1000° C.) epitaxial growth process. Elements present in the core 110 may include, e.g., yttrium oxide (i.e., yttria), oxygen, metallic impurities, other trace elements, and the like. Elements that diffuse out of the core 110 may cause unintended doping of the engineered layers 120 / 122. Elements that are out-emitted from the core 110 may migrate through the chamber and adsorb elsewhere on the wafer, causing impurities in the engineered layers 120 / 122 and epitaxial material 130. Utilizing the encapsulation layers described herein, ceramic materials including polycrystalline AlN designed for non-cleanroom environments may be utilized in semiconductor process flows and cleanroom environments.

[0024]

[0045] FIG. 2A is a secondary ion mass spectrometry (SIMS) profile showing species concentration as a function of depth for an engineered structure according to an embodiment of the present invention. The x-axis represents the depth 202 from the surface of the engineered layer 120 / 122 to the core 110. The line 208 represents the interface between the engineered layer 120 / 122 and the core 110. The first y-axis represents the species concentration 204 in atoms per cubic centimeter. The second y-axis represents the signal intensity of the ions in counts per second 206. The engineered structure of FIG. 2A did not include a barrier layer 118. With reference to FIG. 2A, some species present in the ceramic core 110 (e.g., yttrium, calcium, and aluminum) are reduced to negligible concentrations in the engineered layer 120 / 122. The concentrations of calcium 210, yttrium 220, and aluminum 230 are reduced by 3, 4, and 6 orders of magnitude, respectively.

[0025]

[0046] 2B is a SIMS profile showing species concentration as a function of depth for a processed structure without a barrier layer after annealing according to an embodiment of the present invention. As mentioned above, during semiconductor processing steps, the processed substrate structure provided by an embodiment of the present invention may be exposed to high temperatures (about 1100° C.) for several hours, for example during epitaxial growth of GaN-based layers. For the profile shown in FIG. 2B, the processed substrate structure was annealed at 1100° C. for 4 hours. As shown in FIG. 2B, calcium 210, yttrium 220, and aluminum 230, originally present in low concentrations in the processed layer 120 / 122, diffuse into the processed layer 120 / 122 and reach similar concentrations to the other elements.

[0026]

[0047] Thus, embodiments of the present invention incorporate a barrier layer (e.g., a silicon nitride layer) to prevent out-diffusion of background elements from the polycrystalline ceramic material (e.g., AlN) into the working layers 120 / 122 and optional epitaxial material 130, such as a GaN layer. The silicon nitride layer encapsulates the underlying layers and materials and provides the desired barrier layer 118 functionality.

[0027]

[0048] FIG. 2C is a SIMS profile showing species concentration as a function of depth for a processed structure having a barrier layer 118, represented by dashed line 240, after annealing according to one embodiment of the present invention. The integration of a diffusion barrier layer 118 (e.g., a silicon nitride layer) into the processed substrate structure prevents calcium, yttrium, and aluminum from diffusing into the processed layer during the annealing process that occurred when the diffusion barrier layer was not present. As shown in FIG. 2C, calcium 210, yttrium 220, and aluminum 230 present in the ceramic core remain in low concentrations in the processed layer after annealing. Thus, the use of a barrier layer 118 (e.g., a silicon nitride layer) prevents these elements from diffusing through the diffusion barrier, thereby preventing them from being released into the environment surrounding the processed substrate. Similarly, any other impurities contained within the bulk ceramic material will be accommodated by the barrier layer.

[0028]

[0049] Typically, the ceramic material utilized to form the core 110 is fired at a temperature in the range of 1,800°C. It is expected that this process will drive off a significant amount of impurities present in the ceramic material. These impurities may include yttrium, calcium, and other elements and compounds resulting from the use of yttria as a sintering agent. Subsequent diffusion of these impurities during the epitaxial growth process, which is carried out at much lower temperatures in the range of 800°C to 1100°C, would be expected to be insignificant. However, contrary to conventional expectations, the present inventors have determined that there is significant diffusion of elements through the layers of the engineered substrate even during the epitaxial growth process at temperatures much lower than the firing temperature of the ceramic material. Accordingly, embodiments of the present invention integrate a barrier layer 118 into the engineered substrate 100 to prevent this undesired diffusion.

[0029]

[0050] Referring again to FIG. 1, a bonding layer 120 (e.g., a silicon oxide layer) is deposited on a portion of the barrier layer 118, e.g., on top of the barrier layer, and subsequently used during bonding of the monocrystalline layer 122. The bonding layer 120 may be approximately 1.5 μm thick in some embodiments. The monocrystalline layer 122 may include, for example, Si, SiC, sapphire, GaN, AlN, SiGe, Ge, diamond, Ga2O3, AlGaN, InGaN, InN, and / or ZnO. In some embodiments, the monocrystalline layer may have a thickness of 0-0.5 μm. The monocrystalline layer 122 is suitable for use as a growth layer during an epitaxial growth process to form the epitaxial material 130. The crystalline layer of the epitaxial material 130 is an extension of the underlying semiconductor lattice associated with the monocrystalline layer 122. The unique CTE matching properties of the engineered substrate 100 allow for the growth of a thicker epitaxial material 130 than existing techniques. In some embodiments, the epitaxial material 130 comprises a gallium nitride layer having a thickness of 2 μm to 10 μm, which may be utilized as one of multiple layers utilized in optoelectronic devices, power devices, etc. In one embodiment, the bonding layer 120 comprises a single crystal silicon layer that is attached to the silicon oxide barrier layer 118 using a layer transfer process.

[0030]

[0051] FIG. 3 is a simplified schematic cross-sectional view illustrating an engineered substrate structure according to one embodiment of the present invention. Engineered substrate 300, shown in FIG. 3, is suitable for a variety of electronic and optical applications. Engineered substrate 300 includes a core 110 that can have a coefficient of thermal expansion (CTE) that substantially matches the CTE of an epitaxial material grown on engineered substrate 300. Epitaxial material 130 is not required as an element of the engineered substrate structure, but is shown as optional since it is typically grown on the engineered substrate structure.

[0031]

[0052] For applications involving the growth of gallium nitride (GaN) based materials (epitaxial layers including GaN based layers), the core 110 may be a polycrystalline ceramic material, for example polycrystalline aluminum nitride (AlN). The thickness of the core may be on the order of 100 μm to 1500 μm, for example 725 μm. The core 110 is encapsulated in an adhesion layer 112, which may be referred to as a shell or encapsulation shell. In this embodiment, the adhesion layer 112 completely encapsulates the core, although this is not required by the invention, as will be explained in more detail with respect to FIG. 4.

[0032]

[0053] In one embodiment, adhesion layer 112 comprises a tetraethylorthosilicate (TEOS) oxide layer on the order of 1000 A thick. In other embodiments, the thickness of the adhesion layer varies, for example, from 100 A to 2000 A. While TEOS oxide is utilized for the adhesion layer in some embodiments, other materials that provide adhesion between a subsequently deposited layer and the layer or material below may also be utilized in accordance with embodiments of the present invention. For example, SiO2, SiON, etc., adhere well to ceramic materials and provide a suitable surface for subsequent deposition of, for example, conductive materials. In some embodiments, adhesion layer 112 completely surrounds core 110, forming a fully encapsulated core, and may be formed using an LPCVD process. Adhesion layer 112 provides a surface onto which subsequent layers adhere to form elements of the engineered substrate structure.

[0033]

[0054] In addition to using an LPCVD process, furnace-based process, or the like to form the encapsulating adhesion layer 112, other semiconductor processes may be utilized in accordance with embodiments of the present invention. As an example, a deposition process, e.g., CVD, PECVD, or the like, may be utilized to coat a portion of the core 110, the core 110 may be turned over, and the deposition process may be repeated to coat an additional portion of the core 110.

[0034]

[0055] A conductive layer 314 is formed over at least a portion of the adhesion layer 112. In one embodiment, the conductive layer 314 comprises polysilicon (i.e., polycrystalline silicon) formed by a deposition process on a bottom (e.g., bottom half or back side) of the structure formed by the core 110 and the adhesion layer 112. In embodiments in which the conductive layer 314 is polysilicon, the thickness of the polysilicon layer may be on the order of a few thousand angstroms, for example, 3000 A. In some embodiments, the polysilicon layer may be formed using an LPCVD process.

[0035]

[0056] In one embodiment, the conductive layer 314 may be a polysilicon layer that is doped to provide a highly conductive material, for example, the conductive layer 314 may be doped with boron to provide a P-type polysilicon layer. In some embodiments, the doping with boron is about 1×10 to provide high conductivity. 19 cm -3 ~1×10 20 cm -3 The conductive layer 314 is preferably at a level in the range of 0.1 to 1.0 μm. The presence of the conductive layer 314 is useful in electrostatically chucking the engineered substrate to a semiconductor processing tool, such as a tool having an electrostatic discharge (ESD) chuck. The conductive layer 314 allows for rapid dechucking after processing. Thus, embodiments of the present invention provide a substrate structure that can be processed in the manner utilized with conventional silicon wafers. One of ordinary skill in the art would recognize many variations, modifications, and alternatives.

[0036]

[0057] A second adhesion layer 316 (e.g., a second TEOS oxide layer) is formed to surround the conductive layer 314 (e.g., a polysilicon layer). The thickness of the second adhesion layer 316 is on the order of 1000 A. In some embodiments, the second adhesion layer 316 completely surrounds the conductive layer 114 to form a fully encapsulated structure and may be formed using an LPCVD process.

[0037]

[0058] A barrier layer 118 (e.g., a silicon nitride layer) is formed surrounding the second adhesion layer 316. In some embodiments, the barrier layer 118 has a thickness on the order of 4000 A to 5000 A. In some embodiments, the barrier layer 118 completely surrounds the second adhesion layer 316, forming a completely encapsulated structure, and may be formed using an LPCVD process.

[0038]

[0059] In some embodiments, the use of a barrier layer 118 comprising silicon nitride prevents diffusion and / or outgassing of elements present in the core 110 into the environment of a semiconductor processing chamber in which a fabricated substrate may reside, for example, during a high temperature (e.g., 1000° C.) epitaxial growth process. Elements present in the core include, for example, yttrium oxide (i.e., yttria), oxygen, metallic impurities, other trace elements, etc. Utilizing the encapsulation layers described herein, ceramic materials including polycrystalline AlN designed for non-cleanroom environments can be utilized in semiconductor process flows and cleanroom environments.

[0039]

[0060] In some embodiments, the engineered substrate 100 can conform to Semiconductor Equipment and Materials Institute (SEMI) standard specifications. Because the engineered substrate 100 can conform to SEMI specifications, the engineered substrate 100 can be used with existing semiconductor manufacturing tools. For example, the engineered substrate wafer diameter can be 4 inches, 6 inches, or 8 inches. In some embodiments, an 8-inch engineered substrate wafer can be 725-750 μm thick. In contrast, current silicon substrates used to fabricate gallium nitride epitaxial layers do not conform to SEMI specifications because of their thickness of 1050-1500 μm. As a result of the non-compliance, the silicon substrates cannot be used in equipment that conforms to SEMI specifications.

[0040]

[0061] FIG. 4 is a simplified schematic cross-sectional view illustrating an engineered substrate structure 400 according to another embodiment of the present invention. In the embodiment shown in FIG. 4, an adhesive layer 412 is formed over at least a portion of the core 110, but does not encapsulate the core 110. In this implementation, the adhesive layer 412 is formed on the underside of the core (the backside of the core) to enhance adhesion of a subsequently formed conductive layer 414, as described more fully below. Although the adhesive layer 412 is only shown on the underside of the core in FIG. 4, it will be understood that deposition of adhesive layer material on other portions of the core will not adversely affect the performance of the engineered substrate structure, and such material may be present in various embodiments. Those skilled in the art will recognize many variations, modifications, and alternatives.

[0041]

[0062] The conductive layer 414 is not formed as a shell as shown in FIG. 3, but does not encapsulate the adhesive layer 412 and the core 110, but is substantially aligned with the adhesive layer 412. Although the conductive layer 414 is illustrated as extending along a portion of the bottom or back and side of the adhesive layer 412, this is not required by the present invention. Thus, embodiments may utilize deposition on one side of the substrate structure, masking of one side of the substrate structure, and the like. The conductive layer 414 may be formed on one side of the adhesive layer 412, e.g., a portion of the bottom / back side. The conductive layer 414 provides electrical conduction on one side of the engineered substrate structure 400, which may be advantageous in RF and high power applications. The conductive layer 414 may include doped polysilicon as described with respect to the conductive layer 114 of FIG. 1. In addition to semiconductor-based conductive layers, in other embodiments, the conductive layer 414 is a metal layer, e.g., 500A titanium, and the like.

[0042]

[0063] A portion of the core 110, a portion of the adhesive layer 412, and the conductive layer 414 are covered with a second adhesive layer 416 to enhance adhesion to the material underlying the barrier layer 418. The barrier layer 418 forms an encapsulation structure to prevent diffusion from the underlying layers, as discussed above in connection with Figures 2A, 2B, and 2C.

[0043]

[0064] Referring again to FIG. 4, depending on the implementation, one or more layers may be removed. For example, layers 412, 414 may be removed, leaving only a single adhesive shell 416 and barrier layer 418. In another embodiment, only layer 414 may be removed, leaving only a single adhesive layer 412 below the barrier layer 418. In this embodiment, adhesive layer 412 may also balance the stress and wafer warpage caused by bonding layer 120, deposited on top of barrier layer 418. Building a substrate structure with an insulating layer on top of core 110 (e.g., having only an insulating layer between core 110 and bonding layer 120) may benefit power / RF applications where a highly insulating substrate is desired.

[0044]

[0065] In another embodiment, the barrier layer 418 may directly encapsulate the core 110, followed by the conductive layer 414, followed by the adhesive layer 416. In this embodiment, the bonding layer 120 may be deposited directly onto the adhesive layer 416 from the top. In yet another embodiment, the adhesive layer 416 may be deposited onto the core 110, followed by the barrier layer 418, then the conductive layer 414, and then another adhesive layer 412.

[0045]

[0066] Although some embodiments have been discussed in terms of layers, it should be understood that the term layer can include several sub-layers that are constructed to form the layer of interest. Thus, the term layer does not mean a single layer of a single material, but is intended to encompass one or more materials that are compositely layered to form a desired structure. Those skilled in the art will recognize many variations, modifications, and alternatives.

[0046]

[0067] FIG. 5 is a simplified flow chart illustrating a method for fabricating an engineered substrate according to an embodiment of the present invention. The method can be utilized to fabricate a substrate that is CTE-matched to one or more epitaxial layers grown on the substrate. The method 500 includes forming a support structure by providing a polycrystalline ceramic core (510), encapsulating the polycrystalline ceramic core in a first adhesion layer that forms a shell (e.g., a tetraethylorthosilicate (TEOS) oxide shell) (512), and encapsulating the first adhesion layer in a conductive shell (e.g., a polysilicon shell) (514). The first adhesion layer can be formed as a single layer of TEOS oxide. The conductive shell can be formed as a single layer of polysilicon.

[0047]

[0068] The method also includes encapsulating the conductive shell in a second adhesion layer (e.g., a second TEOS oxide shell) (516) and encapsulating the second adhesion layer in the barrier layer shell (518). The second adhesion layer can be formed as a monolayer of TEOS oxide. The barrier layer shell can be formed as a monolayer of silicon nitride.

[0048]

[0069] Once the support structure is formed by processes 510-518, the method further includes bonding (520) a bonding layer (e.g., a silicon oxide layer) to the support structure and bonding (522) a substantially single crystalline layer, e.g., a single crystalline silicon layer, to the silicon oxide layer. Other substantially single crystalline layers can be used according to embodiments of the invention, including SiC, sapphire, GaN, AlN, SiGe, Ge, diamond, Ga2O3, ZnO, etc. Bonding the bonding layer can include deposition of a bonding material followed by a planarization process as described herein. In embodiments described below, bonding the substantially single crystalline layer (e.g., a single crystalline silicon layer) to the bonding layer utilizes a layer transfer process, where the layer is a single crystalline silicon layer transferred from a silicon wafer.

[0049]

[0070] With reference to FIG. 1, the bonding layer 120 may be formed by depositing a thick (e.g., 4 μm thick) oxide layer followed by a chemical mechanical polishing (CMP) process that thins the oxide to a thickness of about 1.5 μm. The thick initial oxide helps fill voids and surface features present on the support structure that may be present after fabrication of the polycrystalline core and may continue to be present when the encapsulation layer shown in FIG. 1 is formed. The CMP process provides a substantially planar surface free of voids, particles, or other features that can be used during a wafer transfer process to bond a monocrystalline layer 122 (e.g., a monocrystalline silicon layer) to the bonding layer 120. It will be appreciated that the bonding layer need not be characterized by an atomically flat surface, but should provide a substantially planar surface that will support bonding of the monocrystalline layer (e.g., a monocrystalline silicon layer) with the desired reliability.

[0050]

[0071] A layer transfer process is used to bond the monocrystalline layer 122 (e.g., a monocrystalline silicon layer) to the bonding layer 120. In some embodiments, a silicon wafer including a substantially monocrystalline layer 122 (e.g., a monocrystalline silicon layer) is implanted to form a cleavage plane. In this embodiment, after wafer bonding, the silicon substrate can be removed along with the portion of the monocrystalline silicon layer below the cleavage plane, resulting in a delaminated monocrystalline silicon layer. The thickness of the monocrystalline layer 122 can be varied to meet various application specifications. Additionally, the crystal orientation of the monocrystalline layer 122 can be varied to meet application specifications. Additionally, the doping level and profile in the monocrystalline layer can be varied to meet the specific application specifications. In some embodiments, the depth of the implant can be adjusted to be greater than the desired final thickness of the monocrystalline layer 122. The additional thickness allows for removal of a thin portion of the transferred substantially monocrystalline layer that is damaged, leaving an undamaged portion of the desired final thickness. In some embodiments, the surface roughness can be modified for high quality epitaxial growth. One of ordinary skill in the art would recognize many variations, modifications, and alternatives.

[0051]

[0072] In some embodiments, the monocrystalline layer 122 can be thick enough to provide a high quality lattice template for the subsequent growth of one or more epitaxial layers, yet thin enough to be highly compliant. The monocrystalline layer 122 is said to be "compliant" when it is relatively thin so that its physical properties are less constrained and can mimic those properties of the material that surrounds it with less tendency to develop crystalline defects. The compliance of the monocrystalline layer 122 can be inversely proportional to the thickness of the monocrystalline layer 122. The higher the compliance, the lower the defect density of the epitaxial layer grown on the template, allowing for the growth of a thicker epitaxial layer. In some embodiments, the thickness of the monocrystalline layer 122 can be increased by epitaxially growing silicon on an exfoliated silicon layer.

[0052]

[0073] In some embodiments, tailoring the final thickness of the monocrystalline layer 122 can be achieved by thermal oxidation of the top of the exfoliated silicon layer, followed by stripping of the oxide layer with hydrofluoric (HF) acid. For example, an exfoliated silicon layer with an initial thickness of 0.5 μm can be thermally oxidized to form a silicon dioxide layer with a thickness of about 420 nm. After removing the grown thermal oxide, the remaining silicon thickness in the transfer layer can be about 53 nm. During thermal oxidation, the implanted hydrogen can migrate toward the surface. Thus, the subsequent stripping of the oxide layer can remove some damage. Also, thermal oxidation is usually performed at temperatures above 1000° C. Lattice damage can be repaired even at high temperatures.

[0053]

[0074] The silicon oxide layer formed on top of the single crystal layer during thermal oxidation can be stripped using HF acid etching. The etch selectivity between silicon oxide and silicon (SiO2:Si) by HF acid can be adjusted by adjusting the temperature and concentration of the HF solution as well as the stoichiometry and density of the silicon oxide. Etch selectivity refers to the etch rate of one material over another. The selectivity of the HF solution can range from about 10:1 to about 100:1 for (SiO2:Si). High etch selectivity can reduce the surface roughness by a similar factor from the initial surface roughness. However, the surface roughness of the resulting single crystal layer 122 can still be greater than desired. For example, a bulk Si(111) surface may have a root mean square (RMS) surface roughness of less than 0.1 nm as determined by a 2 μm × 2 μm atomic force microscope (AFM) scan before additional processing. In some embodiments, a desired surface roughness for epitaxial growth of gallium nitride material on Si(111) can be, for example, less than 1 nm, less than 0.5 nm, or less than 0.2 nm over a 30 μm×30 μm AFM scan area.

[0054]

[0075] If the surface roughness of the single crystal layer 122 after thermal oxidation and oxide layer stripping exceeds the desired surface roughness, additional surface smoothing can be performed. There are several methods for smoothing silicon surfaces. These methods can include hydrogen annealing, laser trimming, plasma smoothing, and touch polishing (e.g., CMP). These methods may include preferential attack of high aspect ratio surface peaks. Thus, high aspect ratio features on the surface can be removed more quickly than low aspect ratio features, thus resulting in a smoother surface.

[0055]

[0076] It should be understood that the specific steps illustrated in FIG. 5 provide a particular method of manufacturing an engineered substrate according to one embodiment of the present invention. Other sequences of steps may be performed according to alternative embodiments. For example, alternative embodiments of the present invention may perform the steps outlined above in a different order. Additionally, individual steps illustrated in FIG. 5 may include multiple sub-steps that may be performed in various orders as appropriate for the individual step. Additionally, additional steps may be added or removed depending on the particular application. Those skilled in the art will recognize numerous variations, modifications, and alternatives.

[0056]

[0077] 6 is a simplified flow chart illustrating a method of manufacturing an engineered substrate according to another embodiment of the present invention. The method includes forming a support structure by providing a polycrystalline ceramic core (610) and forming an adhesion layer bonded to at least a portion of the polycrystalline ceramic core (612). The first adhesion layer can include a tetraethylorthosilicate (TEOS) oxide layer. The first adhesion layer can be formed as a single layer of TEOS oxide. The method also includes forming a conductive layer bonded to the first adhesion layer (614). The conductive layer can be a polysilicon layer. The conductive layer can be formed as a single layer of polysilicon.

[0057]

[0078] The method also includes forming a second adhesion layer bonded to at least a portion of the first adhesion layer (616) and forming a barrier shell (618). The second adhesion layer can be formed as a monolayer of TEOS oxide. The barrier shell can be formed as a monolayer of silicon nitride or a series of sublayers that form the barrier shell.

[0058]

[0079] Once the support structure is formed by processes 610-618, the method further includes bonding (620) a bonding layer (e.g., a silicon oxide layer) to the support structure and bonding (622) a monocrystalline or substantially monocrystalline layer to the silicon oxide layer. Bonding the bonding layer can include deposition of a bonding material followed by a planarization process as described herein. In embodiments described below, bonding the monocrystalline layer (e.g., a monocrystalline silicon layer) to the bonding layer utilizes a layer transfer process in which the monocrystalline silicon layer is transferred from a silicon wafer.

[0059]

[0080] It should be understood that the specific steps illustrated in FIG. 6 provide a specific method of manufacturing an engineered substrate according to another embodiment of the present invention. Other sequences of steps may be performed according to alternative embodiments. For example, alternative embodiments of the present invention may perform the steps outlined above in a different order. Additionally, individual steps illustrated in FIG. 6 may include multiple sub-steps that may be performed in various orders as appropriate for the individual step. Additionally, additional steps may be added or removed depending on the particular application. Those skilled in the art will recognize numerous variations, modifications, and alternatives.

[0060]

[0081] 7 is a simplified schematic cross-sectional view of an epitaxial / engineered substrate structure 700 for RF and power applications according to one embodiment of the present invention. In some LED applications, the engineered substrate structure provides a growth substrate that enables the growth of high quality GaN layers, and the engineered substrate structure is subsequently removed. However, for RF and power device applications, the engineered substrate structure forms part of the completed device, and as a result, the electrical, thermal, and other properties of the engineered substrate structure, or elements of the engineered substrate structure, are important for the particular application.

[0061]

[0082] Referring to FIG. 1, the single crystal layer 122 can be an exfoliated single crystal silicon layer that has been split from a silicon donor wafer using implant and exfoliation techniques. Typical implants are hydrogen and boron. For power and RF device applications, the electrical properties of the layers and materials in the engineered substrate structure are important. For example, some device architectures utilize highly insulating silicon layers with resistivities greater than 103 ohm-cm to reduce or eliminate leakage through the substrate and interface layers. Other applications have utilized designs that include a conductive silicon layer of a given thickness (e.g., 1 μm) to connect the source of the device to other elements. Therefore, in these applications, it is desirable to control the dimensions and properties of the single crystal silicon layer. In designs where implant and exfoliation techniques are used during layer transfer, residual implant atoms, e.g., hydrogen or boron, are present in the silicon layer, thereby changing the electrical properties. Additionally, it can be difficult to control the thickness, conductivity, and other properties of the thin silicon layer, for example, using adjustments to the implant dose, which can affect the conductivity, and the implant depth, which can affect the thickness of the layer.

[0062]

[0083] According to an embodiment of the present invention, silicon epitaxy on an engineered substrate structure is utilized to achieve desired properties of a single crystal silicon layer suited to a particular device design.

[0063]

[0084] Referring to FIG. 7, an epitaxial / engineered substrate structure 700 includes an engineered substrate structure 710 and an epitaxial single crystal layer 720 formed thereon. In some embodiments, the epitaxial single crystal layer 720 can be a single crystal silicon layer. The engineered substrate structure 710 can be similar to the engineered substrate structures shown in FIGS. 1, 3, and 4. Typically, the single crystal layer 122 (e.g., a single crystal silicon layer) is on the order of 0.5 μm after layer transfer. In some processes, a surface conditioning process can be utilized to reduce the thickness of the single crystal layer 122 to about 0.3 μm. To increase the thickness of the single crystal layer 122 to about 1 μm for use in forming reliable ohmic contacts, an epitaxial process is used, for example, to grow the epitaxial single crystal layer 720 on the single crystal layer 122 formed by the layer transfer process. A variety of epitaxial growth processes can be used to grow the epitaxial single crystal layer 720, including CVD, LPCVD, ALD, MBE, etc. The epitaxial single crystal layer 720 can include, for example, Si, SiC, sapphire, GaN, AlN, SiGe, Ge, diamond, Ga2O3, and / or ZnO. The thickness of the epitaxial single crystal layer 720 can range from about 0.1 μm to about 20 μm, for example, from 0.1 μm to 10 μm.

[0064]

[0085] FIG. 8A is a simplified schematic cross-sectional view showing III-V epitaxial layers on an engineered substrate structure according to an embodiment of the present invention. The structure shown in FIG. 8A can be referred to as a dual epitaxial structure 800, as described below. As shown in FIG. 8A, an engineered substrate structure 810 including an epitaxial single crystal layer 720 has a III-V epitaxial layer 820 formed thereon. In one embodiment, the III-V epitaxial layer includes gallium nitride (GaN). To provide electrical conductivity between portions of the III-V epitaxial layer, which may include multiple auxiliary layers, in this example, a set of vias 824 are formed in the epitaxial single crystal layer 720 from a top surface of the III-V epitaxial layer 820. FIG. 8A shows the vias 824 extending through the epitaxial layer 820 to the epitaxial single crystal layer 720. As an example, these vias can be used to connect an electrode of a diode or transistor to the layer below it by providing an ohmic contact through the via 824, thereby mitigating charge build-up in the device. In some embodiments, one or more of the vias 824 may be insulated on its sidewalls such that it is not electrically connected to the III-V epitaxial layer 820. The electrical contact can facilitate removal of parasitic charge, thereby enabling faster switching of the power device.

[0065]

[0086] In some embodiments, the via 826 can extend to the single crystal layer 122. To address the difficulty of fabricating the via 826 to contact the single crystal layer 122, an additional conductive epitaxial layer 822 can be grown on the single crystal layer 122 and the single crystal layer 720 to increase the size of the target conductive layer of the via 826, i.e., the thickness of the layer where the via terminates. Due to the inherent CTE and diffusion characteristics of the engineered substrate structure 810, the epitaxial single crystal layer 720 and the III-V epitaxial layer 820 can be formed thicker than on conventional substrates. Thus, existing substrate technologies cannot support the growth of epitaxial layers that are defect-free enough to include the conductive epitaxial layer 822 in the device. In some embodiments, the conductive epitaxial layer 822 can be AlN, AlGaN, GaN, or a sufficiently doped semiconductor material. In certain embodiments, the conductive epitaxial layer 822 can have a thickness of 0.1 to 10 μm. In other embodiments, the thickness of the conductive epitaxial layer 822 may vary depending on the requirements of the semiconductor device. In some embodiments, the engineered substrate structure and the single crystal layer 122 may be removed to expose the epitaxial single crystal layer 720 and / or the conductive epitaxial layer 822. After removing the substrate, contacts may be formed on the exposed epitaxial layer. One of ordinary skill in the art would recognize many variations, modifications, and alternatives.

[0066]

[0087] In some embodiments, a III-V epitaxial layer can be grown on the single crystal layer 122. Ohmic contacts using vias can be made into the single crystal layer 0.3 μm across the wafer to terminate the vias in the single crystal layer 122. Utilizing embodiments of the present invention, it is possible to provide single crystal layers several microns thick. Thicknesses of several microns are difficult to achieve using implant and lift processes, as large implant depths require high implant energies. The thick epitaxial single crystal layer then enables applications such as the illustrated vias that enable a variety of device designs.

[0067]

[0088] In addition to increasing the thickness of the "layer" by epitaxially growing epitaxial single crystal layer 720 on single crystal layer 122, other adjustments can be made to the original properties of single crystal layer 122, including modifying electrical conductivity, crystallinity, etc. For example, if a silicon layer on the order of 10 μm is desired prior to additional epitaxial growth of III-V layers or other materials, such a thick layer can be grown according to embodiments of the present invention.

[0068]

[0089] The implantation process may affect the properties of the monocrystalline layer 122, for example, residual boron / hydrogen atoms may cause defects that affect the electrical properties of the silicon crystal layer. In some embodiments of the invention, a portion of the monocrystalline layer 122 may be removed prior to epitaxial growth of the epitaxial monocrystalline layer 720. For example, the monocrystalline silicon layer may be thinned to form a layer having a thickness of 0.1 μm or less to remove most or all of the residual boron / hydrogen atoms. Subsequent growth of the monocrystalline silicon layer is used to provide a monocrystalline material having electrical and / or other properties that are substantially independent of the corresponding properties of a layer formed using a layer transfer process.

[0069]

[0090] In addition to increasing the thickness of the single crystal silicon material bonded to the engineered substrate structure, the electrical properties, including electrical conductivity, of the epitaxial single crystal layer 720 may be different from that of the single crystal layer 122. Doping of the epitaxial single crystal layer 720 during growth can be done by doping with boron to produce P-type silicon and by doping with phosphorus to produce N-type silicon. Undoped silicon can be grown to provide high resistivity silicon for use in devices with insulating regions. Insulating layers can be particularly useful in RF devices.

[0070]

[0091] The lattice constant of the epitaxial single crystal layer 720 can be tailored to be different from that of the single crystal layer 122 during growth to produce a strained epitaxial material. In addition to silicon, other elements can be epitaxially grown to provide layers including silicon germanium, including strained layers. Additionally, the crystal orientation of the crystal planes, for example, growth of (111) silicon on (100) silicon, can be utilized to introduce strain. For example, buffer layers can be grown on the single crystal layer 122, on the epitaxial single crystal layer 720, or between layers to enhance subsequent epitaxial growth. These buffer layers can include III-V semiconductor material layers such as aluminum gallium nitride, indium gallium nitride, and indium aluminum gallium nitride, silicon germanium strained layers. The strain of the III-V semiconductor material layers can be tailored to the desired material properties. Additionally, the buffer layers and other epitaxial layers can be graded with mole fractions, dopants, polarities, and the like. Those skilled in the art will recognize many variations, modifications, and alternatives.

[0071]

[0092] In some embodiments, strain present in the single crystal layer 122 or the epitaxial single crystal layer 720 can be relaxed during growth of subsequent epitaxial layers, including III-V epitaxial layers.

[0072]

[0093] FIG. 8B is a simplified schematic plan view illustrating four dual epitaxial structures according to an embodiment of the present invention. Each of the dual epitaxial structures illustrated in FIG. 8B includes a set of vias 824. The first dual epitaxial structure 830 illustrates a tight via configuration. The second dual epitaxial structure 840 illustrates a distributed via configuration. The distributed via configuration uses vias 824 in active areas of the device that are more susceptible to charge accumulation. The third dual epitaxial structure 850 illustrates a patterned via configuration. The patterned via configuration may space the vias 824 at equal distances across the dual epitaxial structure 850. The fourth dual epitaxial structure 860 illustrates a lateral via 828. The lateral via 828 may be fabricated to run substantially parallel to the epitaxial layers of the dual epitaxial structure 860 and contact the single crystal layer 122 at, for example, an edge 862. One skilled in the art would recognize many variations, modifications, and alternatives.

[0073]

[0094] The engineered substrate as described above can provide epitaxial growth of gallium nitride device layers characterized by a coefficient of thermal expansion (CTE) that is substantially lattice matched to the engineered substrate and substantially matched to the CTE of the engineered substrate. Thus, the engineered substrate can provide excellent thermal stability and shape control. The engineered substrate can also enable scaling of wafer diameter with reusability. Relatively thick (e.g., greater than 20 μm), high-quality epitaxial gallium nitride layers can be formed on the engineered substrate that are crack-free, characterized by low defect density and low post-epitaxial bow and stress. Multiple applications, such as power devices, radio frequency (RF) devices, monolithic microwave integrated circuits (MMICs), displays, light-emitting diodes (LEDs), etc., can be realized on a single platform. Such engineered substrates can also be suitable for various device architectures, such as lateral devices, vertical devices, and chip-scale package (CSP) devices.

[0074]

[0095] Gallium nitride (GaN) and similar wide bandgap semiconductor materials offer superior physical properties over silicon, enabling power semiconductor devices based on these materials to withstand high voltages and temperatures. These properties also enable higher frequency response, greater current density, and faster switching. However, before wide bandgap devices can be commercially accepted, their reliability must be demonstrated, and there is an increasing demand for higher reliability. Continuous operation for higher power densities at the device and package level produces results in terms of higher temperatures and temperature gradients across the package. As explained below, the use of engineered substrates to form CTE-matched epitaxial device layers can mitigate many heat-related failure mechanisms common to wide bandgap devices.

[0075]

[0096] Compound semiconductor devices such as gallium nitride (GaN)-based high electron mobility transistors (HEMTs) can be exposed to high electric fields and high currents (e.g., large signal RF) while being driven deep into saturation. Contact degradation, inverse piezoelectric effect, hot electron effect, and self-heating are some of the common issues. For example, Schottky and ohmic contacts can show increased contact resistance and cracking of the passivation for temperatures above about 300°C. Interdiffusion within the gate metal stack and outdiffusion of gallium into the metal layers can occur. Hot electron effects can occur when electrons accelerated by large electric fields gain very high kinetic energy. Hot electron effects can cause traps to form within the aluminum gallium nitride (AlGaN) layer, at the AlGaN / GaN interface, the passivation layer / GaN cap layer interface, and in the buffer layer.

[0076]

[0097] When traps are formed, current collapse and gate lag can occur, which can cause a reversible degradation of the transconductance and the saturated drain current. A slow current transient is observed even if the drain or gate voltage is changed abruptly. The slow transient response of the drain current when the drain-source voltage is pulsed is called drain lag, or gate lag in the case of the gate-source voltage. When the voltage in the pulse is higher than the quiescent bias point, the buffer traps capture the free charges. This phenomenon is very fast compared to the pulse length. When the voltage in the pulse is lower than the quiescent bias point, the traps release their charge. This process can be very slow, possibly several seconds. Because the free carriers are captured and released, they do not instantly contribute to the output current. This phenomenon is the cause of the current transient.

[0077]

[0098] The combined effects of drain lag and gate lag result in current collapse (a reduction in two-dimensional electron gas [2-DEG] density). Gate lag due to buffer traps is more pronounced with higher deep acceptor densities in the buffer layer. An inverse piezoelectric effect can result when high reverse bias on the gate leads to the generation of crystallographic defects. Beyond a certain critical voltage, irreversible damage to the device can occur, which can result in leakage paths through the defects. Self-heating can occur under high power stress, which can lead to thermal stress-strain. Compound semiconductor devices can also suffer from electric field-induced degradation, such as degradation of the gate metallization, as well as contacts, surfaces, and interfaces. Gate degradation can result in increased leakage current and / or dielectric breakdown.

[0078]

[0099] High temperature reverse bias (HTRB) testing is one of the most common reliability tests for power devices. HTRB testing evaluates long-term stability under high drain-source bias. HTRB testing aims to accelerate thermally activated failure mechanisms using biased operating conditions. During HTRB testing, device samples are stressed at or slightly below their maximum rated reverse breakdown voltage at an ambient temperature close to their maximum rated junction temperature for an extended period of time (e.g., 1000 hours). The high temperatures of this test accelerate failure mechanisms according to the Arrhenius equation, which describes the temperature dependence of reaction rates. Delamination, popping, device rupture, and other mechanical problems can occur during HTRB testing.

[0079]

[0100] A failure mechanism similar to time-dependent dielectric breakdown (TDDB), a common failure mechanism in MOSFETs, is also observed in the gate dielectric of wide bandgap semiconductor devices such as GaN power devices. TDDB occurs when the gate dielectric breaks down due to the application of relatively low electric fields for long periods of time (as opposed to the immediate breakdown caused by strong electric fields). In addition, failure during temperature cycling (TMCL) can be related to package stress, bond pad metallization, mold compound, moisture sensitivity, and other package-level issues.

[0080]

[0101] As mentioned above, the engineered substrate can have a CTE that matches the CTE of the epitaxial GaN device layers grown thereon. The epitaxial GaN device layers can also be lattice matched to the engineered substrate. Thus, the epitaxial GaN device layers can have a lower defect density and higher quality. A relatively thick drift region can be formed by epitaxial growth. Also, large diameter wafers can be produced from the engineered substrate, thereby lowering manufacturing costs. Engineered substrates can improve device reliability. For example, having a CTE that matches the CTE of the epitaxial GaN device can help reduce thermal stress, which is a key factor in device reliability. Device failures related to thermal stress include thermally activated drain-source breakdown, punch-through effects, breakdown along the channel, and breakdown through the buffer layer. Self-heating can also be reduced. Additionally, although some defects can be activated with voltage stress and contribute to lateral and vertical leakage, high quality epitaxial GaN layers with low defect density help improve device reliability. High quality epitaxial GaN layers can also address issues such as localized non-stoichiometric regions that can affect the electric field distribution and dislocation density.

[0081]

[0102] Conventional silicon-based MOSFET technology has nearly reached its physical limits in performance and switching speed. Lateral GaN-based high electron mobility transistors (HEMTs) offer opportunities beyond the realm of silicon-based MOSFETs in medium-to-low power systems such as solar inverters, small form factor power supplies (PFCs), switch mode power supplies (SMPSs), motor drives, RF power amplifiers, solid-state lighting (SSLs), smart grids, and automotive motor drive systems. Lateral GaN-based HEMTs can offer high efficiency, high frequency operation, and low switching and conduction losses, among many other advantages.

[0082]

[0103] FIG. 9 is a simplified schematic cross-sectional view illustrating a power device 900 formed on an engineered substrate 910 according to an embodiment of the present invention. The power device 900 can function as a depletion mode (normally on) HEMT. The power device 900 includes an engineered substrate 910. In some embodiments, the engineered substrate 910 can include a polycrystalline ceramic core, a first adhesion layer bonded to the polycrystalline ceramic core, a barrier layer bonded to the first adhesion layer, a bonding layer bonded to the barrier layer, and a substantially single crystalline layer bonded to the bonding layer, as described above with reference to FIGS. 1, 3, and 4. According to an embodiment, the engineered substrate 910 can further include a substantially single crystalline layer 912 bonded to the bonding layer. For example, the substantially single crystalline layer 912 can include a substantially single layer of crystalline silicon. In some embodiments, the engineered substrate 910 can further include a nucleation layer 914 bonded to the substantially single crystalline layer 912 to facilitate the formation of an epitaxial device layer including a substantially single crystalline GaN-based material. In some embodiments, the nucleation layer 914 may be doped at a level equal to, less than, or more than the surrounding layers. In other embodiments, the composition of the nucleation layer can be designed and implemented with a predetermined composition.

[0083]

[0104] In another embodiment, the polycrystalline ceramic core of the substrate 910 comprises aluminum nitride. In some embodiments, the substrate 910 further comprises a conductive layer bonded to the first adhesive layer and a second adhesive layer bonded to the conductive layer, the conductive layer and the second adhesive layer being disposed between the first adhesive layer and the barrier layer, as described above with reference to FIG. 1. In some embodiments, the first adhesive layer comprises a first tetraethylorthosilicate (TEOS) oxide layer and the second adhesive layer comprises a second TEOS oxide layer. The barrier layer can comprise a silicon nitride layer. The conductive layer can comprise a polysilicon layer.

[0084]

[0105] According to one embodiment, the power device 900 further includes a buffer layer 920 (e.g., a gallium nitride (GaN) buffer layer) coupled to the nucleation layer 914 and the substantially single crystalline layer 912. The buffer layer 920 may be formed by epitaxial growth on either the nucleation layer 914 or the substantially single crystalline layer 912. According to one embodiment, the buffer layer 920 may have a thickness greater than about 20 microns. In some embodiments, the buffer layer 920 may be an aluminum gallium nitride (i.e., Al x Ga 1-x In some embodiments, the layers described as GaN layers may be replaced with AlGaN layers, or may be a combination of GaN layers and AlGaN layers. x Ga 1-x Note that the buffer layer 920 may be replaced by an N layer. As an example, the buffer layer 920 may be made of a first set of mole fractions of Al x Ga 1-x N, and the barrier layer 932 has a second set of mole fractions of Al x Ga 1-x N. One of ordinary skill in the art would recognize many variations, modifications, and alternatives.

[0085]

[0106] A thicker buffer layer can provide the power device 900 with a lower leakage current and a higher breakdown voltage. In some embodiments, the buffer layer 920 can include multiple layers. For example, the buffer layer 920 can include an aluminum nitride layer, an aluminum gallium nitride layer, and a gallium nitride layer. In some embodiments, the buffer layer 920 can include as many as 150 layers of a superlattice, with each layer having a thickness of about 2-3 nm. A superlattice is an artificial lattice fabricated by periodic epitaxial growth. A periodic superlattice is realized by growing alternating layers of two semiconductors on top of each other, with each semiconductor grown to the same thickness and mole fraction each time. According to some embodiments of the present invention, an advantage of using a superlattice instead of other buffer layer designs is that the sheet resistance can be reduced by the superlattice being grown. For example, an AlGaN / GaN superlattice layer over the channel region can reduce the potential barrier height at the heterointerface. In other embodiments, the superlattice does not reduce the potential barrier height at the heterointerface. One skilled in the art would recognize many variations, modifications, and alternatives.

[0086]

[0107] According to one embodiment, the power device 900 further includes a channel region 930 coupled to the buffer layer 920. The channel region 930 has a first end 924, a second end 926, and a central portion 928 disposed between the first end and the second end. The central portion of the channel region 930 may include a channel region barrier layer. In some embodiments, the channel region barrier layer may include a barrier layer 932 (e.g., aluminum gallium nitride (Al x Ga 1-xThe barrier layer 932 may be a GaN (gallium nitride) cap layer, and a cap layer 934 (e.g., a gallium nitride cap layer) coupled to the barrier layer 932. The cap layer reduces reverse leakage through the Schottky contact and helps reduce the peak electric field. It also protects the barrier layer 932 during processing and prevents nitrogen outgassing. In addition, the cap layer 934 also has a favorable impact on device performance, such as increased gain, increased power added efficiency, and improved DC stability.

[0087]

[0108] The power device 900 further includes a source contact 940 disposed at a first end of the channel region 930, a drain contact 950 disposed at a second end of the channel region 930, and a gate contact 960 coupled to the cap layer 934 and disposed at a central portion of the channel region 930. In some embodiments, a via 902 can connect the source contact 940 to the single crystal layer 912 to eliminate parasitic charges in the power device. In contrast to GaN-on-silicon, which can utilize a backside contact through a conductive silicon substrate, embodiments of the invention utilizing insulating engineered substrates can utilize vias such as via 902 to provide electrical connection to the single crystal layer 912. According to embodiments of the invention, the barrier layer 932 and the cap layer 934 are formed by epitaxial growth. As shown in FIG. 9, during operation, a thin layer of two-dimensional electron gas (2DEG) 936 can form in the buffer layer 920 at the interface between the buffer layer 920 and the barrier layer 932. Electrons in this thin layer of two-dimensional electron gas 936 can move quickly without colliding with impurities because the buffer layer 920 is undoped. This allows the channel 938 to have a very low resistivity, which in turn allows for very high electron mobility.

[0088]

[0109] In some embodiments, the power device 900 may further include a passivation layer 970 covering the cap layer 934. The passivation layer 970 may include silicon nitride or other insulating material. The power device 900 may also include a first field plate metal 980 electrically connecting to the source contact 940 forming the source electrode, and a second metal 990 disposed on the drain contact 950 forming the drain electrode.

[0089]

[0110] 10 is a simplified flow chart illustrating a method 1000 of fabricating a lateral power device on an engineered substrate according to one embodiment of the present invention. According to one embodiment, the method 1000 includes forming a substrate 1010 by providing a polycrystalline ceramic core, encapsulating the polycrystalline ceramic core with a first adhesive shell, encapsulating the first adhesive shell with a barrier layer, forming a bonding layer on the barrier layer, and bonding a substantially single crystalline layer to the bonding layer.

[0090]

[0111] The method 1000 includes step 1012 of forming an epitaxial buffer layer (e.g., a gallium nitride (GaN) buffer layer) on the substrate, and forming an epitaxial barrier layer (e.g., an aluminum gallium nitride (Al x Ga 1-x and forming a channel region on the buffer layer by forming an epitaxial cap layer (e.g., a gallium nitride cap layer) on the barrier layer. The channel region has a first end, a second end, and a central portion between the first end and the second end.

[0091]

[0112] The method 1000 further includes step 1016 of forming a source contact at a first end of the channel region, step 1018 of forming a drain contact at a second end of the channel region, and step 1020 of forming a gate contact on the cap layer in a central portion of the channel region.

[0092]

[0113] It should be understood that the specific steps illustrated in FIG. 10 provide a specific method of manufacturing an engineered substrate according to another embodiment of the present invention. Other sequences of steps may be performed according to alternative embodiments. For example, alternative embodiments of the present invention may perform the steps outlined above in a different order. Additionally, individual steps illustrated in FIG. 10 may include multiple sub-steps that may be performed in various orders as appropriate for the individual step. Additionally, additional steps may be added or removed depending on the particular application. Those skilled in the art will recognize numerous variations, modifications, and alternatives.

[0093]

[0114] FIG. 11A is a simplified schematic cross-sectional view showing a lateral power device 1100 formed on an engineered substrate according to another embodiment of the present invention. The power device 1100 can use a recess 1136 in a channel region 1130 to function as an enhancement mode (normally off) HEMT. The power device 1100 includes an engineered substrate 1110. In some embodiments, the engineered substrate 1110 can include a polycrystalline ceramic core, a first adhesion layer bonded to the polycrystalline ceramic core, a barrier layer bonded to the first adhesion layer, a bonding layer bonded to the barrier layer, and a substantially single crystalline layer bonded to the bonding layer, as described above with reference to FIGS. 1, 3, and 4. In some embodiments, the engineered substrate 1110 can further include a substantially single crystalline layer 1112 bonded to the bonding layer. For example, the substantially single crystalline layer 1112 can include substantially single crystalline silicon. In some embodiments, engineered substrate 1110 may further include a nucleation layer (not shown) coupled to substantially single crystalline layer 1112 to facilitate formation of epitaxial device layers.

[0094]

[0115] In one embodiment, the polycrystalline ceramic core of the substrate 1110 comprises aluminum nitride. In some embodiments, as described above with reference to FIG. 1, the substrate 1110 further comprises a conductive layer bonded to the first adhesive layer and a second adhesive layer bonded to the conductive layer, the conductive layer and the second adhesive layer being disposed between the first adhesive layer and the barrier layer. In some embodiments, the first adhesive layer comprises a first tetraethylorthosilicate (TEOS) oxide layer and the second adhesive layer comprises a second TEOS oxide layer. The barrier layer can comprise a silicon nitride layer. The conductive layer can comprise a polysilicon layer.

[0095]

[0116] According to an embodiment, the power device 1100 further includes a buffer layer 1120 (e.g., a gallium nitride (GaN) buffer layer) coupled to the substantially single crystalline layer 1112. The buffer layer 1120 may be formed by epitaxial growth on the substantially single crystalline layer 1112. According to an embodiment, the buffer layer 1120 may have a thickness greater than about 20 microns. A thicker buffer layer may provide the power device 1100 with a lower leakage current and a higher breakdown voltage. In some embodiments, the buffer layer 1120 may include multiple layers. For example, the buffer layer 1120 may be a superlattice including an aluminum nitride layer, an aluminum gallium nitride layer, and a gallium nitride layer. It will be appreciated that one or more nucleation layers may be utilized in the process for growing the buffer layer 1120.

[0096]

[0117] According to one embodiment, the power device 1100 further includes a channel region 1130 coupled to the buffer layer 1120. The channel region 1130 has a first end 1124, a second end 1126, and a central portion 1128 disposed between the first end 1124 and the second end 1126. The central portion of the channel region 1130 may include an epitaxial channel region barrier layer. In some embodiments, the epitaxial channel region barrier layer includes a barrier layer 1132 (e.g., aluminum gallium nitride (Al GaN)) coupled to the buffer layer 1120.x Ga 1-x According to an embodiment of the invention, the barrier layer 1132 is formed by epitaxial growth. The barrier layer 1132 includes a recess 1136 in a central portion of the channel region 1130. The recess may be formed by removing a portion of the barrier layer 1132 using etching or other suitable techniques. The power device 1100 further includes an insulating layer 1134 disposed within the recess and coupled to the barrier layer 1132.

[0097]

[0118] The power device 1100 further includes a source contact 1140 disposed at a first end of the channel region 1130, a drain contact 1150 disposed at a second end of the channel region 1130, and a gate contact 1160 coupled to the insulating layer 1134 and disposed at a central portion of the channel region 1130. In some embodiments, the source contact 1140 can be connected to the single crystal layer 1112 using a via 1102 to remove parasitic charges in the power device 1100. As shown in FIG. 11, a thin layer of two-dimensional electron gas (2DEG) 1138 can be formed in the buffer layer 1120 at the interface between the buffer layer 1120 and the barrier layer 1132. Electrons in this thin layer of 2DEG 1138 can move quickly without colliding with any impurities because the buffer layer 1120 is not doped. This allows the channel region 1130 to have a very low resistivity, which in turn has a very high electron mobility. In depletion mode (normally off), when the gate voltage is zero, recess 1136 and insulating layer 1134 block a portion of the 2DEG.

[0098]

[0119] In some embodiments, the buffer layer 1120 may be implemented as an aluminum gallium nitride (AlGaN) buffer layer. The AlGaN buffer layer may include multiple layers. x Ga 1-xA power device using an N buffer layer has a first predetermined mole fraction (x) of AlN that extends from the engineered substrate and a second predetermined mole fraction (x) near the source, gate, and drain contacts. x Ga 1-x The channel region 1130 can be introduced by fabricating a N buffer layer. The first predetermined mole fraction (x) can be low, for example less than 10%, to provide the desired carrier confinement. In other embodiments, the aluminum mole fraction (x) ranges from 10% to 30%. x Ga 1-x The N epitaxial layer may be doped with iron or carbon to further increase the resistivity of the epitaxial layer, which functions as an insulating or blocking layer. Further description of materials used in and fabrication of epitaxial buffer layers is provided in U.S. Provisional Patent Application No. 62 / 447,857, the disclosure of which is incorporated herein by reference in its entirety for all purposes.

[0099]

[0120] 11B is a simplified schematic cross-sectional view of a lateral power device 1190 having an epitaxial gate structure formed on an engineered substrate according to an embodiment of the present invention. The power device 1190 can function as an enhancement mode (normally off) HEMT by depleting charge in the channel region under zero bias using an epitaxial gate structure such as a P-type gallium nitride based structure 1162. The power device 1190 includes an engineered substrate 1110. In some embodiments, the engineered substrate 1110 may include elements as described above with reference to FIGS. 1, 3, and 4. According to one embodiment, the engineered substrate 1110 may further include a substantially single crystalline layer 1112 bonded to a bonding layer.

[0100]

[0121] In some embodiments, the power device 1190 further includes a buffer layer 1120 coupled to the substantially single crystalline layer 1112. In some embodiments, the buffer layer may be other single crystalline epitaxial layers, for example, other III-V materials such as AlGaN, InGaN, InAlGaN, and combinations thereof. The power device 1190 may include a channel region 1130 coupled to the buffer layer 1120. A central portion of the channel region may include a barrier layer 1132 coupled to the buffer layer 1120. According to embodiments of the invention, the barrier layer 1132 is formed by epitaxial growth.

[0101]

[0122] The power device 1190 further includes a source contact 1140 disposed at a first end of the channel region 1130, a drain contact 1150 disposed at a second end of the channel region, and a gate contact 1164. In some embodiments, the gate contact 1164 may be a partial ohmic contact, or a semi-ohmic contact, such as titanium nitride. The partial ohmic gate contact 1164 may be coupled to the P-type GaN structure 1162. The partial ohmic gate contact 1164 functions to block leakage current that would flow if there was a full ohmic contact. The P-type gallium nitride structure 1162 may be formed by selectively etching a P-type gallium nitride epitaxial layer. In some embodiments, the P-type gallium nitride structure 1162 may be formed using multiple epitaxial layers. When multiple epitaxial layers are used, one or more layers may include a material having a composition different from that of the barrier layer 1132 or different from each other, such as AlGaN.

[0102]

[0123] Properties associated with the P-type gallium nitride structure 1162, such as strain and piezoelectric properties, can be tailored to reduce or limit leakage current. Each layer of the P-type gallium nitride structure can have a different dopant concentration. In some embodiments, the P-type gallium nitride structure 1162 depletes a portion of the channel region 1130 when the gate voltage is zero. The depletion region allows the power device 1190 to function as an enhancement mode (normally off) HEMT.

[0103]

[0124] FIG. 11C is a simplified schematic cross-sectional view showing an exploded view of a P-type gallium nitride structure 1162. In some embodiments, the first layer 1170 can have a first dopant concentration and / or material composition. The second layer 1172 can have a second dopant concentration and / or material composition. The third layer 1174 can have a third dopant concentration and / or material composition. The unique CTE matching properties of the engineered substrate 1110 provide a substrate that can support the growth of thicker and more complex epitaxial layers than existing substrate technologies. In some embodiments, the epitaxial gate structure can include at least one P-type gallium nitride epitaxial layer. The leakage current of the power device 1190 can be controlled by layer-specific dopant concentrations and / or material compositions. Although FIG. 11C shows three epitaxial layers, one skilled in the art would recognize many variations, modifications, and alternatives.

[0104]

[0125] 12 is a simplified flow chart illustrating a method 1200 of fabricating a lateral power device on an engineered substrate according to one embodiment of the present invention. According to one embodiment, the method 1200 includes forming a substrate 1210 by providing a polycrystalline ceramic core, encapsulating the polycrystalline ceramic core with a first adhesive shell, encapsulating the first adhesive shell with a barrier layer, forming a bonding layer on the barrier layer, and bonding a substantially single crystalline layer to the bonding layer.

[0105]

[0126] The method 1200 includes step 1212 of forming an epitaxial buffer layer (e.g., a gallium nitride (GaN) buffer layer) on the substrate, and forming an epitaxial barrier layer (e.g., an aluminum gallium nitride (Al x Ga 1-x and forming 1214 a channel region on the buffer layer by forming a first end, a second end, and a central portion between the first end and the second end. According to one embodiment, the method 1200 further includes forming 1216 a recess in the barrier layer in the central portion of the channel region and forming 1218 an insulating layer in the recess. The insulating layer is coupled to the barrier layer. The method 1200 further includes forming 1220 a source contact at the first end of the channel region, forming 1222 a drain contact at the second end of the channel region, and forming 1224 a gate contact on the insulating layer in the central portion of the channel region.

[0106]

[0127] It should be understood that the specific steps illustrated in FIG. 12 provide a specific method of manufacturing an engineered substrate according to another embodiment of the present invention. Other sequences of steps may be performed according to alternative embodiments. For example, alternative embodiments of the present invention may perform the steps outlined above in a different order. Additionally, individual steps illustrated in FIG. 12 may include multiple sub-steps that may be performed in various orders as appropriate for the individual step. Additionally, additional steps may be added or removed depending on the particular application. Those skilled in the art will recognize numerous variations, modifications, and alternatives.

[0107]

[0128] High power modules of vertical devices (pn diodes and HEMTs) can have many applications. For example, they can be used to drive main motors and industrial motors in hybrid vehicle power systems. Such devices present special challenges, since they require high voltages and high currents at the same time. Currently, these systems typically use SiC-based devices. There is growing interest in using GaN-based devices for their switching performance, which would result in a smaller footprint. Engineered substrates as mentioned above could offer the possibility to manufacture GaN-based devices on a mass scale, within CMOS-compatible Si fabs.

[0108]

[0129] FIG. 13 is a simplified schematic cross-sectional view illustrating a vertical semiconductor diode 1300 formed on an engineered substrate according to an embodiment of the present invention. The semiconductor diode 1300 includes an engineered substrate 1310. In some embodiments, the engineered substrate 1310 can include a polycrystalline ceramic core, a first adhesion layer bonded to the polycrystalline ceramic core, a barrier layer bonded to the first adhesion layer, a bonding layer bonded to the barrier layer, and a substantially single crystalline layer bonded to the bonding layer, as described above with reference to FIGS. 1, 3, and 4. According to an embodiment, the engineered substrate 1310 can further include a substantially single crystalline layer 1312 bonded to the bonding layer. For example, the substantially single crystalline layer 1312 can include substantially single crystalline silicon. In some embodiments, the engineered substrate 1310 can further include a nucleation layer (not shown) bonded to the substantially single crystalline layer 1312 to facilitate formation of epitaxial device layers.

[0109]

[0130] In one embodiment, the polycrystalline ceramic core of the substrate 1310 comprises aluminum nitride. In some embodiments, the substrate 1310 further comprises a conductive layer bonded to the first adhesive layer and a second adhesive layer bonded to the conductive layer, the conductive layer and the second adhesive layer being disposed between the first adhesive layer and the barrier layer, as described above with reference to FIG. 1. In some embodiments, the first adhesive layer comprises a first tetraethylorthosilicate (TEOS) oxide layer and the second adhesive layer comprises a second TEOS oxide layer. The barrier layer can comprise a silicon nitride layer. The conductive layer can comprise a polysilicon layer.

[0110]

[0131] According to one embodiment, the semiconductor diode 1300 further includes a buffer layer 1320 coupled to the substantially single crystalline layer 1312. In some embodiments, the buffer layer 1320 may be a superlattice including multiple layers. For example, the buffer layer 1320 may include an aluminum nitride layer coupled to the single crystalline silicon layer, an aluminum gallium nitride layer coupled to the aluminum nitride layer, and a gallium nitride layer coupled to the aluminum gallium nitride layer. The semiconductor diode 1300 further includes a semi-insulating layer 1330 coupled to the buffer layer 1320. In one embodiment, the semi-insulating layer 1330 includes gallium nitride.

[0111]

[0132] According to some embodiments, the semiconductor diode 1300 further includes a first N-type gallium nitride layer 1342 coupled to the semi-insulating layer 1330, a second N-type gallium nitride layer 1344 coupled to the first N-type gallium nitride layer 1342, and a P-type gallium nitride layer 1346 coupled to the second N-type gallium nitride layer 1344. The first N-type gallium nitride layer 1342 can function as an N region of the PN diode and can have a relatively high N-type doping concentration. The second N-type gallium nitride layer 1344 can function as a drift region and can have a relatively low doping concentration compared to the doping concentration of the first N-type gallium nitride layer 1342. The P-type gallium nitride layer 1346 can function as a P region of the PN diode and can have a relatively high P-type doping concentration.

[0112]

[0133] In an embodiment, a portion of the second N-type gallium nitride layer 1344 and a portion of the P-type gallium nitride layer 1346 may be removed to expose a portion of the first N-type gallium nitride layer 1342 on which a cathode contact 1370 may be formed. In some embodiments, the cathode contact 1370 may comprise a titanium-aluminum (Ti / Al) alloy or other suitable metallic material. A portion of the second N-type gallium nitride layer 1344 and a portion of the P-type gallium nitride layer 1346 may be removed by etching or other suitable techniques. An anode contact 1360 is formed on the remaining portion of the P-type gallium nitride layer 1346. In some embodiments, the anode 1360 may comprise a nickel-platinum (Ni / Pt) alloy, a nickel-gold (Ni / Au) alloy, or the like. The semiconductor diode 1300 may further include a first field plate 1382 coupled to the anode contact 1360 and a second field plate 1384 coupled to the cathode contact 1370. In some embodiments, the semiconductor diode 1300 may further include a passivation layer 1390 covering exposed surfaces of the P-type gallium nitride layer 1346 and the first N-type gallium nitride layer 1342, as well as the second N-type gallium nitride layer 1344. The passivation layer 1390 may include silicon nitride or other insulating material.

[0113]

[0134] In some embodiments, the second N-type gallium nitride layer 1344 can have a thickness of greater than about 20 μm. The inherent CTE matching properties of the engineered substrate 1310 provide the ability to deposit a relatively thick drift region with low dislocation density, which can provide the semiconductor diode 1300 with low leakage current and much higher breakdown voltage, as well as many other advantages.

[0114]

[0135] 14 is a simplified flow chart illustrating a method 1400 of fabricating a vertical semiconductor diode on an engineered substrate according to one embodiment of the present invention. The method 1400 includes forming a substrate 1410 by providing a polycrystalline ceramic core, encapsulating the polycrystalline ceramic core with a first adhesive shell, encapsulating the first adhesive shell with a barrier layer, forming a bonding layer on the barrier layer, and bonding a substantially single crystalline layer to the bonding layer.

[0115]

[0136] The method 1400 further includes a step 1412 of forming a buffer layer on the monocrystalline silicon layer, and a step 1414 of forming a semi-insulating layer on the buffer layer. The method 1400 further includes a step 1416 of forming a first epitaxial N-type gallium nitride layer on the semi-insulating layer, a step 1418 of forming a second epitaxial N-type gallium nitride layer on the first epitaxial N-type gallium nitride layer, and a step 1420 of forming an epitaxial P-type gallium nitride layer on the second epitaxial N-type gallium nitride layer. According to some embodiments, the first N-type gallium nitride layer has a first doping concentration. The second epitaxial N-type gallium nitride layer has a second doping concentration that is lower than the first doping concentration.

[0116]

[0137] According to some embodiments, method 1400 further includes step 1422 of removing a portion of the second epitaxial N-type gallium nitride layer and a portion of the epitaxial P-type gallium nitride layer to expose a portion of the first epitaxial N-type gallium nitride layer. Method 1400 further includes step 1424 of forming an anode contact on a remaining portion of the epitaxial P-type gallium nitride layer and step 1426 of forming a cathode contact on the exposed portion of the first epitaxial N-type gallium nitride layer.

[0117]

[0138] It should be understood that the specific steps illustrated in FIG. 14 provide a specific method of manufacturing an engineered substrate according to another embodiment of the present invention. Other sequences of steps may be performed according to alternative embodiments. For example, alternative embodiments of the present invention may perform the steps outlined above in a different order. Additionally, individual steps illustrated in FIG. 14 may include multiple sub-steps that may be performed in various orders as appropriate for the individual step. Additionally, additional steps may be added or removed depending on the particular application. Those skilled in the art will recognize numerous variations, modifications, and alternatives.

[0118]

[0139] 15 is a simplified schematic cross-sectional view illustrating a vertical semiconductor diode 1500 formed on an engineered substrate according to another embodiment of the present invention. The vertical semiconductor diode can include a first N-type gallium nitride layer 1542 coupled to a cathode contact 1570, which can include a Ti / Al material, a second N-type gallium nitride layer 1544 coupled to the first N-type gallium nitride layer 1542, and a P-type gallium nitride layer 1546 coupled to the second N-type gallium nitride layer 1544. The first N-type gallium nitride layer can function as an N region of the PN diode and can have a relatively high N-type doping concentration. The second N-type gallium nitride layer 1544 can function as a drift region and can have a relatively low doping concentration compared to the doping concentration of the first N-type gallium nitride layer 1542. The P-type gallium nitride layer 1546 can function as a P region of the PN diode and can have a relatively high P-type doping concentration. In some embodiments, the first N-type gallium nitride layer 1542, the P-type gallium nitride layer 1546, and the second N-type gallium nitride layer 1544 may be grown using epitaxial layers. The epitaxial layers may be grown on engineered substrates as described above with reference to Figures 1, 3, and 4. The epitaxial layers may be at least 10 μm thick and 6 inches in diameter.

[0119]

[0140] The vertical semiconductor diode 1500 is similar to the semiconductor diode 1300, except that the substrate 1310, buffer layer 1320, and semi-insulating layer 1330 are removed after the PN diode is formed to form a "true" vertical device structure with an anode 1560 and a cathode 1584 on the opposite side of the wafer. In an alternative embodiment, a portion of the substrate 1310, buffer layer 1320, and semi-insulating layer 1330 form a contact window. The contact window can be used to form a vertical device structure with an anode 1560 and a cathode 1584 on both sides of the wafer.

[0120]

[0141] In some embodiments, the thermal resistance of the vertical semiconductor diode 1500 can be lowered by removing the engineered substrate 1310, the buffer layer 1320, and the semi-insulating layer 1330 from the structure shown in FIG. 13. In some embodiments, the vertical semiconductor diode 1500 can be transferred to copper, which can serve as a cathode electrical contact. The plated copper can also serve as a heat sink for the vertical semiconductor diode 1500. The copper can be 30 μm thick, and the combination of the first N-type gallium nitride layer 1542, the second N-type gallium nitride layer 1544, and the P-type gallium nitride layer 1546 can be 150 μm thick or less. In this embodiment, the thermal resistance of the vertical semiconductor diode is 0.2 K*mm 2 / W or less. In this embodiment, the thermal resistance can be four times lower than a diode formed using an epitaxial gallium nitride layer on a gallium nitride substrate.

[0121]

[0142] In other embodiments, a deposited diamond layer can be formed to provide electrical connectivity to the first N-type gallium nitride layer 1542, improve thermal resistance, and / or provide a cathode electrical contact 1584. Chemical vapor deposition can be used to form the deposited diamond layer. The deposited diamond layer can be doped to form an N-type diamond layer. The deposited diamond layer can be a heat sink for a power device. In some embodiments, the deposited diamond layer can be 20 μm to 50 μm thick. It is understood that a combination of materials including copper and the deposited diamond layer can be used to form the cathode electrical contact.

[0122]

[0143] In some configurations, the epitaxial layer adjacent to the substrate has a higher incidence of defects compared to the epitaxial layer grown further from the interface with the substrate. The defects may include, for example, impurities, crystal mismatches, and dislocations. These initial layer defects can account for a high percentage of the device resistance. The unique CTE matching properties of the engineered substrate 1310 shown in FIG. 13 allow the first N-type gallium nitride layer 1542 adjacent to the engineered substrate 1310 to be thicker than epitaxial layers grown on conventional substrates. In some embodiments, in addition to removing the engineered substrate 1310, a layer of the first N-type gallium nitride layer 1542 adjacent to the engineered substrate 1310 may also be removed. In some embodiments, a cathode electrical contact 1584 may be formed directly on the high quality gallium nitride epitaxial layer after the substrate and the initial higher defect epitaxial layer are removed.

[0123]

[0144] Removing the engineered substrate adds an additional processing step, but power processing contacts are now made on two different sides of the wafer, facilitating metallization, improving current spreading and heat extraction, and reducing electrical resistance. In some embodiments, to provide low electrical resistance, the first N-type gallium nitride layer 1542 is 3×10 18 cm -3 ~5×10 18 cm -3In some embodiments, the electrical resistance can be on the order of 0.1 ohms×mm 2 13, the anode contact 1360 cannot be too close to the sidewall adjacent to the cathode contact 1370 because otherwise dielectric breakdown may occur between the anode contact 1360 and the cathode contact 1370. The vertical semiconductor diode 1500 eliminates this concern.

[0124]

[0145] 16 is a simplified flow chart illustrating a method 1600 of fabricating a vertical semiconductor diode on an engineered substrate according to one embodiment of the present invention. The method 1600 includes forming a substrate 1610 by providing a polycrystalline ceramic core, encapsulating the polycrystalline ceramic core with a first adhesive shell, encapsulating the first adhesive shell with a barrier layer, forming a bonding layer on the barrier layer, and bonding a substantially single crystalline layer to the bonding layer.

[0125]

[0146] The method 1600 further includes a step 1612 of forming a buffer layer on the monocrystalline silicon layer, and a step 1614 of forming a semi-insulating layer on the buffer layer. The method 1600 further includes a step 1616 of forming a first epitaxial N-type gallium nitride layer on the semi-insulating layer, a step 1618 of forming a second epitaxial N-type gallium nitride layer on the first epitaxial N-type gallium nitride layer, and a step 1620 of forming an epitaxial P-type gallium nitride layer on the second epitaxial N-type gallium nitride layer. According to some embodiments, the first N-type gallium nitride layer has a first doping concentration. The second epitaxial N-type gallium nitride layer has a second doping concentration that is lower than the first doping concentration.

[0126]

[0147] According to some embodiments, the method 1600 further includes step 1622 of removing the substrate, buffer layer, and semi-insulating layer to expose a bottom surface of the first N-type gallium nitride layer. In some embodiments, the initial layer of the first N-type gallium nitride layer may be removed. Several techniques may be used to remove the processed substrate, buffer layer, and semi-insulating layer. For example, a chemical such as hydrofluoric acid (HF) may be injected into the side of the wafer holding the vertical semiconductor diode to etch the buffer layer or layers and semi-insulating layers, while leaving the ceramic core and vertical semiconductor diode epitaxial stack intact. Etching the buffer layer or layers and semi-insulating layers separates the vertical semiconductor diode epitaxial stack from the remainder of the processed substrate while preserving the ceramic core for reuse. This chemical lift-off process also reduces the overall stress on the vertical semiconductor diode epitaxial stack by eliminating the polishing process. When using a gallium nitride substrate, the substrate cannot be selectively removed. In addition, gallium nitride substrates contain defects such as facet inversion, residual stress, fragility, and miscut surfaces that affect the quality of the epitaxial layers grown thereon. In some embodiments using gallium nitride substrates, 75% of the resistance may be due to defects in the substrate. Embodiments of the present invention that remove the substrate to expose the epitaxial layers for contact formation can thereby reduce electrical and thermal resistance.

[0127]

[0148] In some embodiments, a sacrificial layer can be used for the chemical lift-off process. The sacrificial layer can be a metal such as titanium (Ti) that is highly soluble when exposed to HF. In some embodiments, the sacrificial layer can include one of titanium (Ti), vanadium (V), chromium (Cr), tantalum (Ta), tungsten (W), rhenium (Re), silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof. In addition to the sacrificial layer, a protective layer can be used. The protective layer can prevent diffusion of material from the sacrificial layer 200, such as Ti, into the GaN epitaxial layer during epitaxial GaN growth. Further description regarding removing the substrate, buffer layer, and semi-insulating layer is provided in U.S. Patent Application No. 15 / 288,506, the disclosure of which is incorporated herein by reference in its entirety for all purposes. The substrate removal process described with respect to the vertical semiconductor diode can be used with any of the devices described herein. One skilled in the art would recognize many variations, modifications, and alternatives.

[0128]

[0149] The method further includes forming 1624 an anode contact on the epitaxial P-type gallium nitride layer and forming 1626 a cathode contact on a bottom surface of the first epitaxial N-type gallium nitride layer.

[0129]

[0150] It should be understood that the specific steps illustrated in FIG. 16 provide a specific method of manufacturing an engineered substrate according to another embodiment of the present invention. Other sequences of steps may be performed according to alternative embodiments. For example, alternative embodiments of the present invention may perform the steps outlined above in a different order. Additionally, individual steps illustrated in FIG. 16 may include multiple sub-steps that may be performed in various orders as appropriate for the individual step. Additionally, additional steps may be added or removed depending on the particular application. Those skilled in the art will recognize numerous variations, modifications, and alternatives.

[0130]

[0151] Power devices may operate under harsh thermal conditions. For example, they may be subjected to thermal cycling up to hundreds of degrees Celsius. Some localized hot spots may reach up to 250°C. Thermal cycling and residual internal stresses may lead to reliability failures such as delamination, dielectric breakdown, etc. Thus, by forming GaN device layers on engineered substrates that feature a CTE that substantially matches the CTE of the power devices, such reliability failures may be eliminated or mitigated because the GaN device layers can expand and contract at the same rate as the engineered substrate.

[0131]

[0152] FIG. 17 is a simplified schematic cross-sectional view illustrating a semiconductor device 1700 formed on an engineered substrate 1710 according to one embodiment of the present invention. The semiconductor device 1700 has a substrate 1710. In some embodiments, the engineered substrate 1710 may include a polycrystalline ceramic core, a first adhesion layer bonded to the polycrystalline ceramic core, a barrier layer bonded to the first adhesion layer, a bonding layer bonded to the barrier layer, and a substantially single crystalline layer bonded to the bonding layer, as described above with reference to FIGS. 1, 3, and 4. According to one embodiment, the engineered substrate 1710 may further include a substantially single crystalline layer bonded to the bonding layer. For example, the substantially single crystalline layer may include substantially single crystalline silicon.

[0132]

[0153] In one embodiment, the polycrystalline ceramic core of the substrate 1710 comprises aluminum nitride. In some embodiments, the substrate 1710 further comprises a conductive layer bonded to the first adhesive layer and a second adhesive layer bonded to the conductive layer, the conductive layer and the second adhesive layer being disposed between the first adhesive layer and the barrier layer, as described above with reference to FIG. 1. In some embodiments, the first adhesive layer comprises a first tetraethylorthosilicate (TEOS) oxide layer and the second adhesive layer comprises a second TEOS oxide layer. The barrier layer can comprise a silicon nitride layer. The conductive layer can comprise a polysilicon layer.

[0133]

[0154] The semiconductor device 1700 includes a device structure 1720 formed on an engineered substrate 1710. According to some embodiments, the device structure 1720 can include a plurality of epitaxial gallium nitride based layers grown on a substantially single crystalline layer of the substrate 1710, the thermal expansion coefficient of the plurality of epitaxial gallium nitride layers being substantially equal to the thermal expansion coefficient of the substrate 1710.

[0134]

[0155] Additionally, the examples and embodiments described herein are for illustrative purposes only, and various modifications or changes will be suggested to those skilled in the art in light thereof, which should be included within the spirit and scope of this application and the scope of the appended claims.

Claims

[Claim 1] A substrate, A polycrystalline ceramic core; a first adhesive layer bonded to the polycrystalline ceramic core; a barrier layer bonded to the first adhesive layer; a bonding layer bonded to the barrier layer; a substrate including a substantially single crystalline layer bonded to the bonding layer; a buffer layer coupled to the substantially single crystalline layer, the buffer layer including a first portion and a second portion adjacent to the first portion; a plurality of semiconductor devices coupled to the buffer layer; 23. An integrated circuit device comprising:

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