Circuit system, main integration circuit and additional component integration circuit
The circuit system addresses the scalability issues of existing PMICs by using a single-line communication interface to allow flexible design and control between integrated circuits, reducing design burdens and enabling efficient adaptation to changes in power lane requirements.
Patent Information
- Application Number
- JP2023173210
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2023-10-04
- Publication Date
- 2025-04-16
AI Technical Summary
Existing power management integrated circuits (PMICs) are not scalable, making it difficult to adapt to changes in the number of power lanes without redesigning the entire system, which increases design burdens and requires the use of unproven PMICs.
A circuit system comprising a first integrated circuit and a second integrated circuit connected via a single-line communication line, allowing for flexible design and scalability by enabling the first integrated circuit to control the second integrated circuit through a bidirectional one-line serial interface, with multiple low times specified in the protocol to accommodate various commands.
This configuration allows for the seamless addition of new integrated circuits to the system, reducing design burdens and enabling continuous use of proven PMICs, while ensuring robust signal processing and synchronization between integrated circuits.
Smart Images
Figure 2025063760000001_ABST
Abstract
Description
[Technical field]
[0001] The present disclosure relates to a circuit system. [Background technology]
[0002] Mobile phones, tablet terminals, notebook personal computers (PCs), desktop PCs, and game consoles are equipped with microprocessors such as a CPU (Central Processing Unit) and a GPU (Graphics Processing Unit) that perform arithmetic processing.
[0003] Electronic devices incorporating microprocessors are being subdivided into multiple circuit blocks in response to the miniaturization of semiconductor manufacturing processes, the increase in peripheral circuits, and the demand for lower power consumption. Each circuit block is configured so that its power supply voltage can be controlled independently.
[0004] In such devices, a power supply controller circuit is used to control multiple power supply systems corresponding to multiple circuit blocks. The power supply controller circuit is also called a power management integrated circuit (PMIC).
[0005] The power supply controller circuit includes a sequencer that is required to reliably control the on / off of multiple power supply lanes in accordance with a predetermined sequence.
[0006] The power controller circuit controls multiple power lanes in time units called slots. For example, after starting a sequence, it is possible to set up a sequence in which the first power lane is turned on in the third slot, the second power lane is turned on in the fourth slot, the third power lane is turned on in the sixth slot, and so on.
[0007] [overview] Suppose a system is designed using a certain PMIC. If the system is modified and the number of power lanes (called the number of lanes or channels) to be controlled exceeds the number of power lanes of the PMIC originally used, the proven PMIC can no longer be used, and the system must be redesigned from scratch using a new, unproven PMIC. If it were possible to continue using the proven PMIC originally used when a system change occurs, the burden on the designer could be significantly reduced.
[0008] Such problems are not limited to PMICs and can occur in integrated circuits for a variety of applications.
[0009] The present disclosure has been made in this context, and it is an exemplary purpose of an embodiment thereof to provide an integrated circuit having expandability for flexible design of a circuit system. [Brief description of the drawings]
[0010] [Figure 1] FIG. 1 is a block diagram of a circuit system according to an embodiment. [Diagram 2] FIG. 2 is a diagram for explaining a communication protocol of the circuit system of FIG. [Diagram 3] FIG. 3 is an operational waveform diagram of the circuit system of FIG. [Figure 4] FIG. 4 is a block diagram showing a configuration example of a transceiver corresponding to the first interface circuit and the second interface circuit. [Diagram 5] FIG. 5 is a block diagram of the power supply system.
[0011] [Detailed Description] (Overview of the embodiment) A summary of some exemplary embodiments of the present disclosure will be described. This summary is intended to provide a simplified overview of some concepts of one or more embodiments for a basic understanding of the embodiments as a prelude to the detailed description that follows, and is not intended to limit the scope of the invention or disclosure. This summary is not intended to be an exhaustive overview of all possible embodiments, nor is it intended to identify key elements of all embodiments or to delineate the scope of some or all aspects. For convenience, the term "one embodiment" may be used to refer to one embodiment (example or variant) or multiple embodiments (examples or variants) disclosed in this specification.
[0012] A circuit system according to one embodiment includes a first integrated circuit, a second integrated circuit, and a single-wire communication line connecting the first integrated circuit and the second integrated circuit. The first integrated circuit and the second integrated circuit are communicatively connected by an open-drain bidirectional single-wire interface that utilizes the communication line. A plurality of low times are defined in a protocol in correspondence with a plurality of commands. The first integrated circuit can transmit any one of the plurality of commands as the first command to the second integrated circuit by fixing the potential of the communication line to a low level during the low time corresponding to the command to be transmitted.
[0013] According to this configuration, it is possible to add a second integrated circuit to a circuit system including a first integrated circuit and control the second integrated circuit by the first integrated circuit, which allows flexible design of the circuit system.
[0014] In one embodiment, when the second integrated circuit receives a first command, which is one of a plurality of commands, the second integrated circuit may fix the potential of the communication line to a low level to return an acknowledgement corresponding to the first command to the first integrated circuit, thereby enabling the first integrated circuit to confirm that the second integrated circuit has correctly received the first command transmitted by the first integrated circuit.
[0015] In one embodiment, when the second integrated circuit receives a first command that is one of a plurality of commands, the second integrated circuit may return a different acknowledge for each of the plurality of commands by fixing the potential of the communication line at a low level for the same time as the low time corresponding to the first command. By making the low time the same for a certain command and its corresponding acknowledge, the configurations of the first integrated circuit and the second integrated circuit can be simplified.
[0016] In one embodiment, the first integrated circuit may perform error handling when it does not receive an acknowledgement corresponding to the first command, thereby enabling robust signal handling.
[0017] In one embodiment, the second integrated circuit may include a second sequencer, and a number of commands may be defined corresponding to transitions between a number of states of the second sequencer, such that the first integrated circuit can control the states of the second sequencer in response to commands sent to the second integrated circuit.
[0018] In one embodiment, a low time corresponding to the synchronization signal may be defined by a protocol. After transmitting the first command, the first integrated circuit may transmit the synchronization signal to the second integrated circuit by fixing the potential of the communication line at a low level during the low time corresponding to the synchronization signal. The second sequencer may operate in synchronization with the synchronization signal.
[0019] In one embodiment, when the second integrated circuit receives the synchronization signal, the second integrated circuit may fix the potential of the communication line to a low level during the low time corresponding to the synchronization signal, thereby returning an acknowledgement corresponding to the synchronization signal to the first integrated circuit. By making the low time of the synchronization signal and the corresponding acknowledgement the same, the configurations of the first integrated circuit and the second integrated circuit can be simplified.
[0020] In one embodiment, the first integrated circuit may include a first sequencer. The first sequencer may operate in synchronization with an acknowledge corresponding to the synchronization signal. This allows the first sequencer and the second sequencer to operate in synchronization with each other.
[0021] In one embodiment, the first integrated circuit may perform error handling when it does not receive an acknowledgement corresponding to the synchronization signal it transmits, thereby enabling robust signal processing.
[0022] In one embodiment, the first integrated circuit is a power management circuit, and the second integrated circuit may be a power supply circuit or a power management circuit.
[0023] A main integrated circuit according to one embodiment can configure a circuit system together with an additional component integrated circuit. The main integrated circuit includes a first interface pin to be connected to the additional component integrated circuit via a single communication line, and an open-drain first interface circuit connected to the first interface pin. A protocol specifies a plurality of low times corresponding to a plurality of commands. The first interface circuit can transmit any one of the plurality of commands as a first command to the additional component integrated circuit by fixing the potential of the communication line to a low level during the low time corresponding to the command to be transmitted.
[0024] An additional component integrated circuit according to an embodiment can configure a circuit system together with a main integrated circuit. The additional component integrated circuit includes a second interface pin to be connected to the main integrated circuit via a single-wire communication line, and an open-drain type second interface circuit connected to the second interface pin. A plurality of low times corresponding to a plurality of commands are defined in a protocol. The second interface circuit detects the time when the main integrated circuit fixes the potential of the communication line to a low level, and is capable of receiving from the main integrated circuit a first command corresponding to the detected time among the plurality of commands.
[0025] (Embodiment) Hereinafter, preferred embodiments will be described with reference to the drawings. The same or equivalent components, parts, and processes shown in each drawing will be given the same reference numerals, and duplicated descriptions will be omitted as appropriate. In addition, the embodiments are illustrative and do not limit the disclosure and invention, and all features and combinations thereof described in the embodiments are not necessarily essential to the disclosure and invention.
[0026] In this specification, "a state in which component A is connected to component B" includes not only a case in which component A and component B are directly physically connected to each other, but also a case in which component A and component B are indirectly connected to each other via other components that do not substantially affect the electrical connection state between them or that do not impair the function or effect achieved by their combination.
[0027] Similarly, "a state in which component C is connected (provided) between components A and B" includes not only the case in which components A and C, or components B and C, are directly connected to each other, but also the case in which they are indirectly connected to each other via other components that do not substantially affect the electrical connection between them or that do not impair the functions or effects achieved by their combination.
[0028] 1 is a block diagram of a circuit system 100 according to an embodiment. The circuit system 100 includes a first integrated circuit 200 and a second integrated circuit 300. The first integrated circuit 200 and the second integrated circuit 300 have a master-slave relationship, with the first integrated circuit 200 being a main IC and the second integrated circuit 300 being an additional component associated with the main IC. The second integrated circuit 300 operates under the control of the first integrated circuit 200.
[0029] The first integrated circuit 200 includes a first functional block 220. The first functional block 220 is configured to execute a main process of the first integrated circuit 200. The function and configuration of the first functional block 220 are not particularly limited.
[0030] Similarly, the second integrated circuit 300 includes a second functional block 320. The second functional block 320 is configured to execute main processing of the second integrated circuit 300. The function and configuration of the second functional block 320 are not particularly limited.
[0031] A first interface pin IF1 of the first integrated circuit 200 and a second interface pin IF2 of the second integrated circuit 300 are connected via a single-wire communication line 102. The first integrated circuit 200 and the second integrated circuit 300 are communicatively connected by an open-drain bidirectional single-wire serial interface 104 that utilizes the communication line 102. The communication line 102 is pulled up to the power supply line VDD via a pull-up resistor Rp1.
[0032] The first integrated circuit 200 and the second integrated circuit 300 are provided with a first interface circuit 210 and a second interface circuit 310 that constitute the serial interface 104 .
[0033] The first functional block 220 generates a command for controlling the second functional block 320 and transmits it to the second functional block 320 via the serial interface 104. Specifically, from the first integrated circuit 200 to the second integrated circuit 300, one arbitrarily selected from a plurality of n (n≧2) commands CMD1 to CMDn can be transmitted as a transmission command (also referred to as a first command). If the plurality of n is 3 or more, advanced control is possible from the first integrated circuit 200 to the second integrated circuit 300. A plurality of low times T CMD1 ~T CMDn is defined in the protocol. The first integrated circuit 200 determines the low time T CMDi During this period, by fixing the communication line 102 to a low level (0 V), it is possible to transmit one of the multiple commands CMD1 to CMDn to the second integrated circuit 300 as a transmission command CMDi.
[0034] The first interface circuit 210 and the second interface circuit 310 are transceivers capable of transmitting and receiving signals in both directions. When the first interface circuit 210 transmits an arbitrary one CMDi of the multiple commands CMD1 to CMDn as a transmission command to the second interface circuit 310, the first interface circuit 210 increases the potential V COM , that is, the potential of the first interface pin IF1 is set to low for a time T CMDi The signal is fixed at a low level during
[0035] The second interface circuit 310 is connected to the second interface pin IF2, i.e., the potential V COM The second interface circuit 310 monitors the time T during which the potential of the second interface pin IF2 is fixed at a low level. LOW Detects and detects time T LOW However, the low time T CMD1 ~T CMDn The time T LOW T CMDi If so, the second interface circuit 310 receives the i-th command CMDi as a transmission command.
[0036] The second interface circuit 310 is configured to return an acknowledgement CMD_ACK to the first interface circuit 210 upon receiving a transmission command CMD from the first interface circuit 210 .
[0037] It is preferable that a plurality of acknowledges CMD_ACK1 to CMD_ACKn are defined corresponding to a plurality of commands CMD1 to CMDn. That is, when the second interface circuit 310 receives a transmission command CMDi, it returns an acknowledge CMD_ACKi. In this way, when the first interface circuit 210 receives an acknowledge CMD_ACKi corresponding to a transmission command CMDi after transmitting the transmission command, it can know that the transmission command has been transmitted correctly.
[0038] Conversely, if the first interface circuit 210 receives an acknowledgment CMD_ACKj (j ≠ i) that does not correspond to a transmission command CMDi after transmitting the command, or if the first interface circuit 210 cannot receive any acknowledgment CMD_ACK, the first interface circuit 210 can know that the transmission command could not be transmitted correctly (a transmission error).
[0039] When a transmission error occurs, the first integrated circuit 200 may execute a predetermined error process. An error pin ERR1 of the first integrated circuit 200 and an error pin ERR2 of the second integrated circuit 300 are connected via an error signal line 106 separate from the communication line 102. The signal line 106 is pulled up to the power line by a pull-up resistor Rp2. When a transmission error occurs, the first functional block 220 fixes the potential of the signal line 106 to a low level and notifies the second functional block 320 of the occurrence of the transmission error. The second functional block 320 executes error process in response to the notification of the transmission error.
[0040] The first functional block 220 may include a first sequencer 222. Similarly, the second functional block 320 may include a second sequencer 322 that should operate in conjunction with the first sequencer 222. In this case, the multiple commands CMD1 to CMDn may include a control command for the second sequencer 322.
[0041] The circuit system 100 as a whole can support n sequence controls SEQ1 to SEQn, and commands CMD1 to CMDn are defined corresponding to the sequence controls SEQ1 to SEQn.
[0042] In the first integrated circuit 200, when an event that triggers the ith (i=1, 2, . . . n) sequence control SEQi is detected, the first interface circuit 210 transmits the ith command CMDi to the second interface circuit 310 as a transmission command, and also initiates the main side processing P corresponding to the ith sequence control SEQi. MAINWhen the second interface circuit 310 receives the transmission command CMDi, the second function block 320 executes the additional component side process P i corresponding to the i-th sequence control SEQi, using the command as a trigger. AUX Run i.
[0043] Furthermore, the first sequencer 222 and the second sequencer 322 execute the process P corresponding to the sequence control SEQi. MAIN i,P AUX In order to execute the operations i in conjunction with each other, a synchronization signal SYNC can be sent from the first interface circuit 210 to the second interface circuit 310.
[0044] In the protocol of the serial interface 104, the low time T SYNC The first interface circuit 210 of the first integrated circuit 200 has a low time T SYNC During this period, the communication line 102 is fixed at a low level, thereby transmitting a synchronization signal SYNC to the second integrated circuit 300.
[0045] The second interface circuit 310 is configured to detect a time T during which the potential of the second interface pin IF2 is fixed to a low level. LOW Detects and detects time T LOW is the low time T SYNC If so, the synchronization signal SYNC is received.
[0046] After transmitting the transmission command CMDi, the first integrated circuit 200 may transmit the synchronization signal SYNC repeatedly multiple times at predetermined time intervals (called time slots) to the second integrated circuit 300. This allows the first sequencer 222 on the first integrated circuit 200 side and the second sequencer 322 on the second integrated circuit 300 side to operate synchronously in association with the time slots.
[0047] Each time the second interface circuit 310 of the second integrated circuit 300 receives the synchronization signal SYNC, the second interface circuit 310 SYNCDuring this period, the communication line 102 is fixed at a low level, thereby returning an acknowledgement SYNC_ACK corresponding to the synchronization signal SYNC to the first integrated circuit 200.
[0048] The second sequencer 322 may operate in synchronization with the second interface circuit 310 receiving the synchronization signal SYNC, and the first sequencer 222 may operate in synchronization with the first interface circuit 210 receiving the acknowledge signal SYNC_ACK.
[0049] The second sequencer 322 may operate in synchronization with the completion of transmission of the acknowledge SYNC_ACK from the second interface circuit 310, and the first sequencer 222 may operate in synchronization with the reception of the acknowledge SYNC_ACK by the first interface circuit 210. In this case, the first sequencer 222 and the second sequencer 322 can realize highly synchronized operations by using the same acknowledge SYNC_ACK as a reference.
[0050] The second sequencer 322 may operate in synchronization with the reception of the synchronization signal SYNC by the second interface circuit 310, and the first sequencer 222 may operate in synchronization with the transmission of the synchronization signal SYNC by the first interface circuit 210.
[0051] When the first integrated circuit 200 does not receive an acknowledge signal SYNC_ACK corresponding to the synchronization signal SYNC that it has transmitted, it determines that a transmission error has occurred and executes error processing. COM is fixed to a low level, and the occurrence of a transmission error is notified to the second functional block 320. In response to the notification of the transmission error, the second functional block 320 executes error processing.
[0052] The above is the configuration of the circuit system 100. Next, the communication protocol of the serial interface 104 will be described.
[0053] 2 is a diagram for explaining a communication protocol of the circuit system 100 of FIG. 1. In FIG. COM The potential V of the communication line 102 is COM changes based on the following times as specified in the protocol: T CMDi : Raw time corresponding to the command T HD Handoff time T CMD_ACK : Low time corresponding to command acknowledgement T CMD_STRB : Command strobe time T SYNC : Low time corresponding to the sync signal T SYNC_ACK : Low time corresponding to the acknowledge of the sync signal T WAIT : Waiting time
[0054] Waiting time T WAIT is a parameter that defines the time interval of the synchronization signal SYNC, and therefore defines the time length of one slot.
[0055] 3 is an operation waveform diagram of the circuit system 100 of FIG. 1. At time t0, an event EVTi occurs which triggers sequence control SEQi. When the first integrated circuit 200 detects this event EVTi, it transmits a corresponding command CMDi as a transmission command to the second integrated circuit 300. The second integrated circuit 300 returns an acknowledge CMD_ACKi corresponding to the transmission command CMDi to the first integrated circuit 200. As a result, the first integrated circuit 200 and the second integrated circuit 300 execute the process P related to the sequence control SEQi. MAIN i, P AUX i becomes executable. MAIN i, P AUX i includes multiple steps, and each step is controlled in a time unit called a slot.
[0056] When the first integrated circuit 200 receives an acknowledge CMD_ACKi corresponding to the transmission command CMDi, it transmits a synchronization signal SYNC to the second integrated circuit 300, and the second integrated circuit 300 returns an acknowledge SYNC_ACK corresponding to the synchronization signal SYNC. For example, the slot of the second sequencer 322 on the second integrated circuit 300 side is incremented upon receiving the synchronization signal SYNC. The slot of the first sequencer 222 on the first integrated circuit 200 side is incremented upon receiving the acknowledge SYNC_ACK.
[0057] The above is the operation of the circuit system 100. According to this circuit system 100, the state of the second integrated circuit 300 can be controlled from the first integrated circuit 200 by communication using the communication line 102. Specifically, it becomes possible to transmit different commands from the first integrated circuit 200 to the second integrated circuit 300. Furthermore, by transmitting a synchronization signal SYNC, synchronized signal processing between the first integrated circuit 200 and the second integrated circuit 300 becomes possible.
[0058] Suppose that a designer has designed a system including only the first integrated circuit 200. Suppose that later, a change occurs in the system and a second integrated circuit 300 is to be added. In this case, by connecting the first integrated circuit 200 and the second integrated circuit 300 with a communication line 102, it becomes possible to control the second integrated circuit 300 from the first integrated circuit 200. In other words, the first integrated circuit 200 and the second integrated circuit 300 have extensibility for flexible design of the circuit system.
[0059] FIG. 4 is a block diagram showing an example of the configuration of a transceiver 400 corresponding to the first interface circuit 210 and the second interface circuit 310. As shown in FIG.
[0060] The transceiver 400 includes a transmitter 410 and a receiver 420. The transmitter 410 includes a transistor 412 whose drain is connected to an interface pin IF, a timer circuit 414, and an encoder 416. The encoder 416 receives information S1 to be transmitted to a communication partner transceiver. If the transceiver 400 is the first interface circuit 210, the information S1 specifies a command CMDi or a synchronization signal SYNC. If the transceiver 400 is the second interface circuit 310, the information S1 specifies an acknowledge CMD_ACKi or a SYNC_ACK.
[0061] The timer circuit 414 turns on the transistor 412 for a time period corresponding to the information S1 received by the encoder 416. For example, when the information S1 indicates a command CMDi, the timer circuit 414 turns on the transistor 412 for a time period T CMDi During this period, transistor 412 is turned on.
[0062] The receiver 420 includes a comparator 422, a timer circuit 424, and a decoder 426. The comparator 422 detects the potential V COM is the threshold voltage V TH The timer circuit 424 receives the comparison signal S2 from the comparator 422 and measures the time during which the comparison signal S2 is at the predetermined level, in other words, the time during which the potential VCOM is at the low level. COM The time T when LOW Measure the time T LOW The decoder 42 receives the signal S3 and outputs a signal S3 indicating the time T LOW The corresponding information S4 is output.
[0063] The configuration of transceiver 400 is not limited to that shown in FIG. 4, and may be any other configuration that is known or that will be available in the future.
[0064] Next, a description will be given of the use of the circuit system 100. The circuit system 100 is a power supply system, and the first integrated circuit 200 and the second integrated circuit 300 may be PMICs (power management ICs). The second integrated circuit 300 may be a power supply IC with only a single channel.
[0065] 5 is a block diagram of a power supply system 500. The power supply system 500 includes a load 502, a first PMIC 600, and a second PMIC 700. The first PMIC 600 corresponds to the first integrated circuit 200 described above, and the second PMIC 700 corresponds to the second integrated circuit 300 described above. The first PMIC 600 and the second PMIC 700 provide a plurality of power supply voltages V DD The load 502 may be a single IC having a plurality of power supply terminals, such as a microcontroller or a SOC (System on Chip), or may be a collection of a plurality of ICs.
[0066] The first PMIC 600 includes a first interface circuit 610 and a multi-channel (m-channel) power supply circuit 620. The first interface circuit 610 corresponds to the first interface circuit 210, and the power supply circuit 620 corresponds to the first functional block 220. The power supply circuit 620 includes a first sequencer 622 and a plurality of power supply units 624_1 to 624_m. The first sequencer 622 corresponds to the first sequencer 222. The power supply units 624_1 to 624_m are connected to a power supply voltage V DD1 ~V DDm The power supply units 624_1 to 624_m can be switching power supplies such as step-down converters or step-up converters, or linear regulators. Note that peripheral circuit components such as capacitors and inductors are not shown in FIG.
[0067] The second PMIC 700 includes a second interface circuit 710 and a multi-channel (n-channel) power supply circuit 720. The second interface circuit 710 corresponds to the second interface circuit 310, and the power supply circuit 720 corresponds to the second functional block 320. The power supply circuit 720 includes a second sequencer 722 and a plurality of power supply units 724_1 to 724_n. The second sequencer 722 corresponds to the second sequencer 322. The power supply units 724_1 to 724_n are connected to a power supply voltage V DD1 ~V DDn The power supply units 724_1 to 724_m can be switching power supplies such as step-down converters or step-up converters, or linear regulators.
[0068] The load 502 can be switched between a plurality of states. The power supply system 500 selects a plurality of power supply voltages V DD The types and names of the states that the load 502 can take are various and are not particularly limited.
[0069] In this power supply system 500, by transmitting a command from the first PMIC 600 to the second PMIC 700, the states of the multiple power supply units 724_1 to 724_n on the second PMIC 700 side can be controlled in synchronization with the states of the power supply units 624_1 to 624_m on the first PMIC 600 side.
[0070] The second PMIC 700 further includes a general purpose input / output (GPIO) circuit 730. The GPIO circuit 730 includes at least one output terminal GPIO. The multiple commands transmitted by the first interface circuit 610 to the second interface circuit 710 may include commands for controlling the state of each output terminal GPIO of the GPIO circuit 730. The first PMIC 600 may also include a GPIO circuit (not shown), and the state of the GPIO circuit on the first PMIC 600 side may be controllable by the first sequencer 622.
[0071] An additional component IC504 can be connected to the output terminal GPIO of the GPIO circuit 730. The additional component IC504 may be an IC having a control terminal for receiving a binary signal of high or low, such as an enable terminal EN, and the on / off state of the additional component IC504 can be controlled according to the state of the output terminal GPIO of the GPIO circuit 730. As a result, in this power supply system 500, by transmitting a command from the first PMIC 600 to the second PMIC 700, the state of the additional component IC504 can be controlled in synchronization with the state of the power supply units 624_1-624_m on the first PMIC 600 side in addition to the state of the multiple power supply units 724_1-724_n on the second PMIC 700 side.
[0072] An IC having any desired function can be connected as the additional component IC 504, but for example, the additional component 504 may be a linear regulator or a controller circuit for a DC / DC converter. In this case, the total number of channels of the power supply system 500 can be further increased, and further, the power supply circuit, which is the additional component IC 504, can be controlled in synchronization with other power supply units.
[0073] The embodiments are merely examples, and it will be understood by those skilled in the art that there are various modifications in the combination of each component and each treatment process, and that such modifications are also included within the scope of the present disclosure or the present invention.
[0074] The first integrated circuit 200 and the second integrated circuit 300 are communicably connected by an open-drain bidirectional one-wire serial interface 104 using a communication line 102. In this bidirectional one-wire serial interface 104, after transmitting a command CMDi and an acknowledge CMD_ACKi, a handoff time T is set to be longer than the transition time from a low level L to a high level H. His defined. During the transition time from low level L to high level H, a conversion circuit that temporarily changes the open-drain format to a push-pull format, or a switching circuit that switches between the push-pull formats, may be included. This conversion / switching circuit allows the circuit system 100 to shorten the handoff time even if the pull-up resistance is increased. This conversion / switching circuit allows the circuit system 100 to perform high-speed communication while suppressing current consumption during communication.
[0075] (Additional Note) One aspect of the technology disclosed in this specification can be understood as follows.
[0076] (Item 1) A first integrated circuit; A second integrated circuit; a single-wire communication line connecting the first integrated circuit and the second integrated circuit; Equipped with the first integrated circuit and the second integrated circuit are communicatively connected by an open-drain bidirectional one-wire interface utilizing the communication line; The protocol specifies multiple row times corresponding to multiple commands. A circuit system, wherein the first integrated circuit is capable of transmitting any one of the plurality of commands as a first command to the second integrated circuit by fixing the potential of the communication line at a low level during a low time corresponding to the command to be transmitted.
[0077] (Item 2) The circuit system described in item 1, wherein when the second integrated circuit receives the first command, which is any one of the plurality of commands, it returns an acknowledgement corresponding to the first command to the first integrated circuit by fixing the potential of the communication line to a low level.
[0078] (Item 3) The circuit system described in item 2, wherein when the second integrated circuit receives the first command which is any one of the plurality of commands, it fixes the potential of the communication line to a low level for the same period as the low period corresponding to the first command, thereby returning a different acknowledgement for each of the plurality of commands.
[0079] (Item 4) 4. The circuit system according to item 3, wherein the first integrated circuit executes error processing when it does not receive the acknowledgement corresponding to the first command.
[0080] (Item 5) 5. The circuit system according to any one of items 1 to 4, wherein the second integrated circuit includes a second sequencer, and the plurality of commands are defined corresponding to transitions between a plurality of states of the second sequencer.
[0081] (Item 6) a low time corresponding to a synchronization signal is defined by the protocol, and the first integrated circuit is capable of transmitting the synchronization signal to the second integrated circuit by fixing a potential of the communication line to a low level during the low time corresponding to the synchronization signal after transmitting the first command; 6. The circuit system according to item 5, wherein the second sequencer operates in synchronization with the synchronization signal.
[0082] (Item 7) 7. The circuit system according to claim 6, wherein, upon receiving the synchronization signal, the second integrated circuit fixes the potential of the communication line to a low level during a low time corresponding to the synchronization signal, thereby returning an acknowledgement corresponding to the synchronization signal to the first integrated circuit.
[0083] (Item 8) the first integrated circuit includes a first sequencer; 8. The circuit system according to item 7, wherein the first sequencer operates in synchronization with the acknowledge corresponding to the synchronization signal.
[0084] (Item 9) 9. The circuit system according to item 7 or 8, wherein the first integrated circuit performs error processing when it does not receive the acknowledgement corresponding to the synchronization signal transmitted by itself.
[0085] (Item 10) the first integrated circuit is a power management circuit; 10. The circuit system of any one of items 1 to 9, wherein the second integrated circuit is a power supply circuit or a power management circuit.
[0086] (Item 11) A main integrated circuit capable of forming a circuit system together with additional component integrated circuits, a first interface pin to be connected to said additional component integrated circuit via a single-wire communication line; a first interface circuit of an open drain type connected to the first interface pin; Equipped with Multiple command row times are specified in the protocol to correspond to multiple commands. The main integrated circuit, wherein the first interface circuit is capable of transmitting any one of the plurality of commands as a first command to the additional component integrated circuit by fixing the potential of the communication line at a low level during a command low time corresponding to the command to be transmitted.
[0087] (Item 12) An additional component integrated circuit capable of forming a circuit system together with a main integrated circuit, a second interface pin to be connected to the main integrated circuit via a single-wire communication line; a second interface circuit of an open drain type connected to the second interface pin; Equipped with Multiple command row times are specified in the protocol to correspond to multiple commands. an additional component integrated circuit, wherein the second interface circuit is capable of detecting a time when the main integrated circuit fixes the potential of the communication line at a low level, and receiving from the main integrated circuit a first command from the plurality of commands that corresponds to the detected time; [Explanation of symbols]
[0088] 100 Circuit System 102 Communication Line 104 Serial Interface 200 1st Integrated Circuit IF Interface Pin 210 First interface circuit 220 First Function Block 222 1st sequencer 300 Second Integrated Circuit 310 Second interface circuit 320 Second Function Block 322 Second sequencer 500 Power System 502 Load 600 1st PMIC 610 First Interface Circuit 620 Power supply circuit 622 1st sequencer 624 Power supply section 700 2nd PMIC 710 Second Interface Circuit 720 Power supply circuit 722 Second sequencer 724 Power supply section
Claims
1. A first integrated circuit; A second integrated circuit; a single-wire communication line connecting the first integrated circuit and the second integrated circuit; Equipped with the first integrated circuit and the second integrated circuit are communicatively connected by an open-drain bidirectional one-wire interface utilizing the communication line; The protocol specifies multiple row times corresponding to multiple commands. A circuit system, wherein the first integrated circuit is capable of transmitting any of the plurality of commands as a first command to the second integrated circuit by fixing the potential of the communication line at a low level during a low time corresponding to the command to be transmitted.
2. 2. The circuit system according to claim 1, wherein when the second integrated circuit receives the first command, which is any one of the plurality of commands, it returns an acknowledgement corresponding to the first command to the first integrated circuit by fixing the potential of the communication line to a low level.
3. 3. The circuit system according to claim 2, wherein, when the second integrated circuit receives the first command which is any one of the plurality of commands, it fixes the potential of the communication line to a low level for a period of time equal to a low time corresponding to the first command, thereby returning a different acknowledgement for each of the plurality of commands.
4. 4. The circuit system according to claim 3, wherein the first integrated circuit executes an error process when the first integrated circuit does not receive the acknowledgement corresponding to the first command.
5. 5. The circuit system according to claim 1, wherein the second integrated circuit includes a second sequencer, and the plurality of commands are defined corresponding to transitions between a plurality of states of the second sequencer.
6. a low time corresponding to a synchronization signal is defined by the protocol, and the first integrated circuit is capable of transmitting the synchronization signal to the second integrated circuit by fixing a potential of the communication line to a low level during the low time corresponding to the synchronization signal after transmitting the first command; The circuit system according to claim 5 , wherein the second sequencer operates in synchronization with the synchronization signal.
7. 7. The circuit system according to claim 6, wherein, upon receiving the synchronization signal, the second integrated circuit returns an acknowledgement corresponding to the synchronization signal to the first integrated circuit by fixing the potential of the communication line at a low level during a low time corresponding to the synchronization signal.
8. the first integrated circuit includes a first sequencer; 8. The circuit system according to claim 7, wherein the first sequencer operates in synchronization with the acknowledge corresponding to the synchronization signal.
9. 8. The circuit system according to claim 7, wherein the first integrated circuit executes an error process when the first integrated circuit does not receive the acknowledgement corresponding to the synchronization signal transmitted by the first integrated circuit.
10. the first integrated circuit is a power management circuit; The circuit system according to claim 1 , wherein the second integrated circuit is a power supply circuit or a power management circuit.
11. A main integrated circuit capable of forming a circuit system together with additional component integrated circuits, a first interface pin to be connected to said additional component integrated circuit via a single-wire communication line; a first interface circuit of an open drain type connected to the first interface pin; Equipped with Multiple command row times are specified in the protocol to correspond to multiple commands. The main integrated circuit, wherein the first interface circuit is capable of transmitting any one of the plurality of commands as a first command to the additional component integrated circuit by fixing the potential of the communication line at a low level during a command low time corresponding to the command to be transmitted.
12. An additional component integrated circuit capable of forming a circuit system together with a main integrated circuit, a second interface pin to be connected to the main integrated circuit via a single-wire communication line; a second interface circuit of an open drain type connected to the second interface pin; Equipped with Multiple command row times are specified in the protocol to correspond to multiple commands. An additional component integrated circuit, wherein the second interface circuit is capable of detecting a time when the main integrated circuit fixes the potential of the communication line at a low level, and receiving from the main integrated circuit a first command from the plurality of commands that corresponds to the detected time.