Capacitor and manufacturing method of the same

Abstract

To release a stress applied on a substrate 1 caused by a first protection film 6A and a dielectric layer 3.SOLUTION: A capacitor 100 comprises: a substrate 1 having a groove 2; lamination films 3 to 5 that include a first main surface 1a of at least the substrate 1, at least one dielectric layer 3 and at least one layer of conductive layer 4, 5 that are alternately laminated in an inner surface of a groove 2; and a first protection film 6A accumulated on the lamination films 3 to 5 accumulated on the first main surface 1a. The first protection film 6A is embedded into a first concave 22a that is formed on front surfaces of the lamination films 3 to 5 caused by a corner part 21a of the groove 2, and a space 7 is formed in an inner part of the groove 2 connected to the first concave 22a.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a capacitor and a method for manufacturing the same. [Background technology]

[0002] Patent Document 1 describes a capacitor that has an opening penetrating the front and back surfaces of a substrate, in which conductive plates and capacitor dielectric layers are alternately formed. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Special Publication No. 2014-505354 Summary of the Invention [Problem to be solved by the invention]

[0004] In Patent Document 1, a gap remains near the center of the opening where the conductive plate and the capacitor dielectric layer cannot be formed, and this gap is flattened by filling it with a dielectric material such as an inorganic material, a polymer material, etc. Therefore, since the material of the semiconductor substrate or the conductive plate and the capacitor dielectric layer is different from the material of the dielectric material filling the gap, there is a problem that a large stress is generated in the substrate near the opening.

[0005] The present invention has been made in view of the above-mentioned problems, and has an object to provide a capacitor and a method for manufacturing a capacitor that can reduce the stress applied to a substrate due to a first protective film and a dielectric layer. [Means for solving the problem]

[0006] A capacitor according to one aspect of the present invention includes a substrate having a groove, a laminated film having at least one dielectric layer and at least one conductive layer alternately laminated on at least a first main surface of the substrate and an inner surface of the groove, and a first protective film deposited on the laminated film deposited on the first main surface. The first protective film is embedded in a first depression formed in the surface of the laminated film due to a corner of the groove, and a space is formed inside the groove connected to the first depression. Effect of the Invention

[0007] According to the present invention, it is possible to reduce the stress applied to the substrate due to the first protective film and the dielectric layer. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a cross-sectional view showing the configuration of a capacitor 100 according to a first embodiment of the present invention. [Diagram 2] FIG. 2 is a cross-sectional view (part 1) showing an example of a method for manufacturing the capacitor 100 in FIG. [Diagram 3] FIG. 3 is a cross-sectional view (part 2) showing an example of a method for manufacturing the capacitor 100 in FIG. [Figure 4] FIG. 4 is a cross-sectional view (part 3) showing one example of a method for manufacturing the capacitor 100 in FIG. [Diagram 5] FIG. 5 is a cross-sectional view (part 4) showing an example of a method for manufacturing the capacitor 100 in FIG. [Figure 6] FIG. 6 is a cross-sectional view (part 5) showing an example of a method for manufacturing the capacitor 100 in FIG. [Figure 7] FIG. 7 is a cross-sectional view (part 6) showing one example of a method for manufacturing the capacitor 100 in FIG. [Figure 8] FIG. 8 is a cross-sectional view (part 7) showing one example of a method for manufacturing the capacitor 100 in FIG. [Figure 9] FIG. 9 is a cross-sectional view (part 8) showing an example of a method for manufacturing the capacitor 100 in FIG. [Figure 10]FIG. 10 is a cross-sectional view (part 9) showing an example of a method for manufacturing the capacitor 100 in FIG. [Figure 11] FIG. 11 is a cross-sectional view (part 10) showing one example of a method for manufacturing the capacitor 100 in FIG. [Figure 12A] FIG. 12A is a cross-sectional view showing the configuration of a capacitor according to a comparative example. [Figure 12B] FIG. 12B is a cross-sectional view showing the configuration of the capacitor corresponding to the first embodiment. [Figure 12C] FIG. 12C is a top view showing the planar shape of the substrate 1 in FIGS. 12A and 12B. [Figure 13] FIG. 13 is a cross-sectional view showing a configuration of a capacitor 101 according to a second embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, a capacitor and a method for manufacturing a capacitor according to the embodiments will be described in detail with reference to the drawings. Note that the embodiments described below are comprehensive or specific examples. The numerical values, shapes, materials, installation positions and connection forms of components shown in the following embodiments are examples and are not intended to limit the present disclosure. In addition, among the components in the following embodiments, components that are not described in the independent claims showing the highest concept are described as optional components. Furthermore, the dimensional ratios in the drawings are exaggerated for the convenience of explanation and may differ from the actual ratios. In addition, the following embodiments and their modified examples may include similar components, and similar components are given common symbols and redundant explanations are omitted.

[0010] (First embodiment) [Capacitor 100] 1 is a schematic cross-sectional view showing a configuration of a capacitor 100 according to a first embodiment of the present invention. The capacitor 100 according to the first embodiment includes a substrate 1. The substrate 1 has a first main surface 1a (front surface) and a second main surface 1b (back surface) facing each other. A groove 2 is formed in the first main surface 1a of the substrate 1. The substrate 1 is a semiconductor substrate, and is a single crystal substrate made of, for example, silicon (Si), germanium (Ge), silicon carbide (SiC), gallium nitride (GaN), or gallium oxide (Ga2O3).

[0011] The capacitor 100 includes a laminated film having at least one dielectric layer 3 and at least one conductive layer 4, 5 alternately laminated on at least the first main surface 1a of the substrate 1 and the inner surface 21c of the groove 2. In the example shown in FIG. 1, the laminated film has a plurality of (five layers as an example) dielectric layers 3 and a plurality of (five layers as an example) conductive layers 4, 5 alternately laminated. The groove 2 penetrates from the first main surface 1a to the second main surface 1b. The laminated films 3 to 5 are deposited on the first main surface 1a and the second main surface 1b of the substrate 1 and the inner surface 21c of the groove 2.

[0012] The laminated films 3-5 are embedded in a part of the inside of the groove 2, but not in the entire groove 2. A space 7 is formed in the central part, which is the remaining part of the inside of the groove 2. The thickness of the laminated films 3-5 embedded in the inside of the groove 2 is equal to or less than half the width of the groove 2, that is, half the length of the groove 2 in the direction parallel to the first main surface 1a of the substrate 1. The conductive layers 4 and 5 are, for example, polysilicon films doped with N-type or P-type impurities, but are not limited thereto and may be metal films or silicide films using materials such as conductive polysilicon carbide, silicon germanium (SiGe), aluminum (Al), etc. The dielectric layer 3 may be a silicon oxide film.

[0013] On the first main surface 1a side of the substrate 1, a first depression 22a is formed on the surface of the laminated film (3-5) due to the corners 21a of the grooves 2. On the second main surface 1b side of the substrate 1, a second depression 22b is formed on the surface of the laminated film (3-5) due to the corners 21b of the grooves 2. The first depression 22a and the second depression 22b are recessed portions with a predetermined curvature on the surface of the laminated film (3-5) due to the laminated film (3-5) being deposited along the shapes of the corners 21a, 21b of the grooves 2.

[0014] The capacitor 100 includes a first protective film 6A deposited on a laminated film 3 to 5 deposited on a first main surface 1a of a substrate 1. The first protective film 6A is embedded in a first recess 22a. A space 7 is formed inside a groove 2 connected to the first recess 22a.

[0015] The capacitor 100 includes a second protective film 6B deposited on the laminated films 3 to 5 deposited on the second main surface 1b of the substrate 1. The second protective film 6B is embedded in the second recess 22b. A space 7 is formed inside the groove 2 connected to the second recess 22b. For example, a filler with adjusted viscosity is embedded only in the first recesses 22a, 22b near the opening of the groove 2 as the first protective film 6A and the second protective film 6B.

[0016] The first recess 22a and the second recess 22b of the laminated films 3 to 5 communicate with each other via a space 7 inside the groove 2. The space 7 is isolated from the outside. In other words, the first protective film 6A embedded in the first recess 22a, the second protective film 6B embedded in the second recess 22b, and the laminated films 3 to 5 isolate the space 7 from the outside.

[0017] The surfaces of the first protective film 6A and the second protective film 6B are planarized. The first protective film 6A and the second protective film 6B can be made of a film containing silicon and oxygen, such as a silicon oxide film. As a particularly suitable example, BPSG (Boro Phospho Silicate Glass) to which boron (B) and phosphorus (P) are added, which becomes a gentle shape when heated, can be used.

[0018] The capacitor 100 includes third protective films 13A and 13B disposed on the first protective film 6A and the second protective film 6B. The third protective films 13A and 13B are made of, for example, a silicon oxide film. The third protective films 13A and 13B are deposited on the inner surfaces of the contact holes 11a, 11b, 11c, 10a, 10b, and 9 and the element isolation region 12. A through hole 15 is formed in the third protective film 13A disposed on the bottom surfaces of the contact holes 11a, 11b, 11c, 10a, 10b, and 9. From the through hole 15, the conductive layers 4 and 5 or the first main surface 1a of the substrate 1 are exposed.

[0019] The capacitor 100 further includes surface electrodes 18, 17 disposed on the third protective film 13A. The surface electrodes 18, 17 include a high potential electrode 18 electrically connected to at least one of the at least one conductive layer 4 and the substrate 1, and a low potential electrode 17 electrically connected to at least one of the conductive layer 5 not electrically connected to the high potential electrode 18 and the substrate 1 not electrically connected to the high potential electrode 18. In the example shown in FIG. 1, the high potential electrode 18 is electrically connected to three conductive layers 4 (high potential side conductive layers 4). The low potential electrode 17 is electrically connected to two conductive layers 5 (low potential side conductive layers 5) and the substrate 1 not electrically connected to the high potential electrode 18. As shown in FIG. 1, the high potential side conductive layers 4 and the low potential side conductive layers 5 are alternately stacked with a dielectric layer 3 interposed between them as viewed from the substrate 1. The substrate 1 is a conductive substrate and is used as one of the electrodes of the capacitor 100. For example, a film in which a titanium (Ti) film and an aluminum (Al) film are laminated in this order when viewed from the substrate 1 side can be used as the high potential electrode 18 and the low potential electrode 17. The surface electrodes 18 and 17 may also be a film containing other metals such as silver (Ag).

[0020] The high potential electrode 18 is disposed in the contact holes 11a, 11b, and 11c, and is electrically connected to the high potential side conductive layer 4 through the through hole 15. The low potential electrode 17 is disposed in the contact holes 10a, 10b, and 9 and the element isolation region 12. The low potential electrode 17 is electrically connected to the low potential side conductive layer 5 through the contact holes 10a and 10b and the through hole 15, and is electrically connected to the substrate 1 through the contact hole 9 and the through hole 15. A third protective film 13A is deposited on the side surfaces of the contact holes 11a, 11b, 11c, 10a, 10b, and 9. The third protective film 13A electrically insulates the high potential electrode 18 and the low potential electrode 17 from the conductive layers 4 and 5 exposed on the side surfaces of the contact holes 11a, 11b, 11c, 10a, 10b, and 9.

[0021] In addition, in the capacitor 100 shown in Figure 1, an element isolation region 12, which is a recess that penetrates the laminated films 3 to 5 and reaches the second main surface 1b of the substrate 1, is also formed on the second main surface 1b side of the substrate 1, and a third protective film 13B is deposited on the side and bottom surfaces of the element isolation region 12.

[0022] The basic operation of the capacitor 100 shown in FIG. 1 will be described. A positive voltage is applied to the high potential electrode 18 with the low potential electrode 17 as a reference. Alternatively, a negative voltage is applied to the low potential electrode 17 with the high potential electrode 18 as a reference. A potential difference is generated between the high potential side conductive layer 4 and the low potential side conductive layer 5, and a positive charge is attracted to the high potential side conductive layer 4 by electrostatic induction, and a negative charge is attracted to the low potential side conductive layer 5. At this time, polarization occurs inside the dielectric layer 3, and electrostatic capacitance is generated. In this way, the capacitor 100 can charge between the conductive layers 4 and 5 by applying a voltage between the electrodes 17 and 18. The low potential electrode 17 and the high potential electrode 18 may be interchanged and a voltage may be applied.

[0023] [Method of manufacturing capacitor 100] 2 to 11, an example of a method for manufacturing the capacitor 100 shown in Fig. 1 will be described. Note that the method for manufacturing the capacitor 100 described below is just one example, and various other manufacturing methods can be used.

[0024] A semiconductor substrate doped with a high concentration of N-type or P-type impurities is prepared as the substrate 1. When a Si substrate is used, an N-type semiconductor substrate can be manufactured by adding an impurity of a pentavalent element such as phosphorus (P) or arsenic (As), and a P-type semiconductor substrate can be manufactured by adding an impurity of a trivalent element such as boron (B) or gallium (Ga).

[0025] In the groove forming step, the groove 2 is formed on the first main surface 1a of the substrate 1. Specifically, as shown in FIG. 2, a part of the substrate 1 is etched to form the groove 2 penetrating the substrate 1 from the first main surface 1a to the second main surface 1b of the substrate 1. For example, first, a mask material (not shown) such as a silicon oxide film is deposited on the first main surface 1a of the substrate 1, and the mask material is patterned using a photolithography method. The patterned mask material has an opening in the portion where the groove 2 is to be formed. The silicon oxide film can be deposited using a thermal CVD (Chemical Vapor Deposition) method or a plasma CVD method. The silicon oxide film can be etched using wet etching using hydrofluoric acid or dry etching such as reactive ion etching. Next, the substrate 1 exposed from the opening of the mask material is etched by dry etching using the mask material to form the groove 2.

[0026] In the groove forming step, the (111) plane along the cleavage plane of the substrate 1 may be exposed on the side surface 21c of the groove 2. For example, the crystal orientation of the substrate 1 used and the pattern shape of the mask material may be adjusted to expose the (111) plane on the side surface 21c. This can increase the strength of the groove 2. The corner 21a where the side surface 21c of the groove 2 intersects with the first main surface 1a of the substrate 1, and the corner 21b where the side surface 21c of the groove 2 intersects with the second main surface 1b of the substrate 1 have an arc shape with a predetermined curvature. This can reduce the concentration of stress on the corners 21a and 21b.

[0027] Next, in a lamination step, at least one dielectric layer 3 and at least one conductive layer 4, 5 are alternately deposited on at least the first main surface 1a of the substrate 1 and the inner surface of the groove 2 to form laminated films 3 to 5. Specifically, five dielectric layers 3 and five conductive layers 4, 5 are alternately deposited on the first main surface 1a and second main surface 1b of the substrate 1 and the inner surface of the groove 2.

[0028] 3, a dielectric layer 3 is deposited on the first and second main surfaces 1a and 1b of the substrate 1 and the inner surface (side surface 21c) of the groove 2. When the dielectric layer 3 is a silicon oxide film, a thermal CVD method can be used as a method for depositing the silicon oxide film. When using the thermal CVD method, a reduced pressure condition is used, so that the silicon oxide film can be deposited with good coverage even when the groove 2 is deep and has a complex shape.

[0029] Next, as shown in FIG. 4, a conductive layer 4 is deposited on the first and second main surfaces 1a and 1b of the substrate 1 and the inner surface (side surface 21c) of the groove 2 so as to cover the dielectric layer 3. When a polysilicon film is used as the conductive layer 4, a low-pressure CVD method can be used as a method for depositing polysilicon. After the deposition of the polysilicon film, an annealing treatment is performed in POCL3 at 950° C. to form N-type polysilicon, which makes the conductive layer 4 conductive. The high-potential side conductive layer 4 and the low-potential side conductive layer 5 can be formed by the same method. The conductive layer 4 may be P-type polysilicon instead of N-type polysilicon.

[0030] By repeating the process of forming the dielectric layer 3 in FIG. 3 and the process of forming the conductive layers 4 and 5 in FIG. 4 a total of five times, the dielectric layer 3 and the conductive layers 4 and 5 are alternately laminated on the first main surface 1a and second main surface 1b of the substrate 1 and the inner surface (side surface 21c) of the groove 2, as shown in FIG. 5.

[0031] At this time, a first depression 22a and a second depression 22b are formed on the surfaces of the laminated films 3 to 5 due to the corners 21a and 21b of the groove 2. The entire inside of the groove 2 is not filled with the laminated films 3 to 5 consisting of the dielectric layer 3 and the conductive layers 4 and 5. A space 7 is left in a part (central part) of the inside of the groove 2. Both ends of the space 7 are connected to the first depression 22a and the second depression 22b, respectively.

[0032] Next, in a space forming step, the first protective film 6A and the second protective film 6B are embedded in the first recess 22a and the second recess 22b to form the space 7 inside the groove 2 that is connected to the first recess 22a and the second recess 22b. That is, the first protective film 6A and the second protective film 6B are used to block the space 7 left inside the groove 2 from the outside.

[0033] 6, a first protective film 6A and a second protective film 6B made of borosilicate glass (BPSG) containing boron and phosphorus impurities in silicon oxide are deposited by, for example, a CVD method on the stacked films 3 to 5 deposited on the first main surface 1a and the second main surface 1b. At this time, the first protective film 6A and the second protective film 6B are not embedded in the center of the first recess 22a and the second recess 22b, and the space 7 in the trench 2 is not blocked from the outside.

[0034] Next, the deposited first protective film 6A and second protective film 6B are subjected to high-temperature annealing (BPSG reflow) to fluidize and flatten the first protective film 6A and second protective film 6B. As a result, the first protective film 6A and second protective film 6B are embedded in the first recess 22a and the second recess 22b, as shown in Fig. 7. Therefore, a space 7 that is isolated from the outside by the first protective film 6A and the second protective film 6B is formed inside the groove 2 that is connected to the first recess 22a and the second recess 22b.

[0035] Next, as shown in FIG. 8, a mask material 8 such as a photoresist is formed on the first protective film 6A and the second protective film 6B, and the mask material 8 is patterned by photolithography. The patterned mask material 8 has openings in the areas where the contact holes 11a, 11b, 11c, 10a, 10b, and 9 and the element isolation region 12 are to be formed. Next, the first protective film 6A and the second protective film 6B exposed from the openings of the mask material 8 are etched by dry etching using the mask material 8, and further, the dielectric layer 3 and the conductive layers 4 and 5 are etched to the desired depth shown in FIG. 8. As a result, the contact holes 11a, 11b, 11c, 10a, 10b, and 9 and the element isolation region 12 are formed. Thereafter, the mask material 8 is removed by oxygen plasma, sulfuric acid, or the like.

[0036] 9, third protective films 13A and 13B are deposited on the first protective film 6A and the second protective film 6B and on the side and bottom surfaces of the contact holes 11a, 11b, 11c, 10a, 10b, 9 and the element isolation region 12.

[0037] 10, the third protective film 13A on the bottom surfaces of the contact holes 11a, 11b, 11c, 10a, 10b, and 9 is etched using a mask material 14 such as a patterned photoresist to form through holes 15. The corresponding substrate 1 or conductive layers 4 and 5 are exposed at the bottom surface of each through hole 15. The third protective film 13A is left on the side surfaces of each contact hole 11a, 11b, 11c, 10a, 10b, and 9. The mask material 14 is then removed.

[0038] 11, a surface electrode 16 is deposited on the third protective film 13A on the first main surface 1a side of the substrate 1. The surface electrode 16 is embedded in the contact holes 11a, 11b, 11c, 10a, 10b, 9, the element isolation region 12, and the through hole 15. The surface electrode 16 is electrically connected to the corresponding substrate 1 or conductive layers 4 and 5. When the surface electrode 16 is a metal film such as titanium (Ti), nickel (Ni), or molybdenum (Mo), the metal film can be formed by sputtering, electron beam (EB) evaporation, or atomic layer deposition (ALD).

[0039] Finally, the surface electrode 16 is etched using a patterned mask material (not shown), thereby forming the high potential electrode 18 and the low potential electrode 17 as shown in Fig. 1. Through the above steps, the capacitor 100 shown in Fig. 1 can be manufactured.

[0040] As shown in Fig. 7, wet etching may be performed in a process after the space 7 isolated from the outside by the first protective film 6A and the second protective film 6B is formed. For example, a photolithography process using a liquid resist is possible in the manufacturing process after the space 7 is formed inside the groove 2. A liquid resist can be used as the mask material 8 in Fig. 8 and the mask material 14 in Fig. 10. Since the space 7 inside the groove 2 is isolated from the outside, the liquid resist can be prevented from entering the space 7.

[0041] As described above, according to the first embodiment, the following advantageous effects can be obtained.

[0042] The inventors calculated the stress applied to the substrate 1 of the capacitor 100 of FIG. 1. In order to simplify the calculation, as shown in FIG. 12A and FIG. 12B, a silicon oxide film (dielectric layer 3) was arranged on the first main surface 1a, the second main surface 1b, and inside the groove 2 of the silicon substrate (substrate 1) instead of the laminated films 3 to 5. FIG. 12B shows a configuration example of a capacitor corresponding to the first embodiment in which a space 7 is formed inside the groove 2, and FIG. 12A shows a configuration example of a capacitor corresponding to a comparative example in which a space 7 is not formed inside the groove 2. FIG. 12C is a plan view of the substrate 1 excluding the silicon oxide film, in which a total of six grooves 2 are formed in a matrix, two vertically and three horizontally. FIG. 12A and FIG. 12B are cross-sectional views taken along the AA cut surface of FIG. 12C. The planar shape (FIG. 12C) of the capacitor corresponding to the first embodiment and the capacitor according to the comparative example is the same. The inventors calculated the stress applied to the substrate 1 for the capacitor shown in FIG. 12A and FIG. 12B.

[0043] For the capacitor without the space 7 in FIG. 12A, the corner P2 of the groove 2 is 9.45×10 8 A stress of 2×10 Pa is applied to the area P1 between the grooves 2 in the longitudinal direction of the grooves 2. 8 On the other hand, in the capacitor having the space 7 in FIG. 12B, a stress of 1.67×10 8 A stress of 1.4 × 10 Pa is applied to the area P1 between the grooves 2 in the longitudinal direction of the grooves 2. 8 A stress of Pa is applied. In this manner, it was found from the calculation results that the stress applied to the substrate 1 is reduced by providing the space 7.

[0044] The first protective film 6A and the second protective film 6B deposited on the laminated films 3 to 5 are embedded in the first depressions 22a and the second depressions 22b formed on the surfaces of the laminated films 3 to 5 due to the corners 21a and 21b of the groove 2, but are not embedded into the inside of the groove 2. A space 7 is formed inside the groove 2. Therefore, the space 7 inside the groove 2 blocks the transmission of stress caused by the first protective film 6A, the second protective film 6B, and the dielectric layer 3, and can relieve the stress caused by the first protective film 6A, the second protective film 6B, and the dielectric layer 3. In the manufacturing process after the space 7 is formed inside the groove 2, a photolithography process using a liquid resist is possible.

[0045] If space 7 is connected to the outside, there is a high possibility that defects such as corrosion of conductive layers 4 and 5 adjacent to space 7 will occur due to the influence of the external environment. By isolating space 7 from the outside, the occurrence of such defects can be suppressed. It becomes possible to introduce wet processing into the manufacturing process of capacitor 100 after forming first protective film 6A and second protective film 6B.

[0046] The laminated films 3 to 5 each have two or more dielectric layers 3 and two or more conductive layers 4, 5 that are alternately laminated together, thereby enabling the capacitance density of the capacitor 100 to be increased.

[0047] The groove 2 penetrates to the second main surface 1b of the substrate 1, and the laminated films 3 to 5 are deposited on the first main surface 1a, the second main surface 1b and the inner surface (side surface 21c) of the groove 2. This makes it possible to increase the area of ​​the side surface 21c of the groove 2, and to increase the capacitance density of the capacitor 100.

[0048] The surface of the first protective film 6A has been subjected to a planarization treatment. If an electrode is formed on the surface of the first protective film 6A that has not been planarized, the unevenness that appears on the surface of the electrode will become large, causing defects such as disconnection and increased resistance. If the surface of the first protective film 6A has been planarized, it is possible to suppress electric field concentration due to the unevenness of the electrode formed on the first protective film 6A.

[0049] The first protective film 6A and the second protective film 6B are films containing silicon and oxygen, which allows the capacitor 100 to have a structure with a high dielectric breakdown field.

[0050] The first protective film 6A and the second protective film 6B are doped with phosphorus (P) and boron (B). The viscosity of the first protective film 6A and the second protective film 6B containing silicon and oxygen can be reduced. Therefore, the first recess 22a and the second recess 22b can be completely filled with the first protective film 6A and the second protective film 6B. That is, the inside of the trench 2 can be sealed while a space 7 is formed inside the trench 2. This suppresses the occurrence of defects and allows wet processing to be introduced into the manufacturing process.

[0051] The substrate 1 is a conductive substrate to which a high concentration of impurities is added. The substrate 1 itself can be used as an electrode of the capacitor 100.

[0052] The substrate 1 may be an insulating substrate, which makes it easy to separate the capacitor 100 from other elements formed on the substrate 1.

[0053] The (111) plane along the cleavage plane of the substrate 1 is exposed on the side surface 21c of the groove 2. This makes it possible to increase the strength of the groove 2.

[0054] The manufacturing method of the capacitor 100 includes a space forming step. In the space forming step, the first protective film 6A and the second protective film 6B are embedded in the first recess 22a and the second recess 22b, and a space 7 is formed inside the groove 2 that is connected to the first recess 22a and the second recess 22b. The space 7 inside the groove 2 blocks the transmission of stress caused by the first protective film 6A, the second protective film 6B, and the dielectric layer 3, and can relieve the stress caused by the first protective film 6A, the second protective film 6B, and the dielectric layer 3. In the manufacturing process after the space 7 is formed inside the groove 2, a photolithography process using a liquid resist is possible.

[0055] In the space forming step, the first protective film 6A and the second protective film 6B made of glass containing impurities of boron and phosphorus are deposited on the laminated films 3 to 5, and the deposited first protective film 6A and the second protective film 6B are heat-treated to fill the first recess 22a and the second recess 22b with the first protective film 6A and the second protective film 6B. The first protective film 6A and the second protective film 6B are filled in the first recess 22a and the second recess 22b by BPSG reflow, which heat-treats the glass containing impurities of boron and phosphorus, and the space 7 can be formed inside the groove 2 connected to the first recess 22a and the second recess 22b. At the same time, the surfaces of the first protective film 6A and the second protective film 6B can be flattened.

[0056] Second embodiment A capacitor 101 according to the second embodiment will be described with reference to Fig. 13. As shown in Fig. 13, groove 2A formed in first main surface 1a of substrate 1 does not penetrate through substrate 1 to second main surface 1b. In other words, groove 2A has a bottom 21d inside substrate 1.

[0057] 1, capacitor 101 in Fig. 13 differs in that laminated films 3 to 5, second protective film 6B, and third protective film 13B are not disposed on the second main surface 1b side of substrate 1. In addition, in capacitor 101 in Fig. 13, laminated films 3 to 5 are deposited on first main surface 1a of substrate 1, and side surface 21c and bottom 21d of groove 2.

[0058] On the other hand, the configuration inside groove 2 and on the first main surface 1a side of substrate 1 of capacitor 101 in FIG. 13 is the same as that of capacitor 100 in FIG.

[0059] The laminated films 3 to 5 are deposited on the first main surface 1a of the substrate 1 and the inner surface of the groove. The entire inside of the groove 2 is not filled up with the laminated films 3 to 5. A space 7A is formed in a part (center) of the inside of the groove. On the first main surface 1a side of the substrate 1, a first recess 22a is formed on the surface of the laminated films (3 to 5) due to the corner 21a of the groove 2. The first protective film 6A is embedded in the first recess 22a. A space 7A is formed inside the groove 2 connected to the first recess 22a. The space 7A is blocked from the outside by the first protective film 6A. The surface of the first protective film 6A is subjected to a planarization process. The third protective film 13A and the surface electrodes 17 and 18 are also the same as those in FIG. 1, and a description thereof will be omitted. In addition, the manufacturing method of the capacitor 101 is also similar to the manufacturing method described in FIG. 2 to FIG. 11 in many parts, and a description thereof will be omitted.

[0060] According to the capacitor 101 of the second embodiment and the manufacturing method thereof, the groove 2 does not penetrate the substrate 1 but has a bottom 21d inside the substrate 1, thereby increasing the rigidity of the substrate 1 compared to when the groove 2 penetrates to the second main surface 1b of the substrate 1.

[0061] As described above, the embodiment of the present invention has been described, but the description and drawings forming a part of this disclosure should not be understood as limiting this invention. From this disclosure, various alternative embodiments, examples and operating techniques will become apparent to those skilled in the art.

[0062] The grooves 2 can be formed with a high aspect ratio by using dry etching as a method for forming the grooves 2. Wet etching may also be used as a method for forming the grooves 2. This allows the grooves 2 to be formed at low cost. [Explanation of symbols]

[0063] 1 Board 1a First main surface 1b Second main surface 2, 2A groove 3 Dielectric layer (laminated film) 4, 5 Conductive layer (laminated film) 6A 1st protective film 6B 2nd protective film 7, 7A space 13A, 13B Third protective film 21a, 21b corner 21c side 22a First recess 22b 2nd recess

Claims

1. A substrate having a first main surface and a second main surface opposed to each other and a groove formed in the first main surface; a laminated film having at least one dielectric layer and at least one conductive layer alternately laminated on at least the first main surface and the inner surface of the groove; a first protective film deposited on the stacked film deposited on the first main surface; the first protective film is embedded in a first depression formed in a surface of the laminated film due to a corner of the groove, A space is formed inside the groove connected to the first recess. Capacitor.

2. 2. The capacitor according to claim 1, wherein the space is isolated from the outside.

3. 2. The capacitor according to claim 1, wherein the laminated film comprises two or more layers of the dielectric layers and two or more layers of the conductive layers, which are alternately laminated.

4. The groove penetrates to the second main surface, the laminated film is deposited on the first main surface, the second main surface, and an inner surface of the groove; the capacitor further comprises a second protective film deposited on the stacked film deposited on the second main surface; the second protective film is embedded in a second recess formed in a surface of the stacked film deposited on the second main surface due to a corner of the groove; The space is formed inside the groove that is connected to the second recess. The capacitor of claim 1.

5. 2. The capacitor according to claim 1, wherein the surface of the first protective film is subjected to a planarization treatment.

6. 2. The capacitor according to claim 1, wherein the first protective film is a film containing silicon and oxygen.

7. 7. The capacitor according to claim 6, wherein the first protective film is doped with phosphorus and boron.

8. 2. The capacitor of claim 1, wherein the substrate is a conductive substrate.

9. 2. The capacitor of claim 1, wherein the substrate is a conductive substrate.

10. 2. A capacitor according to claim 1, wherein a (111) plane along a cleavage plane of said substrate is exposed on a side surface of said groove.

11. a groove forming step of forming a groove on a first main surface of a substrate having a first main surface and a second main surface opposed to each other; a lamination step of forming a laminate film by alternately depositing at least one dielectric layer and at least one conductive layer on at least the first main surface and the inner surface of the groove; a space forming step of filling a first protective film into a first depression formed in a surface of the laminated film due to a corner of the groove, to form a space inside the groove connected to the first depression; A method for manufacturing a capacitor having the above structure.

12. The space forming step includes: depositing the first protective film on the stacked film deposited on the first main surface; by subjecting the deposited first protective film to a heat treatment, the first protective film is embedded in the first recess, and a space is formed inside the groove that is connected to the first recess. The method for producing a capacitor according to claim 11, comprising:

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