Transistor and method for manufacturing transistor

Abstract

To improve yield.SOLUTION: A transistor 15 includes: a semiconductor portion 15D extending along a first direction; a first electrode 15A overlapping a part of the semiconductor portion 15D; a first insulating film 33 interposed between the first electrode 15A and the semiconductor portion 15D; and a second electrode 15B and a third electrode 15C connected to the semiconductor portion 15D. A gate insulating film 33 includes: a first thickness portion 33A and a second thickness portion 33B having the same thickness; a third thickness portion 33C, a fourth thickness portion 33D, and a fifth thickness portion 33E each having a thickness larger than that of the first thickness portion 33A. The first thickness portion 33A and the second thickness portion 33B overlap both the first electrode 15A and the semiconductor portion 15D and are arranged at positions spaced apart from each other in the first direction, the third thickness portion 33C is sandwiched between the first thickness portion 33A and the second thickness portion 33B, and the fourth thickness portion 33D and the fifth thickness portion 33E are arranged to overlap both end portions 15A1, 15A2 of the first electrode 15A and the semiconductor portion 15D.SELECTED DRAWING: Figure 6

Description

[Technical field]

[0001] The technology disclosed in this specification relates to a transistor and a method for manufacturing a transistor. [Background technology]

[0002] Conventionally, one example of a known transistor is that described in Patent Document 1 below. Patent Document 1 discloses a transistor with a single-gate structure and a transistor with a multi-gate structure in which two or more transistors are connected in series. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2010-266490 A Summary of the Invention [Problem to be solved by the invention]

[0004] In the single-gate transistor described in Patent Document 1, when a high voltage is applied, hot carrier injection is likely to occur, which may cause the transistor performance to deteriorate over time. In addition, ESD (Electro-Static Discharge) is likely to occur between the edge of the gate metal and the channel material, which may cause damage to the edge of the gate metal and the channel material due to ESD, resulting in a deterioration in yield.

[0005] In the multi-gate transistor described in the above-mentioned Patent Document 1, hot carrier injection is unlikely to occur even when a high voltage is applied. However, compared to the single-gate structure, the number of gate metal ends is greater, so ESD is more likely to occur between the gate metal ends and the channel material. As a result, there is a risk that ESD will cause damage to the gate metal ends and the channel material, resulting in a decrease in yield.

[0006] The technology described in this specification was developed based on the above circumstances, and aims to improve the yield. [Means for solving the problem]

[0007] (1) A transistor according to the technology described in this specification includes a semiconductor portion extending along a first direction and made of a semiconductor material, a first electrode arranged to overlap a portion of the semiconductor portion, a first insulating film interposed between the first electrode and the semiconductor portion, a second electrode arranged to overlap the portion of the semiconductor portion and connected to the semiconductor portion, and a third electrode arranged to overlap the portion of the semiconductor portion at a position spaced apart in the first direction from a connection position between the second electrode and the semiconductor portion and connected to the semiconductor portion, the first insulating film including a first thickness portion, a second thickness portion having the same thickness as the first thickness portion, a third thickness portion having a thickness larger than the first thickness portion, and a fourth thickness portion having a thickness larger than the first thickness portion. the first thickness portion is disposed at a position overlapping with both the first electrode and the semiconductor portion, the second thickness portion is disposed at a position spaced apart from the first thickness portion in the first direction, the third thickness portion is disposed at a position overlapping with both the first electrode and the semiconductor portion and is sandwiched between the first thickness portion and the second thickness portion in the first direction, the fourth thickness portion is disposed so as to overlap with both one end of the first electrode in the first direction and the semiconductor portion, and the fifth thickness portion is disposed so as to overlap with the other end of the first electrode in the first direction and the semiconductor portion.

[0008] (2) In addition to the above (1), the first insulating film of the transistor may have a laminated structure including a lower insulating film arranged on the upper side of the semiconductor portion, and an upper insulating film arranged on the upper side of the lower insulating film and made of a different material than the lower insulating film.

[0009] (3) In addition to the above (1), the transistor may be configured such that the first insulating film has a single-layer structure.

[0010] (4) In addition to any one of (1) to (3), the third thickness portion, the fourth thickness portion, and the fifth thickness portion may have the same thickness.

[0011] (5) In addition to any one of (1) to (4), the transistor may be configured such that the first thickness portion and the second thickness portion have the same dimension in the first direction.

[0012] (6) In addition to any one of (1) to (4) above, the transistor may be configured such that the second electrode is connected to a signal supply source and a signal is supplied from the signal supply source, while the third electrode is connected to a signal supply target and is capable of supplying the signal to the signal supply target, the first thickness portion is positioned closer to the second electrode in the first direction than the third thickness portion, the second thickness portion is positioned closer to the third electrode in the first direction than the third thickness portion, and has a larger dimension in the first direction than the first thickness portion.

[0013] (7) In addition to any one of (1) to (6) above, the transistor may be configured such that the semiconductor portion uses a polysilicon semiconductor material as the semiconductor material.

[0014] (8) In addition to any one of (1) to (6), the transistor may be configured such that an oxide semiconductor material is used as the semiconductor material of the semiconductor portion.

[0015] (9) A transistor according to the technology described in this specification includes a semiconductor portion extending along a first direction and made of a semiconductor material, a first electrode arranged to overlap a portion of the semiconductor portion, a fourth electrode arranged to overlap a portion of the semiconductor portion and spaced apart in the first direction from the first electrode, a first insulating film interposed between the first electrode and the semiconductor portion, a second electrode arranged to overlap a portion of the semiconductor portion and connected to the semiconductor portion, and a third electrode arranged to overlap a portion of the semiconductor portion at a position spaced apart in the first direction from a connection position between the second electrode and the semiconductor portion and connected to the semiconductor portion, the first insulating film including a first thickness portion, a second thickness portion having the same thickness as the first thickness portion, a third thickness portion having a thickness larger than the first thickness portion, a fourth thickness portion having a thickness larger than the first thickness portion, and a fourth thickness portion having a thickness smaller than the first thickness portion. the first thickness portion is disposed at a position overlapping with both the first electrode and the semiconductor portion, the second thickness portion is disposed at a position overlapping with both the fourth electrode and the semiconductor portion, the third thickness portion is disposed sandwiched between the first thickness portion and the second thickness portion in the first direction, the fourth thickness portion overlaps with both one end of the first electrode in the first direction and the semiconductor portion and is disposed with the first thickness portion sandwiched between the third thickness portion, the fifth thickness portion overlaps with both one end of the fourth electrode in the first direction and the semiconductor portion and is disposed with the second thickness portion sandwiched between the third thickness portion, and the third thickness portion overlaps with both the other end of the first electrode in the first direction and the semiconductor portion, and is disposed with the other end of the fourth electrode in the first direction and the semiconductor portion.

[0016] (10) A method for manufacturing a transistor according to the technology described in this specification includes forming a semiconductor film made of a semiconductor material, patterning the semiconductor film to provide a semiconductor portion extending along a first direction, forming a first insulating film on an upper layer side of the semiconductor portion, forming a first resist film made of a photosensitive material on an upper layer side of the first insulating film, exposing and developing the first resist film, and etching the first insulating film using the first resist film as a mask, thereby forming a first thickness portion overlapping the semiconductor portion, a second thickness portion overlapping the semiconductor portion and disposed at a position spaced apart from the first thickness portion in the first direction and having the same thickness as the first thickness portion, a third thickness portion disposed at a position overlapping the semiconductor portion so as to be sandwiched between the first thickness portion and the second thickness portion in the first direction and having a thickness larger than that of the first thickness portion, a fourth thickness portion overlapping the semiconductor portion and disposed with the first thickness portion sandwiched between the third thickness portion in the first direction and having a thickness larger than that of the first thickness portion, and a fourth thickness portion overlapping the semiconductor portion and disposed with the first thickness portion sandwiched between the third thickness portion and the first thickness portion in the first direction, a fifth thickness portion disposed between the second thickness portion and the third thickness portion in the first direction and having a thickness greater than that of the first thickness portion; a first conductive film is formed on an upper layer side of the first insulating film; a second resist film made of a photosensitive material is formed on an upper layer side of the first conductive film; the second resist film is exposed to light and developed; and the first conductive film is etched using the second resist film as a mask, so that one end in the first direction overlaps with the fourth thickness portion and the other end in the first direction overlaps with the fifth thickness portion. a first electrode having a portion between both ends in the first direction overlapping the first thickness portion, the second thickness portion, and the third thickness portion; a second conductive film is formed above the first electrode; and the second conductive film is patterned to provide a second electrode that is arranged to overlap a portion of the semiconductor portion and is connected to the semiconductor portion, and a third electrode that is arranged to overlap a portion of the semiconductor portion at a position spaced apart in the first direction from a connection position between the second electrode and the semiconductor portion and is connected to the semiconductor portion.

[0017] (11) In addition to the above (10), the method for manufacturing the transistor may include forming the first resist film made of a positive photosensitive material on an upper side of the first insulating film, exposing the first resist film through a first photomask having a first light-shielding region that is arranged to overlap with areas where the fourth thickness portion and the fifth thickness portion are to be formed and blocks light, a first transparent region that is arranged to overlap with areas where the first thickness portion and the second thickness portion are to be formed and transmits light, and a semi-transparent region that is arranged to overlap with the area where the third thickness portion is to be formed and is sandwiched between two of the first transparent regions in the first direction and has a higher light transmittance than the first light-shielding region and a lower light transmittance than the first transparent region, and forming the second resist film made of a negative photosensitive material on an upper side of the first conductive film, exposing the second resist film through the first photomask and developing it.

[0018] (12) A method for manufacturing a transistor according to the technology described in this specification includes forming a semiconductor film made of a semiconductor material, patterning the semiconductor film to provide a semiconductor portion extending along a first direction, forming a first insulating film on an upper layer side of the semiconductor portion, forming a first resist film made of a photosensitive material on an upper layer side of the first insulating film, exposing and developing the first resist film, and etching the first insulating film using the first resist film as a mask, thereby forming a first thickness portion arranged to overlap the semiconductor portion, and a second thickness portion arranged to overlap the semiconductor portion and patterned in the first direction with respect to the first thickness portion. a second thickness portion disposed at a position spaced apart from the semiconductor portion and having the same thickness as the first thickness portion; a third thickness portion disposed so as to be sandwiched between the first thickness portion and the second thickness portion in the first direction at a position overlapping the semiconductor portion and having a thickness greater than that of the first thickness portion; a fourth thickness portion disposed so as to sandwich the first thickness portion between the semiconductor portion and the third thickness portion in the first direction and having a thickness greater than that of the first thickness portion; a fifth thickness portion having a thickness greater than the first thickness portion, forming a first conductive film on an upper side of the first insulating film, forming a second resist film made of a photosensitive material on an upper side of the first conductive film, exposing and developing the second resist film, and etching the first conductive film using the second resist film as a mask, thereby forming a first electrode having one end in the first direction overlapping with the fourth thickness portion, the other end in the first direction overlapping with the third thickness portion, and a portion between both end portions in the first direction overlapping with the first thickness portion, a fourth electrode that overlaps with a fifth thickness portion, has the other end in the first direction overlapping with the third thickness portion, and a portion between both ends in the first direction overlapping with the second thickness portion; and by forming a second conductive film above the first electrode and patterning the second conductive film, a second electrode that is arranged to overlap with a portion of the semiconductor portion and connected to the semiconductor portion, and a third electrode that is arranged to overlap with a portion of the semiconductor portion at a position spaced apart in the first direction from a connection position between the second electrode and the semiconductor portion, and connected to the semiconductor portion.

[0019] (13) In addition to the above (12), the method for manufacturing the transistor may further include forming the first resist film made of a positive photosensitive material on an upper side of the first insulating film, exposing the first resist film through a second photomask having a second light-shielding region arranged to overlap with planned areas for forming the third thickness portion, the fourth thickness portion, and the fifth thickness portion and blocking light, and a second light-transmitting region overlapping with planned areas for forming the first thickness portion and the second thickness portion and transmitting light, and forming the second resist film made of a negative photosensitive material on an upper side of the first conductive film, exposing the second resist film through the second photomask, and developing the first resist film. Effect of the Invention

[0020] The techniques described herein can improve yields. [Brief description of the drawings]

[0021] [Figure 1] 1 is a plan view of a liquid crystal panel, a driver, a flexible substrate, and the like that constitute a liquid crystal display device according to a first embodiment; [Diagram 2] 1 is a cross-sectional view of a liquid crystal panel, a driver, a flexible substrate, and the like according to the first embodiment; [Diagram 3] FIG. 1 is a circuit diagram showing an electrical configuration of an array substrate that constitutes a liquid crystal panel according to a first embodiment. [Figure 4] 1 is a cross-sectional view of a first TFT and a second TFT provided on an array substrate according to a first embodiment; [Diagram 5] FIG. 2 is a plan view of a first TFT according to the first embodiment; [Figure 6] 6 is a cross-sectional view of the first TFT according to the first embodiment taken along line vi-vi in ​​FIG. [Figure 7] 6 is a cross-sectional view of the first TFT according to the first embodiment taken along line vii-vii in FIG. [Figure 8] FIG. 7 is a cross-sectional view similar to FIG. 6, illustrating a state in which a lower-layer insulating film, an upper-layer insulating film, and a first resist film are formed in a fourth step included in the array substrate manufacturing process according to the first embodiment. [Figure 9] FIG. 7 is a cross-sectional view similar to FIG. 6, illustrating a state in which a first resist film is exposed through a first photomask in a fourth step included in the array substrate manufacturing process according to the first embodiment; [Figure 10] FIG. 7 is a cross-sectional view similar to FIG. 6, illustrating a state in which the first resist film is developed in a fourth step included in the array substrate manufacturing process according to the first embodiment. [Figure 11] FIG. 7 is a cross-sectional view similar to FIG. 6, illustrating a state in which the upper insulating film is etched through the first resist film in a fourth step included in the array substrate manufacturing process according to the first embodiment. [Figure 12] FIG. 7 is a cross-sectional view similar to FIG. 6, illustrating a state in which the first resist film has been removed in a fourth step included in the array substrate manufacturing process according to the first embodiment. [Figure 13] FIG. 7 is a cross-sectional view similar to FIG. 6, illustrating a state in which a second metal film and a second resist film are formed in a fifth step included in the array substrate manufacturing process according to the first embodiment. [Figure 14] FIG. 7 is a cross-sectional view similar to FIG. 6, illustrating a state in which the second resist film is exposed through a first photomask in a fifth step included in the array substrate manufacturing process according to the first embodiment; [Figure 15] FIG. 7 is a cross-sectional view similar to FIG. 6, illustrating a state in which the second resist film is developed in a fifth step included in the array substrate manufacturing process according to the first embodiment. [Figure 16] FIG. 7 is a cross-sectional view similar to FIG. 6, illustrating a state in which the second metal film is etched through the second resist film in a fifth step included in the array substrate manufacturing process according to the first embodiment; [Figure 17] FIG. 7 is a cross-sectional view similar to FIG. 6 of a first TFT according to a second embodiment. [Figure 18] FIG. 7 is a cross-sectional view similar to FIG. 6 of a first TFT according to a third embodiment. [Figure 19] 11 is a cross-sectional view of a first TFT and a second TFT provided on an array substrate according to a fourth embodiment. [Figure 20] FIG. 11 is a plan view of a first TFT according to a fourth embodiment; [Figure 21] 20 in a cross-sectional view of the first TFT according to embodiment 4. [Figure 22]22 is a cross-sectional view of the first TFT according to the fourth embodiment taken along line xxii-xxii in FIG. [Figure 23] FIG. 22 is a cross-sectional view similar to FIG. 21 , illustrating a state in which a lower-layer insulating film, an upper-layer insulating film, and a first resist film are formed in a fourth step included in the array substrate manufacturing process according to the fourth embodiment. [Figure 24] FIG. 22 is a cross-sectional view similar to FIG. 21 , illustrating a state in which the first resist film is exposed through a second photomask in a fourth step included in the array substrate manufacturing process according to the fourth embodiment; [Diagram 25] FIG. 22 is a cross-sectional view similar to FIG. 21 , illustrating a state in which the first resist film is developed in a fourth step included in the array substrate manufacturing process according to the fourth embodiment. [Figure 26] FIG. 22 is a cross-sectional view similar to FIG. 21 , illustrating a state in which the upper insulating film is etched through the first resist film in a fourth step included in the array substrate manufacturing process according to the fourth embodiment. [Figure 27] FIG. 22 is a cross-sectional view similar to FIG. 21 , illustrating a state in which the first resist film has been removed in a fourth step included in the array substrate manufacturing process according to the fourth embodiment. [Figure 28] FIG. 22 is a cross-sectional view similar to FIG. 21 , illustrating a state in which a second metal film and a second resist film are formed in a fifth step included in the array substrate manufacturing process according to the fourth embodiment. [Figure 29] FIG. 22 is a cross-sectional view similar to FIG. 21 , illustrating a state in which a second resist film is exposed through a second photomask in a fifth step included in the array substrate manufacturing process according to the fourth embodiment; [Diagram 30] FIG. 22 is a cross-sectional view similar to FIG. 21 , illustrating a state in which the second resist film is developed in a fifth step included in the array substrate manufacturing process according to the fourth embodiment. [Diagram 31] FIG. 22 is a cross-sectional view similar to FIG. 21 , illustrating a state in which the second metal film is etched through the second resist film in a fifth step included in the array substrate manufacturing process according to the fourth embodiment; [Diagram 32] FIG. 7 is a cross-sectional view similar to FIG. 6 of a first TFT according to a fifth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0022] <Embodiment 1> The first embodiment will be described with reference to Fig. 1 to Fig. 17. In this embodiment, a liquid crystal display device 10 having a display function and a touch panel function (position input function) is illustrated. Note that the X-axis, Y-axis, and Z-axis are shown in a part of each drawing, and each axis direction is drawn to be the direction shown in each drawing. Also, the upper side of Fig. 2, Fig. 4, Fig. 6 to Fig. 17 is the front side, and the lower side of the drawings is the back side.

[0023] 1, a liquid crystal display device 10 includes at least a horizontally elongated rectangular liquid crystal panel (display device, display panel) 11 capable of displaying images, and a backlight device (illumination device) which is an external light source that irradiates the liquid crystal panel 11 with light to be used for display. The backlight device is disposed on the rear side (back side) of the liquid crystal panel 11, and includes a light source (e.g., an LED) that emits white light and an optical member that converts the light from the light source into planar light by applying an optical effect. The central portion of the screen of the liquid crystal panel 11 is a display area AA where an image is displayed. In contrast, a frame-shaped outer peripheral portion surrounding the display area AA on the screen of the liquid crystal panel 11 is a non-display area NAA where no image is displayed.

[0024] As shown in FIG. 1, a circuit section (peripheral circuit section) 14 is provided in the non-display area NAA of the liquid crystal panel 11. A pair of the circuit sections 14 are arranged to sandwich the display area AA from both sides in the X-axis direction. The circuit section 14 is provided in a strip-shaped range extending along the Y-axis direction. The circuit section 14 is for supplying scanning signals to gate wiring 26 described later, and is monolithically provided on an array substrate 21 described later. The circuit section 14 is a GDM (Gate Driver Monolithic) circuit. The circuit section 14 includes a shift register circuit that outputs scanning signals at a predetermined timing, a buffer circuit that amplifies the scanning signals, and the like. The circuit section 14 includes various circuit elements, including at least a first TFT (transistor) 15. A detailed configuration of the first TFT 15 will be described later.

[0025] The liquid crystal panel 11 will be described in detail with reference to FIG. 1 and FIG. 2. As shown in FIG. 1 and FIG. 2, the liquid crystal panel 11 is formed by bonding a pair of substrates 20, 21. The front side (front side) of the pair of substrates 20, 21 is the counter substrate (CF substrate, second substrate) 20, and the back side (rear side) is the array substrate (first substrate) 21. The counter substrate 20 and the array substrate 21 are both formed by laminating various films on the inner side of glass substrates 20GS, 21GS. A liquid crystal layer (medium layer) 22 containing liquid crystal molecules, which are a substance whose optical properties change with the application of an electric field, is disposed between the pair of substrates 20, 21. A seal portion 23 that seals the liquid crystal layer 22 is disposed between the outer peripheral ends of the pair of substrates 20, 21. The seal portion 23 is formed in a rectangular frame shape (endless ring shape) so as to surround the liquid crystal layer 22. A polarizing plate 16 is attached to the outer surface of each of the substrates 20 and 21.

[0026] 1 and 2, the short side dimension of the counter substrate 20 is shorter than the short side dimension of the array substrate 21. The counter substrate 20 is attached to the array substrate 21 in such a manner that one end in the short side direction (Y-axis direction) is aligned with the array substrate 21. Therefore, the other end in the short side direction of the array substrate 21 is an exposed portion 21A that protrudes laterally and is exposed relative to the counter substrate 20. The entire exposed portion 21A is a non-display area NAA, and is equipped with a driver (mounted component, signal supply unit) 12 and a flexible substrate 13 for supplying various signals related to the display function and touch panel function described below.

[0027] The driver 12 shown in FIG. 1 and FIG. 2 is composed of an LSI chip having a driving circuit therein. The driver 12 is mounted on the exposed portion 21A of the array substrate 21 by COG (Chip On Glass). The driver 12 processes various signals transmitted by the flexible substrate 13. The driver 12 supplies various signals (e.g., image signals, touch signals, etc.) to wiring in the display area AA (specifically, source wiring 27 and touch wiring 30 described later). The flexible substrate 13 is configured by forming a number of wiring patterns on a base material made of a synthetic resin material (e.g., polyimide resin, etc.) having insulating properties and flexibility. As shown in FIG. 1 and FIG. 2, one end of the flexible substrate 13 is connected to the exposed portion 21A of the array substrate 21, and the other end is connected to an external circuit substrate (e.g., a control substrate). The flexible substrate 13 is connected to an end of the exposed portion 21A on the opposite side to the display area AA side in the Y-axis direction with respect to the driver 12.

[0028] The liquid crystal panel 11 according to this embodiment has both a display function for displaying an image and a touch panel function for detecting a position (input position) input by a user based on the displayed image. A touch panel pattern for exerting the touch panel function is integrated (in-cell) in the liquid crystal panel 11. This touch panel pattern is a so-called projected capacitive type, and its detection method is a self-capacitive type. As shown in FIG. 1, the touch panel pattern is composed of a plurality of touch electrodes (position detection electrodes) 29 arranged in a matrix on the plate surface of the liquid crystal panel 11. The touch electrodes 29 are arranged in a display area AA of the liquid crystal panel 11. Therefore, the display area AA of the liquid crystal panel 11 is approximately coincident with a touch area (position input area) where an input position can be detected, and the non-display area NAA is approximately coincident with a non-touch area (non-position input area) where an input position cannot be detected. When a user approaches a conductive finger (position input object) to the surface (display surface) of the liquid crystal panel 11 to input a position based on an image of the display area AA of the liquid crystal panel 11 that the user is viewing, a capacitance is formed between the finger and the touch electrode 29. As a result, the capacitance detected at the touch electrode 29 near the finger changes as the finger approaches, and becomes different from that of the touch electrode 29 far from the finger, so that it is possible to detect the input position based on the change. Note that the specific number of touch electrodes 29 installed can be changed as appropriate, in addition to the illustration in FIG. 1. The touch electrode 29 has an approximately rectangular shape in a plan view, and the dimension of one side is about several mm. Therefore, the size of the touch electrode 29 in a plan view is much larger than a pixel described later, and is arranged in a range that spans multiple pixels in the X-axis direction and the Y-axis direction.

[0029] Next, the configuration of the display area AA in the array substrate 21 will be described with reference to FIG. 3. At least a second TFT (second transistor) 24 and a pixel electrode 25 are provided on the inner surface side of the display area AA of the array substrate 21, as shown in FIG. 3. The second TFTs 24 and the pixel electrodes 25 are arranged in a matrix shape (row and column shape) with a space between them along the X-axis direction and the Y-axis direction. Around the second TFTs 24 and the pixel electrodes 25, gate wiring (scanning wiring) 26 and source wiring (image wiring, signal wiring) 27 that are orthogonal (intersecting) to each other are arranged. The gate wiring 26 extends along the X-axis direction. The source wiring 27 extends along the Y-axis direction. The second TFT 24 has a second gate electrode 24A connected to the gate wiring 26, a second source electrode 24B connected to the source wiring 27, a second drain electrode 24C connected to the pixel electrode 25, and a second semiconductor portion 24D connected to the second source electrode 24B and the second drain electrode 24C. The second TFT 24 is driven based on a scanning signal supplied to the second gate electrode 24A by the gate wiring 26. Then, a potential related to an image signal (data signal) supplied from the driver 12 to the second source electrode 24B by the source wiring 27 is supplied to the second drain electrode 24C via the second semiconductor portion 24D. As a result, the pixel electrode 25 is charged to a potential related to the image signal. The pixel electrode 25 is disposed in a region surrounded by the gate wiring 26 and the source wiring 27, and has a planar shape of, for example, a substantially rectangular shape.

[0030] As shown in Fig. 3, a common electrode 28 is formed on the inner surface of the display area AA of the array substrate 21 so as to overlap all of the pixel electrodes 25. The common electrode 28 extends over almost the entire display area AA. This common electrode 28 constitutes the touch electrode 29 described above. The common electrode 28 has partition slits that separate adjacent touch electrodes 29. The partition slits divide the common electrode 28 into a grid pattern and the common electrode 28 is made up of a plurality of touch electrodes 29 that are electrically independent from each other.

[0031] As shown in FIG. 3, a plurality of touch wirings (wirings, position detection wirings) 30 connected to a plurality of touch electrodes 29 are provided on the inner surface side of the display area AA of the array substrate 21. The touch wirings 30 extend along the Y-axis direction and are parallel to the source wirings 27. The plurality of touch wirings 30 are individually connected to the plurality of touch electrodes 29. A common signal (reference potential signal) related to the display function and a touch signal (position detection signal) related to the touch function are supplied to the touch wirings 30 from the driver 12 at different timings (time division). The timing when the common signal is supplied from the driver 12 to the touch wirings 30 is the display period, and the timing when the touch signal is supplied from the driver 12 to the touch wirings 30 is the sensing period (position detection period). During the display period, the common signal is supplied to all the touch wirings 30, so that all the touch electrodes 29 become the reference potential and function as the common electrodes 28.

[0032] Next, various films laminated on the glass substrate (substrate) 21GS of the array substrate 21 will be described in detail with reference to Fig. 4. Fig. 4 shows the cross-sectional configuration of the circuit section 14 (first TFT 15) in the non-display area NAA and the cross-sectional configuration of the display area AA (second TFT 24). As shown in Fig. 4, the glass substrate 21GS of the array substrate 21 is laminated with at least a first metal film (light-shielding film), a base coat film 31, a semiconductor film, a gate insulating film (first insulating film) 33, a second metal film (first conductive film) 32 (see Fig. 13), a first interlayer insulating film (second insulating film) 34, a third metal film (second conductive film), a planarizing film 35, a second interlayer insulating film 36, a fourth metal film (third conductive film), a third interlayer insulating film 37, a first transparent electrode film, a fourth interlayer insulating film 38, a second transparent electrode film, and an alignment film in this order from the lower layer side (glass substrate 21GS side).

[0033] The first metal film, the second metal film 32, the third metal film, and the fourth metal film are each a single layer film made of one type of metal material, or a laminated film or alloy made of different types of metal materials, and thus have electrical conductivity and light shielding properties. Specifically, the first metal film is a single layer film made of, for example, Mo (molybdenum), and has a thickness of, for example, about 50 nm. The second metal film 32 is a single layer film made of, for example, Mo (molybdenum), and has a thickness of, for example, about 300 nm. The second metal film 32 is a laminate film made of, for example, Ti (titanium) / Al (aluminum) / Ti from the upper layer side, and has a thickness of, for example, about 50 nm / about 350 nm / about 100 nm. The third metal film is a laminate film made of, for example, Mo / Al / Mo from the upper layer side, and has a thickness of, for example, about 100 nm / about 300 nm / about 30 nm. The semiconductor film is made of a polysilicon semiconductor material (semiconductor material) having a crystalline quality produced by a known method such as laser crystallization, and the polysilicon semiconductor material of the semiconductor film, which has a thickness of, for example, about 50 nm, has a higher electron mobility than amorphous silicon semiconductor material or oxide semiconductor material. The first transparent electrode film and the second transparent electrode film are made of a transparent electrode material such as ITO (Indium Tin Oxide), and each of the film thicknesses is, for example, about 60 nm.

[0034] The base coat film 31, the gate insulating film 33, the first interlayer insulating film 34, the second interlayer insulating film 36, the third interlayer insulating film 37, and the fourth interlayer insulating film 38 are all made of a type of inorganic material (inorganic resin material), such as SiO2 (silicon oxide, silicon oxide) or SiN x Specifically, the base coat film 31 is made of SiO2 / SiN x The first interlayer insulating film 34 is a laminated film made of SiN / SiO2 in that order from the top, and has a thickness of, for example, about 200 nm / 100 nm. The gate insulating film 33 is a laminated film made of SiN / SiO2 in that order from the top, and has a thickness of, for example, about 50 nm / 100 nm. x The second interlayer insulating film 36 is a laminated film made of SiN. xThe third interlayer insulating film 37 is a single layer film of SiN x The fourth interlayer insulating film 38 is a single layer film of SiN x The planarization film 35 is a single layer film having a thickness of, for example, about 200 nm. The planarization film 35 is made of PMMA (acrylic resin), which is a type of organic material (organic resin material), and has a thickness of, for example, about 1 μm to 3 μm. In other words, the planarization film 35 has a thickness larger than those of the other insulating films 31, 33, 34, 36, 37, and 38 made of inorganic materials.

[0035] Next, the cross-sectional configuration of the circuit section 14 will be described in detail. As shown in Fig. 4, the circuit section 14 has a first TFT 15. The first TFT 15 has a first gate electrode (first electrode) 15A, a first source electrode (second electrode) 15B, a first drain electrode (third electrode) 15C, and a first semiconductor section (semiconductor section) 15D. Among these, the first semiconductor section 15D is located at the lowermost layer side with respect to the electrodes 15A to 15C, and is made of a semiconductor film. Therefore, it can be said that the first TFT 15 is a so-called top-gate type transistor.

[0036] 4, the first gate electrode 15A is made of a second metal film 32. The first gate electrode 15A is arranged to overlap the upper layer side of the first semiconductor portion 15D via a gate insulating film 33. The first gate electrode 15A is arranged to overlap a central portion of the first semiconductor portion 15D in the X-axis direction (first direction).

[0037] As shown in FIG. 4, the first source electrode 15B and the first drain electrode 15C are both made of a third metal film. The first source electrode 15B is connected to a signal supply source (e.g., the driver 12, the flexible substrate 13, etc.) so that a signal is supplied from the signal supply source. The first drain electrode 15C is connected to a signal supply target (e.g., the gate wiring 26, etc.) so that a signal (scanning signal) can be supplied to the signal supply target. When a voltage equal to or higher than the threshold voltage of the first TFT 15 is applied to the first gate electrode 215A, a signal supplied from the signal supply source to the first source electrode 15B is transmitted to the first drain electrode 15C through a channel region 215D1 generated in the first semiconductor portion 215D, and is supplied from the first drain electrode 15C to the signal supply target. The first source electrode 15B and the first drain electrode 15C are arranged to overlap a part of each of the first semiconductor portions 15D on the upper layer side via the gate insulating film 33 and the first interlayer insulating film 34. The first source electrode 15B is arranged so as to overlap one end portion (left side in FIG. 4) of the first semiconductor portion 15D in the X-axis direction. The first source electrode 15B and the first semiconductor portion 15D are connected through a first contact hole CH1 formed to open and communicate with the gate insulating film 33 and the first interlayer insulating film 34 interposed therebetween. In other words, the first contact hole CH1 is the connection position between the first source electrode 15B and the first semiconductor portion 15D. The first drain electrode 15C is arranged so as to overlap the other end portion (right side in FIG. 4) of the first semiconductor portion 15D in the X-axis direction. The first drain electrode 15C and the first semiconductor portion 15D are connected through a second contact hole CH2 formed to open and communicate with the gate insulating film 33 and the first interlayer insulating film 34 interposed therebetween. In other words, the second contact hole CH2 is the connection position between the first drain electrode 15C and the first semiconductor portion 15D. The first source electrode 15B and the first drain electrode 15C are spaced apart from each other in the X-axis direction, with the first gate electrode 15A sandwiched between them. The first contact hole CH1 and the second contact hole CH2 are spaced apart from each other in the X-axis direction, with the first gate electrode 15A sandwiched between them.

[0038] Next, the cross-sectional configuration of the display area AA will be described in detail. As shown in Fig. 4, the second TFT 24 is disposed in the display area AA. The second TFT 24 has a second gate electrode 24A, a second source electrode 24B, a second drain electrode 24C, and a second semiconductor portion 24D. Of these, the second semiconductor portion 24D is located at the lowermost layer side with respect to the electrodes 24A to 24C, and is made of a semiconductor film. Therefore, the second TFT 24 can be said to be a top-gate type transistor, similar to the first TFT 15.

[0039] 4, the second gate electrode 24A is composed of a portion of the second metal film 32 that is separate from the first gate electrode 15A. The second gate electrode 24A is arranged to overlap the upper layer side of the second semiconductor portion 24D via the gate insulating film 33. The second gate electrode 24A is arranged to overlap a central portion of the second semiconductor portion 24D in the X-axis direction.

[0040] As shown in FIG. 4, the second source electrode 24B is formed of a portion of the third metal film that is separate from the first source electrode 15B and the first drain electrode 15C. The second drain electrode 24C is formed of a portion of the third metal film that is separate from the first source electrode 15B, the first drain electrode 15C, and the second source electrode 24B. The second source electrode 24B and the second drain electrode 24C are arranged to overlap with each other on the upper layer side of the first semiconductor portion 15D via the gate insulating film 33 and the first interlayer insulating film 34. The second source electrode 24B is arranged to overlap with one end side portion of the second semiconductor portion 24D in the X-axis direction (the left side in FIG. 4). The second source electrode 24B and the second semiconductor portion 24D are connected through a third contact hole CH3 that is opened and formed to communicate with the gate insulating film 33 and the first interlayer insulating film 34 interposed therebetween. The second drain electrode 24C is disposed so as to overlap with the other end portion (right side in FIG. 4) of the second semiconductor portion 24D in the X-axis direction. The second drain electrode 24C and the second semiconductor portion 24D are connected through a fourth contact hole CH4 that is formed and opens through the gate insulating film 33 and the first interlayer insulating film 34 that are interposed therebetween. The second source electrode 24B and the second drain electrode 24C are disposed at positions spaced apart from each other in the X-axis direction, with the second gate electrode 24A sandwiched therebetween.

[0041] As shown in FIG. 4, a pixel electrode 25 and a common electrode 28 (touch electrode 29) are arranged in the display area AA. The pixel electrode 25 is made of a second transparent electrode film. A part of the pixel electrode 25 is arranged to overlap the second drain electrode 24C. The pixel electrode 25 and the second drain electrode 24C are connected through a fifth contact hole CH5 that is opened and formed in the planarization film 35, the second interlayer insulating film 36, the third interlayer insulating film 37, and the fourth interlayer insulating film 38 that are interposed therebetween. In addition, a slit is opened and formed in each of the multiple pixel electrodes 25. Note that the slits are not shown in FIG. 3.

[0042] The common electrode 28 is made of a first transparent electrode film. As shown in FIG. 4, the common electrode 28 is arranged so as to overlap all the pixel electrodes 25 arranged in the display area AA on the lower layer side via a fourth interlayer insulating film 38. A common potential signal that is a common potential (reference potential) is supplied to the common electrode 28. When the pixel electrodes 25 are charged to a potential based on an image signal transmitted to the source wiring 26 with the driving of the second TFT 24, a potential difference is generated between the pixel electrodes 25 and the common electrode 28. Then, a fringe electric field (oblique electric field) including a component along the plate surface of the array substrate 21 and a component in the normal direction to the plate surface of the array substrate 21 is generated between the opening edge of the slit in the pixel electrode 25 and the common electrode 28. Therefore, by utilizing this fringe electric field, the orientation state of the liquid crystal molecules contained in the liquid crystal layer 22 can be controlled, and a predetermined display is performed based on the orientation state of the liquid crystal molecules. That is, the liquid crystal panel 11 according to this embodiment operates in a FFS (Fringe Field Switching) mode. In addition, in the common electrode 28, an opening for preventing a short circuit with the pixel electrode 25 is provided at a position overlapping with the fifth contact hole CH5.

[0043] In addition, as shown in FIG. 4, the touch wiring 30 is arranged in the display area AA. The touch wiring 30 is made of a fourth metal film. The touch wiring 30 is arranged at a position overlapping the source wiring 27 in a planar view. A planarization film 35 and a second interlayer insulating film 36 are interposed between the touch wiring 30 and the source wiring 27 that overlap each other, so that they are kept insulated from each other. A third interlayer insulating film 37 is interposed between the touch wiring 30 and the common electrode 28. The touch wiring 30 and the touch electrode 29 to be connected are connected through a sixth contact hole that is opened and formed in the third interlayer insulating film 37 interposed therebetween. Note that the sixth contact hole is not shown in the drawing.

[0044] In addition, in the display area AA, a light-shielding portion 39 is provided at a position overlapping at least the entire area of ​​the second semiconductor portion 24D. The light-shielding portion 39 is made of a first metal film. The light-shielding portion 39 is arranged to overlap the second semiconductor portion 24D on the lower layer side via the base coat film 31. Therefore, the light-shielding portion 39 can block light irradiated from the lower layer side onto the channel region of the second semiconductor portion 24D from the backlight device. This makes it possible to suppress fluctuations in the characteristics of the second TFT 24 that may occur when light is irradiated onto the channel region of the second semiconductor portion 24D.

[0045] A detailed configuration of the first TFT 15 included in the circuit unit 14 will be described with reference to Figs. 5 to 7. Figs. 5 to 7 only show the configuration (first semiconductor portion 15D and gate insulating film 33) of the first TFT 15 below the first gate electrode 15A. As shown in Fig. 5, the first semiconductor portion 15D of the first TFT 15 extends along the X-axis direction (first direction). The first semiconductor portion 15D has a horizontally elongated, approximately rectangular shape in a plan view. The first semiconductor portion 15D has a width dimension (dimension in the Y-axis direction) according to the amount of current flowing through the circuit to which the first TFT 15 belongs in the circuit unit 14.

[0046] As shown in FIG. 5, the first gate electrode 15A extends along the X-axis direction in parallel with the first semiconductor portion 15D. The first gate electrode 15A has a horizontally elongated, substantially rectangular shape in a plan view. The length dimension (dimension in the X-axis direction) of the first gate electrode 15A is smaller than the width dimension of the first semiconductor portion 15D, and the width dimension (dimension in the Y-axis direction) of the first gate electrode 15A is larger than the length dimension (dimension in the X-axis direction) of the first semiconductor portion 15D. The first gate electrode 15A extends along the Y-axis direction (second direction) and is disposed across the first semiconductor portion 15D so as to overlap the entire width of the first semiconductor portion 15D. Both ends of the first gate electrode 15A in the width direction (Y-axis direction) are disposed so as not to overlap the first semiconductor portion 15D. The first gate electrode 15A is disposed so as to overlap the central portion of the first semiconductor portion 15D in the length direction (X-axis direction). The first semiconductor portion 15D has both end portions in the length direction that do not overlap with the first gate electrode 15A. The first contact hole CH1 and the second contact hole CH2 are arranged to overlap with the both end portions in the length direction of the first semiconductor portion 15D.

[0047] Thus, the first TFT 15 according to the present embodiment has a single gate structure in which one first gate electrode 15A is arranged to overlap with the first semiconductor portion 15D as shown in FIG. 5. In a conventional transistor having a single gate structure, hot carrier injection is likely to occur when a high voltage is applied, which may cause the transistor performance to deteriorate over time. In particular, the first TFT 15 belonging to the buffer circuit included in the circuit portion 14 as in the present embodiment is likely to cause hot carrier injection because a high voltage is applied. In addition, in a conventional transistor having a single gate structure, ESD (Electro-Static Discharge) is likely to occur between the end of the gate electrode and the semiconductor portion, which may cause damage to the end of the gate electrode or the semiconductor portion due to ESD, resulting in a deterioration in yield.

[0048] In this embodiment, the gate insulating film 33 interposed between the first gate electrode 15A and the first semiconductor portion 15D has a thickness that varies depending on the position in the X-axis direction (first direction) as shown in Fig. 6. That is, the gate insulating film 33 has a first thickness portion 33A, a second thickness portion 33B having the same thickness as the first thickness portion 33A, a third thickness portion 33C having a thickness larger than the first thickness portion 33A, a fourth thickness portion 33D having a thickness larger than the first thickness portion 33A, and a fifth thickness portion 33E having a thickness larger than the first thickness portion 33A, which are arranged along the X-axis direction. The first thickness portion 33A, the second thickness portion 33B, the third thickness portion 33C, the fourth thickness portion 33D, and the fifth thickness portion 33E are all arranged at positions that overlap both the first gate electrode 15A and the first semiconductor portion 15D.

[0049] Specifically, the first thickness portion 33A and the second thickness portion 33B are disposed at positions spaced apart in the X-axis direction (first direction) as shown in Figs. 5 and 6. The first thickness portion 33A is disposed at a position spaced apart from the second thickness portion 33B on the left side of Fig. 6. That is, it can be said that the first thickness portion 33A is located closer to the first source electrode 15B (first contact hole CH1 side) in the X-axis direction than the third thickness portion 33C described later, and the second thickness portion 33B is located closer to the first drain electrode 15C (second contact hole CH2 side) in the X-axis direction than the third thickness portion 33C (see Fig. 4). The first thickness portion 33A and the second thickness portion 33B have dimensions L1 and L2 in the X-axis direction that are larger than the dimensions in the X-axis direction of the third thickness portion 33C, the fourth thickness portion 33D, and the fifth thickness portion 33E. The dimension L1 of the first thickness portion 33A in the X-axis direction and the dimension L2 of the second thickness portion 33B in the X-axis direction are almost equal to each other. The third thickness portion 33C is sandwiched between the first thickness portion 33A and the second thickness portion 33B in the X-axis direction. That is, a gap for the third thickness portion 33C is provided between the first thickness portion 33A and the second thickness portion 33B. The third thickness portion 33C is arranged to overlap with the center portion of the first gate electrode 15A in the X-axis direction. The fourth thickness portion 33D is arranged at a position to overlap with one end portion 15A1 (left side in FIG. 6) of the first gate electrode 15A in the X-axis direction. The fourth thickness portion 33D is arranged to sandwich the first thickness portion 33A between the third thickness portion 33C in the X-axis direction. The fifth thickness portion 33E is disposed at a position overlapping the other end 15A2 (right side in FIG. 6) of the first gate electrode 15A in the X-axis direction. The fifth thickness portion 33E is disposed to sandwich the second thickness portion 33B between itself and the third thickness portion 33C in the X-axis direction. It can be said that the first thickness portion 33A, the second thickness portion 33B, and the third thickness portion 33C are disposed to overlap a portion (center portion) of the first gate electrode 15A excluding both end portions 15A1, 15A2 in the X-axis direction.

[0050] In this embodiment, the thicknesses of the first film thickness portion 33A, the second film thickness portion 33B, the third film thickness portion 33C, the fourth film thickness portion 33D, and the fifth film thickness portion 33E are set to a value such that, when a predetermined voltage (a voltage equal to or greater than a threshold voltage) is applied to the first gate electrode 15A, a channel region 15D1 is generated in each of the portions of the first semiconductor portion 15D overlapping with the first film thickness portion 33A, the second film thickness portion 33B, the third film thickness portion 33C, the fourth film thickness portion 33D, and the fifth film thickness portion 33E. That is, the voltage applied to the first gate electrode 15A is set to a value such that the channel region 15D1 is generated not only in the portions of the first semiconductor portion 15D overlapping with the first film thickness portion 33A and the second film thickness portion 33B, which have a relatively small film thickness, but also in the portions of the first semiconductor portion 15D overlapping with the third film thickness portion 33C, the fourth film thickness portion 33D, and the fifth film thickness portion 33E, which have a relatively large film thickness. Therefore, the channel region 15D1 is generated over almost the entire area of ​​the portion of the first semiconductor portion 15D overlapping with the first gate electrode 15A. In FIG. 5, the area in which the channel region 15D1 is generated in the first semiconductor portion 15D is illustrated by being hatched. However, the electric field strength acting on the first semiconductor portion 15D from the first gate electrode 15A varies depending on the film thickness of each of the film thickness portions 33A to 33E. Specifically, the electric field strength acting on the portion of the first semiconductor portion 15D overlapping with the first film thickness portion 33A and the second film thickness portion 33B, which have a relatively small film thickness, from the first gate electrode 15A tends to be relatively strong, and the electric field strength acting on the portion of the first semiconductor portion 15D overlapping with the third film thickness portion 33C, the fourth film thickness portion 33D, and the fifth film thickness portion 33E, which have a relatively large film thickness, from the first gate electrode 15A tends to be relatively weak. The amount of current flowing through the channel region 15D1 tends to increase as the electric field strength acting from the first gate electrode 15A increases, and decrease as the electric field strength decreases. In other words, it can be said that the portions of the channel region 15D1 overlapping with the first thickness portion 33A and the second thickness portion 33B, which have relatively small thicknesses, have a relatively low resistance, and the portions of the channel region 15D1 overlapping with the third thickness portion 33C, the fourth thickness portion 33D, and the fifth thickness portion 33E, which have relatively large thicknesses, have a relatively high resistance.

[0051] According to this configuration, when a predetermined voltage is applied to the first gate electrode 15A, a channel region 15D1 is generated in the first semiconductor portion 15D. Accordingly, electrons move between the first source electrode 15B and the first drain electrode 15C through the channel region 15D1. Here, the gate insulating film 33 interposed between the first gate electrode 15A and the first semiconductor portion 15D has a first thickness portion 33A, a second thickness portion 33B having the same thickness as the first thickness portion 33A, a third thickness portion 33C having a thickness larger than the first thickness portion 33A, a fourth thickness portion 33D having a thickness larger than the first thickness portion 33A, and a fifth thickness portion 33E having a thickness larger than the first thickness portion 33A. Among these, the first thickness portion 33A, the second thickness portion 33B, and the third thickness portion 33C are all arranged to overlap both the first gate electrode 15A and the first semiconductor portion 15D, and the third thickness portion 33C is arranged to be sandwiched between the first thickness portion 33A and the second thickness portion 33B in the X-axis direction. Therefore, the amount of current flowing through the portion of the channel region 15D1 overlapping with the third thickness portion 33C is smaller than the amount of current flowing through the portion of the channel region 15D1 overlapping with the first thickness portion 33A and the second thickness portion 33B. This suppresses the occurrence of hot carrier injection, and can suppress deterioration of transistor performance over time. In addition, the fourth thickness portion 33D and the fifth thickness portion 33E are arranged to overlap both the ends 15A1, 15A2 of the first gate electrode 15A in the X-axis direction and the first semiconductor portion 15D, so that ESD is unlikely to occur between the ends 15A1, 15A2 of the first gate electrode 15A in the X-axis direction and the first semiconductor portion 15D. This makes it difficult for ESD to cause damage to the ends 15A1, 15A2 of the first gate electrode 15A in the X-axis direction and the first semiconductor portion 15D, so that the yield can be improved. In addition, the first thickness portion 33A and the second thickness portion 33B have the same dimensions in the X-axis direction, so that the lengths in the X-axis direction of the portions overlapping the first thickness portion 33A and the second thickness portion 33B of the channel region 15D1 generated in the first semiconductor portion 15D become equal, and the resistances of the portions become equal.In addition, since the first TFT 15 according to this embodiment has a single-gate structure, the length in the X-axis direction from the first source electrode 15B to the first drain electrode 15C is smaller than that of a TFT having a double-gate structure (multi-gate structure), which is preferable for miniaturizing the first TFT 15.

[0052] As shown in FIG. 6, the gate insulating film 33 has a laminated structure of a lower insulating film 40 and an upper insulating film 41. The lower insulating film 40 is disposed on the upper side of the first semiconductor portion 15D. The lower insulating film 40 is made of, for example, SiO2, and has a thickness of, for example, about 100 nm. The upper insulating film 41 is disposed on the upper side of the lower insulating film 40 and on the lower side of the first gate electrode 15A. The upper insulating film 41 is made of a different material from the lower insulating film 40. The upper insulating film 41 has a smaller thickness than the lower insulating film 40. The upper insulating film 41 is made of, for example, SiN, and has a thickness of, for example, about 50 nm. In this manner, by forming the gate insulating film 33 into a laminated structure of a lower insulating film 40 and an upper insulating film 41 which are made of different materials, it is possible to easily provide a first thickness portion 33A and a second thickness portion 33B, a third thickness portion 33C, a fourth thickness portion 33D and a fifth thickness portion 33E which are different in thickness.

[0053] In this embodiment, the first thickness portion 33A and the second thickness portion 33B are made of the lower insulating film 40 as shown in FIG. 6. In contrast, the third thickness portion 33C, the fourth thickness portion 33D, and the fifth thickness portion 33E are made of the upper insulating film 41 and the lower insulating film 40. That is, the third thickness portion 33C, the fourth thickness portion 33D, and the fifth thickness portion 33E have the same thickness. According to this configuration, in manufacturing, the lower insulating film 40 and the upper insulating film 41 are sequentially formed, and then the upper insulating film 41 is selectively removed, so that the first thickness portion 33A and the second thickness portion 33B made of the lower insulating film 40, and the third thickness portion 33C, the fourth thickness portion 33D, and the fifth thickness portion 33E made of the lower insulating film 40 and the upper insulating film 41 can be easily provided. In addition, manufacturing is easier than if the thicknesses of the third thickness portion 33C, the fourth thickness portion 33D, and the fifth thickness portion 33E are all different.

[0054] 7, the gate insulating film 33 has a sixth thickness portion 33F having a thickness larger than that of the first thickness portion 33A. The sixth thickness portion 33F is arranged to overlap with an end portion 15D2 in the Y-axis direction (a second direction intersecting with the first direction) of the first semiconductor portion 15D. The sixth thickness portion 33F has the same thickness as the third thickness portion 33C, the fourth thickness portion 33D, and the fifth thickness portion 33E. That is, the sixth thickness portion 33F is made of the upper insulating film 41 and the lower insulating film 40, like the third thickness portion 33C, the fourth thickness portion 33D, and the fifth thickness portion 33E.

[0055] 6 and 7, the gate insulating film 33 has a seventh thickness portion 33G having a thickness larger than that of the first thickness portion 33A. The seventh thickness portion 33G constitutes a portion of the gate insulating film 33 that does not overlap with both the first gate electrode 15A and the first semiconductor portion 15D in a plan view. The seventh thickness portion 33G has the same thickness as the third thickness portion 33C, the fourth thickness portion 33D, the fifth thickness portion 33E, and the sixth thickness portion 33F. That is, the seventh thickness portion 33G is made of the upper insulating film 41 and the lower insulating film 40, like the third thickness portion 33C, the fourth thickness portion 33D, the fifth thickness portion 33E, and the sixth thickness portion 33F.

[0056] The present embodiment has the above-described structure, and next, a method for manufacturing the liquid crystal panel 11 will be described. The method for manufacturing the liquid crystal panel 11 includes a counter substrate manufacturing process (CF substrate manufacturing process) for manufacturing the counter substrate 20, an array substrate manufacturing process for manufacturing the array substrate 21, and a bonding process for bonding the manufactured counter substrate 20 and array substrate 21 together. Of these processes, the array substrate manufacturing process will be described below.

[0057] The array substrate manufacturing process includes a first step of depositing and patterning a first metal film, a second step of depositing a base coat film 31, a third step of depositing a semiconductor film, performing a laser crystallization process, and then patterning the semiconductor film, a fourth step of depositing and patterning a gate insulating film 33, a fifth step of depositing and patterning a second metal film 32, a sixth step of depositing and patterning a first interlayer insulating film 34, and a seventh step of depositing and patterning a third metal film. The process includes at least an eighth step of forming a flattening film 35, a ninth step of forming a second interlayer insulating film 36, a tenth step of forming and patterning a fourth metal film, an eleventh step of forming a third interlayer insulating film 37, a twelfth step of forming and patterning a first transparent electrode film, a thirteenth step of forming and patterning a fourth interlayer insulating film 38, a fourteenth step of forming and patterning a second transparent electrode film, and a fifteenth step of forming an alignment film and performing an alignment treatment. The fourth and fifth steps will be described in detail below with reference to Figures 8 to 16. Figures 8 to 16 show the same cross-sectional configuration as Figure 6.

[0058] The term "patterning" refers to the processing of a film based on a general photolithography method. Specifically, a photoresist film is formed on the film to be processed, the photoresist film is exposed to light by an exposure device through a photomask having a predetermined pattern, the photoresist film is developed, and etching is performed through the developed photoresist film, thereby processing the film to be processed, i.e., patterning is performed.

[0059] In the fourth step, as shown in FIG. 8, a lower insulating film 40 constituting the gate insulating film 33 is first formed in a solid state on the upper layer side of the first semiconductor portion 15D, then an upper insulating film 41 is formed in a solid state on the upper layer side of the lower insulating film 40, and then a first resist film R1 is formed in a solid state on the upper layer side of the upper insulating film 41. After that, the first resist film R1 is exposed using an exposure device and a first photomask P1 shown in FIG. 9 (first exposure step). The first resist film R1 used in the fourth step is made of a positive-type photosensitive material. Here, the first photomask P1 will be described. As shown in FIG. 9, the first photomask P1 includes a transparent first base material P1A having a sufficiently high light transmittance, a first light-shielding film P1B formed on the main surface of the first base material P1A, and a semi-transparent film P1C formed on the main surface of the first base material P1A and partially laminated on the first light-shielding film P1B. That is, the first photomask P1 is a so-called halftone mask. The first light-shielding film P1B blocks exposure light from a light source of an exposure tool, and the transmittance of the exposure light is set to approximately 0%. The first light-shielding film P1B has a partial opening P1B1. The opening P1B1 is sized to be equal to or larger than the resolution of the exposure tool, and can transmit light within its formation range. The semi-transmitting film P1C transmits exposure light from the light source of the exposure tool with a predetermined transmittance. The semi-transmitting film P1C has a higher transmittance of exposure light than the transmittance of the exposure light in the first light-shielding film P1B, and is set to, for example, approximately 10% to 70%.

[0060] 9, the first light-shielding film P1B has a configuration in which a plurality of openings P1B1 are arranged in an island-shaped area overlapping the planned formation positions of the first semiconductor portions 15D in the non-display area NAA and in an island-shaped area overlapping the planned formation positions of the second semiconductor portions 24D in the display area AA. The semi-transparent film P1C is arranged in an area overlapping with a portion of each of the openings P1B1 arranged in the non-display area NAA in addition to the area overlapping with the first light-shielding film P1B. More specifically, the semi-transparent film P1C is arranged in an area overlapping with the planned formation positions of the third thickness portion 33C of the gate insulating film 33 in the non-display area NAA. On the other hand, the first light-shielding film P1B is arranged in a range in the non-display area NAA where the edge portion of the opening P1B1 overlaps with the planned positions for forming the fourth thickness portion 33D, the fifth thickness portion 33E and the sixth thickness portion 33F of the gate insulating film 33, and the portion other than the edge portion of the opening P1B1 overlaps with the planned position for forming the seventh thickness portion 33G.

[0061] As shown in FIG. 9, the first photomask P1 has a first light-shielding region A1 that blocks light in a region where the first light-shielding film P1B is formed. The light transmittance in the first light-shielding region A1 is set to approximately 0%. In the first photomask P1, a portion of the opening P1B1 that does not overlap with the semi-transmitting film P1C is set to a first light-transmitting region A2 that transmits light. Two first light-transmitting regions A2 are arranged at positions (positions overlapping with the positions where the first film thickness portion 33A and the second film thickness portion 33B are to be formed) spaced apart from each other in the Y-axis direction in the positions where the first semiconductor portions 15D are to be formed. The light transmittance in the first light-transmitting region A2 is set to approximately 100%. In the first photomask P1, a portion of the opening P1B1 that overlaps with the semi-transmitting film P1C is set to a semi-transmitting region A3 that semi-transmits light. The semi-transmitting region A3 is disposed at the center position in the Y-axis direction (overlapping with the position where the third film thickness portion 33C is to be formed) of each of the first semiconductor portions 15D to be formed. That is, the first transmitting region A2 and the semi-transmitting region A3 are disposed alternately in the Y-axis direction at the position where each of the first semiconductor portions 15D is to be formed. The light transmittance in the semi-transmitting region A3 is higher than the transmittance in the first light-shielding region A1 and lower than the transmittance in the first light-transmitting region A2, and is, for example, about 10% to 70%. The first light-shielding region A1, the first transmitting region A2, and the semi-transmitting region A3 constitute an exposure pattern in the first photomask P1.

[0062] In the fourth step, the first resist film R1 is irradiated with exposure light emitted from a light source of an exposure device through the first photomask P1 configured as described above. The exposure amount of the first resist film R1 is different for each portion overlapping with each of the regions A1 to A3 of the first photomask P1, as shown in FIG. 9. That is, the portion of the first resist film R1 overlapping with the first light-shielding region A1 is almost not exposed, the portion overlapping with the first transmission region A2 is sufficiently exposed, and the portion overlapping with the semi-transmission region A3 is exposed with a smaller amount of light than the portion overlapping with the first light-shielding region A1. The first resist film R1 used in the fourth step is made of a positive photosensitive material. Therefore, when the first resist film R1 is developed after the exposure (first development step), the exposed portion of the first resist film R1 (the portion overlapping the first light-shielding region A2) is removed, the non-exposed portion (the portion overlapping the first light-shielding region A1) remains, and the semi-exposed portion (the portion overlapping the semi-transmitting region A3) remains with a film thickness according to the amount of exposure, that is, a film thickness thinner than the non-exposed portion, as shown in Fig. 10. In this way, the first resist film R1 selectively remains in the portions overlapping the first light-shielding region A1 and the semi-transmitting region A3 of the first photomask P1.

[0063] The gate insulating film 33 is etched using the first resist film R1 developed in this manner as a mask (first etching step). In this etching, etching conditions (such as the type of etching gas in the case of dry etching, and the type of etching solution in the case of wet etching) are set so that the etching rate for the upper insulating film 41 constituting the gate insulating film 33 is high and the etching rate for the lower insulating film 40 is low. When the first etching step is performed, as shown in FIG. 11, the upper insulating film 41 constituting the gate insulating film 33 is selectively removed in the exposed portion not covered by the first resist film R1 (the area overlapping the first transmission region A2 of the first photomask P1), but the portion covered by the first resist film R1 (the areas overlapping the first light-shielding region A1 and the semi-transmission region A3 of the first photomask P1) remains without being removed. The lower insulating film 40 constituting the gate insulating film 33 is not entirely removed, including the area overlapping the first transmission region A2. As a result, the gate insulating film 33 can be easily provided with a first thickness portion 33A and a second thickness portion 33B, which are located in a range overlapping the first transmission region A2 of the first photomask P1 and are made of the lower layer insulating film 40, a third thickness portion 33C, which is located in a range overlapping the semi-transmission region A3 and is made of the lower layer insulating film 40 and the upper layer insulating film 41, and a fourth thickness portion 33D, a fifth thickness portion 33E, a sixth thickness portion 33F, and a seventh thickness portion 33G, which are located in a range overlapping the first light-shielding region A1 and are made of the lower layer insulating film 40 and the upper layer insulating film 41. After the etching is completed, the first resist film R1 is removed by ashing as shown in FIG. 12 (first ashing step).

[0064] After the fourth step is performed as described above, the fifth step is performed. In the fifth step, as shown in FIG. 13, the second metal film 32 is formed in a solid state on the upper layer side of the gate insulating film 33, and then the second resist film R2 is formed in a solid state on the upper layer side of the second metal film 32. The second resist film R2 used in the fifth step is made of a negative photosensitive material. Then, the second resist film R2 is exposed using an exposure device and a first photomask P1 (second exposure step). The first photomask P1 used in the second exposure step of this fifth step has the same exposure pattern (first light-shielding region A1, first transmission region A2, and semi-transmission region A3) as the first photomask P1 used in the first exposure step of the fourth step described above. In this way, the first photomask P1 having the same exposure pattern can be used in the first exposure process for exposing the first resist film R1 and the second exposure process for exposing the second resist film R2, which is advantageous in reducing the costs associated with the equipment required for manufacturing.

[0065] In the fifth step, the exposure light emitted from the light source of the exposure device is irradiated onto the second resist film R2 through the first photomask P1 having the same exposure pattern as the first photomask P1 used in the first exposure step of the fourth step. The exposure amount of the second resist film R2 is different for each part overlapping with each of the regions A1 to A3 of the first photomask P1, as shown in FIG. 14. That is, the part of the second resist film R2 overlapping with the first light-shielding region A1 is hardly exposed, the part overlapping with the first transmission region A2 is sufficiently exposed, and the part overlapping with the semi-transmission region A3 is exposed with a smaller amount of light than the part overlapping with the first transmission region A2. The second resist film R2 used in the fifth step is made of a negative photosensitive material. Therefore, when the second resist film R2 is developed after the exposure (second development step), the non-exposed portions of the second resist film R2 (portions overlapping with the first light-shielding region A1) are removed, the exposed portions (portions overlapping with the first transmission region A2) remain, and the semi-exposed portions (portions overlapping with the semi-transmission region A3) remain with a film thickness according to the amount of exposure, that is, a film thickness thinner than that of the exposed portions, as shown in Fig. 15. In this way, the portions of the second resist film R2 that overlap with the first transmission region A2 and the semi-transmission region A3 of the first photomask P1 selectively remain.

[0066] The second metal film 32 is etched using the second resist film R2 developed in this way as a mask (second etching step), and the first gate electrode 15A is provided in a range overlapping the first transparent region A2 and the semi-transparent region A3 of the first photomask P1, as shown in Fig. 16. The first gate electrode 15A provided through the second etching step is arranged such that both ends 15A1 and 15A2 in the X-axis direction overlap the fourth thickness portion 33D and the fifth thickness portion 33E of the gate insulating film 33, and the central portion between both ends 15A1 and 15A2 overlaps the first thickness portion 33A, the second thickness portion 33B and the third thickness portion 33C of the gate insulating film 33. After the etching is completed, the second resist film R2 is removed by ashing, as shown in Fig. 6 (second ashing step). In this way, when the sixth step is carried out after the fifth step is completed, the first interlayer insulating film 34 is formed on the upper layer side of the first gate electrode 15A and then patterned (see FIG. 4).

[0067] As described above, the first TFT (transistor) 15 of this embodiment includes a first semiconductor portion (semiconductor portion) 15D extending along the first direction and made of a semiconductor material, a first gate electrode (first electrode) 15A arranged so as to overlap a portion of the first semiconductor portion 15D, a gate insulating film (first insulating film) 33 interposed between the first gate electrode 15A and the first semiconductor portion 15D, and a gate insulating film (first insulating film) 34 arranged so as to overlap a portion of the first semiconductor portion 15D and connected to the first semiconductor portion 15D. and a first drain electrode (third electrode) 15C arranged to overlap a part of the first semiconductor portion 15D at a position spaced apart in the first direction from a connection position between the first source electrode 15B and the first semiconductor portion 15D and connected to the first semiconductor portion 15D. The gate insulating film 33 includes a first thickness portion 33A, a second thickness portion 33B having the same thickness as the first thickness portion 33A, and a third thickness portion 33B having a thickness larger than that of the first thickness portion 33A. a fourth thickness portion 33D having a thickness larger than that of the first thickness portion 33A, and a fifth thickness portion 33E having a thickness larger than that of the first thickness portion 33A, the first thickness portion 33A being disposed at a position overlapping both the first gate electrode 15A and the first semiconductor portion 15D, the second thickness portion 33B being disposed at a position overlapping both the first gate electrode 15A and the first semiconductor portion 15D and spaced apart in the first direction from the first thickness portion 33A, and the third thickness portion 33C being disposed at a position overlapping both the first gate electrode 15A and the first semiconductor portion 15D and spaced apart in the first direction from the first thickness portion 33A. The fourth thickness portion 33D is arranged so as to overlap both the first gate electrode 15A and the first semiconductor portion 15D and is sandwiched between the first thickness portion 33A and the second thickness portion 33B in the first direction, the fourth thickness portion 33D is arranged so as to overlap both one end portion 15A1 of the first gate electrode 15A in the first direction and the first semiconductor portion 15D, and the fifth thickness portion 33E is arranged so as to overlap both the other end portion 15A2 of the first gate electrode 15A in the first direction and the first semiconductor portion 15D.

[0068] When a voltage equal to or greater than the threshold voltage of the first TFT 15 is applied to the first gate electrode 15A, a channel region 15D1 is generated in the first semiconductor portion 15D. Accordingly, electrons move between the first source electrode 15B and the first drain electrode 15C through the channel region 15D1. Here, the gate insulating film 33 interposed between the first gate electrode 15A and the first semiconductor portion 15D has a first thickness portion 33A, a second thickness portion 33B having the same thickness as the first thickness portion 33A, a third thickness portion 33C having a thickness greater than the first thickness portion 33A, a fourth thickness portion 33D having a thickness greater than the first thickness portion 33A, and a fifth thickness portion 33E having a thickness greater than the first thickness portion 33A. Among these, the first thickness portion 33A, the second thickness portion 33B, and the third thickness portion 33C are arranged so as to overlap both the first gate electrode 15A and the first semiconductor portion 15D, and the third thickness portion 33C is arranged so as to be sandwiched between the first thickness portion 33A and the second thickness portion 33B in the first direction. Therefore, the amount of current flowing through the portion of the channel region 15D1 overlapping with the third thickness portion 33C is smaller than the amount of current flowing through the portion of the channel region 15D1 overlapping with the first thickness portion 33A and the second thickness portion 33B. This suppresses the occurrence of hot carrier injection, and makes it possible to suppress deterioration of the transistor performance over time. Moreover, since the fourth film thickness portion 33D and the fifth film thickness portion 33E are arranged to overlap both the ends 15A1, 15A2 of the first gate electrode 15A in the first direction and the first semiconductor portion 15D, ESD is unlikely to occur between the ends 15A1, 15A2 of the first gate electrode 15A in the first direction and the first semiconductor portion 15D. This makes it difficult for ESD to cause damage to the ends 15A1, 15A2 of the first gate electrode 15A in the first direction and the first semiconductor portion 15D, thereby improving the yield.

[0069] Moreover, the gate insulating film 33 has a laminated structure of a lower insulating film 40 disposed on the upper side of the first semiconductor portion 15D, and an upper insulating film 41 disposed on the upper side of the lower insulating film 40 and made of a different material than the lower insulating film 40. By making the gate insulating film 33 have a laminated structure of the lower insulating film 40 and the upper insulating film 41 made of different materials in this way, it is possible to easily provide the first thickness portion 33A and the second thickness portion 33B, and the third thickness portion 33C, the fourth thickness portion 33D, and the fifth thickness portion 33E, which have different thicknesses.

[0070] Moreover, the third thickness portion 33C, the fourth thickness portion 33D, and the fifth thickness portion 33E have the same thickness, which makes manufacturing easier than if the third thickness portion 33C, the fourth thickness portion 33D, and the fifth thickness portion 33E all had different thicknesses.

[0071] The first thickness portion 33A and the second thickness portion 33B have the same dimensions L1, L2 in the first direction. In this way, the lengths in the first direction of the portions of the channel region 15D1 generated in the first semiconductor portion 15D that overlap with the first thickness portion 33A and the second thickness portion 33B are equal.

[0072] Moreover, the first semiconductor portion 15D is made of a polysilicon semiconductor material, which can provide higher electron mobility than if an amorphous silicon semiconductor material or an oxide semiconductor material were used as the semiconductor material.

[0073] Moreover, the manufacturing method of the first TFT 15 of this embodiment includes forming a semiconductor film made of a semiconductor material, patterning the semiconductor film to provide a first semiconductor portion 15D extending along a first direction, forming a gate insulating film 33 on the upper side of the first semiconductor portion 15D, forming a first resist film R1 made of a photosensitive material on the upper side of the gate insulating film 33, exposing and developing the first resist film R1, and etching the gate insulating film 33 using the first resist film R1 as a mask to form a first thickness portion 33A arranged to overlap the first semiconductor portion 15D. a second thickness portion 33B that overlaps with the first semiconductor portion 15D, is disposed at a position spaced apart from the first thickness portion 33A in the first direction, and has the same thickness as the first thickness portion 33A; a third thickness portion 33C that is disposed to be sandwiched between the first thickness portion 33A and the second thickness portion 33B in the first direction at a position overlapping with the first semiconductor portion 15D, and has a thickness larger than that of the first thickness portion 33A; and a third thickness portion 33C that overlaps with the first semiconductor portion 15D, is disposed with the first thickness portion 33A sandwiched between the third thickness portion 33C in the first direction, and has a thickness larger than that of the first thickness portion 33A. a fourth thickness portion 33D having a thickness greater than that of the first thickness portion 33A, and a fifth thickness portion 33E overlapping with the first semiconductor portion 15D and arranged with the second thickness portion 33B sandwiched between the third thickness portion 33C in the first direction, the fifth thickness portion 33E having a thickness greater than that of the first thickness portion 33A, a second metal film (first conductive film) 32 is formed on the upper side of the gate insulating film 33, a second resist film R2 made of a photosensitive material is formed on the upper side of the second metal film 32, the second resist film R2 is exposed and developed, and the second metal film 32 is etched using the second resist film R2 as a mask, thereby forming the first a first gate electrode 15A having one end 15A1 in the first direction overlapping with a fourth thickness portion 33D and the other end 15A2 in the first direction overlapping with a fifth thickness portion 33E, and a portion between both ends in the first direction overlapping with the first thickness portion 33A, the second thickness portion 33B and the third thickness portion 33C, a third metal film (second conductive film) being formed above the first gate electrode 15A and the third metal film being patterned to form a first source electrode 15B overlapping with a portion of the first semiconductor portion 15D and connected to the first semiconductor portion 15D;A first drain electrode 15C is provided, which is disposed so as to overlap a part of the first semiconductor portion 15D at a position spaced apart in the first direction from a connection position between the first source electrode 15B and the first semiconductor portion 15D and is connected to the first semiconductor portion 15D.

[0074] The first semiconductor portion 15D is provided by forming a semiconductor film and patterning it. After the gate insulating film 33 and the first resist film R1 are formed in sequence on the upper layer side of the first semiconductor portion 15D, the first resist film R1 is exposed and developed. When the gate insulating film 33 is etched through the patterned first resist film R1, the first thickness portion 33A, the second thickness portion 33B, the third thickness portion 33C, the fourth thickness portion 33D, and the fifth thickness portion 33E are provided. After the second metal film 32 and the second resist film R2 are formed in sequence on the upper layer side of the gate insulating film 33, the second resist film R2 is exposed and developed. When the second metal film 32 is etched through the patterned second resist film R2, the first gate electrode 15A is provided. By forming a third metal film on the upper layer side of the first gate electrode 15A and patterning it, the first source electrode 15B and the first drain electrode 15C are provided.

[0075] When a voltage equal to or greater than the threshold voltage of the first TFT 15 thus manufactured is applied to the first gate electrode 15A, a channel region 15D1 is generated in the first semiconductor portion 15D. Accordingly, electrons move between the first source electrode 15B and the first drain electrode 15C through the channel region 15D1. Here, the gate insulating film 33 interposed between the first gate electrode 15A and the first semiconductor portion 15D has a first thickness portion 33A, a second thickness portion 33B having the same thickness as the first thickness portion 33A, a third thickness portion 33C having a thickness greater than the first thickness portion 33A, a fourth thickness portion 33D having a thickness greater than the first thickness portion 33A, and a fifth thickness portion 33E having a thickness greater than the first thickness portion 33A. Among these, the first thickness portion 33A, the second thickness portion 33B, and the third thickness portion 33C are arranged so as to overlap both the first gate electrode 15A and the first semiconductor portion 15D, and the third thickness portion 33C is arranged so as to be sandwiched between the first thickness portion 33A and the second thickness portion 33B in the first direction. Therefore, the amount of current flowing through the portion of the channel region 15D1 overlapping with the third thickness portion 33C is smaller than the amount of current flowing through the portion of the channel region 15D1 overlapping with the first thickness portion 33A and the second thickness portion 33B. This suppresses the occurrence of hot carrier injection, and makes it possible to suppress deterioration of the transistor performance over time. Moreover, since the fourth film thickness portion 33D and the fifth film thickness portion 33E are arranged to overlap both the ends 15A1, 15A2 of the first gate electrode 15A in the first direction and the first semiconductor portion 15D, ESD is unlikely to occur between the ends 15A1, 15A2 of the first gate electrode 15A in the first direction and the first semiconductor portion 15D. This makes it difficult for ESD to cause damage to the ends 15A1, 15A2 of the first gate electrode 15A in the first direction and the first semiconductor portion 15D, thereby improving the yield.

[0076] In addition, a first resist film R1 made of a positive type photosensitive material is formed on the upper side of the gate insulating film 33, the first resist film R1 is exposed to light through a first photomask P1 having a first light-shielding region A1 arranged to overlap with the planned formation areas of the fourth film thickness portion 33D and the fifth film thickness portion 33E and blocking light, a first transparent region A2 overlapping with the planned formation areas of the first film thickness portion 33A and the second film thickness portion 33B and transmitting light, and a semi-transparent region A3 overlapping with the planned formation area of ​​the third film thickness portion 33C and sandwiched between the two first transparent regions A2 in the first direction, having a higher light transmittance than the first light-shielding region A1 and a lower light transmittance than the first transparent region A2. A second resist film R2 made of a negative type photosensitive material is formed on the upper side of the second metal film 32, and the second resist film R2 is exposed to light through the first photomask P1 and then developed.

[0077] The first resist film R1 formed on the upper side of the gate insulating film 33 is exposed through the first photomask P1. The exposure amount of the first resist film R1 differs for each portion overlapping each region of the first photomask P1. That is, the portion of the first resist film R1 overlapping the first light-shielding region A1 is hardly exposed, the portion overlapping the first transmission region A2 is fully exposed, and the portion overlapping the semi-transmission region A3 is exposed with a smaller amount of light than the portion overlapping the first transmission region A2. Since the first resist film R1 is made of a positive photosensitive material, when it is developed, the exposed portion (the portion overlapping the first transmission region A2) is removed, the non-exposed portion (the portion overlapping the first light-shielding region A1) remains, and the semi-exposed portion (the portion overlapping the semi-transmission region A3) remains with a film thickness according to the exposure amount. The gate insulating film 33 is etched using the developed first resist film R1 as a mask to provide a first thickness portion 33A and a second thickness portion 33B located in an area overlapping the first transparent region A2 of the first photomask P1, a third thickness portion 33C located in an area overlapping the semi-transparent region A3, and a fourth thickness portion 33D and a fifth thickness portion 33E located in an area overlapping the first light-shielding region A1.

[0078] The second resist film R2 formed on the upper layer side of the second metal film 32 is exposed through a first photomask P1 having the same exposure pattern as the first photomask P1 used when exposing the first resist film R1. The exposure amount of the second resist film R2 differs for each portion overlapping each region of the first photomask P1. That is, the portion of the second resist film R2 overlapping with the first light-shielding region A1 is hardly exposed, the portion overlapping with the first transmission region A2 is sufficiently exposed, and the portion overlapping with the semi-transmission region A3 is exposed with a smaller amount of light than the portion overlapping with the first transmission region A2. Since the second resist film R2 is made of a negative type photosensitive material, when it is developed, the unexposed portion (the portion overlapping with the first light-shielding region A1) is removed, the exposed portion (the portion overlapping with the first transmission region A2) remains, and the semi-exposed portion (the portion overlapping with the semi-transmission region A3) remains with a film thickness according to the exposure amount. The second metal film 32 is etched using the developed second resist film R2 as a mask to provide a first gate electrode 15A located in an area overlapping with the first transparent region A2 and semi-transparent region A3 of the first photomask P1.

[0079] As described above, the first photomask P1 having the same exposure pattern can be used in the process of exposing the first resist film R1 and the process of exposing the second resist film R2, which is advantageous in reducing the costs associated with the equipment required for manufacturing.

[0080] <Embodiment 2> A second embodiment will be described with reference to Fig. 17. In this second embodiment, a case where the configuration of the gate insulating film 133 is changed is shown. Note that a duplicated description of the structure, action, and effects similar to those of the first embodiment will be omitted.

[0081] The gate insulating film 133 according to this embodiment has a single-layer structure as shown in FIG. 17. The gate insulating film 133 is made of, for example, SiO2. The gate insulating film 133 has different thicknesses depending on the portions, and the first and second thickness portions 133A and 133B have thicknesses of, for example, about 100 nm, and the third, fourth, fifth, sixth, and seventh thickness portions 133C, 133D, 133E, 133F, and 133G have thicknesses of, for example, about 150 nm. To form such a gate insulating film 133, the etching process time and the like are adjusted in the first etching step of the fourth process to control the depth to which the exposed portions not covered by the first resist film R1 (see FIG. 11) are removed.

[0082] As described above, according to the present embodiment, the gate insulating film 133 has a single-layer structure. Compared with a case in which the gate insulating film has a laminated structure made of a plurality of insulating films, the number of film formation processes required for manufacturing can be reduced.

[0083] <Embodiment 3> A third embodiment will be described with reference to Fig. 18. In this third embodiment, the configurations of the first thickness portion 233A and the second thickness portion 233B are changed from those of the first embodiment. Note that a duplicated description of the structure, action, and effect similar to those of the first embodiment will be omitted.

[0084] As shown in Fig. 18, the first thickness portion 233A and the second thickness portion 233B according to this embodiment have different dimensions L201, L202 in the X-axis direction. First, the first thickness portion 233A is located closer to the first source electrode 15B in the X-axis direction than the third thickness portion 233C (see Fig. 4), that is, on the left side of Fig. 18. In contrast, the second thickness portion 233B is located closer to the first drain electrode 15C in the X-axis direction than the third thickness portion 233C (see Fig. 4), that is, on the right side of Fig. 18. The dimension L202 in the X-axis direction of the second thickness portion 233B is larger than the dimension L201 in the X-axis direction of the first thickness portion 233A.

[0085] Here, in the first semiconductor portion 215D, electric field concentration tends to occur more easily in the vicinity of the first drain electrode 15C connected to the signal supply target than in other portions. In particular, the first TFT 15 belonging to the buffer circuit is concerned about the occurrence of the electric field concentration because a high voltage is applied to the first TFT 15. In this respect, according to the present embodiment, the second thickness portion 233B located closer to the first drain electrode 15C in the X-axis direction than the third thickness portion 233C has a larger dimension L202 in the X-axis direction than the first thickness portion 233A located closer to the first source electrode 15B in the X-axis direction than the third thickness portion 233C, so that the resistance of the portion of the channel region 215D1 generated in the first semiconductor portion 215D that overlaps with the second thickness portion 233B becomes high. As a result, electric field concentration is less likely to occur in the vicinity of the first drain electrode 15C of the first semiconductor portion 215D, and the occurrence of hot carrier injection is further suppressed.

[0086] As described above, according to this embodiment, the first source electrode 15B is connected to a signal supply source (driver 12 or flexible substrate 13) and is supplied with a signal from the signal supply source, whereas the first drain electrode 15C is connected to a signal supply target (gate wiring 26) and is capable of supplying a signal to the signal supply target, the first thickness portion 233A is located closer to the first source electrode 15B in the first direction than the third thickness portion 233C, the second thickness portion 233B is located closer to the first drain electrode 15C in the first direction than the third thickness portion 233C, and has a dimension L202 in the first direction larger than that of the first thickness portion 233A. When a voltage equal to or greater than the threshold voltage of the first TFT 15 is applied to the first gate electrode 215A, a signal supplied from the signal supply source to the first source electrode 15B is transmitted to the first drain electrode 15C via a channel region 215D1 generated in the first semiconductor portion 215D, and is supplied from the first drain electrode 15C to the signal supply target. Here, in the first semiconductor portion 215D, electric field concentration tends to occur more easily in the vicinity of the first drain electrode 15C connected to the signal supply target than in other portions. In this respect, the second thickness portion 233B located closer to the first drain electrode 15C in the first direction than the third thickness portion 233C has a larger dimension L202 in the first direction than the first thickness portion 233A located closer to the first source electrode 15B in the first direction than the third thickness portion 233C, so that the resistance of the portion of the channel region 215D1 generated in the first semiconductor portion 215D that overlaps with the second thickness portion 233B becomes high. As a result, electric field concentration is less likely to occur in the vicinity of the first drain electrode 15C in the first semiconductor portion 215D, and the occurrence of hot carrier injection is further suppressed.

[0087] <Embodiment 4> A fourth embodiment will be described with reference to Fig. 19 to Fig. 31. In this fourth embodiment, the configurations of the first TFT 315 and the gate insulating film 333 are changed from those of the first embodiment. Note that a duplicated description of the structure, operation, and effects similar to those of the first embodiment will be omitted.

[0088] As shown in FIG. 19, the first TFT 315 according to this embodiment includes two gate electrodes 315E and 315F instead of the single first gate electrode 15A (see FIG. 4) described in the first embodiment. The two gate electrodes 315E and 315F include a first gate electrode (first electrode) 315E and a third gate electrode (fourth electrode) 315F that are spaced apart in the X-axis direction (first direction). Of these, the first gate electrode 315E is arranged to be biased toward the first source electrode 315B (left side in FIG. 19) from the center position of the first semiconductor part 315G in the X-axis direction. The third gate electrode 315F is arranged to be biased toward the first drain electrode 315C (right side in FIG. 19) from the center position of the first semiconductor part 315G in the X-axis direction. The first semiconductor part 315G extends along the X-axis direction and has a horizontally elongated substantially rectangular shape in a plan view, as in the first embodiment. The first semiconductor portion 315G overlaps with the first gate electrode 315E at a portion between the center position in the X-axis direction and a portion connected to the first source electrode 315B (a portion overlapping with the first contact hole CH301). The first semiconductor portion 315G overlaps with the third gate electrode 315F at a portion between the center position in the X-axis direction and a portion connected to the first drain electrode 315C (a portion overlapping with the second contact hole CH302).

[0089] In this embodiment, the semiconductor film constituting the first semiconductor portion 315G described above is partially made conductive by ion implantation processing in which dopants (impurities) are ion-implanted during the manufacturing process, and as a result, the first semiconductor portion 315G includes a conductive region 315G1 as shown in FIG. 20. The region of the first semiconductor portion 315G that is not subjected to the conductive processing is the non-conductive region. The non-conductive region in the first semiconductor portion 315G is made capable of transferring charges only under specific conditions (when signals are supplied to both gate electrodes 315E, 315F). In other words, the non-conductive region is the channel region 315G2. Note that in FIG. 20, the conductive region 315G1 and the channel region 315G2 in the first semiconductor portion 315G are illustrated with different hatching. The channel region 315G2 is a portion of the first semiconductor portion 315G that overlaps with each of the gate electrodes 315E, 315F in a plan view. That is, the first semiconductor portion 315G has two channel regions 315G2 at positions spaced apart from each other in the X-axis direction. More specifically, the channel region 315G2 includes a first channel region 315G2A overlapping the first gate electrode 315E and a second channel region 315G2B overlapping the third gate electrode 315F. The conductor region 315G1 is a portion of the first semiconductor portion 315G that does not overlap with each gate electrode 315E, 315F in a plan view. The conductor region 315G1 has a lower resistivity than the non-conductor region, and is always capable of transferring charges, so that it functions as a conductor. The conductorization process of the semiconductor film is performed in the manufacturing process of the array substrate 21 by providing a structure (each gate electrode 315E, 315F, etc.) made of the second metal film 332, and then using the structure (each gate electrode 315E, 315F, etc.) as a mask. In the conductorization process, the conductorization process is selectively performed on the portions of the semiconductor film that are not covered by the composition consisting of the second metal film 332 (non-overlapping portions, exposed portions), and the conductorization process is not performed on the portions that are covered by the composition consisting of the second metal film 332 (overlapping portions, non-exposed portions).The conductor region 315G1 includes a first conductor region (source region) 315G1A connected to the first source electrode 315B, a second conductor region (drain region) 315G1B connected to the first drain electrode 315C, and a third conductor region 315G1C sandwiched between the two channel regions 315G2. A portion of the first conductor region 315G1A overlaps the first contact hole CH301. A portion of the second conductor region 315G1B overlaps the second contact hole CH302.

[0090] As shown in Fig. 20, the first gate electrode 315E and the third gate electrode 315F each extend along the Y-axis direction and have a vertically elongated rectangular shape in a plan view. The first gate electrode 315E and the third gate electrode 315F each have a length dimension (dimension in the Y-axis direction) larger than the width dimension of the first semiconductor portion 315G and a width dimension (dimension in the X-axis direction) smaller than the length dimension (dimension in the X-axis direction) of the first semiconductor portion 315G. The first gate electrode 315E and the third gate electrode 315F are both disposed across the first semiconductor portion 315G so as to overlap the entire width of the first semiconductor portion 315G. The first gate electrode 315E and the third gate electrode 315F each have both ends in the length direction (Y-axis direction) that do not overlap the first semiconductor portion 315G.

[0091] As described above, the first TFT 315 according to the present embodiment has a double-gate (multi-gate) structure in which two gate electrodes 315E and 315F are arranged to overlap with the first semiconductor portion 315G, as shown in FIG. 20. According to the first TFT 315 having the double-gate structure as in the present embodiment, hot carrier injection is unlikely to occur even when a high voltage is applied. However, the first TFT 315 having the double-gate structure has more ends of the gate electrodes 315E and 315F than the first TFT 15 having the single-gate structure described in the first embodiment, so that ESD is more likely to occur between the ends of the gate electrodes 315E and 315F and the first semiconductor portion 315G. Therefore, the ends of the gate electrodes 315E and 315F and the first semiconductor portion 315G may be damaged due to ESD, resulting in a deterioration in yield.

[0092] In this regard, in this embodiment, the gate insulating film 333 interposed between the first gate electrode 315E and the third gate electrode 315F and the first semiconductor portion 315G has a configuration in which the film thickness changes depending on the position in the X-axis direction (first direction) as shown in Fig. 21. That is, the gate insulating film 333 has a first film thickness portion 333H, a second film thickness portion 333I having the same film thickness as the first film thickness portion 333H, a third film thickness portion 333J having a film thickness larger than the first film thickness portion 333H, a fourth film thickness portion 333K having a film thickness larger than the first film thickness portion 333H, and a fifth film thickness portion 333L having a film thickness larger than the first film thickness portion 333H, which are arranged along the X-axis direction.

[0093] As shown in FIG. 21, the first thickness portion 333H and the second thickness portion 333I are arranged at positions spaced apart from each other in the X-axis direction (first direction). The first thickness portion 333H overlaps both the first gate electrode 315E and the first semiconductor portion 315G, whereas the second thickness portion 333I is arranged to overlap both the third gate electrode 315F and the first semiconductor portion 315G. In detail, the first thickness portion 333H is arranged to overlap a part of the first semiconductor portion 315G and a central portion of the first gate electrode 315E in the X-axis direction (a portion excluding both ends 315E1, 315E2). The second thickness portion 333I is arranged to overlap a part of the first semiconductor portion 315G and a central portion of the third gate electrode 315F in the X-axis direction (a portion excluding both ends 315F1, 315F2). The dimension L301 in the X-axis direction of the first thickness portion 333H and the dimension L302 in the X-axis direction of the second thickness portion 333I are almost equal to each other. The third thickness portion 333J is sandwiched between the first thickness portion 333H and the second thickness portion 333I in the X-axis direction. That is, a space for the third thickness portion 333J is provided between the first thickness portion 333H and the second thickness portion 333I. The third thickness portion 333J is disposed so as to overlap with a central portion in the X-axis direction of the first semiconductor portion 315G. The dimension in the X-axis direction of the third thickness portion 333J is larger than the dimension in the X-axis direction of the third thickness portion 33C (see FIG. 6) described in the first embodiment. Therefore, the sum of the dimensions in the X-axis direction of the first thickness portion 333H, the second thickness portion 333I, and the third thickness portion 333J is larger than the sum of the dimensions in the X-axis direction of the first thickness portion 33A, the second thickness portion 33B, and the third thickness portion 33C (see FIG. 6) described in the first embodiment. The fourth thickness portion 333K is disposed at a position overlapping with the end portion 315E1 on one side (left side in FIG. 21) of the first gate electrode 315E in the X-axis direction. The fourth thickness portion 333K is disposed to sandwich the first thickness portion 333H between the fourth thickness portion 333K and the third thickness portion 333J in the X-axis direction. The fifth thickness portion 333L is disposed at a position overlapping with the end portion 315F1 on one side (right side in FIG. 21) of the third gate electrode 315F in the X-axis direction.The fifth thickness portion 333L is disposed so as to sandwich the second thickness portion 333I between the fifth thickness portion 333L and the third thickness portion 333J in the X-axis direction. The third thickness portion 333J is disposed so as to overlap both an end 315E2 on the other side (right side in FIG. 21) of the first gate electrode 315E in the X-axis direction and the first semiconductor portion 315G, and also overlaps both an end 315F2 on the other side (left side in FIG. 21) of the third gate electrode 315F in the X-axis direction and the first semiconductor portion 315G.

[0094] In this embodiment, the thicknesses of the first and second thickness portions 333H and 333I are set to a value such that, when a predetermined voltage (a voltage equal to or greater than a threshold voltage) is applied to the first and third gate electrodes 315E and 315F, a channel region 315G2 is generated in each of the portions of the first semiconductor portion 315G overlapping with the first and second thickness portions 333H and 333I. That is, the voltages applied to the first and third gate electrodes 315E and 315F are set to a value such that a channel region 315G2 is generated in the portions of the first semiconductor portion 315G overlapping with the first and second thickness portions 333H and 333I, which have relatively small thicknesses. Therefore, channel regions 315G2A and 315G2B are generated in each of the non-conductive regions, which are the portions of the first semiconductor portion 315G overlapping with the first and third gate electrodes 315E and 315F.

[0095] According to this configuration, when a predetermined voltage is applied to the first gate electrode 315E and the third gate electrode 315F, a channel region 315G2 is generated in the first semiconductor portion 315G. Accordingly, electrons move between the first source electrode 315B and the first drain electrode 315C through the channel region 315G2. Here, the gate insulating film 333 interposed between the first gate electrode 315E and the third gate electrode 315F and the first semiconductor portion 315G has a first thickness portion 333H, a second thickness portion 333I having the same thickness as the first thickness portion 333H, a third thickness portion 333J having a thickness larger than the first thickness portion 333H, a fourth thickness portion 333K having a thickness larger than the first thickness portion 333H, and a fifth thickness portion 333L having a thickness larger than the first thickness portion 333H. Of these, the third thick portion 333J is arranged in the X-axis direction to be sandwiched between the first thick portion 333H that overlaps with both the first gate electrode 315E and the first semiconductor portion 315G, and the second thick portion 333I that overlaps with both the third gate electrode 315F and the first semiconductor portion 315G. Therefore, compared to the conventional single gate structure, the resistance of the channel region 315G2 is higher, thereby suppressing the occurrence of hot carrier injection and suppressing deterioration of transistor performance over time. In addition, the fourth thickness portion 333K is arranged to overlap both one end 315E1 of the first gate electrode 315E in the X-axis direction and the first semiconductor portion 315G, the fifth thickness portion 333L is arranged to overlap both one end 315F1 of the third gate electrode 315F in the X-axis direction and the first semiconductor portion 315G, and the third thickness portion 333J is arranged to overlap both the other end 315E2 of the first gate electrode 315E in the X-axis direction and the first semiconductor portion 315G and to overlap both the other end 315F2 of the third gate electrode 315F in the X-axis direction and the first semiconductor portion 315G. Therefore, ESD is less likely to occur between the ends 315E1, 315E2, 315F1, 315F2 of the first gate electrode 315E and the third gate electrode 315F in the X-axis direction and the first semiconductor portion 315G.This makes it difficult for ESD to occur to the ends 315E1, 315E2, 315F1, 315F2 in the X-axis direction of the first gate electrode 315E and the third gate electrode 315F and the first semiconductor portion 315G, thereby improving the yield. In addition, since the first thickness portion 333H and the second thickness portion 333I have the same dimensions in the X-axis direction, the lengths in the X-axis direction of the channel regions 315G2A, 315G2B generated in the first semiconductor portion 315G become equal, and the resistances of these portions become equal.

[0096] As shown in FIG. 21, the gate insulating film 333 has a laminated structure of a lower insulating film 340 and an upper insulating film 341. The lower insulating film 340 is disposed on the upper layer side of the first semiconductor portion 315G. The lower insulating film 340 is made of, for example, SiO2, and has a thickness of, for example, about 100 nm. The upper insulating film 341 is disposed on the upper layer side of the lower insulating film 340 and on the lower layer side of the first gate electrode 315E. The upper insulating film 341 is made of a different material from the lower insulating film 340. The thickness of the upper insulating film 341 is smaller than the thickness of the lower insulating film 340. The upper insulating film 341 is made of, for example, SiN, and has a thickness of, for example, about 50 nm. In this manner, by forming the gate insulating film 333 as a laminated structure of a lower insulating film 340 and an upper insulating film 341 made of different materials, it is possible to easily provide a first thickness portion 333H and a second thickness portion 333I, and a third thickness portion 333J, a fourth thickness portion 333K and a fifth thickness portion 333L, each having a different thickness.

[0097] In this embodiment, the first thickness portion 333H and the second thickness portion 333I are made of the lower insulating film 340 as shown in FIG. 21. In contrast, the third thickness portion 333J, the fourth thickness portion 333K, and the fifth thickness portion 333L are made of the upper insulating film 341 and the lower insulating film 340. That is, the third thickness portion 333J, the fourth thickness portion 333K, and the fifth thickness portion 333L have the same thickness. According to this configuration, in manufacturing, the lower insulating film 340 and the upper insulating film 341 are sequentially formed, and then the upper insulating film 341 is selectively removed, so that the first thickness portion 333H and the second thickness portion 333I made of the lower insulating film 340 and the third thickness portion 333J, the fourth thickness portion 333K, and the fifth thickness portion 333L made of the lower insulating film 340 and the upper insulating film 341 can be easily provided. Furthermore, manufacturing is easier than if the third thickness portion 333J, the fourth thickness portion 333K, and the fifth thickness portion 333L were all different thicknesses.

[0098] 22, the gate insulating film 333 has a sixth thickness portion 333M having a thickness larger than that of the first thickness portion 333H. The sixth thickness portion 333M is arranged to overlap with an end portion 315G3 in the Y-axis direction (a second direction intersecting with the first direction) of the first semiconductor portion 315G. The sixth thickness portion 333M has the same thickness as the third thickness portion 333J, the fourth thickness portion 333K, and the fifth thickness portion 333L. That is, the sixth thickness portion 333M is made of the upper insulating film 341 and the lower insulating film 340, like the third thickness portion 333J, the fourth thickness portion 333K, and the fifth thickness portion 333L.

[0099] 21 and 22, the gate insulating film 333 has a seventh thickness portion 333N having a thickness larger than that of the first thickness portion 333H. The seventh thickness portion 333N constitutes a portion of the gate insulating film 333 that does not overlap with both the first gate electrode 315E and the first semiconductor portion 315G in a plan view. The seventh thickness portion 333N has the same thickness as the third thickness portion 333J, the fourth thickness portion 333K, the fifth thickness portion 333L, and the sixth thickness portion 333M. That is, the seventh thickness portion 333N is made of the upper insulating film 341 and the lower insulating film 340, like the third thickness portion 333J, the fourth thickness portion 333K, the fifth thickness portion 333L, and the sixth thickness portion 333M.

[0100] The present embodiment has the above-described structure, and the following describes the array substrate manufacturing process included in the method for manufacturing the liquid crystal panel 11. The array substrate manufacturing process includes the first to fifteenth steps described in the first embodiment, and the fourth and fifth steps, which are different from the first embodiment, will be described in detail below with reference to Figures 23 to 31. Figures 23 to 31 show the same cross-sectional configuration as Figure 21.

[0101] In the fourth step, as shown in FIG. 23, a lower insulating film 340 constituting a gate insulating film 333 is first formed in a solid state on the upper layer side of the first semiconductor portion 315G, then an upper insulating film 341 is formed in a solid state on the upper layer side of the lower insulating film 340, and then a first resist film R301 is formed in a solid state on the upper layer side of the upper insulating film 341. Then, the first resist film R301 is exposed using an exposure device and a second photomask P2 shown in FIG. 24 (first exposure step). The first resist film R301 used in the fourth step is made of a positive-type photosensitive material. Here, the second photomask P2 will be described. As shown in FIG. 24, the second photomask P2 includes a transparent second base material P2A having sufficiently high light transmittance and a second light-shielding film P2B formed on the main surface of the second base material P2A. The second light-shielding film P2B blocks exposure light from a light source of the exposure device, and the transmittance of the exposure light is set to approximately 0%. The second light-shielding film P2B has a partial opening P2B1. The opening P2B1 is sized to be equal to or larger than the resolution of an exposure tool, and allows light to pass through within its formation range.

[0102] As shown in Fig. 24, the second light-shielding film P2B has two openings P2B1 arranged in each island-shaped area overlapping the planned formation positions of the first semiconductor portions 315G in the non-display area NAA, and one opening P2B1 arranged in each island-shaped area overlapping the planned formation positions of the second semiconductor portions 324D in the display area AA. In detail, the openings P2B1 are arranged in areas overlapping the planned formation positions of the first thickness portion 333H and the second thickness portion 333I of the gate insulating film 333. On the other hand, the second light-shielding film P2B is arranged in the non-display area NAA in an area where the opening edge portion of the opening P2B1 overlaps the planned formation positions of the third thickness portion 333J, the fourth thickness portion 333K, the fifth thickness portion 333L, and the sixth thickness portion 333M of the gate insulating film 333, and a portion other than the opening edge portion of the opening P2B1 is arranged in an area where the opening edge portion of the opening P2B1 overlaps the planned formation position of the seventh thickness portion 333N.

[0103] As shown in FIG. 24, the second photomask P2 has a second light-shielding region A4 that blocks light, which is a region where the second light-shielding film P2B is formed. The light transmittance in the second light-shielding region A4 is set to approximately 0%. The second photomask P2 has a second light-transmitting region A5 that transmits light, which is a region where the opening P2B1 is formed. The second light-transmitting regions A5 are arranged in pairs at positions spaced apart from each other in the Y-axis direction (positions that overlap with the positions where the first film thickness portion 333H and the second film thickness portion 333I are to be formed) in the positions where each first semiconductor portion 315G is to be formed. The light transmittance in the second light-transmitting region A5 is set to approximately 100%. The second light-shielding region A4 and the second light-transmitting region A5 constitute an exposure pattern in the second photomask P2.

[0104] In the fourth step, the exposure light emitted from the light source of the exposure device is irradiated onto the first resist film R301 through the second photomask P2 configured as described above. The exposure amount of the first resist film R301 is different for each portion overlapping with each region A4, A5 of the second photomask P2, as shown in FIG. 24. That is, the portion of the first resist film R301 overlapping with the second light-shielding region A4 is almost not exposed and is left unexposed, and the portion overlapping with the second transmission region A5 is fully exposed. The first resist film R301 used in the fourth step is made of a positive-type photosensitive material. Therefore, when the first resist film R301 is developed after the exposure (first development step), the exposed portion of the first resist film R301 (the portion overlapping with the second transmission region A5) is removed and the unexposed portion (the portion overlapping with the second light-shielding region A4) remains, as shown in FIG. 25. In this manner, the first resist film R301 selectively remains in the portion overlapping the second light-shielding region A4 of the second photomask P2.

[0105] The gate insulating film 333 is etched using the first resist film R301 developed in this manner as a mask (first etching step). In this etching, etching conditions (such as the type of etching gas in the case of dry etching, and the type of etching solution in the case of wet etching) are set so that the etching rate for the upper insulating film 341 constituting the gate insulating film 333 is high and the etching rate for the lower insulating film 340 is low. When the first etching step is performed, as shown in FIG. 26, the upper insulating film 341 constituting the gate insulating film 333 is selectively removed in the exposed portion not covered by the first resist film R301 (the area overlapping with the second transmission region A5 of the second photomask P2), but the portion covered by the first resist film R301 (the areas overlapping with the second light-shielding region A4 of the second photomask P2) remains without being removed. The lower insulating film 340 constituting the gate insulating film 333 is not entirely removed, including the area overlapping with the second transmission region A5. As a result, the gate insulating film 333 can be easily provided with a first thickness portion 333H and a second thickness portion 333I, each of which is located in a range overlapping the second transmission region A5 of the second photomask P2 and is made of the lower layer insulating film 340, a third thickness portion 333J, each of which is located in a range overlapping the semi-transmission region A3 and is made of the lower layer insulating film 340 and the upper layer insulating film 341, and a fourth thickness portion 333K, a fifth thickness portion 333L, a sixth thickness portion 333M, and a seventh thickness portion 333N, each of which is located in a range overlapping the second light-shielding region A4 and is made of the lower layer insulating film 340 and the upper layer insulating film 341. After the etching is completed, the first resist film R301 is removed by ashing as shown in FIG. 27 (first ashing step).

[0106] After the fourth step is performed as described above, the fifth step is performed. In the fifth step, as shown in FIG. 28, the second metal film 332 is formed in a solid shape on the upper layer side of the gate insulating film 333, and then the second resist film R302 is formed in a solid shape on the upper layer side of the second metal film 332. The second resist film R302 used in the fifth step is made of a negative photosensitive material. Then, the second resist film R302 is exposed using an exposure device and a second photomask P2 (second exposure step). The second photomask P2 used in the second exposure step of this fifth step has the same exposure pattern (second light-shielding region A4 and second transmission region A5) as the second photomask P2 used in the first exposure step of the fourth step described above. In this way, the second photomask P2 having the same exposure pattern can be used in the first exposure process for exposing the first resist film R301 and the second exposure process for exposing the second resist film R302, which is advantageous in reducing the costs associated with the equipment required for manufacturing.

[0107] In the fifth step, the exposure light emitted from the light source of the exposure device is irradiated onto the second resist film R302 through the second photomask P2 having the same exposure pattern as the second photomask P2 used in the first exposure step of the fourth step. The exposure amount of the second resist film R302 is different for each part overlapping with the regions A4 and A5 of the second photomask P2, as shown in FIG. 29. That is, the part of the second resist film R302 overlapping with the second light-shielding region A4 is hardly exposed, and the part overlapping with the second transmission region A5 is fully exposed. The second resist film R302 used in the fifth step is made of a negative type photosensitive material. Therefore, when the second resist film R302 is developed after the exposure (second development step), the unexposed part of the second resist film R302 (the part overlapping with the second light-shielding region A4) is removed, and the exposed part (the part overlapping with the second transmission region A5) remains, as shown in FIG. 30. In this manner, the second resist film R302 selectively remains in the portions overlapping the second transmission regions A5 of the second photomask P2.

[0108] The second metal film 332 is etched using the second resist film R302 developed in this way as a mask (second etching step), and the first gate electrode 315E is provided in a range overlapping the second transmission region A5 of the second photomask P2 as shown in Fig. 31. The first gate electrode 315E provided through the second etching step is arranged such that both ends 315E1 and 315E2 overlap the fourth thickness portion 333K and the fifth thickness portion 333L of the gate insulating film 333 in the X-axis direction, and the central portion between both ends 315E1 and 315E2 overlaps the first thickness portion 333H, the second thickness portion 333I and the third thickness portion 333J of the gate insulating film 333. After the etching is completed, the second resist film R302 is removed by ashing as shown in Fig. 21 (second ashing step). In the fifth step, the semiconductor film is conductorized using the configuration (each gate electrode 315E, 315F, etc.) of the second metal film 332 patterned as described above as a mask. When the conductorization process is performed, dopants are selectively ion-implanted into the portion of the semiconductor film that is not covered by the configuration of the second metal film 332, and dopants are not ion-implanted into the portion that is covered by the configuration of the second metal film 332. As a result, a conductorized region 315G1 (a first conductorized region 315G1A, a second conductorized region 315G1B, and a third conductorized region 315G1C) is generated in the semiconductor film. When the sixth step is performed after the fifth step is completed in this manner, a first interlayer insulating film 334 is formed on the upper layer side of the first gate electrode 315E and then patterned (see FIG. 19).

[0109] As described above, the first TFT 315 of the present embodiment includes a first semiconductor portion 315G extending along the first direction and made of a semiconductor material, a first gate electrode (first electrode) 315E arranged so as to overlap a part of the first semiconductor portion 315G, a third gate electrode (fourth electrode) 315F arranged so as to overlap a part of the first semiconductor portion 315G and spaced apart from the first gate electrode 315E in the first direction, and a second gate electrode (fourth electrode) 315F interposed between the first gate electrode 315E and the first semiconductor portion 315G. a first source electrode 315B arranged to overlap a portion of the first semiconductor portion 315G and connected to the first semiconductor portion 315G, and a first drain electrode 315C arranged to overlap a portion of the first semiconductor portion 315G at a position spaced apart in the first direction from a connection position between the first source electrode 315B and the first semiconductor portion 315G, and connected to the first semiconductor portion 315G; and the gate insulating film 333 includes a first thickness portion 333H and a second thickness portion 333I having the same thickness as the first thickness portion 333H. a third thickness portion 333J having a thickness larger than that of the first thickness portion 333H, a fourth thickness portion 333K having a thickness larger than that of the first thickness portion 333H, and a fifth thickness portion 333L having a thickness larger than that of the first thickness portion 333H, the first thickness portion 333H being disposed at a position overlapping with both the first gate electrode 315E and the first semiconductor portion 315G, the second thickness portion 333I being disposed at a position overlapping with both the third gate electrode 315F and the first semiconductor portion 315G, the third thickness portion 333J being disposed at a position overlapping with the first thickness portion 333H in the first direction, The fourth thickness portion 333K overlaps both one end 315E1 of the first gate electrode 315E in the first direction and the first semiconductor portion 315G and is arranged with the first thickness portion 333H sandwiched between the fifth thickness portion 333L and the third thickness portion 333J, the fifth thickness portion 333L overlaps both one end 315F1 of the third gate electrode 315F in the first direction and the first semiconductor portion 315G and is arranged with the second thickness portion 333I sandwiched between the fifth thickness portion 333L and the third thickness portion 333J, and the third thickness portion 333JThe third gate electrode 315F is disposed so as to overlap both the other end 315E2 in the first direction of the first gate electrode 315E and the first semiconductor portion 315G, and also so as to overlap both the other end 315F2 in the first direction of the third gate electrode 315F and the first semiconductor portion 315G.

[0110] When a voltage equal to or greater than the threshold voltage of the first TFT 315 is applied to the first gate electrode 315E, a channel region 315G2 is generated in the first semiconductor portion 315G. Accordingly, electrons move between the first source electrode 315B and the first drain electrode 315C through the channel region 315G2. Here, the gate insulating film 333 interposed between the first gate electrode 315E and the third gate electrode 315F and the first semiconductor portion 315G has a first thickness portion 333H, a second thickness portion 333I having the same thickness as the first thickness portion 333H, a third thickness portion 333J having a thickness greater than the first thickness portion 333H, a fourth thickness portion 333K having a thickness greater than the first thickness portion 333H, and a fifth thickness portion 333L having a thickness greater than the first thickness portion 333H. Of these, the third thickness portion 333J is arranged to be sandwiched in the first direction between the first thickness portion 333H that overlaps both the first gate electrode 315E and the first semiconductor portion 315G, and the second thickness portion 333I that overlaps both the third gate electrode 315F and the first semiconductor portion 315G. Therefore, compared to the conventional single gate structure, the resistance of the channel region 315G2 is higher, thereby suppressing the occurrence of hot carrier injection and suppressing deterioration of transistor performance over time. In addition, the fourth thickness portion 333K is arranged to overlap both one end 315E1 in the first direction of the first gate electrode 315E and the first semiconductor portion 315G, the fifth thickness portion 333L is arranged to overlap both one end 315F1 in the first direction of the third gate electrode 315F and the first semiconductor portion 315G, and the third thickness portion 333J is arranged to overlap the other end 315F1 in the first direction of the first gate electrode 315E. Since the end 315E1, 315E2, 315F1, 315F2 overlaps with both the end 315E2 and the first semiconductor portion 315G, and also overlaps with the other end 315F2 in the first direction of the third gate electrode 315F and the first semiconductor portion 315G, ESD is less likely to occur between the ends 315E1, 315E2, 315F1, 315F2 of the first gate electrode 315E and the third gate electrode 315F in the first direction and the first semiconductor portion 315G.This makes it difficult for the ends 315E1, 315E2, 315F1, 315F2 in the first direction of the first gate electrode 315E and the third gate electrode 315F and the first semiconductor portion 315G to be damaged due to ESD, thereby improving the yield.

[0111] Further, in the manufacturing method of the first TFT 315 of this embodiment, a semiconductor film made of a semiconductor material is formed, and the semiconductor film is patterned to provide a first semiconductor portion 315G extending along a first direction, a gate insulating film 333 is formed on the upper side of the first semiconductor portion 315G, a first resist film R301 made of a photosensitive material is formed on the upper side of the gate insulating film 333, the first resist film R301 is exposed and developed, and the gate insulating film 333 is etched using the first resist film R301 as a mask to form a first semiconductor portion 315G that is arranged to overlap with the first semiconductor portion 315G. a first thickness portion 333H overlapping the first semiconductor portion 315G, a second thickness portion 333I arranged at a position spaced apart from the first thickness portion 333H in the first direction and having the same thickness as the first thickness portion 333H, a third thickness portion 333J arranged to be sandwiched between the first thickness portion 333H and the second thickness portion 333I in the first direction at a position overlapping the first semiconductor portion 315G and having a thickness greater than that of the first thickness portion 333H, and a third thickness portion 333J overlapping the first semiconductor portion 315G and being sandwiched between the first thickness portion 333H and the third thickness portion 333J in the first direction. a fourth thickness portion 333K arranged to sandwich the first thickness portion 333I therebetween and having a thickness greater than that of the first thickness portion 333H, and a fifth thickness portion 333L overlapping the first semiconductor portion 315G and arranged to sandwich the second thickness portion 333I between the third thickness portion 333J in the first direction and having a thickness greater than that of the first thickness portion 333H; a second metal film 332 is formed on the upper side of the gate insulating film 333, a second resist film R302 made of a photosensitive material is formed on the upper side of the second metal film 332, the second resist film R302 is exposed and developed, and the second resist film R302 is used as a mask to form a gate insulating film. 3, the second metal film 332 is etched to obtain a first gate electrode 315E having one end 315E1 in the first direction overlapping with the fourth thickness portion 333K, the other end 315E2 in the first direction overlapping with the third thickness portion 333J, and a portion between both ends 315E1, 315E2 in the first direction overlapping with the first thickness portion 333H, and a first gate electrode 315E having one end 315F1 in the first direction overlapping with the fifth thickness portion 333L, the other end 315F2 in the first direction overlapping with the third thickness portion 333J, and both ends 315F1,A third gate electrode 315F, the portion between which is 315F2 overlaps with the second thickness portion 333I, is provided, a third metal film (second conductive film) is formed above the first gate electrode 315E, and the third metal film is patterned to provide a first source electrode 315B that is arranged to overlap with a portion of the first semiconductor portion 315G and connected to the first semiconductor portion 315G, and a first drain electrode 315C that is arranged to overlap with a portion of the first semiconductor portion 315G at a position spaced apart in the first direction from the connection position between the first source electrode 315B and the first semiconductor portion 315G and connected to the first semiconductor portion 315G.

[0112] The first semiconductor portion 315G is provided by forming and patterning a semiconductor film. After the gate insulating film 333 and the first resist film R301 are formed in sequence on the upper layer side of the first semiconductor portion 315G, the first resist film R301 is exposed and developed. When the gate insulating film 333 is etched through the patterned first resist film R301, a first thickness portion 333H, a second thickness portion 333I, a third thickness portion 333J, a fourth thickness portion 333K, and a fifth thickness portion 333L are provided. After the second metal film 332 and the second resist film R302 are formed in sequence on the upper layer side of the gate insulating film 333, the second resist film R302 is exposed and developed. When the second metal film 332 is etched through the patterned second resist film R302, the first gate electrode 315E is provided. A third metal film is formed above the first gate electrode 315E and patterned to provide a first source electrode 315B and a first drain electrode 315C.

[0113] When a voltage equal to or greater than the threshold voltage of the first TFT 315 thus manufactured is applied to the first gate electrode 315E, a channel region 315G2 is generated in the first semiconductor portion 315G. Accordingly, electrons move between the first source electrode 315B and the first drain electrode 315C through the channel region 315G2. Here, the gate insulating film 333 interposed between the first gate electrode 315E and the first semiconductor portion 315G has a first thickness portion 333H, a second thickness portion 333I having the same thickness as the first thickness portion 333H, a third thickness portion 333J having a thickness greater than the first thickness portion 333H, a fourth thickness portion 333K having a thickness greater than the first thickness portion 333H, and a fifth thickness portion 333L having a thickness greater than the first thickness portion 333H. Of these, the third thickness portion 333J is arranged to be sandwiched in the first direction between the first thickness portion 333H that overlaps both the first gate electrode 315E and the first semiconductor portion 315G, and the second thickness portion 333I that overlaps both the third gate electrode 315F and the first semiconductor portion 315G. Therefore, compared to the conventional single gate structure, the resistance of the channel region 315G2 is higher, thereby suppressing the occurrence of hot carrier injection and suppressing deterioration of transistor performance over time. In addition, the fourth thickness portion 333K is arranged to overlap both one end 315E1 in the first direction of the first gate electrode 315E and the first semiconductor portion 315G, the fifth thickness portion 333L is arranged to overlap both one end 315F1 in the first direction of the third gate electrode 315F and the first semiconductor portion 315G, and the third thickness portion 333J is arranged to overlap the other end 315F1 in the first direction of the first gate electrode 315E. Since the end 315E1, 315E2, 315F1, 315F2 overlaps with both the end 315E2 and the first semiconductor portion 315G, and also overlaps with the other end 315F2 in the first direction of the third gate electrode 315F and the first semiconductor portion 315G, ESD is less likely to occur between the ends 315E1, 315E2, 315F1, 315F2 of the first gate electrode 315E and the third gate electrode 315F in the first direction and the first semiconductor portion 315G.This makes it difficult for the ends 315E1, 315E2, 315F1, 315F2 in the first direction of the first gate electrode 315E and the third gate electrode 315F and the first semiconductor portion 315G to be damaged due to ESD, thereby improving the yield.

[0114] In addition, a first resist film R301 made of a positive photosensitive material is formed on the upper side of the gate insulating film 333, and the first resist film R301 is exposed to light through a second photomask P2 having a second light-shielding area A4 that is arranged to overlap with the planned areas for forming the third thickness portion 333J, the fourth thickness portion 333K, and the fifth thickness portion 333L and blocks light, and a second transmission area A5 that overlaps with the planned areas for forming the first thickness portion 333H and the second thickness portion 333I and transmits light, and then developed. A second resist film R302 made of a negative photosensitive material is formed on the upper side of the second metal film 332, and the second resist film R302 is exposed to light through the second photomask P2 and then developed.

[0115] The first resist film R301 formed on the upper side of the gate insulating film 333 is exposed through the second photomask P2. The amount of exposure of the first resist film R301 varies depending on the portion overlapping each region of the second photomask P2. That is, the portion of the first resist film R301 overlapping with the second light-shielding region A4 is hardly exposed, and the portion overlapping with the second transmission region A5 is sufficiently exposed. Since the first resist film R301 is made of a positive photosensitive material, when it is developed, the exposed portion (the portion overlapping with the second transmission region A5) is removed, and the unexposed portion (the portion overlapping with the second light-shielding region A4) remains. The gate insulating film 333 is etched using the developed first resist film R301 as a mask to provide a first thickness portion 333H and a second thickness portion 333I located in an area overlapping with the second transmission region A5 of the second photomask P2, and a third thickness portion 333J, a fourth thickness portion 333K and a fifth thickness portion 333L located in an area overlapping with the second light-shielding region A4.

[0116] The second resist film R302 formed on the upper side of the second metal film 332 is exposed through a second photomask P2 having the same exposure pattern as the second photomask P2 used when exposing the first resist film R301. The amount of exposure of the second resist film R302 differs for each portion overlapping each region of the second photomask P2. That is, the portion of the second resist film R302 overlapping the second light-shielding region A4 is hardly exposed, and the portion overlapping the second transmission region A5 is sufficiently exposed. Since the second resist film R302 is made of a negative photosensitive material, when it is developed, the unexposed portion (the portion overlapping the second light-shielding region A4) is removed, and the exposed portion (the portion overlapping the second transmission region A5) remains. The second metal film 332 is etched using the developed second resist film R302 as a mask, thereby providing a first gate electrode 315E and a third gate electrode 315F located in an area overlapping with the second transparent region A5 of the second photomask P2.

[0117] As described above, the second photomask P2 having the same exposure pattern can be used in the process of exposing the first resist film R301 and the process of exposing the second resist film R302, which is advantageous in reducing the costs associated with the equipment required for manufacturing.

[0118] <Embodiment 5> A fifth embodiment will be described with reference to Fig. 32. In this fifth embodiment, the configuration of the semiconductor film is changed from that of the first embodiment. Note that a duplicated description of the structure, action, and effect similar to those of the first embodiment will be omitted.

[0119] As shown in FIG. 32, the semiconductor film constituting the first semiconductor portion 415D according to this embodiment uses an oxide semiconductor material as a semiconductor material. The oxide semiconductor material used in the semiconductor film may contain at least one metal element selected from In, Ga, and Zn, for example, and may be an In-Ga-Zn-O-based semiconductor (for example, indium gallium zinc oxide). Here, the In-Ga-Zn-O-based semiconductor is a ternary oxide of In (indium), Ga (gallium), and Zn (zinc), and the ratio (composition ratio) of In, Ga, and Zn is not particularly limited, and includes, for example, In:Ga:Zn=2:2:1, In:Ga:Zn=1:1:1, In:Ga:Zn=1:1:2, etc. The In-Ga-Zn-O-based semiconductor used in the semiconductor film may be amorphous or crystalline. The semiconductor film may contain other oxide semiconductors instead of the In-Ga-Zn-O-based semiconductor. For example, an In-Sn-Zn-O based semiconductor (e.g., In2O3-SnO2-ZnO; InSnZnO) may be included. The In-Sn-Zn-O based semiconductor is a ternary oxide of In (indium), Sn (tin) and Zn (zinc). Alternatively, the semiconductor film may contain an In-W-Zn-O-based semiconductor containing W (tungsten), an In-W-Sn-Zn-O-based semiconductor, an In-Al-Zn-O-based semiconductor, an In-Al-Sn-Zn-O-based semiconductor, a Zn-O-based semiconductor, an In-Zn-O-based semiconductor, a Zn-Ti-O-based semiconductor, a Cd-Ge-O-based semiconductor, a Cd-Pb-O-based semiconductor, CdO (cadmium oxide), an Mg-Zn-O-based semiconductor, an In-Ga-Sn-O-based semiconductor, an In-Ga-O-based semiconductor, a Zr-In-Zn-O-based semiconductor, an Hf-In-Zn-O-based semiconductor, an Al-Ga-Zn-O-based semiconductor, a Ga-Zn-O-based semiconductor, an In-Ga-Zn-Sn-O-based semiconductor, etc. The oxide semiconductor material of the semiconductor film has a characteristic of having a high resistance value when no voltage is applied (off state) compared to a polysilicon semiconductor material. Furthermore, the oxide semiconductor material of the semiconductor film has a higher electron mobility than the amorphous silicon semiconductor material.

[0120] As described above, according to the present embodiment, the first semiconductor portion 415D uses an oxide semiconductor material as a semiconductor material. In the first semiconductor portion 415D made of an oxide semiconductor material, the portions overlapping with the fourth thickness portion 433D and the fifth thickness portion 433E tend to have a locally high resistance due to an oxidation-reduction reaction. As a result, electric field concentration is less likely to occur in the vicinity of the first source electrode 15B and the first drain electrode 15C in the first semiconductor portion 415D, and the occurrence of hot carrier injection is further suppressed.

[0121] <Other embodiments> The technology disclosed in this specification is not limited to the embodiments described above and illustrated in the drawings, and the following embodiments, for example, are also included in the technical scope.

[0122] (1) The gate insulating film 33, 133, 333 may have an eighth thickness portion arranged at a position spaced apart from the second thickness portion 33B, 133B, 233B, 333I on the opposite side to the first thickness portion 33A, 133A, 233A, 333H in the X-axis direction, the eighth thickness portion having the same thickness as the first thickness portion 33A, 133A, 233A, 333H, and a ninth thickness portion sandwiched between the second thickness portion 33B, 133B, 233B, 333I and the eighth thickness portion in the X-axis direction, the ninth thickness portion having a thickness greater than that of the first thickness portion 33A, 133A, 233A, 333H.

[0123] (2) In the configurations described in the first, third, fourth and fifth embodiments, the first thick portion 33A, 233A, 333H and the second thick portion 33B, 233B, 333I may partially include the upper insulating film 41, 341 in addition to the lower insulating film 40, 340. That is, when etching is performed in the fourth step, the upper portion of the upper insulating film 41, 341 may be removed, and the lower portion of the upper insulating film 41, 341 may be left.

[0124] (3) In the configuration described in embodiment 3, the ratio between the dimension L201 in the X-axis direction of the first thick portion 233A and the dimension L202 in the X-axis direction of the second thick portion 233B can be changed as appropriate to a value other than that shown in the figure.

[0125] (4) In the configuration described in the fourth embodiment, the arrangement of the first gate electrode 315E and the third gate electrode 315F in the X-axis direction may be reversed.

[0126] (5) In the configuration described in the fourth embodiment, in the fifth step included in the array substrate manufacturing process, when the semiconductor film is subjected to the conductorization process, a resist mask can be used to control the range (conductorized region 315G1) into which the dopant is ion-implanted. In this case, the portions of the semiconductor film that overlap with the gate electrodes 315E and 315F can be made into the conductorized region 315G1, and the portions that do not overlap with the gate electrodes 315E and 315F can be made into the non-conductorized region. In other words, the design freedom regarding the formation ranges of the conductorized region 315G1 and the non-conductorized region is increased.

[0127] (6) In the configuration described in the fourth embodiment, the semiconductor film does not need to be subjected to a conductive treatment. In that case, electrodes may be provided to be connected to both of the portions (channel regions 315G2) of the semiconductor film that overlap with the gate electrodes 315E and 315F.

[0128] (7) The configuration described in the second embodiment may be combined with the configurations described in the third to fifth embodiments.

[0129] (8) The configuration described in the third embodiment may be combined with the configurations described in the fourth and fifth embodiments.

[0130] (9) The configuration described in the fourth embodiment may be combined with the configuration described in the fifth embodiment.

[0131] (10) The specific materials used for each film on the array substrate 21 and the specific thicknesses of each film can be changed appropriately to those not mentioned above.

[0132] (11) The first gate electrodes 15A, 215A, 315E and the third gate electrode 315F may be configured to intersect with the first semiconductor portions 15D, 215D, 315G, 415D at an angle other than 90°.

[0133] (12) The specific planar shapes of the first semiconductor portions 15D, 215D, 315G, and 415D can be appropriately changed to shapes other than those shown in the drawings. The first semiconductor portions 15D, 215D, 315G, and 415D can be bent midway as long as they include a portion extending along the X-axis direction. In addition, the specific planar shapes of the first gate electrodes 15A, 215A, and 315E and the third gate electrode 315F can also be appropriately changed to shapes other than those shown in the drawings.

[0134] (13) In the configurations described in the first to third and fifth embodiments, in each of the exposure steps included in the fourth and fifth steps, it is also possible to use a gray-tone mask as the first photomask P1 in addition to a half-tone mask.

[0135] (14) It is also possible to use different exposure patterns for the photomasks used in the fourth and fifth steps.

[0136] (15) Instead of the driver 12, an SSD (Source Shared Driving) circuit or the like may be monolithically provided on the array substrate 21. In that case, the first TFTs 15, 315 may also be included as circuit elements of the SSD circuit.

[0137] (16) The driver 12 may be attached to the flexible substrate 13 .

[0138] (17) Instead of the circuit section 14, a gate driver may be attached to the array substrate 21.

[0139] (18) It is also possible to change the stacking order of the semiconductor film and the second metal film 32, 332. That is, in the first TFT 15, 315, the gate insulating film 33, 133, 333 may be located on the upper layer side of the first gate electrode 15A, 215A, 315E and the third gate electrode 315F made of the second metal film 32, 332, and the first semiconductor portion 15D, 215D, 315G, 415D made of the semiconductor film may be located on the upper layer side of the gate insulating film 33, 133, 333. In this case, the first TFT 15, 315 is a bottom gate type. The semiconductor film may be made of an amorphous silicon thin film. The second TFT 24 is also a bottom gate type.

[0140] (19) The first TFT 15, 315 and the second TFT 24 may be of a double gate type or the like other than a top gate type or a bottom gate type.

[0141] (20) Of the pixel electrode 25 and the common electrode 28, the "upper electrode" that is the electrode located on the upper layer side may be the common electrode 28, and the "lower electrode" that is the electrode located on the lower layer side may be the pixel electrode 25. In this case, a slit is provided in the common electrode 28 that is the "upper electrode".

[0142] (21) The touch panel pattern may be a mutual capacitance type other than a self-capacitance type.

[0143] (22) The liquid crystal panel 11 may not have a touch panel pattern (touch panel function). In this case, the common electrode 28 has a non-divided structure, the touch electrode 29 is not formed, and the touch wiring 30 (third metal film) is not formed.

[0144] (23) The display mode of the liquid crystal panel 11 may be VA mode, IPS mode, or the like other than FFS mode.

[0145] (24) The liquid crystal panel 11 may be a reflective or semi-transmissive type instead of a transmissive type. If the liquid crystal panel 11 is a reflective type, the backlight device can be omitted.

[0146] (25) A display panel other than the liquid crystal panel 11 (such as an organic electroluminescence (EL) display panel) may be used. [Explanation of symbols]

[0147] 12... driver (signal supply source), 13... flexible substrate (signal supply source), 15, 315... first TFT (transistor), 15A, 215A... first gate electrode (first electrode), 15A1... one end, 15A2... other end, 15B, 315B... first source electrode (second electrode), 15C, 315C... first drain electrode (third electrode), 15D, 215D, 415D... 1 semiconductor portion (semiconductor portion), 26... gate wiring (signal supply target), 32... second metal film (first conductive film), 33, 133, 333... gate insulating film (first insulating film), 33A, 133A, 233A... first thickness portion, 33B, 133B, 233B... second thickness portion, 33C, 133C, 233C... third thickness portion, 33D, 133D, 433D... fourth thickness portion, 33E, 133E, 433E ...fifth thickness portion, 40, 340...lower insulating film, 41, 341...upper insulating film, 315E...first gate electrode (first electrode), 315E1...one end, 315E2...the other end, 315F...third gate electrode (fourth electrode), 315F1...one end, 315F2...the other end, 315G...first semiconductor portion (semiconductor portion), 333H...first thickness portion, 333I...second thickness portion, 333 J...third thickness portion, 333K...fourth thickness portion, 333L...fifth thickness portion, A1...first light-shielding region, A2...first transparent region, A3...semi-transparent region, A4...second light-shielding region, A5...second transparent region, L1, L2, L201, L202, L301, L302...dimensions, P1...first photomask, P2...second photomask, R1, R301...first resist film, R2, R302...second resist film

Claims

1. a semiconductor portion extending along a first direction and made of a semiconductor material; A first electrode disposed so as to overlap a portion of the semiconductor portion; a first insulating film interposed between the first electrode and the semiconductor portion; a second electrode disposed so as to overlap a portion of the semiconductor portion and connected to the semiconductor portion; a third electrode that is arranged to overlap a part of the semiconductor portion at a position spaced apart in the first direction from a connection position between the second electrode and the semiconductor portion and is connected to the semiconductor portion, the first insulating film has a first thickness portion, a second thickness portion having the same thickness as the first thickness portion, a third thickness portion having a thickness larger than that of the first thickness portion, a fourth thickness portion having a thickness larger than that of the first thickness portion, and a fifth thickness portion having a thickness larger than that of the first thickness portion; the first thickness portion is disposed at a position overlapping both the first electrode and the semiconductor portion, the second thickness portion overlaps both the first electrode and the semiconductor portion and is disposed at a position spaced apart from the first thickness portion in the first direction; the third thickness portion overlaps both the first electrode and the semiconductor portion and is disposed between the first thickness portion and the second thickness portion in the first direction, the fourth thickness portion is disposed so as to overlap both one end of the first electrode in the first direction and the semiconductor portion, The fifth film thickness portion is disposed so as to overlap both the other end of the first electrode in the first direction and the semiconductor portion.

2. 2. The transistor according to claim 1, wherein the first insulating film has a laminated structure including a lower insulating film arranged on the upper side of the semiconductor portion, and an upper insulating film arranged on the upper side of the lower insulating film and made of a different material than the lower insulating film.

3. 2. The transistor according to claim 1, wherein the first insulating film has a single layer structure.

4. 4. The transistor according to claim 1, wherein the third thickness portion, the fourth thickness portion, and the fifth thickness portion have the same thickness.

5. The transistor according to claim 1 , wherein the first thickness portion and the second thickness portion have the same dimension in the first direction.

6. the second electrode is connected to a signal supply source and receives a signal from the signal supply source, whereas the third electrode is connected to a signal supply target and is capable of supplying the signal to the signal supply target; the first thickness portion is located closer to the second electrode in the first direction than the third thickness portion, 4. The transistor according to claim 1, wherein the second thickness portion is located closer to the third electrode in the first direction than the third thickness portion and has a larger dimension in the first direction than the first thickness portion.

7. 4. The transistor according to claim 1, wherein the semiconductor portion uses a polysilicon semiconductor material as the semiconductor material.

8. The transistor according to claim 1 , wherein the semiconductor portion uses an oxide semiconductor material as the semiconductor material.

9. a semiconductor portion extending along a first direction and made of a semiconductor material; A first electrode disposed so as to overlap a portion of the semiconductor portion; a fourth electrode that overlaps a portion of the semiconductor portion and is disposed at a position spaced apart from the first electrode in the first direction; a first insulating film interposed between the first electrode and the semiconductor portion, and between the fourth electrode and the semiconductor portion; a second electrode disposed so as to overlap a portion of the semiconductor portion and connected to the semiconductor portion; a third electrode that is arranged to overlap a part of the semiconductor portion at a position spaced apart in the first direction from a connection position between the second electrode and the semiconductor portion and is connected to the semiconductor portion, the first insulating film has a first thickness portion, a second thickness portion having the same thickness as the first thickness portion, a third thickness portion having a thickness larger than that of the first thickness portion, a fourth thickness portion having a thickness larger than that of the first thickness portion, and a fifth thickness portion having a thickness larger than that of the first thickness portion; the first thickness portion is disposed at a position overlapping both the first electrode and the semiconductor portion, the second thickness portion is disposed at a position overlapping both the fourth electrode and the semiconductor portion, the third thickness portion is disposed between the first thickness portion and the second thickness portion in the first direction, the fourth thickness portion overlaps both one end of the first electrode in the first direction and the semiconductor portion, and is disposed with the first thickness portion sandwiched between the fourth thickness portion and the third thickness portion, the fifth thickness portion overlaps both one end of the fourth electrode in the first direction and the semiconductor portion, and is disposed between the fifth thickness portion and the third thickness portion with the second thickness portion interposed therebetween; The third thickness portion is a transistor arranged so as to overlap both the other end of the first electrode in the first direction and the semiconductor portion, and to overlap both the other end of the fourth electrode in the first direction and the semiconductor portion.

10. forming a semiconductor film made of a semiconductor material and patterning the semiconductor film to provide a semiconductor portion extending along a first direction; A first insulating film is formed on an upper layer side of the semiconductor portion; forming a first resist film made of a photosensitive material on an upper layer side of the first insulating film; The first resist film is exposed and developed; The first insulating film is etched using the first resist film as a mask to provide a first thickness portion arranged to overlap the semiconductor portion, a second thickness portion overlapping the semiconductor portion and arranged at a position spaced apart from the first thickness portion in the first direction and having the same thickness as the first thickness portion, a third thickness portion arranged to be sandwiched between the first thickness portion and the second thickness portion in the first direction at the position overlapping the semiconductor portion and having a thickness greater than that of the first thickness portion, a fourth thickness portion overlapping the semiconductor portion and arranged to sandwich the first thickness portion between the third thickness portion in the first direction and having a thickness greater than that of the first thickness portion, and a fifth thickness portion overlapping the semiconductor portion and arranged to sandwich the second thickness portion between the third thickness portion in the first direction and having a thickness greater than that of the first thickness portion, forming a first conductive film on an upper layer side of the first insulating film; forming a second resist film made of a photosensitive material on an upper layer side of the first conductive film; The second resist film is exposed and developed; by etching the first conductive film using the second resist film as a mask, a first electrode is provided, one end in the first direction overlaps with the fourth thickness portion, the other end in the first direction overlaps with the fifth thickness portion, and portions between both end portions in the first direction overlap with the first thickness portion, the second thickness portion, and the third thickness portion; A method for manufacturing a transistor, comprising: depositing a second conductive film above the first electrode; and patterning the second conductive film to provide a second electrode that is arranged to overlap a portion of the semiconductor portion and is connected to the semiconductor portion; and a third electrode that is arranged to overlap a portion of the semiconductor portion at a position spaced in the first direction from a connection position between the second electrode and the semiconductor portion and is connected to the semiconductor portion.

11. forming the first resist film made of a positive photosensitive material on an upper layer side of the first insulating film; exposing the first resist film through a first photomask having a first light-shielding region that is arranged so as to overlap with areas where the fourth thickness portion and the fifth thickness portion are to be formed and blocks light, a first transmission region that is arranged so as to overlap with areas where the first thickness portion and the second thickness portion are to be formed and transmits light, and a semi-transmission region that is arranged so as to overlap with the area where the third thickness portion is to be formed and is sandwiched between two of the first transmission regions in the first direction, and has a higher light transmittance than the first light-shielding region and a lower light transmittance than the first transmission region; and developing the first resist film through this first photomask; forming the second resist film made of a negative photosensitive material on an upper layer side of the first conductive film; 11. The method for manufacturing a transistor according to claim 10, wherein the second resist film is exposed through the first photomask and then developed.

12. forming a semiconductor film made of a semiconductor material and patterning the semiconductor film to provide a semiconductor portion extending along a first direction; A first insulating film is formed on an upper layer side of the semiconductor portion; forming a first resist film made of a photosensitive material on an upper layer side of the first insulating film; The first resist film is exposed and developed; The first insulating film is etched using the first resist film as a mask to provide a first thickness portion arranged to overlap the semiconductor portion, a second thickness portion overlapping the semiconductor portion and arranged at a position spaced apart from the first thickness portion in the first direction and having the same thickness as the first thickness portion, a third thickness portion arranged to be sandwiched between the first thickness portion and the second thickness portion in the first direction at the position overlapping the semiconductor portion and having a thickness greater than that of the first thickness portion, a fourth thickness portion overlapping the semiconductor portion and arranged to sandwich the first thickness portion between the third thickness portion in the first direction and having a thickness greater than that of the first thickness portion, and a fifth thickness portion overlapping the semiconductor portion and arranged to sandwich the second thickness portion between the third thickness portion in the first direction and having a thickness greater than that of the first thickness portion, forming a first conductive film on an upper layer side of the first insulating film; forming a second resist film made of a photosensitive material on an upper layer side of the first conductive film; The second resist film is exposed and developed; by etching the first conductive film using the second resist film as a mask, a first electrode having one end in the first direction overlapping with the fourth thickness portion, the other end in the first direction overlapping with the third thickness portion, and a portion between both ends in the first direction overlapping with the first thickness portion, and a fourth electrode having one end in the first direction overlapping with the fifth thickness portion, the other end in the first direction overlapping with the third thickness portion, and a portion between both ends in the first direction overlapping with the second thickness portion, A method for manufacturing a transistor, comprising: depositing a second conductive film above the first electrode; and patterning the second conductive film to provide a second electrode that is arranged to overlap a portion of the semiconductor portion and is connected to the semiconductor portion; and a third electrode that is arranged to overlap a portion of the semiconductor portion at a position spaced in the first direction from a connection position between the second electrode and the semiconductor portion and is connected to the semiconductor portion.

13. forming the first resist film made of a positive photosensitive material on an upper layer side of the first insulating film; exposing the first resist film through a second photomask having a second light-shielding region that is arranged so as to overlap areas where the third thickness portion, the fourth thickness portion, and the fifth thickness portion are to be formed and that blocks light, and a second light-transmitting region that is arranged so as to overlap areas where the first thickness portion and the second thickness portion are to be formed and that transmits light; and developing the first resist film; forming the second resist film made of a negative photosensitive material on an upper layer side of the first conductive film; 13. The method for manufacturing a transistor according to claim 12, wherein the second resist film is exposed through the second photomask and then developed.

Images