Semiconductor device

Abstract

To provide a semiconductor device that is miniaturized, is reduced in power consumption, and increases an arithmetic processing speed.SOLUTION: In a semiconductor device 10, a computation block 20 includes multiple memory circuits 30, a switching circuit 41, a product-sum operation circuit 42, and a dedicated operation circuit comprising an activation function operation circuit 43, a quantization operation circuit 44, and a pre-pooling operation circuit 45. Each of the multiple memory circuits has a function of holding weight data. The switching circuit has a function of switching a conductive state of one of the memory circuits and the product-sum operation circuit. The sum product-sum operation circuit outputs a first output signal based on product-sum operation processing of input data, and weight data selected by the switching circuit to the dedicated operation circuit. A layer having multiple memory circuits is provided while being laminated on a layer having the switching circuit, the product-sum operation circuit, and the dedicated operation circuit.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] This specification describes semiconductor devices and the like.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. Examples of the technical field of one embodiment of the present invention disclosed in this specification and the like include a semiconductor device, an imaging device, a display device, a light-emitting device, a power storage device, a memory device, a display system, an electronic device, a lighting device, an input device, an input / output device, a driving method thereof, or a manufacturing method thereof. [Background technology]

[0003] Electronic devices having semiconductor devices including a CPU (Central Processing Unit) and the like are in widespread use. In order to process a large amount of data at high speed in such electronic devices, there has been active technological development to improve the performance of the semiconductor devices. One technology that achieves high performance is, for example, the so-called SoC (System on Chip) in which an accelerator such as a GPU (Graphics Processing Unit) is tightly coupled with a CPU. In a semiconductor device with high performance due to the SoC, heat generation and increased power consumption become problems.

[0004] In AI (Artificial Intelligence) technology, the amount of calculations and the number of parameters become enormous, so the amount of calculations increases. Since the increase in the amount of calculations leads to an increase in heat generation and power consumption, architectures for reducing the amount of calculations have been actively proposed. Representative architectures include the Binary Neural Network (BNN) and the Ternary Neural Network (TNN), which are particularly effective in reducing circuit scale and power consumption (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0005] [Patent Document 1] International Publication No. 2019 / 078924 Summary of the Invention [Problem to be solved by the invention]

[0006] In AI technology, multiplication and accumulation calculations using weight data and input data are repeated a huge number of times, so it is necessary to store a large amount of weight data and intermediate data in the memory cell array. In addition to multiplication and accumulation calculations, AI technology generally performs processes other than multiplication and accumulation, such as activation calculations and pooling calculations. Therefore, when implementing calculations using AI technology in an integrated circuit, there is a risk that the circuit area for arranging the memory cell array and dedicated calculation circuits will increase significantly.

[0007] Furthermore, AI technology requires faster calculation processing. When AI technology calculations are implemented in an integrated circuit, weight data and intermediate data are read out to the calculation circuit via bit lines in the memory cell array. The weight data and intermediate data are read out more frequently from the bit lines. This increases the charge and discharge energy of the bit lines, which may increase power consumption.

[0008] In order to reduce the charge / discharge energy of the bit line, it is effective to shorten the bit line, but this may result in a significant increase in the area of ​​the peripheral circuitry, since the arithmetic circuits and the memory cell arrays are arranged alternately.

[0009] An object of one embodiment of the present invention is to provide a miniaturized semiconductor device.An object of one embodiment of the present invention is to provide a semiconductor device with low power consumption.An object of one embodiment of the present invention is to provide a semiconductor device with improved arithmetic processing speed.An object of one embodiment of the present invention is to provide a semiconductor device with a novel structure.

[0010] Note that one embodiment of the present invention does not necessarily have to solve all of the above problems, but only needs to solve at least one of the problems. Furthermore, the description of the above problems does not preclude the existence of other problems. Problems other than these will become apparent from the description in the specification, claims, drawings, etc., and other problems can be extracted from the description in the specification, claims, drawings, etc. [Means for solving the problem]

[0011] One embodiment of the present invention is a semiconductor device including a plurality of memory circuits, a switching circuit, a first arithmetic circuit, and a second arithmetic circuit, each of the plurality of memory circuits having a function of holding weight data, the switching circuit having a function of switching a conduction state between one of the plurality of memory circuits and the first arithmetic circuit, the first arithmetic circuit outputting a first output signal based on a product-sum operation of input data and the weight data selected by the switching circuit to the second arithmetic circuit, and the plurality of memory circuits being provided in a layer stacked on a layer having the switching circuit, the first arithmetic circuit, and the second arithmetic circuit.

[0012] One embodiment of the present invention is a semiconductor device including a plurality of memory circuits, a switching circuit, a first arithmetic circuit, and a second arithmetic circuit, each of the plurality of memory circuits having a function of holding weight data, the switching circuit having a function of switching a conduction state between one of the plurality of memory circuits and the first arithmetic circuit, the first arithmetic circuit outputting a first output signal based on a product-sum operation of input data and the weight data selected by the switching circuit to the second arithmetic circuit, the second arithmetic circuit having a function of performing an activation function operation, a quantization operation, and a first pooling operation, and the plurality of memory circuits are provided in a layer stacked on a layer having the switching circuit, the first arithmetic circuit, and the second arithmetic circuit.

[0013] One embodiment of the present invention is preferably a semiconductor device including a plurality of memory circuits, a switching circuit, a first arithmetic circuit, a second arithmetic circuit, and a third arithmetic circuit, each of the plurality of memory circuits having a function of holding weight data, the switching circuit having a function of switching a conduction state between any one of the plurality of memory circuits and the first arithmetic circuit, the first arithmetic circuit outputting a first output signal based on a product-sum operation of input data and the weight data selected by the switching circuit to the second arithmetic circuit, the second arithmetic circuit having a function of performing an activation function operation, a quantization operation, and a first pooling operation, and the third arithmetic circuit having a function of performing a second pooling operation of a second output signal output by the second arithmetic circuit, and the plurality of memory circuits are provided in a layer stacked on a layer having the switching circuit, the first arithmetic circuit, and the second arithmetic circuit.

[0014] In one embodiment of the present invention, the memory circuit preferably includes a first transistor, and the first transistor preferably includes a semiconductor layer including a metal oxide in a channel formation region.

[0015] In one embodiment of the present invention, the metal oxide is a semiconductor device containing In, Ga, and Zn.

[0016] In one embodiment of the present invention, the switching circuit, the first arithmetic circuit, and the second arithmetic circuit each include a second transistor, and the second transistor includes a semiconductor layer having silicon in a channel formation region.

[0017] Other aspects of the present invention will be described in the following embodiment and in the drawings. Effect of the Invention

[0018] According to one embodiment of the present invention, a miniaturized semiconductor device can be provided. According to another embodiment of the present invention, a semiconductor device with low power consumption can be provided. According to another embodiment of the present invention, a semiconductor device with improved arithmetic processing speed can be provided. Alternatively, a semiconductor device with a novel structure can be provided.

[0019] The description of multiple effects does not preclude the existence of other effects. In addition, one embodiment of the present invention does not necessarily have all of the exemplified effects. In addition, problems, effects, and novel features other than those described above regarding one embodiment of the present invention will become apparent from the description and drawings in this specification. [Brief description of the drawings]

[0020] [Figure 1] 1A and 1B are diagrams illustrating a configuration example of a semiconductor device. [Diagram 2] FIG. 2 is a diagram illustrating a configuration example of a semiconductor device. [Diagram 3] FIG. 3 is a diagram illustrating a configuration example of a semiconductor device. [Figure 4] 4A and 4B are diagrams illustrating a configuration example of a semiconductor device. [Diagram 5] 5A and 5B are diagrams illustrating a configuration example of a semiconductor device. [Figure 6] 6A, 6B, and 6C are diagrams for explaining configuration examples of a semiconductor device. [Figure 7] 7A and 7B are diagrams illustrating a configuration example of a semiconductor device. [Figure 8] FIG. 8 is a diagram illustrating a configuration example of a semiconductor device. [Figure 9] 9A and 9B are diagrams illustrating a configuration example of a semiconductor device. [Figure 10] FIG. 10 is a diagram illustrating a configuration example of a semiconductor device. [Figure 11] FIG. 11 is a diagram illustrating a configuration example of a semiconductor device. [Figure 12] FIG. 12 is a diagram illustrating a configuration example of a semiconductor device. [Figure 13] 13A and 13B are diagrams illustrating a configuration example of a semiconductor device. [Figure 14] 14A and 14B are diagrams illustrating a configuration example of a semiconductor device. [Figure 15]FIG. 15 is a diagram illustrating a configuration example of a semiconductor device. [Figure 16] 16A and 16B are diagrams illustrating a configuration example of a semiconductor device. [Figure 17] FIG. 17 is a diagram illustrating an example of the configuration of a computation system. [Figure 18] FIG. 18 is a diagram illustrating an example of the configuration of a CPU. [Figure 19] 19A and 19B are diagrams for explaining an example of the configuration of a CPU. [Figure 20] FIG. 20 is a diagram illustrating an example of the configuration of a CPU. [Figure 21] FIG. 21 is a diagram illustrating a configuration example of a transistor. [Figure 22] 22A and 22B are diagrams showing configuration examples of transistors. [Diagram 23] 23A and 23B are diagrams for explaining a configuration example of an integrated circuit. [Figure 24] 24A and 24B are diagrams for explaining an application example of an integrated circuit. [Diagram 25] 25A and 25B are diagrams for explaining an application example of an integrated circuit. [Figure 26] 26A, 26B, and 26C are diagrams for explaining an application example of an integrated circuit. [Figure 27] FIG. 27 is a diagram for explaining an application example of an integrated circuit. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0021] The following describes an embodiment of the present invention. However, one embodiment of the present invention is not limited to the following description, and it will be easily understood by those skilled in the art that the embodiment and details can be modified in various ways without departing from the spirit and scope of the present invention. Therefore, one embodiment of the present invention should not be interpreted as being limited to the description of the embodiment shown below.

[0022] In this specification, the ordinal numbers "first," "second," and "third" are used to avoid confusion of components. Therefore, they do not limit the number of components. Furthermore, they do not limit the order of the components. For example, a component referred to as "first" in one embodiment of this specification may be a component referred to as "second" in another embodiment or in the claims. For example, a component referred to as "first" in one embodiment of this specification may be omitted in another embodiment or in the claims.

[0023] In the drawings, the same elements or elements having similar functions, elements made of the same material, or elements formed at the same time may be given the same reference numerals, and repeated description thereof may be omitted.

[0024] In this specification, for example, the power supply potential VDD may be abbreviated to potential VDD, VDD, etc. This also applies to other components (for example, signals, voltages, circuits, elements, electrodes, wiring, etc.).

[0025] Furthermore, when the same reference symbol is used for multiple elements, particularly when it is necessary to distinguish between them, identification symbols such as “_1”, “_2”, "[n]”, "[m,n]”, etc. may be added to the reference symbol. For example, the second wiring GL is written as wiring GL[2].

[0026] (Embodiment 1) The structure, operation, and the like of a semiconductor device according to one embodiment of the present invention will be described.

[0027] In this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. Semiconductor elements such as transistors, semiconductor circuits, arithmetic devices, and memory devices are all embodiments of semiconductor devices. Display devices (such as liquid crystal display devices and light-emitting display devices), projection devices, lighting devices, electro-optical devices, power storage devices, memory devices, semiconductor circuits, imaging devices, electronic devices, and the like may be considered to include semiconductor devices.

[0028] Fig. 1A is a diagram for explaining a semiconductor device 10 according to one embodiment of the present invention, and Fig. 1B is a diagram for explaining a configuration example of a processing block included in the semiconductor device 10.

[0029] The semiconductor device 10 has a function as an accelerator that executes a program (also called a kernel or a kernel program) called from a host program. The semiconductor device 10 can perform, for example, parallel processing of matrix operations in graphic processing, parallel processing of product-sum operations in neural networks, and parallel processing of floating-point operations in scientific and technological calculations.

[0030] As shown in Fig. 1A, the semiconductor device 10 has a plurality of operation blocks 20. The operation block 20 has a memory circuit section 30 (also referred to as a memory cell array) and an operation circuit section 40. As shown in Fig. 1A and Fig. 1B, the memory circuit section 30 and the operation circuit section 40 are provided in different layers in a direction approximately perpendicular to the xy plane in the figure (z direction in Fig. 1A). In other words, the memory circuit section 30 and the operation circuit section 40 are provided in a stacked manner.

[0031] Note that "approximately perpendicular" refers to a state in which the electrodes are arranged at an angle of 85 degrees or more and 95 degrees or less. Note that in this specification, the X direction, Y direction, and Z direction shown in Figure 1B and other figures are mutually orthogonal or intersect each other. The X direction and Y direction are parallel or approximately parallel to the substrate surface, and the Z direction is perpendicular or approximately perpendicular to the substrate surface.

[0032] The memory circuit section 30 has a plurality of circuit blocks 31. Each circuit block 31 has a plurality of memory circuits 32. Writing and reading of data to the memory circuits 32 is controlled by the driving circuits 12 and 13. The driving circuits 12 and 13 are also referred to as data control circuits.

[0033] The data stored in the memory circuit 32 is data (weight data) corresponding to weight parameters used in the product-sum calculation of the neural network. By making the weight data digital data, the semiconductor device can be made resistant to noise and capable of high-speed calculation. The weight data may also be analog data.

[0034] In the layer including the memory circuit portion 30, a memory circuit 32 included in a circuit block 31 is connected to a switching circuit 41 included in the arithmetic circuit portion 40 via wirings LBL_1 to LBL_4 (also referred to as local bit lines or read bit lines) shown as an example. The memory circuit 32 included in the memory circuit portion 30 includes a transistor having an oxide semiconductor in a channel formation region (OS transistor).

[0035] A layer having an arithmetic circuit unit 40 has a switching circuit 41, a product-sum arithmetic circuit 42, an activation function arithmetic circuit 43 which is a dedicated arithmetic circuit, a quantization arithmetic circuit 44, and a pre-pooling arithmetic circuit 45. Control and processing such as input and output of data in the arithmetic circuit unit 40 are controlled by a control circuit 14 and a processing circuit 15. The control circuit 14 and the processing circuit 15 are also called an arithmetic control circuit, an arithmetic processing circuit, or an arithmetic circuit.

[0036] The switching circuit 41 has a function of selecting the potentials of the wirings LBL_1 to LBL_4 extending from each of the multiple circuit blocks 31 and transmitting the selected potential to the wiring GBL (also referred to as a global bit line). The switching circuit 41 can be, for example, a three-state buffer in which the state of the output potential is controlled by a control signal. Note that the switching circuit 41 is preferably formed of a transistor having silicon in a channel formation region (Si transistor). This configuration allows the connection state to be switched at high speed.

[0037] The wirings LBL_1 to LBL_4 (wirings LBL) are used to transmit the weight data from the memory circuit unit 30 to the arithmetic circuit unit 40. To read the weight data from the memory circuit unit 30 to the wirings LBL at high speed, it is preferable to shorten the wirings LBL. It is also preferable to shorten the wirings LBL in order to reduce the energy consumed during charging and discharging. In other words, it is preferable to configure the switching circuit 41 so that it is located close to the wirings LBL (arrows extending in the z direction in the figure) that extend in the z direction. By shortening the physical distance between the arithmetic circuit unit 40 and the memory circuit unit 30, for example, by stacking the wiring distance, it is possible to reduce the parasitic capacitance generated in the signal lines, thereby enabling low power consumption.

[0038] The product-sum operation circuit 42 has a function of executing an arithmetic process such as a product-sum operation. The product-sum operation circuit 42 may be simply called an arithmetic circuit or a first arithmetic circuit. The product-sum operation circuit 42 performs a product-sum operation between the input data input from the control circuit 14 and the weight data provided to the wiring GBL. The input data and the weight data are preferably digital data. Digital data is less susceptible to the effects of noise. Therefore, the product-sum operation circuit 42 is suitable for performing arithmetic processes that require highly accurate arithmetic results. The product-sum operation circuit 42 is preferably composed of Si transistors.

[0039] The activation function calculation circuit 43 has a function of performing processing based on an activation function on the data obtained by the product-sum calculation. Examples of the activation function that can be used include a sigmoid function, a tanh function, a softmax function, a ReLU (Rectified Linear Unit) function, and a threshold function. The ReLU function is a function that outputs "0" when the input value is negative, and outputs the input value as is when the input value is "0" or more. The activation function calculation circuit 43 is preferably composed of Si transistors.

[0040] The quantization calculation circuit 44 has a function of performing quantization calculation processing to reduce the bit width of input data in order to reduce the amount of calculation in the subsequent calculation. In multiply-and-accumulate calculation, the bit width increases due to repeated calculation processing. Therefore, the quantization calculation circuit 44 reduces the bit width by bit-shifting the input data and rounding off the data at the decimal point. The quantization calculation circuit 44 is preferably composed of Si transistors.

[0041] The pre-pooling calculation circuit 45 has a function of performing a part of the calculation of the pooling calculation process. For example, in the case of 3×3 pooling, the calculation using only some of the numerical values, rather than all the numerical values ​​in the 3×3 region, may be called pre-pooling, pre-pooling calculation process, or first pooling calculation process. Alternatively, since the pre-pooling calculation process is a calculation process that performs a part of the pooling calculation process, it may be called partial pooling calculation process or first partial pooling calculation process. In max pooling, for example, the pre-pooling calculation circuit 45 corresponds to a circuit that extracts the maximum value of data in a part of the region, for example, in one dimension, as output data of the pre-pooling calculation circuit 45. It is preferable that the pre-pooling calculation circuit 45 is composed of Si transistors.

[0042] The output data obtained by the pre-pooling arithmetic circuit 45 is output to the processing circuit 15. For example, by performing arithmetic processing in a post-pooling arithmetic circuit in the processing circuit 15, data that has been subjected to arithmetic processing equivalent to the pooling arithmetic processing can be obtained. For example, in the case of 3×3 pooling, performing pre-pooling arithmetic processing using the numerical values ​​of a 3×1 area and performing pooling arithmetic processing equivalent to 3×3 pooling using the data obtained by the pre-pooling arithmetic processing may be called post-pooling, post-pooling arithmetic processing, or second pooling arithmetic processing. Alternatively, since the post-pooling arithmetic processing is an arithmetic processing that performs a part of the pooling arithmetic processing, it may be called a partial pooling arithmetic processing or a second partial pooling arithmetic processing. A processing circuit having a post-pooling arithmetic circuit may be called an arithmetic circuit or a third arithmetic circuit. Specific examples of arithmetic processing in the pre-pooling arithmetic circuit and the post-pooling arithmetic circuit will be described later.

[0043] The switching circuit 41, the product-sum operation circuit 42, the activation function operation circuit 43, which is a dedicated operation circuit, the quantization operation circuit 44, and the prepooling operation circuit 45 can be stacked with the OS transistors by using Si transistors. That is, the memory circuit unit 30 made of OS transistors can be stacked with the operation circuit unit 40, which can be made of Si transistors. Therefore, the area in which the memory circuit unit 30 can be arranged can be increased without increasing the circuit area. By setting the area in which the memory circuit unit 30 is provided on the substrate in which the operation circuit unit 40 is provided, the memory capacity required for the operation processing in the semiconductor device 10 functioning as an accelerator can be increased compared to the case in which the memory circuit unit 30 and the operation circuit unit 40 are arranged on the same layer. By increasing the memory capacity, the number of times data required for the operation processing is transferred from an external storage device to the semiconductor device can be reduced, thereby reducing power consumption.

[0044] The memory circuit 32 of the memory circuit unit 30 can have a NOSRAM circuit configuration. "NOSRAM (registered trademark)" is an abbreviation for "Nonvolatile Oxide Semiconductor RAM." NOSRAM refers to a memory in which the memory cells are two-transistor type (2T) or three-transistor type (3T) gain cells, and the access transistors are OS transistors.

[0045] In the off state, OS transistors have an extremely small leakage current, which is the current that flows between the source and drain. NOSRAM can be used as a non-volatile memory by using its extremely small leakage current characteristic to retain a charge corresponding to the data within the memory circuit. NOSRAM in particular can read the retained data without destroying it (non-destructive readout), making it suitable for parallel processing of product-sum operations in neural networks, which require a large number of repeated data read operations.

[0046] The memory circuit 32 is preferably a memory having an OS transistor such as NOSRAM or DOSRAM (hereinafter also referred to as an OS memory). Since the band gap of a metal oxide functioning as an oxide semiconductor is 2.5 eV or more, the OS transistor has a very small off-state current. For example, when the source-drain voltage is 3.5 V and the temperature is at room temperature (25° C.), the off-state current per 1 μm of channel width is 1×10 -20 Less than A, 1×10 -22 Less than A or 1×10 -24 The amount of charge leaked from the retention node through the OS transistor in the OS memory can be made smaller than A. Therefore, the OS memory can function as a nonvolatile memory circuit, which enables power gating of the semiconductor device 10.

[0047] A semiconductor device in which transistors are integrated at a high density may generate heat due to the operation of the circuit. This heat increases the temperature of the transistor, which may change the characteristics of the transistor, causing a change in field-effect mobility and a decrease in operating frequency. OS transistors have higher heat resistance than Si transistors, so that the field-effect mobility is less likely to change due to temperature changes, and the operating frequency is also less likely to decrease. Furthermore, OS transistors tend to maintain the characteristic that the drain current increases exponentially with respect to the gate-source voltage, even when the temperature rises. Therefore, the use of OS transistors allows stable operation in high temperature environments.

[0048] Metal oxides applicable to OS transistors include Zn oxide, Zn-Sn oxide, Ga-Sn oxide, In-Ga oxide, In-Zn oxide, and In-M-Zn oxide (M is Ti, Ga, Y, Zr, La, Ce, Nd, Sn, or Hf). In particular, metal oxides using Ga as M are preferably used for OS transistors because they can be made into transistors with excellent electrical characteristics such as field effect mobility by adjusting the ratio of elements. In addition, the oxide containing indium and zinc may contain one or more elements selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and the like.

[0049] In order to improve the reliability and electrical characteristics of an OS transistor, the metal oxide applied to the semiconductor layer is preferably a metal oxide having a crystalline part, such as CAAC-OS, CAC-OS, or nc-OS. CAAC-OS is an abbreviation for c-axis-aligned crystalline oxide semiconductor. CAC-OS is an abbreviation for cloud-aligned composite oxide semiconductor. nc-OS is an abbreviation for nanocrystalline oxide semiconductor.

[0050] CAAC-OS has a c-axis orientation and a distorted crystal structure in which multiple nanocrystals are connected in the ab-plane direction. The distortion refers to a location where the lattice orientation changes between a region with a uniform lattice arrangement and a region with a different uniform lattice arrangement in the region where multiple nanocrystals are connected.

[0051] CAC-OS has the function of flowing electrons (or holes) that act as carriers, and the function of not flowing electrons that act as carriers. By separating the function of flowing electrons from the function of not flowing electrons, it is possible to maximize both functions. In other words, by using CAC-OS in the channel formation region of an OS transistor, it is possible to achieve both a high on-current and an extremely low off-current.

[0052] Metal oxides have a large band gap, electrons are less likely to be excited, and the effective mass of holes is large, so that OS transistors are less likely to experience avalanche breakdown and the like compared to general Si transistors. Therefore, for example, hot carrier degradation caused by avalanche breakdown can be suppressed. Suppressing hot carrier degradation allows OS transistors to be driven at a high drain voltage.

[0053] OS transistors are accumulation-type transistors that use electrons as majority carriers. Therefore, they are less susceptible to drain-induced barrier lowering (DIBL), which is one of the short-channel effects, compared to inversion-type transistors (typically, Si transistors) that have a pn junction. In other words, OS transistors have higher resistance to short-channel effects than Si transistors.

[0054] Because OS transistors have high resistance to short channel effects, their channel length can be reduced without degrading their reliability, and so their use can increase the degree of circuit integration. As the channel length is reduced, the drain electric field becomes stronger, but as mentioned above, OS transistors are less susceptible to avalanche breakdown than Si transistors.

[0055] In addition, because OS transistors have high resistance to short channel effects, it is possible to make the gate insulating film thicker than that of Si transistors. For example, even in a minute transistor with a channel length and width of 50 nm or less, it may be possible to provide a thick gate insulating film of about 10 nm. By making the gate insulating film thicker, the parasitic capacitance can be reduced, thereby improving the operating speed of the circuit. Furthermore, by making the gate insulating film thicker, the leakage current through the gate insulating film is reduced, which leads to a reduction in static current consumption.

[0056] As described above, the semiconductor device 10 can retain data even when the supply of power supply voltage is stopped by including the memory circuit 32, which is an OS memory. This enables power gating of the semiconductor device 10, and allows a significant reduction in power consumption.

[0057] Next, referring to FIG. 2, a block diagram showing an entire arithmetic processing system 100 including a semiconductor device 10 that functions as an AI accelerator will be described.

[0058] 2 illustrates an accelerator unit 130 having a plurality of semiconductor devices 10 described in FIG. 1A and FIG. 1B, as well as a CPU 110 and a bus 120. The CPU 110 has a CPU core 200 and a backup circuit 222. The accelerator unit 130 has a plurality of semiconductor devices 10 as well as a control unit 131 for controlling input and output of data between the semiconductor devices 10.

[0059] The CPU 110 has a function of performing general-purpose processing such as executing an operating system, controlling data, and executing various calculations and programs. The CPU 110 has a CPU core 200. The CPU core 200 corresponds to one or more CPU cores. The CPU 110 also has a backup circuit 222 that can hold data in the CPU core 200 even if the supply of power voltage is stopped. The supply of power voltage can be controlled by electrically disconnecting it from the power domain using a power switch or the like. The power voltage is sometimes called a drive voltage. For example, an OS memory having an OS transistor is suitable as the backup circuit 222.

[0060] The backup circuit 222, which is configured with OS transistors, can be stacked with the CPU core 200, which can be configured with Si transistors. Since the area of ​​the backup circuit 222 is smaller than the area of ​​the CPU core 200, the backup circuit 222 can be arranged on the CPU core 200 without increasing the circuit area. The backup circuit 222 has a function of retaining data in a register of the CPU core 200. The backup circuit 222 is also called a data retention circuit. Details of the configuration of the CPU core 200 including the backup circuit 222 having OS transistors will also be described in the third embodiment.

[0061] The control unit 131 has an internal memory circuit such as an SRAM. The control unit 131 holds output data obtained from the multiple semiconductor devices 10 in the memory circuit. The control unit 131 is configured to output the output data MAC held in the memory circuit to the multiple semiconductor devices. This configuration makes it possible to perform parallel calculations using multiple semiconductor devices with an increased parallel number.

[0062] The bus 120 electrically connects the CPU 110 and the accelerator unit 130. That is, the CPU 110 and the semiconductor device 10 can transmit data via the bus 120.

[0063] FIG. 3 is a diagram for explaining transistors suitable for the memory circuit section 30 and the arithmetic circuit section 40 in the arithmetic block 20 shown in FIG. 1B.

[0064] The memory circuit portion 30 includes a memory circuit 32. The memory circuit 32 includes a transistor 21. When the semiconductor layer 22 included in the transistor 21 is an oxide semiconductor (metal oxide), the memory circuit 32 can be formed using the above-described OS transistor.

[0065] The arithmetic circuit unit 40 includes a switching circuit 41, a product-sum arithmetic circuit 42, an activation function arithmetic circuit 43 which is a dedicated arithmetic circuit, a quantization arithmetic circuit 44, and a pre-pooling arithmetic circuit 45. Each circuit included in the arithmetic circuit unit 40 includes a transistor 23. The semiconductor layer 24 included in the transistor 23 can be made of silicon, so that each circuit included in the arithmetic circuit unit 40 includes the above-mentioned Si transistor.

[0066] By locating the memory circuit unit 30 in an area on the substrate where the arithmetic circuit unit 40 is located, it is possible to increase the storage capacity required for arithmetic processing in the semiconductor device 10 functioning as an accelerator, i.e., the number of memory circuits, compared to a case where the memory circuit unit 30 and the arithmetic circuit unit 40 are located on the same layer. By increasing the storage capacity, it is possible to reduce the number of times data required for arithmetic processing is transferred from an external storage device to the semiconductor device, thereby achieving low power consumption.

[0067] 4A is a block diagram for explaining input and output of data to and from each circuit in the semiconductor device 10 according to one embodiment of the present invention. In FIG. 4A, a switching circuit 41, a product-sum calculation circuit 42, an activation function calculation circuit 43 which is a dedicated calculation circuit, a quantization calculation circuit 44, and a pre-pooling calculation circuit 45 are illustrated.

[0068] The switching circuit 41 has a function of switching the conductive state between any one of the memory circuits 32 and the product-sum calculation circuit 42. For example, the switching circuit 41 selects the weight data W1 to W2 outputted to the wiring GBL from the data held in the memory circuit 32 in the circuit block 31 of the memory circuit unit 30. N (N is a natural number equal to or greater than 2). Then, the switching circuit 41 selects the selected weight data as weight data W SEL and outputs the result to the product-sum calculation circuit 42 via the wiring GBL.

[0069] The sum-of-products calculation circuit 42 outputs data (output signal) based on the sum-of-products calculation process of the input data and the weight data selected by the switching circuit 41 to the dedicated calculation circuit 46. For example, the sum-of-products calculation circuit 42 outputs the weight data W SEL and input data A input from the control circuit 14. IN The data MAC obtained by the product-sum calculation is output to the activation function calculation circuit 43 in the dedicated calculation circuit 46.

[0070] The dedicated arithmetic circuit 46 is a circuit for performing arithmetic processing of product-sum arithmetic processing in a neural network used for convolutional calculation, such as arithmetic processing based on an activation function, arithmetic processing for quantization, arithmetic processing for pooling arithmetic processing, or arithmetic processing for normalization (normalization). The dedicated arithmetic circuit 46 may be called an arithmetic circuit or a second arithmetic circuit. As an example, the dedicated arithmetic circuit 46 is illustrated as having a configuration including an activation function arithmetic circuit 43, a quantization arithmetic circuit 44, and a pre-pooling arithmetic circuit 45, but may have other configurations.

[0071] The activation function calculation circuit 43 performs calculation processing based on the activation function on the input data MAC, and outputs the data FUNC obtained by the calculation processing based on the activation function. The data FUNC is output to the quantization calculation circuit 44 in the dedicated calculation circuit 46.

[0072] The quantization calculation circuit 44 is a circuit for performing quantization calculation processing on the input data FUNC and outputting it as data QUA. The quantization calculation processing adjusts the bit width of the input data by bit shifting the input data and rounding off the data at the decimal point. The data QUA is output to a pre-pooling calculation circuit 45 in the dedicated calculation circuit 46.

[0073] The pre-pooling arithmetic circuit 45 is a circuit for outputting data PPD that has been subjected to pre-pooling arithmetic processing by performing a part of the pooling arithmetic processing on the input data QUA. By having the pre-pooling arithmetic circuit 45, the dedicated arithmetic circuit 46 can perform a part of the pooling arithmetic processing. The data PPD is output to a post-pooling arithmetic circuit 47 included in the processing circuit 15, as shown in FIG. 4B. The processing circuit 15 including the post-pooling arithmetic circuit 47 may be called an arithmetic circuit or a third arithmetic circuit.

[0074] The post-pooling calculation circuit 47 is a circuit for performing calculation processing on the input data PPD and outputting data PD that has been subjected to pooling calculation processing on the data QUA. By having the post-pooling calculation circuit 47, the processing circuit 15 can reduce the area compared to when performing all calculation processing of the pooling calculation processing. The data PD is converted into the input data A by the control circuit 14. IN It is used as.

[0075] Fig. 5A is a diagram for explaining an example of a circuit configuration applicable to the circuit block 31 of the memory circuit unit 30 in the semiconductor device 10 of the present invention. Fig. 5A illustrates write word lines WWL_1 to WWL_M, read word lines RWL_1 to RWL_M, write bit lines WBL_1 to WBL_N, and wirings LBL_1 to LBL_N arranged in a matrix of M rows and N columns (M and N are natural numbers of 2 or more). Also illustrated is a memory circuit 32 connected to each word line and bit line.

[0076] 5B is a diagram illustrating an example of a circuit configuration applicable to the memory circuit 32. The memory circuit 32 includes a transistor 61, a transistor 62, a transistor 63, and a capacitor 64 (also referred to as a capacitor).

[0077] One of the source or drain of the transistor 61 is connected to the write bit line WBL. The gate of the transistor 61 is connected to the write word line WWL. The other of the source or drain of the transistor 61 is connected to one electrode of the capacitance element 64 and the gate of the transistor 62. One of the source or drain of the transistor 62 and the other electrode of the capacitance element 64 are connected to a wiring that provides a fixed potential, such as a ground potential. The other of the source or drain of the transistor 62 is connected to one of the source or drain of the transistor 63. The gate of the transistor 63 is connected to the read word line RWL. The other of the source or drain of the transistor 63 is connected to a wiring LBL. The wiring LBL is connected to a wiring GBL via a switching circuit 41. The wiring LBL is connected to the switching circuit 41 via a wiring that is provided so as to extend in a direction substantially perpendicular to the substrate surface on which the Si transistors of the arithmetic circuit unit 40 are provided.

[0078] The circuit configuration of the memory circuit 32 shown in FIG. 5B corresponds to a NOSRAM of a three-transistor type (3T) gain cell. Transistors 61 to 63 are OS transistors. In the off state, the current flowing between the source and drain of an OS transistor, that is, the leakage current, is extremely small. NOSRAM can be used as a non-volatile memory by using the characteristic of extremely small leakage current to hold charges corresponding to data in the memory circuit.

[0079] The circuit configuration applicable to the memory circuit 32 in Fig. 5A is not limited to the 3T type NOSRAM in Fig. 5B. For example, a circuit equivalent to the DOSRAM illustrated in Fig. 6A may be used. Fig. 6A illustrates a memory circuit 32A having a transistor 61A and a capacitance element 64A. The transistor 61A is an OS transistor. The memory circuit 32A is illustrated as an example connected to a bit line BL, a word line WL, and a back gate line BGL.

[0080] The circuit configuration applicable to the memory circuit 32 of FIG. 5A may be a circuit corresponding to a 2T-type NOSRAM illustrated in FIG. 6B. FIG. 6B illustrates a memory circuit 32B having a transistor 61B, a transistor 62B, and a capacitance element 64B. The transistors 61B and 62B are OS transistors. The transistors 61B and 62B may be OS transistors having semiconductor layers arranged in different layers, or may be OS transistors having semiconductor layers arranged in the same layer. The memory circuit 32B is illustrated as an example connected to a write bit line WBL, a wiring LBL functioning as a read bit line, a write word line WWL, a read word line RWL, a source line SL, and a back gate line BGL.

[0081] The circuit configuration applicable to the memory circuit 32 of FIG. 5A may be a circuit combining 3T-type NOSRAMs shown in FIG. 6C. FIG. 6C illustrates a memory circuit 32C having a memory circuit 32_P and a memory circuit 32_N that can hold data with different logic. FIG. 6C illustrates a memory circuit 32_P having a transistor 61_P, a transistor 62_P, a transistor 63_P, and a capacitance element 64_P, and a memory circuit 32_N having a transistor 61_N, a transistor 62_N, a transistor 63_N, and a capacitance element 64_N. Each transistor in the memory circuit 32_P and the memory circuit 32_N is an OS transistor. Each transistor in the memory circuit 32_P and the memory circuit 32_N may be an OS transistor having a semiconductor layer arranged in different layers, or may be an OS transistor having a semiconductor layer arranged in the same layer. The memory circuit 32C is illustrated as being connected to a write bit line WBL_P, a wiring LBL_P, a write bit line WBL_N, a wiring LBL_N, a write word line WWL, and a read word line RWL. The memory circuit 32C can hold data of different logic and read out data of different logic to the wiring LBL_P and the wiring LBL_N.

[0082] 6C, an exclusive OR circuit (XOR circuit) may be provided so that data equivalent to the multiplication of data held in the memory circuit 32_P and the memory circuit 32_N is output to the wiring LBL. With this configuration, it is possible to omit the operation equivalent to the multiplication in the product-sum operation circuit 42, thereby achieving low power consumption.

[0083] 7A is a diagram for explaining the switching circuit 41. In FIG. 7A, it is assumed that weight data W1 to W6 are read out from the memory circuit 32 in the circuit block 31 to the wirings LBL_1 to LBL_6. Also, the weight data selected from the weight data W1 to W6 by the switching circuit 41 and provided to the wiring GBL is weight data W SEL The sum-of-products calculation circuit 42 receives input data A IN is given, and a data MAC corresponding to the multiply-and-accumulate data is obtained.

[0084] The wiring LBL_1 to LBL_6 extends in the vertical direction to connect the upper and lower layers. P is shorter than the wirings extending in the horizontal direction. Therefore, the parasitic capacitance of the wirings LBL_1 to LBL_6 can be reduced, and the charge required for charging and discharging the wirings can be reduced, resulting in low power consumption and improved computing efficiency. In addition, the readout from the memory circuit 32 to the wirings LBL_1 to LBL_6 can be performed at high speed.

[0085] The weight data W SEL The weight data W SEL can be configured to provide the sum-of-products operation circuits 42 via wiring GBL. This configuration is suitable for the arithmetic processing of a convolutional neural network that performs arithmetic processing using the same weight data.

[0086] Fig. 7B is an example of a circuit configuration applicable to the switching circuit 41 shown in Fig. 7A. The three-state buffer shown in Fig. 7B has a function of amplifying and transmitting the potential of the wiring LBL to the wiring GBL in response to a control signal EN. The switching circuit 41 can be regarded as a multiplexer. It has a function of selecting one of multiple input signals.

[0087] In FIG. 7A, the switching circuit 41 selects one of the multiple wirings LBL and outputs the weight data W SEL is provided to the wiring GBL is illustrated, but other configurations may be used. For example, a configuration in which a plurality of switching circuits are provided as the switching circuit may be used. In addition, in FIG. 7A, a configuration in which each memory circuit 32 holds 1-bit data (i.e., data of '1' or '0') and performs arithmetic processing using the data has been described, but one embodiment of the present invention can also be applied to a configuration in which arithmetic processing is performed using multi-bit data. In the case of multi-bit (e.g., n-bit) data, a configuration may be used in which multi-bit weight data to be provided to the wiring GBL is selected using a switching circuit 41 connected to the wirings LBL_1 to LBL_n, the number of which corresponds to the number of bits.

[0088] When the memory circuit unit 30 and the arithmetic circuit unit 40 are separate chips, the bus width is limited according to the number of pins on the chip. On the other hand, in a configuration in which the memory circuit unit 30 and the arithmetic circuit unit 40 are stacked as in one embodiment of the present invention, the number of parallel data required for arithmetic processing can be increased according to the opening where the wiring LBL is provided, making it possible to perform arithmetic processing efficiently.

[0089] Fig. 8 shows a timing chart for explaining the operation of each component described in Fig. 7A. The product-sum calculation circuit 42 performs calculation processing in response to the toggle operation (e.g., time T0 to T6) of the clock signal CLK. By adopting a configuration that increases the frequency of the clock signal CLK, it is possible to speed up the calculation processing.

[0090] Input data A IN When the weight data is to be switched at high speed in response to the clock signal CLK, the data of the wiring GBL which provides the weight data must be switched at high speed.

[0091] In one embodiment of the present invention, the weight data selected from the wiring LBL to the wiring GBL by the switching circuit 41 is read out in advance to the wirings LBL_1 to LBL_6, so that the data of the wiring GBL to which the weight data is applied can be switched at high speed. For example, the weight data W1 can be read out to the wiring LBL_1 at time T0, and the switching circuit 41 can be switched at time T1 to output the weight data W1 from the wiring LBL_1 to the wiring GBL. At times T1 to T6, the weight data W1 to W6 are read out to the wiring LBL, and the weight data W1 on the wiring GBL is output. SEL By differentiating the selection of and the time of, the weight data W according to the clock signal CLK is SEL The above-mentioned switching may be performed.

[0092] FIG. 9A shows a specific example of the configuration of the product-sum operation circuit 42. FIG. 9A illustrates an example of the configuration of the product-sum operation circuit 42 that can perform product-sum operation on 8-bit weight data and 8-bit input data. FIG. 9A illustrates a multiplication circuit 51, an addition circuit 52, and a register 53. The 16-bit data multiplied by the multiplication circuit 51 is input to the addition circuit 52. The output of the addition circuit 52 is held in the register 53, and is added to the data multiplied by the multiplication circuit 51 by the addition circuit 52 to perform the product-sum operation. The register 53 is controlled by a clock signal CLK and a reset signal reset_B. Note that "α" in "17+α" in the figure indicates a carry that occurs when the multiplied data is added. With this configuration, the weight data W SEL and input data A IN It is possible to obtain a data MAC equivalent to a multiply-and-accumulate operation with

[0093] In addition, although Fig. 9A has been described as a configuration in which arithmetic processing is performed using 8-bit data, one embodiment of the present invention can also be applied to a configuration in which 1-bit data is used. This configuration is illustrated in Fig. 9B, similarly to Fig. 9A. In the case of 1-bit data, arithmetic processing according to the number of bits may be performed, as illustrated in Fig. 9B.

[0094] Fig. 10 is a diagram showing a configuration example of the above-mentioned activation function calculation circuit 43. The activation function calculation circuit 43 shown in Fig. 10 is a circuit having a function of calculating an activation function based on a ReLU function, as an example.

[0095] The activation function calculation circuit 43 shown in FIG. 10 has a plurality of multiplexers 54. For example, 8-bit data MAC[0] to MAC[7] is input to the multiplexer 54. Data 0 is also input to the multiplexer 54. The multiplexer 54 outputs data MAC[0] to MAC[7] or data 0 as data FUNC[0] to FUNC[7] depending on data MAC[7], which is the most significant bit of data MAC. When data MAC is a signed integer, if the most significant bit of data MAC is 0, it represents a positive value, and if it is 1, it represents a negative value. Therefore, the activation function calculation circuit 43 can calculate an activation function based on the ReLU function.

[0096] Fig. 11 is a diagram showing a configuration example of the above-mentioned pre-pooling calculation circuit 45. The pre-pooling calculation circuit 45 shown in Fig. 11 is a circuit having a function of performing calculation of a pre-pooling calculation process based on max pooling, as an example.

[0097] The pre-pooling calculation circuit 45 shown in FIG. 11 has a comparison circuit 55 and a register 56. The comparison circuit 55 receives data to be an initial value or data input from the register 56 and data QUA output from the quantization calculation circuit 44. The comparison circuit 55 compares the two input data and outputs the data with a larger value to the register 56 as data QUA[C]. The data QUA[C] is held in the register 56. The held data QUA[C] becomes data PPD, which is an output signal of the pre-pooling calculation circuit 45, or data QUA[MAX] input to the comparison circuit 55.

[0098] The operation of the pre-pooling calculation circuit 45 will be described with reference to Fig. 12. In Fig. 12, it is assumed that data QUA[1], data QUA[2] to data QUA[N] are input one after another as data QUA output from the quantization calculation circuit 44 in response to changes in the clock signal CLK. The comparison circuit 55 sets data input as an initial value to data QUA[0].

[0099] In period P1, data QUA[0] and data QUA[1] are input to the comparison circuit 55. If data QUA[1] is greater than data QUA[0], data QUA[1] is held in the register 56 as output data of the comparison circuit 55, that is, data QUA[C].

[0100] Next, in period P2, data QUA[2] is input to the comparator circuit 55 in response to a change in the clock signal CLK. In addition, data QUA[1] held in the register 56 during period P1 is input to the comparator circuit 55. If data QUA[2] is larger than data QUA[1], data QUA[2] is output from the comparator circuit 55, that is, data QUA[C] is held in the register 56.

[0101] The comparator circuit 55 compares the values ​​of the data QUA input in order, and holds the larger data in the register 56, so that the largest data QUA[MAX] of the input data QUA is held in the register 56. In the period PN, the data QUA[N] is input to the comparator circuit 55. The comparator circuit 55 also receives the data QUA[MAX] held in the register 56 up to the period P(N-1). If the data QUA[MAX] is larger than the data QUA[N], the data QUA[MAX] is output from the comparator circuit 55, that is, is held in the register 56 as the data QUA[C]. The data QUA[MAX] held in the register 56 is then output as the data PPD.

[0102] The operation described in FIG. 12 is performed by a plurality of dedicated calculation circuits, and the obtained data PPD is compared again, whereby data PD obtained by pooling calculation processing can be obtained.

[0103] For example, a case where the dedicated arithmetic circuits 46_1 to 46_3 are provided as in the configuration example shown in FIG. 13A and 3×3 pooling arithmetic processing is performed will be described. In the dedicated arithmetic circuits 46_1 to 46_3, the data QUA[1] to [9] from the quantization arithmetic circuit 44 is divided and processed, and the pre-pooling arithmetic circuit 45 can obtain the data PPD[1] to [3]. That is, the pre-pooling arithmetic circuit 45 can extract the maximum value of the data in one dimension as the data PPD output from the pre-pooling arithmetic circuit 45. The data PPD[1] to [3] are compared by the post-pooling arithmetic circuit 47 in the processing circuit 15 to obtain the data PD. The post-pooling arithmetic circuit 47 has the function of a comparison circuit that compares the magnitude of the value of the input data PPD. That is, the post-pooling arithmetic circuit 47 can extract the maximum value of the two-dimensional data that is 3×3, that is, the data PD that is the max pooling of 3×3, as output data.

[0104] In the example of FIG. 13A, the data QUA[1] to [9] are divided and processed by the operation shown in FIG. 13B, and the pre-pooling calculation circuit 45 can obtain the data PPD[1] to [3]. For example, the dedicated calculation circuit 46_1 compares the data QUA[1] to [3] to obtain the data PPD[1]. The dedicated calculation circuit 46_2 compares the data QUA[4] to [6] to obtain the data PPD[2]. The dedicated calculation circuit 46_3 compares the data QUA[7] to [9] to obtain the data PPD[3]. With this configuration, the data PPD can be obtained with a small number of clocks because the data PPD is obtained using different dedicated calculation circuits.

[0105] 14A, when data PD is obtained by outputting data QUA[1] to [9] from a plurality of quantization calculation circuits 44_1 to 44_9 to a post-pooling calculation circuit 47 without obtaining data PPD from the pre-pooling calculation circuit 45, the number of wirings for transmitting data increases. Therefore, it may be difficult to reduce the size and power consumption of the semiconductor device 10.

[0106] Furthermore, for example, as shown in FIG. 14B, when data PD is obtained by comparing data QUA[1] to [9] input to one pre-pooling arithmetic circuit 45, it may take time to obtain the data PD depending on the number of data QUA, making it difficult to speed up the arithmetic processing in the semiconductor device 10.

[0107] In the configuration of the semiconductor device 10 in this embodiment, when each arithmetic process in the neural network is performed by a dedicated arithmetic circuit, in a configuration in which arithmetic processes are performed using multiple data such as pooling arithmetic processes, it is possible to configure the semiconductor device 10 to perform distributed arithmetic processes. In addition, since the wiring connecting the dedicated arithmetic circuit and the product-sum arithmetic circuit can be shortened, it is possible to suppress an increase in the area required for arranging the dedicated arithmetic circuit. In addition, since it is possible to configure the dedicated arithmetic circuit to have multiple memory circuits, it is possible to increase the area in which the memory circuits can be arranged. As a result, a huge number of weight data can be held in the memory circuit section, and the number of times weight data is transferred from an external memory circuit can be reduced, thereby achieving low power consumption.

[0108] Fig. 15 illustrates an example of the configuration of the memory circuit section 30, which is stacked on the arithmetic circuit section 40, and its peripheral circuits, as described in Fig. 1A and Fig. 1B. Specifically, Fig. 15 illustrates the drive circuit 12, the drive circuit 13, the control circuit 14, the processing circuit 15, the switching circuit 41, the product-sum calculation circuit 42, the activation function calculation circuit 43, the quantization calculation circuit 44, and the pre-pooling calculation circuit 45. Fig. 15 also illustrates a post-pooling calculation circuit 47 in the processing circuit 15.

[0109] Although not shown in FIG. 15, each circuit in FIG. 15 is configured to receive and input control signals for controlling each circuit, input data, and output data from and to an external circuit.

[0110] Fig. 16A is a diagram in which blocks that control the memory circuit unit 30 are extracted from each configuration shown in Fig. 15. In Fig. 16A, in addition to the memory circuit 32 included in the circuit block 31 in the memory circuit unit 30, the drive circuit 12 and the drive circuit 13 are extracted and illustrated.

[0111] The driving circuits 12 and 13 process input signals from the outside to generate signals for writing weight data to the memory circuits and signals for reading weight data from the memory circuits. The generated signals are provided to the memory circuits via wiring.

[0112] Fig. 16B is a diagram in which blocks for controlling the arithmetic circuit unit 40 are extracted from each configuration shown in Fig. 15. Fig. 16B illustrates the switching circuit 41, the product-sum calculation circuit 42, the activation function calculation circuit 43, the quantization calculation circuit 44, and the pre-pooling calculation circuit 45 of the arithmetic circuit unit 40, as well as the control circuit 14, the processing circuit 15, and the post-pooling calculation circuit 47 in the processing circuit 15.

[0113] The control circuit 14 receives input data A IN The control circuit 14 outputs a control signal for controlling the switching circuit 41. The switching circuit 41 selects the weight data read from the memory circuit 32 and outputs the weight data W SEL The activation function calculation circuit 43, the quantization calculation circuit 44, and the pre-pooling calculation circuit 45, which are dedicated calculation circuits, perform calculation processing of the data MAC generated by the product-sum calculation circuit 42, and output the data PPD that has been subjected to the pre-pooling calculation processing to the post-pooling calculation circuit 47 in the processing circuit 15. The post-pooling calculation circuit 47 in the processing circuit 15 outputs the data PD that has been subjected to the pooling calculation processing to the control circuit 14, and the control circuit 14 converts the input data A IN The generated data is re-input to the arithmetic circuit section 40.

[0114] In the semiconductor device 10, the control circuit 14 can output the processed data as input data to the arithmetic circuit unit 40 again. Therefore, the arithmetic process can be executed without reading the data in the middle of the calculation to a main memory or the like outside the semiconductor device 10. In addition, in the semiconductor device 10, the electrical connection between the memory circuit unit and the arithmetic circuit unit can be made through wiring in an opening provided in an insulating film or the like, so that the number of parallel operations can be increased by increasing the number of wirings. Therefore, in the semiconductor device 10, parallel calculation of a number of bits greater than the data bus width of the CPU 110 is possible. In addition to the sum-of-products calculation circuit, a circuit for performing dedicated calculation processing such as activation function calculation processing is stacked with the memory circuit, so that the area in which the memory circuit can be arranged can be increased. As a result, a huge number of weight data can be held in the memory circuit unit, and the number of times weight data is transferred from the external memory circuit can be reduced, thereby achieving low power consumption.

[0115] In one embodiment of the present invention, a configuration in which one arithmetic process such as pooling arithmetic process is distributed to multiple locations to perform the process can shorten the wiring connecting the dedicated arithmetic circuit and the product-sum arithmetic circuit. Therefore, a configuration in which arithmetic process is distributed to multiple locations to perform the process is effective in suppressing an increase in the area required to arrange the dedicated arithmetic circuit. This configuration is also effective in a configuration in which the memory circuit unit and the arithmetic circuit unit shown in FIG. 1 are not stacked, for example, in the configurations shown in FIG. 15, FIG. 16A, and FIG. 16B, the memory circuit unit 30, the arithmetic circuit unit 40, and peripheral circuits such as the drive circuit 12, the drive circuit 13, the control circuit 14, and the processing circuit 15 are composed of Si transistors, and the memory circuit unit 30 and the arithmetic circuit unit 40 are not stacked.

[0116] As described above, one embodiment of the present invention can provide a miniaturized semiconductor device that functions as an accelerator. Alternatively, one embodiment of the present invention can provide a semiconductor device that functions as an accelerator and has low power consumption. Alternatively, one embodiment of the present invention can provide a semiconductor device that functions as an accelerator and has a novel structure.

[0117] (Embodiment 2) In this embodiment, an example of an operation in the case where part of the calculations of a program executed by the CPU 110 described in the above embodiment is executed by an accelerator described as the semiconductor device 10 will be described.

[0118] FIG. 17 is a diagram for explaining an example of an operation when part of the calculations of a program executed by a CPU is executed by an accelerator.

[0119] The host program is executed by the CPU (host program execution; step S1).

[0120] When the CPU confirms an instruction to reserve an area for data required when performing calculations using the accelerator in the memory circuit unit (memory reserve instruction; step S2), it reserves the area for data in the memory circuit unit (memory reserve; step S3).

[0121] Next, the CPU transmits weight data, which is input data, from the main memory or an external storage device to the memory circuit unit (data transmission; step S4). The memory circuit unit receives the weight data and stores the weight data in the area secured in step S3 (data reception; step S5).

[0122] When the CPU confirms an instruction to start the kernel program (start of kernel program; step S6), the accelerator starts executing the kernel program (start of operation; step S7).

[0123] Immediately after the accelerator starts executing the kernel program, the CPU may be switched from a state performing calculations to a PG (power gating) state (PG state transition; step S8). In this case, the CPU is switched from the PG state to a state performing calculations (PG state stop; step S9) immediately before the accelerator finishes executing the kernel program. By putting the CPU into the PG state during the period from step S8 to step S9, it is possible to suppress power consumption and heat generation in the entire calculation processing system.

[0124] When the accelerator finishes the execution of the kernel program, the output data is stored in a storage unit that holds the calculation results in the accelerator (end of calculation; step S10).

[0125] After the execution of the kernel program is completed, if the CPU confirms an instruction to transmit output data stored in the memory unit to the main memory or an external storage device (data transmission request; step S11), the output data is transmitted to the main memory or the external storage device and stored in the main memory or the external storage device (data transmission; step S12).

[0126] By repeating the above operations from step S1 to step S12, it is possible to suppress the power consumption and heat generation of the CPU and the accelerator, while allowing the accelerator to execute part of the computations executed by the CPU. The semiconductor device according to one embodiment of the present invention has a non-von Neumann architecture, and can perform computations with extremely low power consumption compared to a von Neumann architecture, which consumes a lot of power as the processing speed increases.

[0127] This embodiment mode can be appropriately combined with the descriptions of other embodiment modes.

[0128] (Embodiment 3) In this embodiment, an example of a CPU having a CPU core capable of power gating will be described.

[0129] 18 shows an example of the configuration of the CPU 110. The CPU 110 has a CPU core (CPU Core) 200, an L1 (level 1) cache memory device (L1 Cache) 202, an L2 cache memory device (L2 Cache) 203, a bus interface unit (Bus I / F) 205, power switches 210 to 212, and a level shifter (LS) 214. The CPU core 200 has a flip-flop 220.

[0130] The CPU core 200 , the L1 cache memory device 202 , and the L2 cache memory device 203 are interconnected via a bus interface unit 205 .

[0131] The PMU 193 generates a clock signal GCLK1 and various PG (power gating) control signals in response to interrupt signals (Interrupts) input from the outside and signals such as a signal SLEEP1 issued by the CPU 110. The clock signal GCLK1 and the PG control signals are input to the CPU 110. The PG control signals control the power switches 210 to 212 and the flip-flop 220.

[0132] Power switches 210 and 211 respectively control the supply of voltages VDDD and VDD1 to a virtual power line V_VDD (hereinafter referred to as a V_VDD line). A power switch 212 controls the supply of a voltage VDDH to a level shifter (LS) 214. A voltage VSSS is input to the CPU 110 and the PMU 193 without passing through a power switch. A voltage VDDD is input to the PMU 193 without passing through a power switch.

[0133] The voltages VDDD and VDD1 are drive voltages for the CMOS circuits. The voltage VDD1 is lower than the voltage VDDD and is the drive voltage in the sleep state. The voltage VDDH is a drive voltage for the OS transistors and is higher than the voltage VDDD.

[0134] Each of the L1 cache memory device 202, the L2 cache memory device 203, and the bus interface unit 205 has at least one power domain that can be power-gated. The power domain that can be power-gated is provided with one or more power switches. These power switches are controlled by a PG control signal.

[0135] The flip-flop 220 is used as a register. A backup circuit is provided in the flip-flop 220. The flip-flop 220 will be described below.

[0136] 19A shows an example of the circuit configuration of the flip-flop 220. The flip-flop 220 includes a scan flip-flop 221 and a backup circuit 222.

[0137] The scan flip-flop 221 has nodes D1, Q1, SD, SE, RT, CK, and a clock buffer circuit 221A.

[0138] Node D1 is a data input node, node Q1 is a data output node, and node SD is an input node for scan test data. Node SE is an input node for signal SCE. Node CK is an input node for clock signal GCLK1. Clock signal GCLK1 is input to clock buffer circuit 221A. Analog switches of scan flip-flop 221 are connected to nodes CK1 and CKB1 of clock buffer circuit 221A. Node RT is an input node for a reset signal.

[0139] A signal SCE is a scan enable signal, and is generated by the PMU 193. The PMU 193 generates signals BK and RC. A level shifter 214 level-shifts the signals BK and RC to generate signals BKH and RCH. The signal BK is a backup signal, and the signal RC is a recovery signal.

[0140] The circuit configuration of the scan flip-flop 221 is not limited to that shown in Fig. 19. Flip-flops provided in a standard circuit library can be applied.

[0141] The backup circuit 222 includes nodes SD_IN and SN11, transistors M11 to M13, and a capacitive element C11.

[0142] The node SD_IN is an input node for scan test data, and is connected to the node Q1 of the scan flip-flop 221. The node SN11 is a storage node of the backup circuit 222. The capacitive element C11 is a storage capacitor for storing the voltage of the node SN11.

[0143] The transistor M11 controls the conduction state between the node Q1 and the node SN11. The transistor M12 controls the conduction state between the node SN11 and the node SD. The transistor M13 controls the conduction state between the node SD_IN and the node SD. The on / off of the transistors M11 and M13 is controlled by a signal BKH, and the on / off of the transistor M12 is controlled by a signal RCH.

[0144] The transistors M11 to M13 are OS transistors, similar to the transistors 61 to 63 included in the above-described memory circuit 32. The transistors M11 to M13 are illustrated as having back gates. The back gates of the transistors M11 to M13 are connected to a power supply line that supplies a voltage VBG1.

[0145] At least the transistors M11 and M12 are preferably OS transistors. OS transistors have an extremely small off-state current, which can suppress a voltage drop at the node SN11 and consume almost no power to retain data, so that the backup circuit 222 has nonvolatile characteristics. Since data is rewritten by charging and discharging the capacitive element C11, the backup circuit 222 is theoretically capable of writing and reading data without any restrictions on the number of times it can be rewritten, and can write and read data with low energy.

[0146] It is highly preferable that all the transistors in the backup circuit 222 are OS transistors. As shown in Fig. 19B, the backup circuit 222 can be stacked on a scan flip-flop 221 that is configured with a silicon CMOS circuit.

[0147] Since the backup circuit 222 has a very small number of elements compared to the scan flip-flop 221, there is no need to change the circuit configuration and layout of the scan flip-flop 221 in order to stack the backup circuit 222. In other words, the backup circuit 222 is a highly versatile backup circuit. In addition, since the backup circuit 222 can be provided in the region in which the scan flip-flop 221 is formed, the area overhead of the flip-flop 220 can be reduced to zero even if the backup circuit 222 is incorporated. Therefore, by providing the backup circuit 222 in the flip-flop 220, power gating of the CPU core 200 becomes possible. Since little energy is required for power gating, the CPU core 200 can be power gated with high efficiency.

[0148] By providing the backup circuit 222, a parasitic capacitance due to the transistor M11 is added to the node Q1, but since it is small compared to the parasitic capacitance due to the logic circuit connected to the node Q1, it does not affect the operation of the scan flip-flop 221. In other words, even if the backup circuit 222 is provided, the performance of the flip-flop 220 does not substantially deteriorate.

[0149] For example, a clock gating state, a power gating state, or a pause state can be set as the low power consumption state of the CPU core 200. The PMU 193 selects the low power consumption mode of the CPU core 200 based on an interrupt signal, a signal SLEEP1, etc. For example, when transitioning from a normal operation state to a clock gating state, the PMU 193 stops generating the clock signal GCLK1.

[0150] For example, when transitioning from a normal operation state to a hibernation state, the PMU 193 performs voltage and / or frequency scaling. For example, when performing voltage scaling, the PMU 193 turns off the power switch 210 and turns on the power switch 211 to input the voltage VDD1 to the CPU core 200. The voltage VDD1 is a voltage that does not cause data to be lost in the scan flip-flop 221. When performing frequency scaling, the PMU 193 reduces the frequency of the clock signal GCLK1.

[0151] When the CPU core 200 is transitioned from a normal operation state to a power gating state, an operation is performed to back up the data of the scan flip-flop 221 in the backup circuit 222. When the CPU core 200 is returned from the power gating state to the normal operation state, an operation is performed to recover the data of the backup circuit 222 to the scan flip-flop 221.

[0152] Fig. 20 shows an example of a power gating sequence of the CPU core 200. In Fig. 20, t1 to t7 represent time. Signals PSE0 to PSE2 are control signals for the power switches 210 to 212, and are generated by the PMU 193. When the signal PSE0 is "H" / "L", the power switch 210 is on / off. The same is true for the signals PSE1 and PSE2.

[0153] Before time t1, the state is normal operation. The power switch 210 is on, and the voltage VDDD is input to the CPU core 200. The scan flip-flop 221 performs normal operation. At this time, since the level shifter 214 does not need to operate, the power switch 212 is off, and the signals SCE, BK, and RC are "L". Since the node SE is "L", the scan flip-flop 221 stores the data of the node D1. Note that in the example of FIG. 20, at time t1, the node SN11 of the backup circuit 222 is "L".

[0154] The operation during backup will be described. At time t1, the PMU 193 stops the clock signal GCLK1 and sets the signals PSE2 and BK to “H.” The level shifter 214 becomes active and outputs the signal BKH at “H” to the backup circuit 222.

[0155] The transistor M11 of the backup circuit 222 turns on, and the data of the node Q1 of the scan flip-flop 221 is written to the node SN11 of the backup circuit 222. If the node Q1 of the scan flip-flop 221 is "L", the node SN11 remains "L", and if the node Q1 is "H", the node SN11 becomes "H".

[0156] The PMU 193 sets the signals PSE2 and BK to "L" at time t2, and sets the signal PSE0 to "L" at time t3. At time t3, the state of the CPU core 200 transitions to a power gating state. Note that the signal PSE0 may fall at the same timing as the signal BK falls.

[0157] The operation during power gating will be described. When the signal PSE0 goes to "L", the voltage of the V_VDD line drops, and the data at the node Q1 is lost. The node SN11 continues to hold the data at the node Q1 at time t3.

[0158] The operation during recovery will be explained below. At time t4, the PMU 193 changes the signal PSE0 to "H", transitioning from the power gating state to the recovery state. Charging of the V_VDD line begins, and when the voltage of the V_VDD line reaches VDDD (time t5), the PMU 193 changes the signals PSE2, RC, and SCE to "H".

[0159] The transistor M12 turns on, and the charge of the capacitive element C11 is distributed to the nodes SN11 and SD. If the node SN11 is "H", the voltage of the node SD rises. Since the node SE is "H", the data of the node SD is written to the input side latch circuit of the scan flip-flop 221. When the clock signal GCLK1 is input to the node CK at time t6, the data of the input side latch circuit is written to the node Q1. In other words, the data of the node SN11 is written to the node Q1.

[0160] At time t7, the PMU 193 sets the signals PSE2, SCE, and RC to "L," and the recovery operation ends.

[0161] The backup circuit 222 using OS transistors has low dynamic and static power consumption, and is therefore very suitable for normally-off computing. The CPU 110 including the CPU core 200 having the backup circuit 222 using OS transistors can be called an NoffCPU (registered trademark). The NoffCPU has a non-volatile memory, and can stop the power supply when operation is not required. Even if the flip-flop 220 is installed, it is possible to prevent almost no performance degradation of the CPU core 200 and almost no increase in dynamic power.

[0162] The CPU core 200 may have multiple power domains that can be power-gated. The multiple power domains are provided with one or more power switches for controlling the input of voltage. The CPU core 200 may also have one or more power domains in which power gating is not performed. For example, a power gating control circuit for controlling the flip-flop 220 and the power switches 210 to 212 may be provided in the power domain in which power gating is not performed.

[0163] The application of the flip-flop 220 is not limited to the CPU 110. In the CPU 110, the flip-flop 220 can be applied to a register provided in a power domain capable of power gating.

[0164] This embodiment mode can be appropriately combined with the descriptions of other embodiment modes.

[0165] (Embodiment 4) In this embodiment, an example of a configuration of a transistor applicable to the CPU 110 described in the above embodiment and the accelerator described as the semiconductor device 10 will be described. As an example, a configuration in which transistors having different electrical characteristics are stacked will be described. By using this configuration, the design freedom of the semiconductor device can be increased. In addition, by stacking transistors having different electrical characteristics, the integration degree of the semiconductor device can be increased.

[0166] FIG. 21 shows a part of a cross-sectional structure of the semiconductor device. The semiconductor device shown in FIG. 21 includes a transistor 550, a transistor 500, and a capacitor 600. FIG. 22A is a cross-sectional view of the transistor 500 in the channel length direction, and FIG. 22B is a cross-sectional view of the transistor 500 in the channel width direction. For example, the transistor 500 corresponds to an OS transistor included in the memory circuit 32 described in the above embodiment, that is, a transistor having an oxide semiconductor in a channel formation region. The transistor 550 corresponds to a Si transistor included in the arithmetic circuit unit 40 described in the above embodiment, that is, a transistor having silicon in a channel formation region. The capacitor 600 corresponds to a capacitor included in the memory circuit 32.

[0167] The transistor 500 is an OS transistor. An OS transistor has an extremely small off-state current. Therefore, a data voltage or charge written to a storage node through the transistor 500 can be held for a long period of time. That is, the frequency of a refresh operation of the storage node can be reduced or the refresh operation is not required, so that the power consumption of a semiconductor device can be reduced.

[0168] In FIG. 21, the transistor 500 is provided above the transistor 550 , and the capacitor 600 is provided above the transistor 550 and the transistor 500 .

[0169] The transistor 550 is provided on a substrate 311. The substrate 311 is, for example, a p-type silicon substrate. The substrate 311 may be an n-type silicon substrate. The oxide layer 314 is preferably an insulating layer (also referred to as a BOX layer) formed by buried oxide in the substrate 311, for example, silicon oxide. The transistor 550 is provided on single crystal silicon provided on the substrate 311 via the oxide layer 314, that is, a so-called SOI (Silicon On Insulator) substrate.

[0170] A substrate 311 in the SOI substrate is provided with an insulator 313 functioning as an element isolation layer. The substrate 311 also has a well region 312. The well region 312 is a region to which n-type or p-type conductivity is imparted according to the conductivity type of the transistor 550. A semiconductor region 315, and low-resistance regions 316a and 316b functioning as source and drain regions are provided in the single crystal silicon in the SOI substrate. Also, a low-resistance region 316c is provided on the well region 312.

[0171] The transistor 550 can be provided overlapping the well region 312 to which an impurity element that imparts conductivity is added. The well region 312 can function as a bottom gate electrode of the transistor 550 by independently changing the potential through the low resistance region 316c. Therefore, the threshold voltage of the transistor 550 can be controlled. In particular, by applying a negative potential to the well region 312, the threshold voltage of the transistor 550 can be increased and the off-current can be reduced. Therefore, by applying a negative potential to the well region 312, the drain current when the potential applied to the gate electrode of the Si transistor is 0 V can be reduced. As a result, the power consumption based on the through current or the like in the arithmetic circuit unit 40 having the transistor 550 can be reduced, and the arithmetic efficiency can be improved.

[0172] The transistor 550 is preferably a so-called fin type in which a top surface of a semiconductor layer and side surfaces in a channel width direction are covered with a conductor 318 via an insulator 317. By making the transistor 550 a fin type, the effective channel width is increased, and thus the on characteristics of the transistor 550 can be improved. In addition, the contribution of the electric field of the gate electrode can be increased, and thus the off characteristics of the transistor 550 can be improved.

[0173] Note that the transistor 550 may be either a p-channel transistor or an n-channel transistor.

[0174] The conductor 318 may function as a first gate (also called a top gate) electrode. The well region 312 may function as a second gate (also called a bottom gate) electrode. In this case, the potential applied to the well region 312 can be controlled via the low resistance region 316c.

[0175] The region where the channel of the semiconductor region 315 is formed, the region nearby the region, the low resistance region 316a which becomes the source region or drain region, the low resistance region 316b, the low resistance region 316c which is connected to the electrode which controls the potential of the well region 312, and the like preferably contain a semiconductor such as a silicon-based semiconductor, and preferably contain single crystal silicon. Alternatively, they may be formed of a material having Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), and the like. A configuration using silicon in which the effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing may be used. Alternatively, the transistor 550 may be a HEMT (High Electron Mobility Transistor) by using GaAs and GaAlAs, and the like.

[0176] Well region 312, low resistance region 316a, low resistance region 316b, and low resistance region 316c include the semiconductor material applied to semiconductor region 315 as well as an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron.

[0177] The conductor 318 functioning as the gate electrode can be a conductive material such as a semiconductor material such as silicon containing an element that imparts n-type conductivity such as arsenic or phosphorus, or an element that imparts p-type conductivity such as boron, a metal material, an alloy material, or a metal oxide material. The conductor 318 can also be a silicide such as nickel silicide.

[0178] Since the work function is determined by the material of the conductor, the threshold voltage of the transistor can be adjusted by selecting the material of the conductor. Specifically, it is preferable to use a material such as titanium nitride or tantalum nitride for the conductor. Furthermore, in order to achieve both electrical conductivity and embeddability, it is preferable to use a metal material such as tungsten or aluminum as the conductor in a laminated state, and in particular, it is preferable to use tungsten in terms of heat resistance.

[0179] The low-resistance region 316a, the low-resistance region 316b, and the low-resistance region 316c may be configured to be provided by stacking another conductor, for example, a silicide such as nickel silicide. With this configuration, the conductivity of the region functioning as an electrode can be increased. In addition, in this case, an insulator functioning as a sidewall spacer (also called a sidewall insulating layer) may be provided on the side surface of the conductor 318 functioning as the gate electrode and the side surface of the insulator functioning as the gate insulating film. With this configuration, it is possible to prevent the conductor 318 from being electrically connected to the low-resistance region 316a and the low-resistance region 316b.

[0180] An insulator 320, an insulator 322, an insulator 324, and an insulator 326 are stacked in this order over the transistor 550.

[0181] As the insulators 320, 322, 324, and 326, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, or the like can be used.

[0182] In this specification, silicon oxynitride refers to a material having a higher oxygen content than nitrogen, silicon nitride oxide refers to a material having a higher nitrogen content than oxygen, aluminum oxynitride refers to a material having a higher oxygen content than nitrogen, and aluminum nitride oxide refers to a material having a higher nitrogen content than oxygen.

[0183] The insulator 322 may function as a planarizing film that planarizes steps caused by the transistor 550 or the like provided thereunder. For example, the top surface of the insulator 322 may be planarized by planarization treatment using a chemical mechanical polishing (CMP) method or the like to improve the planarity.

[0184] The insulator 324 is preferably a film having a barrier property that prevents hydrogen or impurities from diffusing from the substrate 311, the transistor 550, or the like to a region where the transistor 500 is provided.

[0185] As an example of a film having a barrier property against hydrogen, for example, silicon nitride formed by a CVD method can be used. Here, when hydrogen diffuses into a semiconductor element having an oxide semiconductor such as the transistor 500, the characteristics of the semiconductor element may deteriorate. Therefore, it is preferable to use a film that suppresses the diffusion of hydrogen between the transistor 500 and the transistor 550. Specifically, the film that suppresses the diffusion of hydrogen is a film that releases a small amount of hydrogen.

[0186] The amount of desorption of hydrogen can be analyzed, for example, by using thermal desorption spectrometry (TDS). For example, the amount of desorption of hydrogen from the insulator 324 is calculated as 10×10 per area of ​​the insulator 324 when the surface temperature of the film is in the range of 50° C. to 500° C. in the TDS analysis. 15 atoms / cm 2 Less than or equal to 5×10 15 atoms / cm 2 The following is acceptable.

[0187] The insulator 326 preferably has a lower dielectric constant than the insulator 324. For example, the relative dielectric constant of the insulator 326 is preferably less than 4, and more preferably less than 3. For example, the relative dielectric constant of the insulator 326 is preferably 0.7 times or less, and more preferably 0.6 times or less, the relative dielectric constant of the insulator 324. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance generated between wirings can be reduced.

[0188] Conductors 328 and 330, which connect to the capacitor 600 or the transistor 500, are embedded in the insulators 320, 322, 324, and 326. The conductors 328 and 330 function as plugs or wiring. A plurality of conductors that function as plugs or wiring may be collectively assigned the same reference numeral. In this specification and the like, the wiring and the plug connected to the wiring may be integrated. That is, a part of the conductor may function as the wiring, and a part of the conductor may function as the plug.

[0189] As the material for each plug and wiring (conductor 328, conductor 330, etc.), a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material can be used in a single layer or a laminated layer. It is preferable to use a high melting point material such as tungsten or molybdenum that has both heat resistance and conductivity, and tungsten is preferably used. Alternatively, it is preferable to form the plug and wiring from a low resistance conductive material such as aluminum or copper. By using a low resistance conductive material, the wiring resistance can be reduced.

[0190] A wiring layer may be provided over the insulator 326 and the conductor 330. For example, in FIG. 21 , an insulator 350, an insulator 352, and an insulator 354 are stacked in this order. A conductor 356 is formed in the insulator 350, the insulator 352, and the insulator 354. The conductor 356 functions as a plug or wiring connected to the transistor 550. Note that the conductor 356 can be provided using a material similar to that of the conductor 328 and the conductor 330.

[0191] Note that, for example, the insulator 350 is preferably an insulator having a barrier property against hydrogen, similar to the insulator 324. The conductor 356 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening of the insulator 350 having a barrier property against hydrogen. With this structure, the transistor 550 and the transistor 500 can be separated by a barrier layer, and diffusion of hydrogen from the transistor 550 to the transistor 500 can be suppressed.

[0192] Note that, for example, tantalum nitride or the like may be used as a conductor having a barrier property against hydrogen. By stacking tantalum nitride and tungsten having high conductivity, diffusion of hydrogen from the transistor 550 can be suppressed while maintaining the conductivity of the wiring. In this case, it is preferable that the tantalum nitride layer having a barrier property against hydrogen be in contact with the insulator 350 having a barrier property against hydrogen.

[0193] A wiring layer may be provided on the insulator 354 and the conductor 356. For example, in FIG. 21, an insulator 360, an insulator 362, and an insulator 364 are stacked in this order. A conductor 366 is formed in the insulator 360, the insulator 362, and the insulator 364. The conductor 366 functions as a plug or a wiring. The conductor 366 can be provided using a material similar to that of the conductor 328 and the conductor 330.

[0194] Note that, for example, the insulator 360 is preferably an insulator having a barrier property against hydrogen, similar to the insulator 324. The conductor 366 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening of the insulator 360 having a barrier property against hydrogen. With this structure, the transistor 550 and the transistor 500 can be separated by a barrier layer, and diffusion of hydrogen from the transistor 550 to the transistor 500 can be suppressed.

[0195] A wiring layer may be provided over the insulator 364 and the conductor 366. For example, in FIG. 21, an insulator 370, an insulator 372, and an insulator 374 are stacked in this order. A conductor 376 is formed in the insulator 370, the insulator 372, and the insulator 374. The conductor 376 functions as a plug or a wiring. The conductor 376 can be provided using a material similar to that of the conductor 328 and the conductor 330.

[0196] Note that, for example, the insulator 370 is preferably an insulator having a barrier property against hydrogen, similar to the insulator 324. The conductor 376 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening of the insulator 370 having a barrier property against hydrogen. With this structure, the transistor 550 and the transistor 500 can be separated by a barrier layer, and diffusion of hydrogen from the transistor 550 to the transistor 500 can be suppressed.

[0197] A wiring layer may be provided over the insulator 374 and the conductor 376. For example, in FIG. 21, an insulator 380, an insulator 382, ​​and an insulator 384 are stacked in this order. A conductor 386 is formed in the insulator 380, the insulator 382, ​​and the insulator 384. The conductor 386 functions as a plug or a wiring. The conductor 386 can be provided using a material similar to that of the conductor 328 and the conductor 330.

[0198] Note that, for example, the insulator 380 is preferably an insulator having a barrier property against hydrogen, similar to the insulator 324. The conductor 386 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening of the insulator 380 having a barrier property against hydrogen. With this structure, the transistor 550 and the transistor 500 can be separated by a barrier layer, and diffusion of hydrogen from the transistor 550 to the transistor 500 can be suppressed.

[0199] In the above, a wiring layer including the conductor 356, a wiring layer including the conductor 366, a wiring layer including the conductor 376, and a wiring layer including the conductor 386 have been described, but the semiconductor device of this embodiment is not limited to this. There may be three or fewer wiring layers similar to the wiring layer including the conductor 356, or there may be five or more wiring layers similar to the wiring layer including the conductor 356.

[0200] An insulator 510, an insulator 512, an insulator 514, and an insulator 516 are stacked in this order on the insulator 384. Any of the insulator 510, the insulator 512, the insulator 514, and the insulator 516 is preferably made of a substance that has a barrier property against oxygen or hydrogen.

[0201] For example, the insulator 510 and the insulator 514 are preferably formed using a film having a barrier property against hydrogen and impurities in a region where the transistor 500 is provided, such as the substrate 311 or a region where the transistor 550 is provided. Therefore, a material similar to that of the insulator 324 can be used.

[0202] As an example of a film having a barrier property against hydrogen, silicon nitride formed by a CVD method can be used. Here, when hydrogen diffuses into a semiconductor element having an oxide semiconductor such as the transistor 500, the characteristics of the semiconductor element may deteriorate. Therefore, a film that suppresses the diffusion of hydrogen is preferably used between the transistor 500 and the transistor 550.

[0203] As a film having a barrier property against hydrogen, for example, the insulator 510 and the insulator 514 are preferably made of a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide.

[0204] In particular, aluminum oxide has a high blocking effect of preventing the film from permeating both oxygen and impurities such as hydrogen and moisture, which are factors that cause fluctuations in the electrical characteristics of a transistor. Therefore, aluminum oxide can prevent impurities such as hydrogen and moisture from entering the transistor 500 during and after the transistor manufacturing process. In addition, aluminum oxide can suppress the release of oxygen from the oxide that constitutes the transistor 500. Therefore, aluminum oxide is suitable for use as a protective film for the transistor 500.

[0205] For example, the insulator 512 and the insulator 516 can be made of a material similar to that of the insulator 320. By using a material with a relatively low dielectric constant for these insulators, the parasitic capacitance generated between wirings can be reduced. For example, the insulator 512 and the insulator 516 can be made of a silicon oxide film, a silicon oxynitride film, or the like.

[0206] A conductor 518, a conductor constituting the transistor 500 (for example, the conductor 503), and the like are embedded in the insulator 510, the insulator 512, the insulator 514, and the insulator 516. Note that the conductor 518 functions as a plug or a wiring connected to the capacitor 600 or the transistor 550. The conductor 518 can be provided using a material similar to that of the conductor 328 and the conductor 330.

[0207] In particular, the insulator 510 and the conductor 518 in the region in contact with the insulator 514 are preferably conductors having barrier properties against oxygen, hydrogen, and water. With this structure, the transistor 550 and the transistor 500 can be separated by a layer having barrier properties against oxygen, hydrogen, and water, and diffusion of hydrogen from the transistor 550 to the transistor 500 can be suppressed.

[0208] Above the insulator 516 is a transistor 500 .

[0209] As shown in Figures 22A and 22B, transistor 500 has a conductor 503 arranged so as to be embedded in insulator 514 and insulator 516, an insulator 522 arranged on insulator 516 and conductor 503, an insulator 524 arranged on insulator 522, an oxide 530a arranged on insulator 524, an oxide 530b arranged on oxide 530a, conductors 542a and 542b arranged apart from each other on oxide 530b, an insulator 580 arranged on conductor 542a and conductor 542b and having an opening formed therebetween overlapping with conductor 542a and conductor 542b, an insulator 545 arranged on the bottom and side surfaces of the opening, and a conductor 560 arranged on the formation surface of insulator 545.

[0210] 22A and 22B, it is preferable that an insulator 544 is disposed between the oxide 530a, the oxide 530b, the conductor 542a, and the conductor 542b and the insulator 580. It is preferable that the conductor 560 has a conductor 560a provided inside the insulator 545 and a conductor 560b provided so as to be embedded inside the conductor 560a, as shown in FIG. 22A and 22B. It is preferable that an insulator 574 is disposed on the insulator 580, the conductor 560, and the insulator 545, as shown in FIG. 22A and 22B.

[0211] In this specification and other documents, oxide 530a and oxide 530b may be collectively referred to as oxide 530.

[0212] Note that, in the transistor 500, a two-layer structure of the oxide 530a and the oxide 530b is shown in the region where the channel is formed and in the vicinity thereof, but the present invention is not limited to this structure. For example, a single layer of the oxide 530b or a stacked structure of three or more layers may be used.

[0213] In addition, although the conductor 560 in the transistor 500 has a two-layer structure, the present invention is not limited to this. For example, the conductor 560 may have a single-layer structure or a three-or-more-layer structure. The transistor 500 shown in FIGS. 21, 22A, and 22B is merely an example and is not limited to this structure. An appropriate transistor may be used depending on the circuit configuration, driving method, and the like.

[0214] Here, the conductor 560 functions as a gate electrode of the transistor, and the conductors 542a and 542b function as a source electrode and a drain electrode, respectively. As described above, the conductor 560 is formed so as to be embedded in the opening of the insulator 580 and in the region sandwiched between the conductors 542a and 542b. The arrangement of the conductors 560, 542a, and 542b is selected in a self-aligned manner with respect to the opening of the insulator 580. That is, in the transistor 500, the gate electrode can be arranged in a self-aligned manner between the source electrode and the drain electrode. Therefore, the conductor 560 can be formed without providing a margin for alignment, so that the area occupied by the transistor 500 can be reduced. This allows the semiconductor device to be miniaturized and highly integrated.

[0215] Furthermore, since the conductor 560 is formed in a self-aligned manner in the region between the conductor 542a and the conductor 542b, the conductor 560 does not have a region that overlaps with the conductor 542a or the conductor 542b. This makes it possible to reduce the parasitic capacitance formed between the conductor 560 and the conductor 542a and between the conductor 560 and the conductor 542b. This makes it possible to improve the switching speed of the transistor 500 and provide high frequency characteristics.

[0216] The conductor 560 may function as a first gate (also referred to as a top gate) electrode. The conductor 503 may function as a second gate (also referred to as a bottom gate) electrode. In this case, the threshold voltage of the transistor 500 can be controlled by changing the potential applied to the conductor 503 independently of the potential applied to the conductor 560. In particular, by applying a negative potential to the conductor 503, the threshold voltage of the transistor 500 can be increased and the off-current can be reduced. Therefore, the drain current when the potential applied to the conductor 560 is 0 V can be reduced by applying a negative potential to the conductor 503 compared to the case where a negative potential is not applied.

[0217] The conductor 503 is disposed so as to overlap the oxide 530 and the conductor 560. In this manner, when a potential is applied to the conductor 560 and the conductor 503, the electric field generated from the conductor 560 and the electric field generated from the conductor 503 are connected, and a channel formation region formed in the oxide 530 can be covered.

[0218] In this specification and the like, a transistor configuration in which a channel formation region is electrically surrounded by the electric field of a pair of gate electrodes (a first gate electrode and a second gate electrode) is called a surrounded channel (S-channel) configuration. The S-channel configuration disclosed in this specification and the like is different from a fin type configuration and a planar type configuration. By adopting the S-channel configuration, it is possible to obtain a transistor that is more resistant to the short channel effect, in other words, in which the short channel effect is less likely to occur.

[0219] The conductor 503 has a structure similar to that of the conductor 518, and the conductor 503a is formed in contact with the inner walls of the openings of the insulator 514 and the insulator 516, and the conductor 503b is formed further inside. Note that, although the transistor 500 shows a structure in which the conductor 503a and the conductor 503b are stacked, the present invention is not limited to this. For example, the conductor 503 may have a single layer structure or a stacked structure of three or more layers.

[0220] Here, the conductor 503a is preferably made of a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms (the impurities are less likely to permeate through). Alternatively, it is preferable to use a conductive material having a function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.) (the oxygen is less likely to permeate through). Note that in this specification, the function of suppressing the diffusion of impurities or oxygen refers to the function of suppressing the diffusion of any one or all of the impurities and oxygen.

[0221] For example, the conductor 503a has a function of suppressing the diffusion of oxygen, so that the conductor 503b can be prevented from being oxidized and the conductivity from decreasing.

[0222] In addition, when the conductor 503 also functions as a wiring, it is preferable that the conductor 503b is made of a highly conductive material containing tungsten, copper, or aluminum as a main component. Note that, although the conductor 503 is illustrated in this embodiment as a stack of the conductors 503a and 503b, the conductor 503 may have a single layer structure.

[0223] The insulator 522 and the insulator 524 function as a second gate insulating film.

[0224] Here, it is preferable that the insulator 524 in contact with the oxide 530 is an insulator containing more oxygen than the oxygen that satisfies the stoichiometric composition. The oxygen is easily released from the film by heating. In this specification and the like, oxygen released by heating may be called "excess oxygen." In other words, it is preferable that the insulator 524 has a region containing excess oxygen (also called "excess oxygen region"). By providing such an insulator containing excess oxygen in contact with the oxide 530, oxygen vacancies (V O In addition, when hydrogen enters an oxygen vacancy in the oxide 530, the defect (hereinafter, V O H.) may function as a donor and generate electrons as carriers. Some of the hydrogen may bond with oxygen that is bonded to a metal atom to generate electrons as carriers. Therefore, a transistor using an oxide semiconductor containing a large amount of hydrogen is likely to have normally-on characteristics. Furthermore, hydrogen in an oxide semiconductor is easily moved by stress such as heat or an electric field. Therefore, if an oxide semiconductor contains a large amount of hydrogen, the reliability of the transistor may be deteriorated. In one embodiment of the present invention, V in the oxide 530 O It is preferable to reduce H as much as possible and make it high-purity intrinsic or substantially high-purity intrinsic.O In order to obtain an oxide semiconductor in which H is sufficiently reduced, it is important to remove impurities such as moisture and hydrogen from the oxide semiconductor (also called "dehydration" or "dehydrogenation treatment") and to supply oxygen to the oxide semiconductor to compensate for oxygen vacancies (also called "oxygenation treatment"). O By using an oxide semiconductor in which impurities such as H are sufficiently reduced for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0225] Specifically, it is preferable to use an oxide material from which some oxygen is released by heating as an insulator having an excess oxygen region. An oxide material from which oxygen is released by heating is an oxide material from which the amount of released oxygen converted into oxygen atoms is 1.0×10 18 atoms / cm 3 More than 1.0×10 19 atoms / cm 3 More preferably, 2.0×10 19 atoms / cm 3 or more than 3.0×10 20 atoms / cm 3 The oxide film is one having the above-mentioned properties. The surface temperature of the film during the TDS analysis is preferably in the range of 100° C. or more and 700° C. or less, or 100° C. or more and 400° C. or less.

[0226] In addition, the oxide 530 may be brought into contact with the insulator having the excess oxygen region and subjected to one or more of heat treatment, microwave treatment, and RF treatment. By carrying out such treatment, water or hydrogen in the oxide 530 can be removed. For example, a reaction occurs in the oxide 530 that breaks the bond of VoH, in other words, "V O The reaction "H → Vo + H" occurs, and the hydrogen can be dehydrogenated. Some of the hydrogen generated at this time may combine with oxygen to become H2O and be removed from the oxide 530 or the insulator near the oxide 530. Some of the hydrogen may also be gettered to the conductor 542.

[0227] In addition, the microwave treatment is preferably performed using, for example, a device having a power source that generates high-density plasma or a device having a power source that applies RF to the substrate side. For example, high-density oxygen radicals can be generated by using a gas containing oxygen and high-density plasma, and the oxygen radicals generated by the high-density plasma can be efficiently introduced into the oxide 530 or an insulator near the oxide 530 by applying RF to the substrate side. In addition, the pressure of the microwave treatment may be set to 133 Pa or more, preferably 200 Pa or more, and more preferably 400 Pa or more. In addition, for example, oxygen and argon are used as gases to be introduced into the microwave treatment device, and the oxygen flow rate ratio (O2 / (O2+Ar)) is 50% or less, preferably 10% or more and 30% or less.

[0228] In addition, in a manufacturing process of the transistor 500, it is preferable to perform heat treatment while the surface of the oxide 530 is exposed. The heat treatment may be performed, for example, at a temperature of 100° C. or higher and 450° C. or lower, more preferably 350° C. or higher and 400° C. or lower. Note that the heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing an oxidizing gas at 10 ppm or higher, 1% or higher, or 10% or higher. For example, the heat treatment is preferably performed in an oxygen atmosphere. In this way, oxygen is supplied to the oxide 530 to reduce oxygen deficiencies (V O ) can be reduced. The heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas in order to compensate for the desorbed oxygen after the heat treatment in a nitrogen gas or inert gas atmosphere. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas in order to compensate for the desorbed oxygen. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas in succession to a heat treatment in a nitrogen gas or inert gas atmosphere.

[0229] By subjecting the oxide 530 to oxygen addition treatment, the oxygen vacancies in the oxide 530 can be repaired by the supplied oxygen, in other words, the reaction of "Vo+O→null" can be promoted. Furthermore, the supplied oxygen reacts with the hydrogen remaining in the oxide 530, and the hydrogen can be removed as H2O (dehydrated). As a result, the hydrogen remaining in the oxide 530 recombines with the oxygen vacancies to form V O The formation of H can be suppressed.

[0230] When the insulator 524 has an excess oxygen region, it is preferable that the insulator 522 has a function of suppressing the diffusion of oxygen (eg, oxygen atoms, oxygen molecules, etc.) (the oxygen is less likely to permeate).

[0231] The insulator 522 preferably has a function of suppressing diffusion of oxygen and impurities, so that oxygen contained in the oxide 530 does not diffuse toward the conductor 503. Furthermore, reaction of the conductor 503 with the insulator 524 and oxygen contained in the oxide 530 can be suppressed.

[0232] The insulator 522 is preferably a single layer or a multilayer insulator containing a so-called high-k material, such as aluminum oxide, hafnium oxide, oxide containing aluminum and hafnium (hafnium aluminate), tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST). As transistors become smaller and more highly integrated, problems such as leakage current may occur due to the thinning of the gate insulating film. By using a high-k material for the insulator that functions as the gate insulating film, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.

[0233] In particular, it is preferable to use an insulator containing an oxide of one or both of aluminum and hafnium, which are insulating materials having a function of suppressing the diffusion of impurities and oxygen (the oxygen is unlikely to permeate through them). As an insulator containing an oxide of one or both of aluminum and hafnium, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like. When the insulator 522 is formed using such a material, the insulator 522 functions as a layer that suppresses the release of oxygen from the oxide 530 and the intrusion of impurities such as hydrogen into the oxide 530 from the periphery of the transistor 500.

[0234] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators. Alternatively, these insulators may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may be stacked on the above insulators.

[0235] 22A and 22B, the insulator 522 and the insulator 524 are illustrated as the second gate insulating film having a three-layer stack structure, but the second gate insulating film may have a single layer, two layers, or four or more layers. In this case, the second gate insulating film is not limited to a stack structure made of the same material, and may have a stack structure made of different materials.

[0236] In the transistor 500, a metal oxide functioning as an oxide semiconductor is used for the oxide 530 including the channel formation region. For example, a metal oxide such as In-M-Zn oxide (wherein the element M is one or more elements selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, or the like) may be used for the oxide 530.

[0237] The metal oxide functioning as an oxide semiconductor may be formed by a sputtering method or an ALD (Atomic Layer Deposition) method. Note that the metal oxide functioning as an oxide semiconductor will be described in detail in another embodiment.

[0238] The metal oxide that functions as a channel formation region in the oxide 530 preferably has a band gap of 2 eV or more, preferably 2.5 eV or more. In this manner, by using a metal oxide with a wide band gap, the off-state current of the transistor can be reduced.

[0239] The oxide 530 has the oxide 530a below the oxide 530b, and thus can suppress the diffusion of impurities from components formed below the oxide 530a to the oxide 530b.

[0240] The oxide 530 preferably has a laminated structure of a plurality of oxide layers having different atomic ratios of metal atoms. Specifically, the atomic ratio of element M among the constituent elements in the metal oxide used for the oxide 530a is preferably larger than the atomic ratio of element M among the constituent elements in the metal oxide used for the oxide 530b. In addition, the atomic ratio of element M to In in the metal oxide used for the oxide 530a is preferably larger than the atomic ratio of element M to In in the metal oxide used for the oxide 530b. In addition, the atomic ratio of In to element M in the metal oxide used for the oxide 530b is preferably larger than the atomic ratio of In to element M in the metal oxide used for the oxide 530a.

[0241] In addition, it is preferable that the energy of the conduction band minimum of the oxide 530a is higher than that of the oxide 530b, or, in other words, it is preferable that the electron affinity of the oxide 530a is smaller than that of the oxide 530b.

[0242] Here, at the junction between the oxide 530a and the oxide 530b, the energy level of the conduction band minimum changes gradually. In other words, it can be said that the energy level of the conduction band minimum at the junction between the oxide 530a and the oxide 530b changes continuously or is a continuous junction. To achieve this, it is preferable to reduce the defect level density of the mixed layer formed at the interface between the oxide 530a and the oxide 530b.

[0243] Specifically, the oxide 530a and the oxide 530b have a common element other than oxygen (as a main component), so that a mixed layer with a low density of defect states can be formed. For example, when the oxide 530b is an In-Ga-Zn oxide, the oxide 530a may be an In-Ga-Zn oxide, a Ga-Zn oxide, or a gallium oxide.

[0244] At this time, the main carrier path is the oxide 530b. By configuring the oxide 530a as described above, the defect state density at the interface between the oxide 530a and the oxide 530b can be reduced. Therefore, the effect of interface scattering on carrier conduction is reduced, and the transistor 500 can obtain a high on-state current.

[0245] Conductors 542a and 542b functioning as a source electrode and a drain electrode are provided on the oxide 530b. As the conductors 542a and 542b, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, an alloy containing the above-mentioned metal elements as a component, or an alloy combining the above-mentioned metal elements. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, or the like. In addition, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are conductive materials that are difficult to oxidize, or materials that maintain conductivity even when oxygen is absorbed, and are therefore preferable.Furthermore, metal nitride films such as tantalum nitride are preferable because they have barrier properties against hydrogen or oxygen.

[0246] 22A, the conductor 542a and the conductor 542b are shown as a single layer, but may be a laminated structure of two or more layers. For example, a tantalum nitride film and a tungsten film may be laminated. A titanium film and an aluminum film may be laminated. A two-layer structure in which an aluminum film is laminated on a tungsten film, a two-layer structure in which a copper film is laminated on a copper-magnesium-aluminum alloy film, a two-layer structure in which a copper film is laminated on a titanium film, or a two-layer structure in which a copper film is laminated on a tungsten film may be used.

[0247] In addition, there are three-layer structures in which a titanium film or titanium nitride film is laminated with an aluminum film or copper film on the titanium film or titanium nitride film, and a titanium film or titanium nitride film is further formed thereon, and a three-layer structure in which a molybdenum film or molybdenum nitride film is laminated with an aluminum film or copper film on the molybdenum film or molybdenum nitride film, and a molybdenum film or molybdenum nitride film is further formed thereon, etc. Note that a transparent conductive material containing indium oxide, tin oxide, or zinc oxide may be used.

[0248] 22A, regions 543a and 543b may be formed as low-resistance regions at and near the interface of the oxide 530 with the conductor 542a (conductor 542b). In this case, the region 543a functions as one of the source region and the drain region, and the region 543b functions as the other of the source region and the drain region. A channel formation region is formed in a region sandwiched between the regions 543a and 543b.

[0249] By providing the conductor 542a (conductor 542b) so as to be in contact with the oxide 530, the oxygen concentration in the region 543a (region 543b) may be reduced. Also, a metal compound layer containing a metal contained in the conductor 542a (conductor 542b) and a component of the oxide 530 may be formed in the region 543a (region 543b). In such a case, the carrier density in the region 543a (region 543b) increases, and the region 543a (region 543b) becomes a low-resistance region.

[0250] The insulator 544 is provided to cover the conductor 542a and the conductor 542b and suppresses oxidation of the conductor 542a and the conductor 542b. In this case, the insulator 544 may be provided to cover the side surface of the oxide 530 and to be in contact with the insulator 524.

[0251] The insulator 544 can be a metal oxide containing one or more elements selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, neodymium, lanthanum, magnesium, etc. Alternatively, the insulator 544 can be silicon nitride oxide, silicon nitride, or the like.

[0252] In particular, it is preferable to use, as the insulator 544, an insulator containing an oxide of either or both of aluminum and hafnium, such as aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate). In particular, hafnium aluminate has higher heat resistance than a hafnium oxide film. Therefore, it is preferable because it is less likely to crystallize in a heat treatment in a later process. Note that the insulator 544 is not an essential component when the conductors 542a and 542b are made of a material having oxidation resistance or when the conductivity does not decrease significantly even when oxygen is absorbed. It may be designed appropriately depending on the desired transistor characteristics.

[0253] The insulator 544 can prevent impurities such as water and hydrogen contained in the insulator 580 from diffusing to the oxide 530b through the insulator 545. The insulator 580 can also prevent the conductor 560 from being oxidized by excess oxygen contained in the insulator 580.

[0254] The insulator 545 functions as a first gate insulating film. Like the insulator 524 described above, the insulator 545 is preferably formed using an insulator that contains excess oxygen and releases oxygen by heating.

[0255] Specifically, silicon oxide having excess oxygen, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, and silicon oxide having vacancies can be used. In particular, silicon oxide and silicon oxynitride are preferable because they are stable against heat.

[0256] By providing an insulator containing excess oxygen as the insulator 545, oxygen can be effectively supplied from the insulator 545 to the channel formation region of the oxide 530b. Similarly to the insulator 524, the concentration of impurities such as water or hydrogen in the insulator 545 is preferably reduced. The thickness of the insulator 545 is preferably 1 nm or more and 20 nm or less. The microwave treatment described above may be performed before and / or after the formation of the insulator 545.

[0257] Furthermore, in order to efficiently supply excess oxygen contained in the insulator 545 to the oxide 530, a metal oxide may be provided between the insulator 545 and the conductor 560. The metal oxide preferably suppresses oxygen diffusion from the insulator 545 to the conductor 560. By providing a metal oxide that suppresses oxygen diffusion, the diffusion of excess oxygen from the insulator 545 to the conductor 560 can be suppressed. That is, a decrease in the amount of excess oxygen supplied to the oxide 530 can be suppressed. Furthermore, oxidation of the conductor 560 due to the excess oxygen can be suppressed. As the metal oxide, a material that can be used for the insulator 544 can be used.

[0258] The insulator 545 may have a layered structure, similar to the second gate insulating film. As transistors become smaller and more highly integrated, problems such as leakage current may occur due to the thinning of the gate insulating film. Therefore, by making the insulator that functions as the gate insulating film have a layered structure of a high-k material and a thermally stable material, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness. In addition, a layered structure that is thermally stable and has a high relative dielectric constant can be obtained.

[0259] Although the conductor 560 functioning as the first gate electrode is shown as having a two-layer structure in FIGS. 22A and 22B, it may have a single-layer structure or a laminated structure of three or more layers.

[0260] The conductor 560a is preferably made of a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms. Alternatively, it is preferably made of a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.). The conductor 560a has a function of suppressing the diffusion of oxygen, so that it is possible to suppress the conductor 560b from being oxidized by the oxygen contained in the insulator 545 and its conductivity from decreasing. As a conductive material having a function of suppressing the diffusion of oxygen, for example, tantalum, tantalum nitride, ruthenium, or ruthenium oxide is preferably used. In addition, an oxide semiconductor applicable to the oxide 530 can be used as the conductor 560a. In that case, the conductor 560b can be formed by a sputtering method to reduce the electrical resistance value of the conductor 560a and make it a conductor. This can be called an OC (Oxide Conductor) electrode.

[0261] The conductor 560b is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductor 560b also functions as wiring, so it is preferable to use a conductor with high conductivity. For example, a conductive material containing tungsten, copper, or aluminum as a main component can be used. The conductor 560b may have a layered structure, for example, a layered structure of titanium or titanium nitride and the above conductive material.

[0262] The insulator 580 is provided on the conductor 542a and the conductor 542b via the insulator 544. The insulator 580 preferably has an excess oxygen region. For example, the insulator 580 preferably has silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, silicon oxide having voids, or a resin. In particular, silicon oxide and silicon oxynitride are preferable because they are thermally stable. In particular, silicon oxide and silicon oxide having voids are preferable because they can easily form an excess oxygen region in a later step.

[0263] The insulator 580 preferably has an excess oxygen region. By providing the insulator 580 from which oxygen is released by heating, oxygen in the insulator 580 can be efficiently supplied to the oxide 530. Note that the concentration of impurities such as water or hydrogen in the insulator 580 is preferably reduced.

[0264] The opening of insulator 580 is formed to overlap the region between conductor 542a and conductor 542b, so that conductor 560 is formed so as to be embedded in the opening of insulator 580 and the region sandwiched between conductor 542a and conductor 542b.

[0265] In miniaturizing a semiconductor device, it is necessary to shorten the gate length, but it is also necessary to prevent the conductivity of the conductor 560 from decreasing. If the film thickness of the conductor 560 is increased for that purpose, the conductor 560 may have a shape with a high aspect ratio. In this embodiment, the conductor 560 is provided so as to be embedded in the opening of the insulator 580, so that even if the conductor 560 has a shape with a high aspect ratio, the conductor 560 can be formed without collapsing during the process.

[0266] The insulator 574 is preferably provided in contact with a top surface of the insulator 580, a top surface of the conductor 560, and a top surface of the insulator 545. By forming the insulator 574 by a sputtering method, an excess oxygen region can be provided in the insulator 545 and the insulator 580. This allows oxygen to be supplied from the excess oxygen region into the oxide 530.

[0267] For example, the insulator 574 can be a metal oxide containing one or more elements selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, and the like.

[0268] In particular, aluminum oxide has high barrier properties and can suppress the diffusion of hydrogen and nitrogen even in a thin film with a thickness of 0.5 nm to 3.0 nm. Therefore, aluminum oxide formed by sputtering can function as a barrier film against impurities such as hydrogen as well as an oxygen source.

[0269] An insulator 581 functioning as an interlayer film is preferably provided over the insulator 574. Like the insulator 524, the insulator 581 preferably has a reduced concentration of impurities such as water or hydrogen.

[0270] Conductor 540a and conductor 540b are arranged in openings formed in insulator 581, insulator 574, insulator 580, and insulator 544. Conductor 540a and conductor 540b are provided facing each other with conductor 560 interposed therebetween. Conductor 540a and conductor 540b have the same configuration as conductor 546 and conductor 548, which will be described later.

[0271] An insulator 582 is provided over the insulator 581. The insulator 582 is preferably made of a substance that has a barrier property against oxygen and hydrogen. Therefore, the insulator 582 can be made of a material similar to that of the insulator 514. For example, the insulator 582 is preferably made of a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide.

[0272] In particular, aluminum oxide has a high blocking effect of preventing the film from permeating both oxygen and impurities such as hydrogen and moisture, which are factors that cause fluctuations in the electrical characteristics of a transistor. Therefore, aluminum oxide can prevent impurities such as hydrogen and moisture from entering the transistor 500 during and after the transistor manufacturing process. In addition, aluminum oxide can suppress the release of oxygen from the oxide that constitutes the transistor 500. Therefore, aluminum oxide is suitable for use as a protective film for the transistor 500.

[0273] An insulator 586 is provided over the insulator 582. The insulator 586 can be formed using a material similar to that of the insulator 320. By using a material with a relatively low dielectric constant for these insulators, parasitic capacitance between wirings can be reduced. For example, a silicon oxide film, a silicon oxynitride film, or the like can be used as the insulator 586.

[0274] In addition, conductors 546, 548, etc. are embedded in insulators 522, 524, 544, 580, 574, 581, 582, and 586.

[0275] The conductor 546 and the conductor 548 function as a plug or a wiring that connects to the capacitor 600, the transistor 500, or the transistor 550. The conductor 546 and the conductor 548 can be formed using a material similar to that of the conductor 328 and the conductor 330.

[0276] After the transistor 500 is formed, an opening may be formed to surround the transistor 500, and an insulator having a high barrier property against hydrogen or water may be formed to cover the opening. By surrounding the transistor 500 with the insulator having a high barrier property, it is possible to prevent moisture and hydrogen from entering from the outside. Alternatively, a plurality of transistors 500 may be collectively surrounded by an insulator having a high barrier property against hydrogen or water. When an opening is formed to surround the transistor 500, for example, an opening reaching the insulator 522 or the insulator 514 is formed, and the insulator having a high barrier property is formed in contact with the insulator 522 or the insulator 514, which is preferable because it serves as part of the manufacturing process of the transistor 500. Note that the insulator having a high barrier property against hydrogen or water may be made of a material similar to that of the insulator 522 or the insulator 514, for example.

[0277] Next, a capacitor 600 is provided above the transistor 500. The capacitor 600 includes a conductor 610, a conductor 620, and an insulator 630.

[0278] A conductor 612 may be provided over the conductor 546 and the conductor 548. The conductor 612 functions as a plug or a wiring connected to the transistor 500. The conductor 610 functions as an electrode of the capacitor 600. Note that the conductor 612 and the conductor 610 can be formed at the same time.

[0279] A metal film containing an element selected from molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, and scandium, or a metal nitride film containing the above-mentioned element (tantalum nitride film, titanium nitride film, molybdenum nitride film, tungsten nitride film), etc. can be used for the conductor 612 and the conductor 610. Alternatively, a conductive material such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide with added silicon oxide can also be used.

[0280] In this embodiment, the conductor 612 and the conductor 610 have a single-layer structure, but the present invention is not limited to this structure and may have a stacked structure of two or more layers. For example, a conductor having a barrier property and a conductor having high adhesion to the conductor having high conductivity may be formed between a conductor having a barrier property and a conductor having high conductivity.

[0281] The conductor 620 is provided so as to overlap with the conductor 610 with the insulator 630 interposed therebetween. Note that the conductor 620 can be made of a conductive material such as a metal material, an alloy material, or a metal oxide material. It is preferable to use a high melting point material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is particularly preferable to use tungsten. When the conductor 620 is formed simultaneously with other components such as a conductor, a low resistance metal material such as Cu (copper) or Al (aluminum) may be used.

[0282] An insulator 640 is provided over the conductor 620 and the insulator 630. The insulator 640 can be provided using a material similar to that of the insulator 320. The insulator 640 may also function as a planarizing film that covers the uneven shape underneath.

[0283] With this structure, miniaturization or high integration can be achieved in a semiconductor device including a transistor including an oxide semiconductor.

[0284] The configurations, structures, methods, and the like described in this embodiment can be used in appropriate combination with the configurations, structures, methods, and the like described in other embodiment modes and examples.

[0285] (Embodiment 5) In this embodiment, the configuration of an integrated circuit including each component of the arithmetic processing system 100 described in the above embodiment will be described with reference to FIGS. 23A and 23B.

[0286] Fig. 23A is an example of a schematic diagram for explaining an integrated circuit including each component of the arithmetic processing system 100. The integrated circuit 390 shown in Fig. 23A can be formed as a single integrated circuit by integrating each circuit by forming a part of the circuits of the CPU 110 and the accelerator described as the semiconductor device 10 using OS transistors.

[0287] As shown in FIG. 23A, the CPU 110 may be configured to have a backup circuit 222 in a layer having OS transistors above the CPU core 200. Also, as shown in FIG. 23A, in the accelerator described as the semiconductor device 10, the memory circuit section 30 may be provided in a layer having OS transistors above the layer having Si transistors constituting the arithmetic circuit section 40. In addition, the layer having OS transistors may be provided with an OS memory 300N or the like. As the OS memory 300N, in addition to the NOSRAM described in the above embodiment, a DOSRAM may be applied. Also, in the OS memory 300N, a layer having OS transistors may be stacked on a driving circuit provided in a layer having Si transistors, thereby improving memory density.

[0288] As shown in FIG. 23A, in the case of an SoC in which the CPU 110, the accelerator described as the semiconductor device 10, the OS memory 300N, and other circuits are tightly coupled, there is a problem of heat generation, but the OS transistor is preferable because the fluctuation amount of the electrical characteristics due to heat is smaller than that of a Si transistor. Also, by integrating the circuits in the three-dimensional direction as shown in FIG. 23A, the parasitic capacitance can be reduced compared to a stacked structure using a silicon through electrode (Through Silicon Via: TSV) or the like. The power consumption required for charging and discharging each wiring can be reduced. Therefore, the efficiency of the calculation processing can be improved.

[0289] Fig. 23B shows an example of a semiconductor chip incorporating an integrated circuit 390. A semiconductor chip 391 shown in Fig. 23B has leads 392 and an integrated circuit 390. As described in Fig. 23A, the integrated circuit 390 has various circuits shown in the above embodiments provided on one die. The integrated circuit 390 has a layered structure and is broadly divided into a layer having Si transistors (Si transistor layer 393), a wiring layer 394, and a layer having OS transistors (OS transistor layer 395). The OS transistor layer 395 can be provided by being layered on the Si transistor layer 393, which makes it easy to miniaturize the semiconductor chip 391.

[0290] 23B, a QFP (Quad Flat Package) is applied to the package of the semiconductor chip 391, but the form of the package is not limited to this. Other configuration examples include DIP (Dual In-line Package), PGA (Pin Grid Array), SOP (Small Outline Package), SSOP (Shrink Small Outline Package), TSOP (Thin-Small Outline Package), LCC (Leaded Chip Carrier), QFN (Quad Flat Non-leaded package), BGA (Ball Grid Array), FBGA (Fine pitch Ball Grid Array), DTP (Dual Tape carrier Package), QTP (Quad Tape-carrier Package), etc., which are insertion mounting types.

[0291] An arithmetic circuit and a switching circuit having Si transistors, and a memory circuit having OS transistors can all be formed in the Si transistor layer 393, the wiring layer 394, and the OS transistor layer 395. That is, the elements constituting the semiconductor device can be formed in the same manufacturing process. Therefore, even if the number of constituting elements increases, the IC shown in FIG. 23B does not need to increase the manufacturing process, and the semiconductor device can be incorporated at low cost.

[0292] According to the above-described embodiment of the present invention, a novel semiconductor device and electronic device can be provided. According to another embodiment of the present invention, a semiconductor device and electronic device with low power consumption can be provided. According to another embodiment of the present invention, a semiconductor device and electronic device in which heat generation can be suppressed can be provided.

[0293] This embodiment mode can be appropriately combined with the descriptions of other embodiment modes.

[0294] (Embodiment 6) In this embodiment mode, an electronic device, a mobile object, and a computing system to which the integrated circuit 390 described in the above embodiment mode can be applied will be described with reference to FIGS.

[0295] Fig. 24A shows an external view of an automobile as an example of a moving body. Fig. 24B shows a simplified diagram of data exchange within the automobile. The automobile 590 has a plurality of cameras 591 and the like. The automobile 590 also includes various sensors (not shown) such as an infrared radar, a millimeter wave radar, and a laser radar.

[0296] In an automobile 590, the above-mentioned integrated circuit 390 (or a semiconductor chip 391 incorporating the above-mentioned integrated circuit 390) can be used for a camera 591 or the like. The automobile 590 processes a plurality of images obtained by the camera 591 in a plurality of imaging directions 592 using the integrated circuit 390 described in the above embodiment, and analyzes the plurality of images collectively using a host controller 594 or the like via a bus 593 or the like, thereby determining the surrounding traffic conditions, such as the presence or absence of guardrails or pedestrians, and performing automatic driving. The automobile 590 can also be used in a system that performs road guidance, hazard prediction, and the like.

[0297] In the integrated circuit 390, the obtained image data can be subjected to arithmetic processing such as a neural network, thereby enabling processes such as increasing the image resolution, reducing image noise, facial recognition (for crime prevention purposes, etc.), object recognition (for autonomous driving purposes, etc.), image compression, image correction (wide dynamic range), image restoration for lensless image sensors, positioning, character recognition, and reducing reflected glare.

[0298] In the above description, an automobile is described as an example of a moving body, but the moving body is not limited to an automobile. For example, a moving body may be a train, a monorail, a ship, an aircraft (helicopter, unmanned aerial vehicle (drone), airplane, rocket), etc., and a computer according to one embodiment of the present invention may be applied to these moving bodies to provide a system using artificial intelligence.

[0299] Fig. 25A is an external view showing an example of a portable electronic device. Fig. 25B is a simplified diagram showing data exchange within the portable electronic device. Portable electronic device 595 has a printed wiring board 596, a speaker 597, a camera 598, a microphone 599, and the like.

[0300] In portable electronic device 595, the integrated circuit 390 can be provided on printed circuit board 596. Portable electronic device 595 can improve user convenience by processing and analyzing a plurality of pieces of data obtained by speaker 597, camera 598, microphone 599, etc., using integrated circuit 390 described in the above embodiment. Also, the portable electronic device can be used in a system that performs voice guidance, image search, etc.

[0301] In the integrated circuit 390, the obtained image data can be subjected to arithmetic processing such as a neural network, thereby enabling processes such as increasing the image resolution, reducing image noise, facial recognition (for crime prevention purposes, etc.), object recognition (for autonomous driving purposes, etc.), image compression, image correction (wide dynamic range), image restoration for lensless image sensors, positioning, character recognition, and reducing reflected glare.

[0302] A portable game machine 1100 shown in FIG. 26A includes a housing 1101, a housing 1102, a housing 1103, a display unit 1104, a connection unit 1105, an operation key 1107, and the like. The housings 1101, 1102, and 1103 are removable. By attaching the connection unit 1105 provided in the housing 1101 to the housing 1108, a video output to the display unit 1104 can be output to another video device. On the other hand, by attaching the housings 1102 and 1103 to the housing 1109, the housings 1102 and 1103 are integrated to function as an operation unit. The integrated circuit 390 described in the above embodiment can be incorporated in a chip provided on a substrate of the housings 1102 and 1103.

[0303] 26B shows a stick-type electronic device 1120 of a USB connection type. The electronic device 1120 has a housing 1121, a cap 1122, a USB connector 1123, and a board 1124. The board 1124 is housed in the housing 1121. For example, a memory chip 1125 and a controller chip 1126 are attached to the board 1124. The integrated circuit 390 shown in the previous embodiment can be incorporated in the controller chip 1126 of the board 1124, etc.

[0304] 26C shows a humanoid robot 1130. The robot 1130 has sensors 2101 to 2106 and a control circuit 2110. For example, the integrated circuit 390 shown in the previous embodiment can be incorporated into the control circuit 2110.

[0305] The integrated circuit 390 described in the above embodiment can be used in a server that communicates with the electronic device instead of being built into the electronic device. In this case, the electronic device and the server constitute a computing system. Figure 27 shows an example of the configuration of a system 3000.

[0306] The system 3000 is configured with an electronic device 3001 and a server 3002. Communication between the electronic device 3001 and the server 3002 can be performed via an Internet line 3003.

[0307] Server 3002 has a plurality of racks 3004. A plurality of boards 3005 are provided in the plurality of racks, and integrated circuits 390 described in the above embodiment can be mounted on the boards 3005. This forms a neural network in server 3002. Server 3002 can perform neural network calculations using data input from electronic device 3001 via internet line 3003. Results of calculations by server 3002 can be transmitted to electronic device 3001 via internet line 3003 as necessary. This can reduce the calculation load on electronic device 3001.

[0308] This embodiment mode can be appropriately combined with the descriptions of other embodiment modes.

[0309] (Additional Notes Regarding the Description of the Present Specification, etc.) The above embodiment and each configuration in the embodiment will be described below with additional notes.

[0310] The configurations shown in each embodiment can be combined with the configurations shown in other embodiments or examples to form one aspect of the present invention. In addition, when multiple configuration examples are shown in one embodiment, the configuration examples can be combined as appropriate.

[0311] In addition, the content (or a part of the content) described in one embodiment can be applied to, combined with, or replaced by another content (or a part of the content) described in that embodiment, and / or the content (or a part of the content) described in one or more other embodiments.

[0312] The contents described in the embodiments refer to contents described in each embodiment using various figures or contents described using text in the specification.

[0313] In addition, a figure (or a part of it) described in one embodiment can be combined with another part of that figure, with another figure (or a part of it) described in that embodiment, and / or with a figure (or a part of it) described in one or more other embodiments to form even more figures.

[0314] In addition, in the present specification and the like, in the block diagrams, the components are classified by function and shown as mutually independent blocks. However, in actual circuits and the like, it is difficult to separate the components by function, and there may be cases where one circuit is involved in multiple functions, or where one function is involved across multiple circuits. Therefore, the blocks in the block diagrams are not limited to the components described in the specification, and may be rephrased appropriately according to the situation.

[0315] In addition, in the drawings, the size, layer thickness, or region are shown at an arbitrary size for convenience of explanation. Therefore, they are not necessarily limited to the scale. Note that the drawings are shown diagrammatically for clarity, and are not limited to the shapes or values ​​shown in the drawings. For example, it is possible to include variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing deviations.

[0316] In addition, the positional relationship of components shown in the drawings is relative. Therefore, when describing components with reference to the drawings, terms such as "above" and "below" that indicate the positional relationship may be used for convenience. The positional relationship of components is not limited to the contents described in this specification, and can be rephrased appropriately depending on the situation.

[0317] In this specification and the like, when describing the connection relationship of a transistor, the term "one of the source or drain" (or first electrode or first terminal) is used, and the other of the source and drain is used as the "other of the source or drain" (or second electrode or second terminal). This is because the source and drain of a transistor vary depending on the structure or operating conditions of the transistor. The source and drain of a transistor can be appropriately referred to as source (drain) terminal, source (drain) electrode, etc. depending on the situation.

[0318] In addition, the terms "electrode" and "wiring" used in this specification and the like do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring", and vice versa. Furthermore, the terms "electrode" and "wiring" include cases where multiple "electrodes" or "wirings" are formed integrally.

[0319] In addition, in this specification and the like, voltage and potential can be interchanged as appropriate. Voltage is a potential difference from a reference potential, and if the reference potential is a ground voltage (earth voltage), for example, voltage can be interchanged with potential. Ground potential does not necessarily mean 0V. Note that potential is relative, and the potential applied to wiring, etc. may be changed depending on the reference potential.

[0320] In this specification and the like, a node can be referred to as a terminal, a wiring, an electrode, a conductive layer, a conductor, an impurity region, etc. depending on a circuit configuration, a device structure, etc. Also, a terminal, a wiring, etc. can be referred to as a node.

[0321] In this specification, A and B are connected means that A and B are electrically connected. Here, A and B are electrically connected means a connection in which an electrical signal between A and B can be transmitted when an object (an element such as a switch, a transistor element, or a diode, or a circuit including the element and wiring) exists between A and B. Note that when A and B are electrically connected, this includes a case in which A and B are directly connected. Here, A and B are directly connected means a connection in which an electrical signal between A and B can be transmitted through wiring (or electrodes) between A and B without passing through the object. In other words, a direct connection means a connection that can be regarded as the same circuit diagram when expressed as an equivalent circuit.

[0322] In this specification, a switch refers to a device that has a function of controlling whether a current flows or not by being in a conductive state (on state) or a non-conductive state (off state), or a device that has a function of selecting and switching a path for a current to flow.

[0323] In this specification, the channel length refers to, for example, in a top view of a transistor, a region where a semiconductor (or a portion in the semiconductor through which current flows when the transistor is on) and a gate overlap, or a distance between the source and drain in a region where a channel is formed.

[0324] In this specification, the channel width refers to, for example, the length of the region where a semiconductor (or the portion in the semiconductor through which current flows when the transistor is on) and a gate electrode overlap, or the length of the portion where a source and a drain face each other in a region in which a channel is formed.

[0325] In this specification and the like, the terms "film" and "layer" can be interchanged depending on the circumstances. For example, the term "conductive layer" can be changed to the term "conductive film". Or, for example, the term "insulating film" can be changed to the term "insulating layer". [Explanation of symbols]

[0326] C11: Capacitor, CK1: Node, D1: Node, GCLK1: Clock signal, LBL_n: Wiring, LBL_N: Wiring, LBL_1: Wiring, LBL_4: Wiring, LBL_6: Wiring, M11: Transistor, M12: Transistor, M13: Transistor, PSE0: Signal, PSE1: Signal, PSE2: Signal, Q1: Node, RWL_M: Read word line, RWL_1: Read word line, SLEEP1: Signal, SN11: Node, t1: Time, t2: Time, t3: Time, t4: Time, t5: Time, t6: Time, t7: Time, T0: Time, T1: Time, T6 : time, WBL_1: write bit line, WWL_M: write word line, WWL_1: write word line, 10: semiconductor device, 12: drive circuit, 13: drive circuit, 14: control circuit, 15: processing circuit, 20: operation block, 21: transistor, 22: semiconductor layer, 23: transistor, 24: semiconductor layer, 30: memory circuit section, 31: circuit block, 32: memory circuit, 32_N: memory circuit, 32_P: memory circuit, 32A: memory circuit, 32B: memory circuit, 32C: memory circuit, 40: operation circuit section, 41: switching circuit, 42: product-sum operation circuit, 43: activation function operation arithmetic circuit, 44: quantization arithmetic circuit, 44_1: quantization arithmetic circuit, 44_9: quantization arithmetic circuit, 45: pre-pooling arithmetic circuit, 47: post-pooling arithmetic circuit, 46: dedicated arithmetic circuit, 46_1: dedicated arithmetic circuit, 46_2: dedicated arithmetic circuit, 46_3: dedicated arithmetic circuit, 51: multiplication circuit, 52: addition circuit, 53: register, 54: multiplexer, 55: comparison circuit, 56: register, 61: transistor, 61_N: transistor, 61_P: transistor, 61A: transistor, 61B: transistor, 62: transistor, 62_N: transistor, 62 _P: transistor, 62B: transistor, 63: transistor, 63_N: transistor, 63_P: transistor, 64: capacitive element, 64_N: capacitive element, 64_P: capacitive element, 64A: capacitive element, 64B: capacitive element, 100: arithmetic processing system, 110: CPU, 120: bus, 130: accelerator unit, 131: control unit, 193: PMU, 200: CPU core, 202: cache memory device, 203: cache memory device, 205: bus interface unit, 210: power switch, 211: power switch, 212: power switch,214: level shifter, 220: flip-flop, 221: scan flip-flop, 221A: clock buffer circuit, 222: backup circuit, 300N: OS memory, 311: substrate, 312: well region, 313: insulator, 314: oxide layer, 315: semiconductor region, 316a: low resistance region, 316b: low resistance region, 316c: low resistance region, 317: insulator, 318: conductor, 320: insulator, 322: insulator, 324: insulator, 326: insulator, 328: conductor, 330: conductor, 350: insulator, 352: insulator, 354: insulator, 35 6: conductor, 360: insulator, 362: insulator, 364: insulator, 366: conductor, 370: insulator, 372: insulator, 374: insulator, 376: conductor, 380: insulator, 382: insulator, 384: insulator, 386: conductor, 390: integrated circuit, 391: semiconductor chip, 392: lead, 393: Si transistor layer, 394: wiring layer, 395: OS transistor layer, 500: transistor, 503: conductor, 503a: conductor, 503b: conductor, 510: insulator, 512: insulator, 514: insulator, 516: insulator, 518: conductor, 522: insulator body, 524: insulator, 530: oxide, 530a: oxide, 530b: oxide, 540a: conductor, 540b: conductor, 542: conductor, 542a: conductor, 542b: conductor, 543a: region, 543b: region, 544: insulator, 545: insulator, 546: conductor, 548: conductor, 550: transistor, 560: conductor, 560a: conductor, 560b: conductor, 574: insulator, 580: insulator, 581: insulator, 582: insulator, 586: insulator, 590: automobile, 591: camera, 592: imaging direction, 593: bus, 594: host control controller, 595: portable electronic device, 596: printed wiring board, 597: speaker, 598: camera, 599: microphone, 600: capacitive element, 610: conductor, 612: conductor, 620: conductor, 630: insulator, 640: insulator, 1100: portable game machine, 1101: housing, 1102: housing, 1103: housing, 1104: display unit, 1105: connection unit, 1107: operation keys, 1108: housing, 1109: housing, 1120: electronic device, 1121: housing, 1122: cap, 1123: USB connector, 1124: board, 1125: memory chip,1126: controller chip, 1130: robot, 2101: sensor, 2106: sensor, 2110: control circuit, 3000: system, 3001: electronic device, 3002: server, 3003: internet line, 3004: rack, 3005: board,

Claims

[Claim 1] The memory device includes a plurality of memory circuits, a switching circuit, a first arithmetic circuit, and a second arithmetic circuit, Each of the plurality of memory circuits has a function of storing weight data, the switching circuit has a function of switching a conductive state between any one of the plurality of memory circuits and the first arithmetic circuit; the first arithmetic circuit outputs a first output signal based on a product-sum operation of input data and the weight data selected by the switching circuit to the second arithmetic circuit; the plurality of memory circuits are provided in a layer stacked on a layer having the switching circuit, the first arithmetic circuit, and the second arithmetic circuit.

Images