Power semiconductor device and power converter comprising the same

Abstract

To provide a power semiconductor device, a power semiconductor module and a power converter that improve the SCWA (Short Circuit withstand time) while minimizing the Ron increase.SOLUTION: A power semiconductor device 100 includes: a substrate 110; a first conductivity type epitaxial layer 120; a stepped second conductivity type well 130; source regions 140 disposed to be partially spaced apart from a first region of the stepped second conductivity type well; a buried insulating layer 150 disposed in a second region of the second conductivity type well between the source regions; a gate insulating layer 160 disposed on the stepped second conductivity type well; a gate 170 disposed on the gate insulating layer; an interlayer insulating layer 180 disposed on the gate; and a source electrode 190 disposed on the source regions. The stepped second conductivity type well includes a second conductivity type second-first well 131 having a width W1, and a second conductivity type second-second well 132 having a width W3 narrower than the width W1 and disposed under the second conductivity type second-first well.SELECTED DRAWING: Figure 3b

Description

[Technical field]

[0001] The embodiments relate to a power semiconductor element, a power semiconductor module including the power semiconductor element, and a power conversion device. The embodiments also relate to a method for manufacturing the power semiconductor element. [Background technology]

[0002] Power semiconductors are one of the key elements that determine the efficiency, speed, durability and reliability of power electronic systems.

[0003] Recently, with the development of the power electronics industry, the silicon ((Silicon)Si) power semiconductors that have been used until now have reached their physical limits, and research into WBG (Wide Bandgap) power semiconductors such as silicon carbide ((Silicon Carbide)SiC) and gallium nitride ((Galium Nitride)GaN) as replacements is being actively conducted.

[0004] WBG power semiconductor elements have a band gap energy approximately three times that of Si power semiconductor elements, which gives them the following characteristics: low intrinsic carrier concentration, high dielectric breakdown field (approximately 4 to 20 times), high thermal conductivity (approximately 3 to 13 times), and large electron saturation velocity (approximately 2 to 2.5 times).

[0005] These characteristics allow them to operate in high-temperature, high-voltage environments, and they have high switching speeds and low switching losses. Among these, gallium nitride (GaN) power semiconductor elements can be used in low-voltage systems, while silicon carbide (SiC) power semiconductor elements are suitable for high-voltage systems.

[0006] SiC MOSFET power semiconductors are generally referred to as VDMOSFET, which stands for vertical diffused structure, or simply as DMOSFET, which has a double-diffused structure. SiC MOSFETs can also be classified into planar MOSFETs and trench MOSFETs depending on the channel direction.

[0007] On the other hand, conventional SiC VDMOSFETs use a shallow P-well structure for ease of fabrication within the scope of ensuring the breakdown voltage, which has a lower R compared to deep P-wells. JFET (JFET refers to the distance between a pair of P-well regions located under a gate electrode.)

[0008] Meanwhile, for power semiconductor MOSFET devices with high power switching capabilities, the longer the Short Circuit Withstand Time (SCWT), which refers to the time during which the device can operate stably when exposed to a short circuit current, the more robust the device is.

[0009] Conventional SiC VDMOSFETs have superior electrical characteristics compared to Si MOSFETs due to their high breakdown voltage and low Ron characteristics, but they have a problem in that the device is less robust due to their relatively short SCWT. Summary of the Invention [Problem to be solved by the invention]

[0010] One of the technical objectives of the embodiment is to provide a power semiconductor device capable of solving the short SCWT (Short Circuit Withstand Time) problem of SiC MOSFETs and a power conversion device including the same.

[0011] The technical problems of the embodiments are not limited to those described in this section, but include those that can be understood from the description of the invention. [Means for solving the problem]

[0012] A power semiconductor device according to an embodiment may include a substrate and a stepped well, the stepped well may include a first region, a second region, and an insulating layer within the first region.

[0013] The first region may have a first width W1 and the second region may have a third width W3, the first width W1 being greater than the third width W3.

[0014] The second region may be located below the first region.

[0015] The insulating layer may be a buried insulating layer having a second width W2, and a third width W3 may be greater than the second width W2.

[0016] An embodiment further includes a source region including a first portion and a second portion, the first portion and the second portion of the source region being separated by the insulating layer.

[0017] At least a second region of the stepped well may be formed in a first conductivity type epitaxial layer over the substrate, the first and second regions of the stepped well both having a second conductivity type, and the source region may have the first conductivity type.

[0018] At least one of the substrate or epitaxial layer may include silicon carbide (SiC).

[0019] The doping concentration of the second region of the stepped well may be less than or equal to the doping concentration of the first region of the stepped well.

[0020] An embodiment may include a gate insulating film disposed on the stepped well, a gate disposed on the gate insulating layer, an interlayer insulating film disposed on the gate, and a source electrode disposed in a source region of the element.

[0021] Moreover, the embodiment further includes an ion implantation region disposed on at least one side of the stepped well, wherein a width of the source electrode contact region is greater than a width of the ion implantation region, and the source electrode contact region can be in contact with the source region and the ion implantation region.

[0022] An embodiment also includes a plurality of stepped wells, a first well of the plurality of stepped wells separated from a second well of the plurality of stepped wells by an ion implanted region.

[0023] Also, a power converter according to the embodiment may include one or more of any one of the power semiconductor devices.

[0024] In addition, a manufacturing method of a power semiconductor device according to an embodiment may include the steps of forming a first epitaxial layer of a first conductivity type and a first well of a second conductivity type on a substrate, forming a source region having a first conductivity type in the first well, forming an ion implantation region having a second conductivity type in the first well and penetrating the source region, extending deeper into the first well than the source region, forming one or more JFET (junction field effect) regions on both sides of the ion implantation region, forming a trench in the first well, and forming a stepped well structure having the first well and a second well below the first well.

[0025] An insulating layer is disposed in the trench.

[0026] The step of forming the stepped well structure may include performing ion implantation into a bottom surface of the trench to create a second well.

[0027] The step of forming the stepped well structure may include performing a number of ion implantation steps and performing an activation process.

[0028] The step of performing multiple ion implantations can include performing ion implantations with 90° tilt and rotation on each of the four sides of the trench, and at least one ion implantation on the bottom surface.

[0029] The second well may have a second conductivity type dopant concentration that is the same as or less than that of the first well.

[0030] In the stepped well structure, the second well may have a width smaller than a width of the first well.

[0031] The forming of the trench may produce a first portion of the source region and a second portion of the source region.

[0032] The insulating layer is disposed between the first portion and the second portion.

[0033] The first epitaxial layer in the region below the first well is not exposed due to the formation of the trench.

[0034] The power semiconductor device according to the embodiment may include a substrate 110, a first conductive type epitaxial layer 120 disposed on the substrate 110, a stepped second conductive type well 130 disposed on the first conductive type epitaxial layer 120, a source region 140 partially spaced apart in a first region of the stepped second conductive type well 130, a buried insulating layer 150 disposed in a second region of the second conductive type well 130 between the spaced apart source regions 140, a gate insulating layer 160 disposed on the stepped second conductive type well 130, a gate 170 disposed on the gate insulating layer 160, an interlayer insulating layer 180 disposed on the gate 170, and a source electrode 190 disposed on the source region 140.

[0035] The stepped second conductive type well 130 may include a second conductive type 2-1 well 131 having a first width W1, and a second conductive type 2-2 well 132 having a third width W3 narrower than the first width W1 and disposed below the second conductive type 2-1 well 131.

[0036] The buried insulating layer 150 is disposed in the second conductivity type well 130 between the spaced apart source regions 140 .

[0037] The horizontal width of the buried insulating layer 150 may have a third width W 3 that is smaller than the second width W 2 of the second conductive type 2-2 well 132 .

[0038] The doping concentration of the second conductive type 2-2 well 132 may be the same as or lower than the doping concentration of the second conductive type 2-1 well 131 .

[0039] The embodiment may further include a second conductivity type ion implantation region 135 disposed on one side of the stepped second conductivity type well 130 .

[0040] A horizontal width Ws of the contact region 190C of the source electrode 190 may be greater than a horizontal width of the second conductive type ion implantation region 135.

[0041] A contact region 190 C of the source electrode 190 may contact the source region 140 and the second conductive type ion implantation region 135 .

[0042] A method for manufacturing a power semiconductor device according to the embodiment includes the steps of forming a first epitaxial layer 120 of a first conductivity type and a first well 131 of a second conductivity type on a substrate 110, forming a source region 140 of a first conductivity type in the first well of the second conductivity type, forming an ion implantation region 135 of a second conductivity type in the first well so as to penetrate the source region and extend deeper into the first well than the source region, forming one or more junction field effect (JFET) regions 122 on both sides of the ion implantation region, forming a trench T in the first well and forming the trench T so that the first epitaxial layer in a region below the first well is not exposed by the formation of the trench, and forming a stepped well structure including the first well and a second well disposed below the first well.

[0043] Additionally, embodiments may further include forming an insulating layer 150 in the trench.

[0044] Forming the stepped well structure may include performing an ion implant into a bottom surface of the trench to create the second well.

[0045] The step of forming the stepped well structure may include a step of performing a plurality of ion implantation steps and an activation step.

[0046] The multiple ion implantation steps may include the steps of performing ion implantation with a 90° tilt and rotation on each of the four sides of the trench, and performing at least one or more ion implantations on the bottom surface.

[0047] The second well may have a second conductivity type dopant concentration that is the same as or lower than that of the first well.

[0048] In the stepped well structure, a width of the second well may be smaller than a width of the first well.

[0049] The step of forming the trench may include forming a first portion of the source region and a second portion of the source region, the insulating layer being disposed between the first portion and the second portion. Effect of the Invention

[0050] According to the power semiconductor device and the power semiconductor module and power conversion device including the same according to the embodiment, the stepped second conductive type well 130 is designed to be positioned deep, thereby minimizing the increase in Ron and improving the SCWT.

[0051] For example, according to the embodiment, the width of the second conductivity type 2-2 well 132 arranged on the lower side of the stepped second conductivity type well 130 is controlled to be smaller than the width of the second conductivity type 2-1 well 131 arranged on the upper side, thereby expanding and designing the JFET region so that it is further separated in the depth direction of the substrate, thereby maintaining high breakdown voltage characteristics and reducing R. JFET There is a special technical effect of improving the loss of Ron characteristics by preventing an increase in

[0052] In addition, according to the embodiment, by designing the stepped second conductivity type well 130 including the second conductivity type 2-2 well 132 to be positioned deeply, the physical distance between the bottom surface of the second conductivity type well 130 and the channel is increased and electric field concentration in the channel is alleviated, thereby improving the short channel effect and reducing the channel resistance.

[0053] In addition, according to the embodiment, a special technical effect of enhancing the SCWT characteristics is achieved by designing the stepped second conductivity type well 130, which includes the second conductivity type 2-1 well 131 and the second conductivity type 2-2 well 132 arranged with a narrow width below it, to be positioned deeply.

[0054] As a result, the embodiment has a special technical effect of increasing the SCWT (Short Circuit Withstand Time) of the SiC VDMOSFET, thereby improving the robustness of the power semiconductor device, the power semiconductor module including the same, and the power conversion device.

[0055] The technical effects of the embodiments are not limited to those described in this section, but include those that can be understood from the description of the invention. [Brief description of the drawings]

[0056] [Figure 1] FIG. 1 is a diagram illustrating a configuration example of a power conversion device according to an embodiment. [Diagram 2] FIG. 2 is a cross-sectional view of a power semiconductor element according to an embodiment. [Figure 3a] FIG. 3a is a cross-sectional view of a power semiconductor element according to an embodiment. [Figure 3b] 3b is a detailed cross-sectional view of the power semiconductor device according to the embodiment shown in FIG. 3a. [Figure 4a] FIG. 4a is a plan view of a power semiconductor element according to an embodiment. [Figure 4b] 4b is a partial three-dimensional cross-sectional view taken along line AA' of the power semiconductor device according to the embodiment shown in FIG. 4a. [Figure 5a] FIG. 5a is a cross-sectional view of a manufacturing process of a power semiconductor element according to an embodiment. [Figure 5b] FIG. 5b is a cross-sectional view of a manufacturing process of the power semiconductor element according to the embodiment. [Figure 5c] FIG. 5c is a cross-sectional view of a manufacturing process of the power semiconductor element according to the embodiment. [Figure 5d] FIG. 5D is a cross-sectional view of a manufacturing process of the power semiconductor device according to the embodiment. [Figure 5e] FIG. 5E is a cross-sectional view of a manufacturing process of the power semiconductor element according to the embodiment. [Figure 5f] FIG. 5F is a cross-sectional view of a manufacturing process of the power semiconductor element according to the embodiment. [Figure 5g] FIG. 5g is a cross-sectional view of a manufacturing process of the power semiconductor device according to the embodiment. [Figure 5h] FIG. 5H is a cross-sectional view of a manufacturing process of the power semiconductor device according to the embodiment. [Figure 5i] FIG. 5i is a cross-sectional view of a manufacturing process of a power semiconductor element according to an embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0057] Hereinafter, the invention according to the embodiment for solving the above problems will be described in more detail with reference to the drawings.

[0058] The suffixes "module" and "section" for components used in the following description are merely given to facilitate the writing of the specification and do not impart any particular significance or role to the components themselves. Therefore, the terms "module" and "section" can be used interchangeably.

[0059] Terms including ordinal numbers such as first, second, etc. may be used to describe various components, but the components are not limited by the terms. The terms are used only to distinguish one component from another.

[0060] A singular expression includes a plural expression unless the context clearly indicates otherwise.

[0061] In this application, the terms "including," "having," or "comprising" are intended to specify the presence of any feature, number, step, operation, component, part, or combination thereof set forth in the specification, but are not to be understood as precluding the presence or additional possibility of one or more other features, number, steps, operations, components, parts, or combinations thereof.

[0062] (Example) FIG. 1 is a diagram illustrating a configuration example of a power conversion device 1000 according to an embodiment.

[0063] The power conversion device 1000 according to the embodiment can receive DC power from a battery or a fuel cell, convert it into AC power, and supply the AC power to a predetermined load. For example, the power conversion device 1000 according to the embodiment can include an inverter, and can receive DC power from a battery, convert it into three-phase AC power, and supply it to a motor M. The motor M can provide power to an electric vehicle, a fuel cell vehicle, etc.

[0064] The power conversion device 1000 according to the embodiment may include at least one power semiconductor device 100. The power semiconductor device 100 may be, for example, a metal oxide semiconductor field effect transistor (MOSFET), but is not limited thereto, and may include an insulated gate bipolar transistor (IGBT) according to the embodiment. According to the embodiment, the SiC MOSFET of the embodiment may have various structures. For example, the embodiment may include a trench structure MOSFET, a vertical double injection structure MOSFET (DIMOSFET), or a side diffusion structure MOSFET.

[0065] For example, the power conversion device 1000 may include a plurality of power semiconductor elements 100a, 100b, 100c, 100d, 100e, and 100f. The power conversion device 1000 may also include a plurality of diodes (not shown). Each of the plurality of diodes may be included in the power semiconductor elements 100a, 100b, 100c, 100d, 100e, and 100f in the form of an internal diode, but is not limited thereto and may be disposed separately.

[0066] 1, DC power can be converted into AC power by controlling the on / off of a plurality of power semiconductor elements 100a-100f. For example, the power conversion device 1000 according to the embodiment can supply positive power to the motor M by turning on the first power semiconductor element 100a and turning off the second power semiconductor element 100b in a first time interval of one cycle, and can supply negative power to the motor M by turning off the first power semiconductor element 100a and turning on the second power semiconductor element 100b in a second time interval of one cycle.

[0067] In the embodiment, a group of power semiconductor elements arranged in series on the high voltage line and the low voltage line on the input side may be called an arm. For example, the first power semiconductor element 100a and the second power semiconductor element 100b may form a first arm, the third power semiconductor element 100c and the fourth power semiconductor element 100d may form a second arm, and the fifth power semiconductor element 100e and the sixth power semiconductor element 100f may form a third arm.

[0068] The upper and lower power semiconductor devices in each arm are controlled not to be turned on at the same time. For example, the first and second power semiconductor devices 100a and 100b in the first arm are not turned on at the same time but can be turned on and off alternately.

[0069] A high voltage is applied to each of the power semiconductor elements 100a-100f when the elements are turned off. For example, when the first power semiconductor element 100a is turned on and the second power semiconductor element 100b is turned off, the input voltage is applied to the second power semiconductor element 100b as is. The voltage input to the second power semiconductor element 100b is a relatively high voltage, and the withstand voltage of each of the power semiconductor elements 100a-100f is designed to be at a high level so that the elements can withstand such a high voltage.

[0070] Each of the power semiconductor elements 100a to 100f can conduct a high current when it is turned on. The motor M is driven by a relatively high current, and this high current is supplied to the motor M through the power semiconductors that are turned on.

[0071] A high voltage applied to each of the power semiconductor elements 100a-100f may induce high switching loss. A high current passing through the power semiconductor elements 100a-100f may induce high conduction loss. In order to dissipate heat generated by such losses, the power semiconductor elements 100a-100f may be packaged in a power semiconductor module including a heat dissipation means.

[0072] The power semiconductor device 100 of the embodiment may be a silicon carbide (SiC) power semiconductor device, which is capable of operating in a high temperature and high voltage environment and has a high switching speed and low switching loss.

[0073] Meanwhile, the power conversion device 1000 according to the embodiment may include a plurality of power semiconductor modules.

[0074] For example, the multiple power semiconductor elements 100a to 100f shown in FIG. 1 may be packaged in one power semiconductor module, or the power semiconductor elements constituting each arm may be packaged in one power semiconductor module.

[0075] For example, the first power semiconductor device 100a, the second power semiconductor device 100b, the third power semiconductor device 100c, the fourth power semiconductor device 100d, the fifth power semiconductor device 100e, and the sixth power semiconductor device 100f shown in FIG. 1 may be packaged into one power semiconductor module.

[0076] In order to increase the current capacity, additional power semiconductor elements may be arranged in parallel with each of the power semiconductor elements 100a to 100f. In this case, the number of power semiconductor elements included in the power semiconductor module may be more than six.

[0077] The power converter 1000 according to the embodiment may include a diode-type power semiconductor element in addition to the transistor-type power semiconductor elements 100a to 100f. For example, a first diode (not shown) may be arranged in parallel with the first power semiconductor element 100a, and a second diode (not shown) may be arranged in parallel with the second power semiconductor element 100b. Such diodes may also be packaged together in one power semiconductor module. The diodes may also be arranged in the form of internal diodes in each power semiconductor element.

[0078] Next, the power semiconductor elements constituting each arm may be packaged into one power semiconductor module.

[0079] For example, the first power semiconductor element 100a and the second power semiconductor element 100b constituting the first arm may be packaged in a first power semiconductor module, the third power semiconductor element 100c and the fourth power semiconductor element 100d constituting the second arm may be packaged in a second power semiconductor module, and the fifth power semiconductor element 100e and the sixth power semiconductor element 100f constituting the third arm may be packaged in a third power semiconductor module.

[0080] In addition, there may be additional power semiconductor elements arranged in parallel with each of the power semiconductor elements 100a-100f to increase the current capacity, and in this case, the number of power semiconductor elements included in each power semiconductor module may be more than two. Each arm may also include a diode-type power semiconductor element (not shown) in addition to the transistor-type power semiconductor elements 100a-100f, and such a diode may also be packaged together in one power semiconductor module. The diode may also be arranged in the form of an internal diode in each power semiconductor element.

[0081] Next, Fig. 2 is a cross-sectional view of one of the power semiconductor devices 100 according to the embodiment. The power semiconductor device 100 can be used in a circuit or other module, such as the power conversion device 1000 described in relation to Fig. 11.

[0082] A power semiconductor device 100 such as a MOSFET according to an embodiment may include a source electrode 190 and a gate electrode 175 disposed on a given semiconductor epitaxial layer 120 , and a drain electrode 105 disposed on a lower side of the semiconductor epitaxial layer 120 .

[0083] In an embodiment, the source electrode 190 or the gate electrode 175 may include an Al-based metal, and the drain electrode 105 may include, but is not limited to, Ti / Ni / Ag metal including a Ti layer, a Ni layer, and an Ag layer, NiV / Ag, V(vanadium) / Ni / Ag, etc.

[0084] One of the technical objectives of the embodiment is to provide a power semiconductor device that improves the low SCWT (short circuit withstand time) of SiC MOSFETs, and a power conversion device including the same.

[0085] Hereinafter, a power semiconductor device 100 according to an embodiment for solving the above technical problem will be described.

[0086] FIG. 3a is a cross-sectional view of a power semiconductor device 100 according to an embodiment, and FIG. 3b is a detailed view of the cross-sectional view of the power semiconductor device 100 according to the embodiment shown in FIG. 3a.

[0087] Next, FIG. 4a is a plan view of a power semiconductor device 100 according to an embodiment, and FIG. 4b is a partial three-dimensional cross-sectional view taken along line AA' of the power semiconductor device 100 according to the embodiment shown in FIG. 4a.

[0088] First, referring to FIG. 3a, the power semiconductor device 100 of the embodiment may include a substrate 110, a first conductive type epitaxial layer 120, a stepped second conductive type well 130, a buried insulating layer 150, a first conductive type source region 140, a gate insulating layer 160, a junction field region 122, a second conductive type ion implantation region 135 (see FIG. 4b), a gate 170, an interlayer insulating layer 180, and / or a source electrode 190.

[0089] The stepped second conductive type well 130 may include a second conductive type 2-1 well 131 and a second conductive type 2-2 well 132 .

[0090] The first conductivity type may be, but is not limited to, N-type and the second conductivity type may be, but is not limited to, P-type. The substrate 110 and the first conductivity type epitaxial layer 120 may include SiC (Silicon Carbide).

[0091] Specifically, referring to FIG. 3a, the power semiconductor device 100 of the embodiment may include a substrate 110, a first conductive type epitaxial layer 120 disposed on the substrate 110, a stepped second conductive type well 130 disposed on the first conductive type epitaxial layer 120, a source region 140 partially spaced apart in a first region of the stepped second conductive type well 130, a buried insulating layer 150 disposed in a second region of the second conductive type well 130 between the spaced apart source regions 140, and a second conductive type ion implantation region 135 disposed on one side of the stepped second conductive type well 130.

[0092] In addition, the power semiconductor device 100 of the embodiment may include a gate insulating layer 160 arranged on the stepped second conductive well 130, a gate 170 arranged on the gate insulating layer 160, an interlayer insulating layer 180 arranged on the gate 170, and a source electrode 190 arranged on the source region 140.

[0093] On the other hand, ion implantation is not easy for SiC (Silicon Carbide) used in the embodiment due to its material characteristics. For example, ion implantation must be performed with an energy of about 650 KeV to form a p-well of about 1 μm, but there are technical difficulties in applying this to mass production to form a well by implanting ions to a depth of 2 μm to 3 μm.

[0094] As a result, the embodiment can solve the above technical difficulties. For example, the embodiment forms a second conductive type 2-1 well 131, removes a portion of the second conductive type 2-1 well 131 to form a trench structure, and then performs ion implantation using the trench structure to form a second conductive type 2-2 well 132, thereby implementing a stepped second conductive type well 130, thereby enhancing SCWT characteristics.

[0095] Specifically, referring to FIG. 3b, the stepped second conductive type well 130 may include a second conductive type 2-1 well 131 having a first width W1 and a second conductive type 2-2 well 132 having a third width W3 narrower than the first width W1 and disposed below the second conductive type 2-1 well 131.

[0096] The buried insulating layer 150 is disposed in the second conductivity type well 130 between the spaced apart source regions 140 and may have a third width W3 that is smaller than the second width W2 of the second conductivity type 2-2 well 132.

[0097] As a result, according to the embodiment, by providing the stepped second conductivity type well 130 including the second conductivity type 2-1 well 131 having a first width W1 and the second conductivity type 2-2 well 132 arranged therebelow, which has a third width W3 narrower than the first width W1, there is a technical effect of enhancing the SCWT characteristics (internal technology significantly improves the SCWT of a VDMOSFET from a level of approximately 2.4 μs to a level of approximately 6.8 μs when the present invention is applied).

[0098] In particular, according to the embodiment, the third width W3 of the second conductive type 2-2 well 132 arranged on the lower side is controlled to be smaller than the first width W1 of the second conductive type 2-1 well 131 arranged on the upper side, so that the JFET region is designed to be further separated in the depth direction of the substrate, thereby maintaining high breakdown voltage characteristics and reducing R. JFET There is a special technical effect of improving the loss of Ron characteristics by preventing an increase in

[0099] For example, the distance between a pair of second-conductivity type 2-2 wells 132 (about twice JW2) is designed to be wider than the distance between a pair of second-conductivity type 2-1 wells 131 arranged thereover (about twice JW1). JFET There is a special technical effect that the Ron characteristic can be improved by preventing an increase in

[0100] Next, FIG. 4a is a plan view of a power semiconductor element 100 according to an embodiment, and FIG. 4b is a partial three-dimensional cross-sectional view along line A-A' of the power semiconductor element 100 according to the embodiment shown in FIG. 4a (the buried insulating layer 150 is omitted).

[0101] 4a and 4b, the power semiconductor device 100 of the embodiment may include a substrate 110, a first conductive type epitaxial layer 120 disposed on the substrate 110, a stepped second conductive type well 130 disposed on the first conductive type epitaxial layer 120, source regions 140 partially spaced apart in a first region of the stepped second conductive type well 130, a buried insulating layer 150 disposed in the second conductive type well 130 between the spaced apart source regions 140, and a second conductive type ion implantation region 135 disposed on one side of the stepped second conductive type well 130.

[0102] Referring to FIG. 4b, the power semiconductor device 100 of the embodiment may include a source electrode 190 disposed on the source region 140 and the second conductive type ion implantation region 135, and the horizontal width Ws of the source electrode contact region 190C may be greater than the horizontal width of the second conductive type ion implantation region 135 and may be in contact with the source region 140 and the second conductive type ion implantation region 135.

[0103] Referring to FIG. 4b, in the embodiment, the width of the second conductive type 2-2 well 132 arranged on the lower side is controlled to be smaller than the width of the second conductive type 2-1 well 131 arranged on the upper side, so that the JFET region is designed to be further separated in the depth direction of the substrate, thereby maintaining high breakdown voltage characteristics and reducing R. JFET There is a special technical effect of improving the loss of Ron characteristics by preventing an increase in

[0104] In addition, according to the embodiment, a special technical effect of enhancing the SCWT characteristics is achieved by designing the stepped second conductivity type well 130, which includes the second conductivity type 2-1 well and the second conductivity type 2-2 well 132 arranged with a narrow width below it, to be positioned deeply.

[0105] As a result, the embodiments have a special technical effect of increasing the robustness of a power semiconductor device, a power semiconductor module including the same, and a power conversion device, which can increase the SCWT (Short Circuit Withstand Time) of a SiC VDMOSFET.

[0106] Next, a manufacturing process of the power semiconductor device 100 according to the embodiment will be described with reference to FIGS. 5a to 5i.

[0107] 5a, a substrate 110 including a first conductive type epitaxial layer 120 may be prepared, and a second conductive type 2-1 well 131 may be formed in the first conductive type epitaxial layer 120. The substrate 110 and the first conductive type epitaxial layer 120 may include, but are not limited to, a 4H-SiC material. For example, the substrate 110 and the first conductive type epitaxial layer 120 may include, but are not limited to, a 3C-SiC or 6H-SiC material. The first conductive type epitaxial layer 120 may be, but is not limited to, an N-type drift region.

[0108] The second conductive type 2-1 well 131 has a P-type dopant concentration of about 1×10 16 cm -3 ~Approx. 1×1019 cm -3 For example, Al, boron, or the like may be implanted, but the present invention is not limited to this.

[0109] 5b, a first conductive type source region 140 may be formed in the second conductive type 2-1 well 131. For example, an N-type dopant such as nitrogen or phosphorus may be doped at about 1×10 17 cm -3 ~Approx. 2×10 20 cm -3 The first conductive type source region 140 may be formed by implanting ions at a concentration of 100 .mu.m or more.

[0110] 5c, a second conductive type ion implantation region 135 may be formed. For example, Al, boron, or the like may be implanted into the second conductive type 2-1 well 131 at a deeper position through the first conductive type source region 140 to form the second conductive type ion implantation region 135.

[0111] 5d, junction field regions 122 may be formed on both sides of the second conductive type ion implantation region 135. The junction field regions 122 may be referred to as JFET regions. The junction field regions 122 may be formed by ion implantation of a P-type dopant such as phosphorus, and may improve Vth, saturation current, and on-resistance characteristics.

[0112] 5e, a trench T may be formed in the second conductive type 2-1 well 131. For example, the trench T may be formed to etch away a portion of the source region 140, the second conductive type ion implantation region 135, and the second conductive type 2-1 well 131. The trench T prevents the first conductive type epi layer 120 from being exposed.

[0113] Next, referring to Figures 5f and 5g (Figure 5g is a three-dimensional cross-section of Figure 5f), a second conductivity type 2-2 well 132 can be formed on the bottom and sidewalls of the trench T by an ion implantation process to manufacture a stepped second conductivity type well 130.

[0114] For example, the second-conductivity-type 2-2 well 132 can be formed by ion implantation into the sidewalls and bottom surface of the trench T of the second-conductivity-type 2-1 well 131, thereby manufacturing the stepped second-conductivity-type well 130. For example, after four ion implantations with 90° inclination and rotation are performed on each of the four sidewall surfaces and one ion implantation on the bottom surface, the second-conductivity-type 2-2 well 132 can be formed by an activation process.

[0115] In addition, according to the embodiment, the width of the second conductive type 2-2 well 132 arranged on the lower side is controlled to be smaller than the width of the second conductive type 2-1 well 131 arranged on the upper side, so that the JFET region is designed to be further separated in the depth direction of the substrate, thereby maintaining high breakdown voltage characteristics and reducing R. JFET There is a special technical effect of improving the loss of Ron characteristics by preventing an increase in

[0116] 5h, a buried insulating layer 150 may be formed in the second conductive well 130 between the source regions 140 spaced apart by trenches. The buried insulating layer 150 may be formed of an oxide, a nitride, or the like.

[0117] Next, referring to FIG. 5i, a gate insulating layer 160 is formed on the stepped second conductive well 130, a gate 170 is formed on the gate insulating layer 160, an interlayer insulating layer 180 is formed on the gate 170, and a source electrode 190 can be formed on the source region 140 after partially opening the interlayer insulating layer 180.

[0118] The gate insulating layer 160 may be, but is not limited to, a thermal oxide film or a deposited oxide film. The gate 170 may be, but is not limited to, polysilicon. The interlayer insulating layer 180 may be, but is not limited to, an oxide film or a nitride film. The source electrode 190 may be, but is not limited to, Al.

[0119] According to the power semiconductor device and the power semiconductor module and power conversion device including the same according to the embodiment, the stepped second conductive type well 130 is designed to be positioned deeply, thereby minimizing the increase in Ron and improving the SCWT.

[0120] The design and manufacture of power semiconductor devices is in a race for optimum performance, which can sometimes give rise to conflicting problems.

[0121] For example, as described above, a power semiconductor MOSFET device having a high power switching function can have higher robustness as the Short Circuit Withstand Time (SCWT) increases.

[0122] On the other hand, SiC VDMOSFETs with shallow P-well structure, which are adopted for ease of fabrication within the scope of ensuring the breakdown voltage, have a problem in that the device has low robustness due to its relatively short SCWT.

[0123] In order to solve such problems, one of the technical objectives of the embodiment is to provide a power semiconductor element including a stepped second conductive type well designed to be located deep, and a power conversion device including the same.

[0124] According to some embodiments, the stepped second conductivity type well 130 may include a second conductivity type 2-1 well 131 arranged at an upper portion and a second conductivity type 2-2 well 132 arranged at a lower portion. In this case, the width of the second conductivity type 2-2 well 132 arranged at the lower portion is controlled to be smaller than the width of the second conductivity type 2-1 well 131 arranged at the upper portion. Thus, the JFET regions are designed to be further apart in the depth direction of the substrate. Thus, a high withstand voltage characteristic is maintained and R JFET This has the special technical effect of preventing an increase in the Ron characteristic and improving the loss of the Ron characteristic.

[0125] According to some embodiments, a power semiconductor device may include a substrate, a first conductivity type epilayer disposed on the substrate, a stepped second conductivity type well disposed on the first conductivity type epilayer, a source region partially spaced from a first region, a buried insulating layer disposed in a second region of the second conductivity type well between the spaced-apart source region, a gate insulating layer disposed on the stepped second conductivity type well, a gate disposed on the gate insulating layer, an interlayer insulating layer disposed on the gate, and a source electrode disposed on the source region.

[0126] The stepped second conductivity type well of the embodiment may include a second conductivity type 2-1 well having a first width, and a second conductivity type 2-2 well having a third width narrower than the first width and disposed below the second conductivity type 2-1 well.

[0127] The buried insulating layer is disposed in a region of the well of the second conductivity type between the spaced apart source regions.

[0128] The lateral width of the buried insulating layer may be a second width smaller than a third width of the second conductivity type 2-2 well.

[0129] The doping concentration of the second conductivity type 2-2 well may be equal to or lower than the doping concentration of the second conductivity type 2-1 well.

[0130] Also, the power semiconductor device according to the embodiment may include a second conductivity type ion implantation region disposed on one side of the stepped second conductivity type well.

[0131] The lateral width of the contact region of the source electrode may be larger than the lateral width of the second conductivity type ion implantation region.

[0132] The contact area of ​​the source electrode can contact the source region and the second conductivity type ion implanted region.

[0133] A power converter according to an embodiment may include at least one of the power semiconductor devices described above.

[0134] In addition, according to the embodiment, the stepped second conductive type well 130 may include a second conductive type 2-1 well 131 and a second conductive type 2-2 well 132 arranged at a narrow width below the second conductive type 2-1 well 131, and the second conductive type 2-2 well 132 is designed to be positioned deep, resulting in a special technical effect of improving SCWT characteristics.

[0135] Although various embodiments are described herein, they are presented by way of example only and should not be construed as limiting the scope of the invention. Thus, the breadth and scope of the present invention should not be limited by any of the exemplary aspects described above. Moreover, any combination of the above-described elements in all possible variations thereof is encompassed by the present disclosure unless otherwise expressly stated herein or clearly contradicted by context.

[0136] Also, while the methods have been described as a series of steps, it will be understood that this is for purposes of illustration only, and that steps may be added or omitted, the order of steps may be rearranged, and some steps may be performed in parallel.

Claims

1. A substrate; a stepped well; The step well includes a first region, a second region, and an insulating layer within the first region.

2. The first region has a first width W1, The second region has a third width W3. The power semiconductor device according to claim 1 , wherein the first width W1 is greater than a third width W3.

3. The second region is located below the first region, the insulating layer is a buried insulating layer having a second width W2; The power semiconductor device according to claim 2 , wherein the third width W3 is greater than the second width W2.

4. further comprising a source region including a first portion and a second portion; The power semiconductor device of claim 1 , wherein the first and second portions of the source region are separated by the insulating layer.

5. (i) at least a second region of the step well is formed in a first conductivity type epitaxial layer on the substrate; (ii) the first region and the second region of the step well both have a second conductivity type; 5. The power semiconductor device of claim 4, wherein (iii) the source region has the first conductivity type.

6. at least one of the substrate or epitaxial layer comprises silicon carbide (SiC); The power semiconductor device of claim 5 , wherein a doping concentration of the second region of the stepped well is less than or equal to a doping concentration of the first region of the stepped well.

7. a gate insulating film disposed on the stepped well; a gate disposed on the gate insulating layer; an interlayer insulating film disposed on the gate; The power semiconductor device according to claim 1 .

8. further comprising an ion implantation region disposed on at least one side of the stepped well; a width of the contact region of the source electrode is greater than a width of the ion implantation region; The power semiconductor device according to claim 7 , wherein the contact region of the source electrode contacts the source region and the ion-implanted region.

9. A plurality of stepped wells are included; The power semiconductor device of claim 1 , wherein a first well of the plurality of stepped wells is separated from a second well of the plurality of stepped wells by an ion implantation region.

10. A power conversion device comprising one or more power semiconductor elements according to any one of claims 1 to 9.

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