SiC EPITAXIAL WAFER

Abstract

To provide a SiC epitaxial wafer capable of estimating the density of basal plane dislocation in a SiC substrate in a nondestructive manner.SOLUTION: A SiC epitaxial wafer according to the present embodiment includes a SiC substrate and a SiC epitaxial layer deposited on the SiC substrate, wherein the SiC substrate has a basal plane dislocation density of 1 dislocation / cm2 or more and 3000 dislocations / cm2 or less, and the SiC epitaxial layer has a double Shockley (2SSF) type stacking fault density of 4 dislocations / cm2 or more and 10 dislocations / cm2 or less and has a stacking fault density other than the double Shockley (2SSF) type stacking fault density of 2 dislocations / cm2.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a SiC epitaxial wafer. [Background technology]

[0002] Silicon carbide (SiC) has an electric breakdown field one order of magnitude larger than silicon (Si) and a band gap three times larger. Silicon carbide (SiC) also has properties such as a thermal conductivity about three times higher than silicon (Si). For this reason, silicon carbide (SiC) is expected to be applied to power devices, high-frequency devices, high-temperature operating devices, and the like. For this reason, SiC epitaxial wafers have come to be used in the above-mentioned semiconductor devices in recent years.

[0003] SiC epitaxial wafers are obtained by stacking a SiC epitaxial layer on the surface of a SiC substrate. Hereinafter, the substrate before the SiC epitaxial layer is stacked is referred to as the SiC substrate, and the substrate after the SiC epitaxial layer is stacked is referred to as the SiC epitaxial wafer. SiC substrates are produced by slicing from SiC ingots. SiC devices such as power devices, high frequency devices, and high temperature operating devices are obtained by forming devices in the SiC epitaxial layer of the SiC epitaxial wafer and then chipping the SiC epitaxial wafer.

[0004] SiC epitaxial wafers generally contain inherent crystal defects. Some crystal defects adversely affect downstream processes and impede the normal operation of SiC devices. Such defects are called killer defects. For example, basal plane dislocations (BPDs) are said to cause stacking faults, which are one type of killer defect (see, for example, Patent Document 1).

[0005] Furthermore, Patent Document 2 discloses that there are multiple types of stacking faults, and discloses a method for reducing the total number of stacking faults and among them, double-Shockley type stacking faults. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Patent No. 5961357 [Patent Document 2] Patent No. 6824088 Summary of the Invention [Problem to be solved by the invention]

[0007] As described above, understanding the location and number of basal plane dislocations (BPDs), which cause killer defects, is important when fabricating SiC devices. However, after stacking the SiC epitaxial layer, it is difficult to nondestructively determine the location where basal plane dislocations are concentrated and the number of basal plane dislocations in the SiC substrate.

[0008] The present invention has been made in consideration of the above problems, and has an object to provide a SiC epitaxial wafer that makes it possible to estimate the positions where basal plane dislocations are concentrated and the number of basal plane dislocations in a SiC substrate even after a SiC epitaxial layer is stacked. [Means for solving the problem]

[0009] (1) A SiC epitaxial wafer according to a first aspect includes a SiC substrate and a SiC epitaxial layer formed on the SiC substrate. The SiC substrate has a basal plane dislocation density of 1 / cm. 2 More than 3000 pieces / cm 2 The SiC epitaxial layer has a double Shockley (2SSF) stacking fault density of 4 / cm 2 More than 10 pieces / cm 2 The density of stacking faults other than the double Shockley (2SSF) type stacking faults is 2 / cm or less. 2 The following is the result.

[0010] (2) The SiC epitaxial wafer according to the above aspect may have a diameter of 145 mm or more.

[0011] (3) The SiC epitaxial wafer according to the above aspect may have a diameter of 195 mm or more.

[0012] (4) The SiC epitaxial wafer according to the above aspect has a double Shockley (2SSF) stacking fault density of 6 / cm 2 More than 10 pieces / cm 2 The following is also fine.

[0013] (5) The SiC epitaxial wafer according to the above aspect has a double Shockley (2SSF) stacking fault density of 8 / cm 2 More than 10 pieces / cm 2 The following is also fine.

[0014] (6) The SiC epitaxial wafer according to the above aspect has a double Shockley (2SSF) stacking fault density of 4 / cm 2 More than 6 pieces / cm 2 The following is also fine. Effect of the Invention

[0015] In the SiC epitaxial wafer according to the above aspect, even after the SiC epitaxial layer is laminated, the positions where basal plane dislocations are concentrated and the number of basal plane dislocations in the SiC substrate can be estimated. [Brief description of the drawings]

[0016] [Figure 1] FIG. 2 is a cross-sectional view of the SiC substrate according to the embodiment. [Diagram 2] FIG. 2 is a plan view of the SiC substrate according to the embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0017] The SiC epitaxial wafer and the like according to this embodiment will be described in detail below with reference to the drawings as appropriate. The drawings used in the following description may show characteristic parts in an enlarged scale for the sake of convenience in order to make the characteristics of this embodiment easier to understand, and the dimensional ratios of each component may differ from the actual ones. The materials, dimensions, and the like exemplified in the following description are merely examples, and the present invention is not limited thereto, and may be appropriately modified and implemented within the scope of the present invention.

[0018] In this specification, individual orientations are indicated by [] and collective orientations by <>. For negative indices, a "-" (bar) is placed above the number in crystallography, but in this specification, a negative sign is placed before the number.

[0019] Fig. 1 is a cross-sectional view of a SiC epitaxial wafer 1 according to the present embodiment. Fig. 2 is a plan view of the SiC epitaxial wafer 1 according to the present embodiment.

[0020] The SiC epitaxial wafer 1 includes a SiC substrate 2 and a SiC epitaxial layer 3. The shape of the SiC epitaxial wafer 1 in a plan view is substantially circular. The SiC epitaxial wafer 1 may have a notch 4 for grasping the direction of the crystal axis. The SiC substrate 10 may have an orientation flat instead of the notch 4.

[0021] The diameter of the SiC epitaxial wafer 1 is, for example, 145 mm or more, and preferably 149 mm or more. The diameter of the SiC epitaxial wafer 1 is preferably 155 mm or less, and more preferably 151 mm or less. The diameter of the SiC epitaxial wafer 1 may be, for example, 195 mm or more, and preferably 199 mm or more. The diameter of the SiC epitaxial wafer 1 is preferably 205 mm or less, and more preferably 201 mm or less.

[0022] The SiC substrate 2 is made of, for example, n-type SiC. The polytype of the SiC substrate 2 is not particularly limited and may be any of 2H, 3C, 4H, and 6H. The SiC substrate 2 is, for example, 4H—SiC.

[0023] The SiC substrate 2 has a basal plane dislocation (BPD) density of 1 / cm 2 More than 3000 pieces / cm 2 The reason is as follows. If basal plane dislocations in the SiC substrate 2 are inherited by the SiC epitaxial layer 3, they may generate stacking faults, which are a type of killer defect. For this reason, it is ideal for the SiC substrate 2 to be free of basal plane dislocations. However, it is difficult to stably manufacture a SiC substrate that does not have basal plane dislocations. In contrast, if the SiC substrate 2 has a basal plane dislocation density within a desired range, it can be manufactured relatively stably. In other words, if the density of basal plane dislocations is less than 1 / cm, 2 More than 3000 pieces / cm 2 The following SiC substrate 2 satisfies the required quality and is stably available.

[0024] In the SiC epitaxial wafer 1 according to the present disclosure, since the positions where basal plane dislocations are concentrated in the SiC substrate 2 and the number of basal plane dislocations can be estimated after laminating the SiC epitaxial layer 3, it is not necessary to constantly measure the density of basal plane dislocations in the SiC substrate 2. When it becomes necessary to evaluate the density of basal plane dislocations in the SiC substrate 2, it can be measured, for example, by using a photoluminescence method.

[0025] The SiC epitaxial layer 3 is laminated on one surface of the SiC substrate 2. The SiC epitaxial layer 3 has a double Shockley (2SSF) stacking fault density of 4 / cm 2 More than 10 pieces / cm 2 The density of double Shockley (2SSF) stacking faults is 6 / cm 2 More than 10 pieces / cm 2 More preferably, 7 / cm or less. 2 More than 10 pieces / cm 2 More preferably, 8 particles / cm or less. 2 More than 10 pieces / cm 2It is particularly preferable that the density range is 4 / cm or less. When the density range is within this range, it is easier to grasp the positions where many basal plane dislocations are concentrated in the SiC substrate (i.e., positions with high basal plane dislocation density) and the number of basal plane dislocations. In addition, the density of double Shockley (2SSF) stacking faults is 4 / cm or less. 2 More than 6 pieces / cm 2 or less. When the density range is within this range, the occurrence of device failure can be suppressed while grasping the positions where many basal plane dislocations are concentrated in the SiC substrate (i.e., positions with high basal plane dislocation density) and the number of basal plane dislocations. Double Shockley (2SSF) stacking faults are caused by basal plane dislocations.

[0026] The SiC epitaxial layer 3 has a stacking fault density of 2 / cm other than double Shockley (2SSF) type stacking faults. 2 The density of stacking faults other than double Shockley (2SSF) type stacking faults is 1 / cm 2 It is preferable that the number of particles is less than 0.5 / cm. 2 It is more preferable that the density of stacking faults other than double Shockley (2SSF) type stacking faults is lower, so that device failures due to stacking faults other than double Shockley (2SSF) type stacking faults can be further suppressed.

[0027] There are various types of stacking faults. They are classified into Frank type, Shockley type, and mixed type. Furthermore, within each of the Frank type, Shockley type, and mixed type, they are further classified according to the number of layers in which the defect occurs. Table 1 shows the classification of stacking faults. Table 1 corresponds to Table 1 in Kamata et al., Appl. Phys. Lett. 97, 172107 (2010).

[0028] [Table 1]

[0029] The classification of stacking faults can be determined by the following procedure. First, a mapping of stacking faults in the SiC epitaxial wafer 1 is measured using a photoluminescence method. The density of stacking faults in the SiC epitaxial layer 3 is, for example, 4 / cm. 2 More than 12 pieces / cm 2 At this point, it is not possible to classify each of the stacking faults, and it is not clear what type they are.

[0030] Next, a spectrum measurement is performed for each of the mapped stacking faults. The spectrum measurement is performed using MiPLATO manufactured by EtaMax. In the spectrum measurement, light with an excitation wavelength of 355 nm is irradiated onto the SiC epitaxial layer 3, and the fluorescence wavelength generated from each stacking fault is measured. The fluorescence wavelength is measured by using a spectrometer to measure the intensity of the light generated from the stacking faults for each wavelength, and the peak wavelength at which the emission intensity is maximum is determined. The band gap of the stacking fault varies depending on the number of layers in the stacking direction in which the defect occurs, and the peak wavelength of the emission from the stacking fault also varies depending on the difference in the band gap. Therefore, each stacking fault can be classified based on the assumed peak wavelength of the spectrum.

[0031] The double Shockley type stacking fault has a peak wavelength of 500 nm. The double Shockley type stacking fault is one of the killer defects, and ideally should not exist. The double Shockley type stacking fault occurs due to basal plane dislocations in the SiC substrate 2. When the SiC substrate 2 has a certain number or more of basal plane dislocations, it is difficult to reduce the number of double Shockley type stacking faults to zero. Since the SiC substrate 2 in the present disclosure has a certain number or more of basal plane dislocations, the SiC epitaxial layer 3 has double Shockley type stacking faults caused by basal plane dislocations.

[0032] Stacking faults other than double Shockley type stacking faults have peak wavelengths at positions other than 500 nm. Stacking faults other than double Shockley type stacking faults can also be killer defects. The fewer stacking faults other than double Shockley type stacking faults, the better, and their density should be 2 / cm. 2It is preferable that the stacking faults other than the double Shockley type stacking faults are caused by factors other than basal plane dislocations.

[0033] The SiC epitaxial layer 3 of the SiC epitaxial wafer 1 according to this embodiment has almost no stacking faults other than double Shockley type stacking faults. Therefore, it can be estimated that most of the stacking faults confirmed after the SiC epitaxial layer 3 is stacked are caused by basal plane dislocations in the SiC substrate 2. Therefore, in the SiC epitaxial wafer 1 according to this embodiment, the position where many basal plane dislocations are concentrated and the number of basal plane dislocations in the SiC substrate 2 can be estimated by measuring the stacking faults after the SiC epitaxial layer 3 is formed by a photoluminescence method. If the SiC epitaxial layer 3 has many stacking faults other than double Shockley type stacking faults, the estimation accuracy is reduced. However, since the SiC epitaxial layer 3 of the SiC epitaxial wafer 1 according to this embodiment has almost no stacking faults other than double Shockley type stacking faults, the estimation accuracy is high. Information on the density, position, number, etc. of basal plane dislocations in SiC substrate 2 is important information for quality assurance of SiC epitaxial wafer 1.

[0034] As described above, the SiC epitaxial wafer 1 according to this embodiment can non-destructively estimate the positions where many basal plane dislocations are concentrated in the SiC substrate 2 and the number of basal plane dislocations, even after the SiC epitaxial layer 3 is laminated. Therefore, the SiC epitaxial wafer 1 according to this embodiment is a highly reliable SiC epitaxial wafer, with the quality of the SiC substrate 2 also being guaranteed. Furthermore, in the SiC substrate 2, positions where many basal plane dislocations are concentrated (i.e., positions where the basal plane dislocation density is high) are likely to cause device failure. The SiC epitaxial wafer 1 according to this embodiment can grasp in advance the positions of parts where device failure is likely to occur.

[0035] Next, a method for manufacturing the SiC epitaxial wafer 1 according to this embodiment will be described.

[0036] First, a SiC substrate 2 is prepared. The SiC substrate 2 has a basal plane dislocation density of 4 / cm 2 More than 3000 pieces / cm 2 The following is used: Although it is difficult to obtain and fabricate a SiC substrate without basal plane dislocations, it is relatively easy to obtain a SiC substrate 2 having basal plane dislocations within a predetermined range.

[0037] Next, the SiC epitaxial layer 3 is laminated on the SiC substrate 2. The SiC epitaxial layer 3 is formed by using, for example, a chemical vapor deposition method (CVD method).

[0038] In the SiC epitaxial layer 3 according to the present embodiment, it is necessary to selectively control the density of a specific defect among stacking faults, and therefore more strict control is required compared to the case of controlling the density of all stacking faults. The crystal growth conditions that bring the density of a specific defect among stacking faults into a specific range may differ for each film formation apparatus, and tuning according to each film formation apparatus is required.

[0039] Therefore, first, as a pre-process, the growth conditions of the SiC epitaxial layer 3 are tuned. In the pre-process, the growth conditions of the SiC epitaxial layer 3 are determined to suit a specific film formation apparatus. This pre-process is performed for each film formation apparatus. In addition, if the inside of the film formation apparatus is cleaned, the pre-process is performed again. In the pre-process, the adjusted film formation is repeated multiple times until the growth conditions of the SiC epitaxial layer 3 are determined. In the pre-process, the parameters of temperature, C / Si ratio, and growth rate are changed in three stages: the initial, middle, and final stages of crystal growth.

[0040] For example, if one only wants to reduce double-Shockley type stacking faults, this can be achieved by setting the C / Si ratio in three stages, the initial, middle, and final stages of crystal growth, within preferred ranges, as described in Patent Document 2. On the other hand, if one wants to reduce the number of stacking faults other than double-Shockley type while keeping the number of double-Shockley type stacking faults within a specified range, this cannot be achieved by simply setting an optimal range. It is necessary to determine the conditions in advance of the process, taking into account the unique characteristics of each device.

[0041] First, in the first adjustment deposition, the temperature, C / Si ratio, and growth rate of each of the three growth stages are set as first conditions to deposit the SiC epitaxial layer 3. After the first adjustment deposition, the SiC epitaxial layer 3 is subjected to photoluminescence measurement to determine the density of a predetermined stacking fault in the SiC epitaxial layer 3.

[0042] Next, in the second adjusted deposition, the SiC epitaxial layer 3 is deposited under second conditions obtained by changing at least one of the temperature, C / Si ratio, and growth rate in each of the three growth stages from the first conditions. After the second adjusted deposition, the SiC epitaxial layer 3 is subjected to photoluminescence measurement to determine the density of a predetermined stacking fault in the SiC epitaxial layer 3.

[0043] Then, the results of the first and second adjustment depositions are fed back to determine the conditions for the third adjustment deposition. In the third adjustment deposition, at least one of the temperature, C / Si ratio, and growth rate in each of the three growth stages is changed from the first and second conditions.

[0044] This process of adjusting the film formation and feedback of the measurement results is repeated to determine the final growth conditions for the SiC epitaxial layer 3. The process of adjusting the film formation and feedback of the measurement results is repeated while minutely changing the growth conditions, and the final growth conditions for the SiC epitaxial layer 3 are precisely determined according to the unique characteristics of each film formation apparatus.

[0045] The temperature conditions for the adjustment deposition are changed in the range of 1500° C. to 1700° C. in each of the three growth stages. The temperature conditions are finally tuned in a range of 1° C.

[0046] The C / Si ratio of the adjustment film is changed in the range of 0.8 to 1.5 in each of the three growth stages. The C / Si ratio is finally tuned in the range of 0.05. C / Si is the ratio of the C source gas to the Si source gas on the growth surface of the SiC epitaxial layer 3.

[0047] The growth rate of the adjustment deposition is changed in the range of 5 μm / h to 100 μm / h in each of the three growth stages. The growth rate is finally tuned in the range of 5 μm / h.

[0048] Next, under the deposition conditions determined in the preliminary step, actual deposition of the SiC epitaxial layer 3 is performed. Through this procedure, the SiC epitaxial wafer 1 according to this embodiment can be fabricated.

[0049] As described above, the SiC epitaxial wafer 1 according to this embodiment can be manufactured by setting conditions taking into consideration the inherent characteristics of each device. Since the SiC epitaxial wafer 1 according to this embodiment has almost no stacking faults other than double Shockley stacking faults, the number of basal plane dislocations in the SiC substrate 2 and the positions where many basal plane dislocations are concentrated can be estimated by identifying the double Shockley stacking faults. That is, the SiC epitaxial wafer 1 according to this embodiment can guarantee the quality of the SiC substrate 2 even after the SiC epitaxial layer 3 is stacked.

[0050] Although the preferred embodiment of the present invention has been described in detail above, the present invention is not limited to the specific embodiment, and various modifications and changes are possible within the scope of the gist of the present invention described in the claims. EXAMPLES

[0051] "Example 1" First, a SiC substrate 2 having a diameter of 150 mm was prepared. The SiC substrate 2 had a basal plane dislocation density of 1 / cm 2 More than 3000 pieces / cm 2 The following were selected and used:

[0052] Next, the SiC epitaxial layer 3 was formed on the SiC substrate 2. The growth conditions of the SiC epitaxial layer 3 were set in advance by repeating adjusted film formation and feedback. Defects on the surface of the SiC epitaxial layer 3 were observed using a photoluminescence method. The density of stacking faults in the SiC epitaxial layer 3 was 5.33 / cm. 2 The density of double Shockley-type stacking faults due to basal plane dislocations in the SiC epitaxial layer 3 was 4.05 / cm 2 The density of stacking faults other than double Shockley type stacking faults was 1.29 / cm 2 It should be noted that the density of stacking faults in the SiC epitaxial layer 3, the density of double Shockley type stacking faults caused by basal plane dislocations, and the density of stacking faults other than double Shockley type stacking faults are rounded values, and the density of stacking faults in the SiC epitaxial layer 3 does not necessarily match the sum of the density of double Shockley type stacking faults and the density of stacking faults other than double Shockley type stacking faults.

[0053] Next, a cross section of the position where the stacking fault was confirmed in the SiC epitaxial wafer 1 was measured. In the SiC epitaxial wafer 1 of Example 1, most of the defects identified as stacking faults were double Shockley type stacking faults. Furthermore, many basal plane dislocations were confirmed in the SiC substrate 2 at the position where the double Shockley type stacking fault was confirmed.

[0054] From the above, in the SiC epitaxial wafer 1 of Example 1, information on basal plane dislocations in the SiC substrate 2 could be estimated from information on stacking faults measured after the SiC epitaxial layer 3 was formed.

[0055] "Example 2" In Example 2, a SiC epitaxial wafer 1 was produced under the same conditions as in Example 1. Then, defects on the surface of the SiC epitaxial layer 3 were observed using a photoluminescence method. The density of stacking faults in the SiC epitaxial layer 3 was 9.17 / cm2 The density of double Shockley-type stacking faults due to basal plane dislocations in the SiC epitaxial layer 3 was 7.35 / cm 2 The density of stacking faults other than double Shockley type stacking faults was 1.81 / cm 2 In addition, a cross section of the position where the stacking fault was confirmed in the SiC epitaxial wafer 1 was measured. In the SiC epitaxial wafer 1 of Example 1, most of the defects identified as stacking faults were double Shockley type stacking faults. Furthermore, many basal plane dislocations were confirmed in the SiC substrate 2 at the position where the double Shockley type stacking fault was confirmed. In other words, information on the basal plane dislocations in the SiC substrate 2 could be estimated from information on the stacking faults measured after the SiC epitaxial layer 3 was formed.

[0056] "Comparative Example 1" As in Example 1, a SiC substrate 2 having a diameter of 150 mm was prepared. The SiC substrate 2 had a basal plane dislocation density of 1 / cm 2 More than 3000 pieces / cm 2 The following were selected and used:

[0057] Next, the SiC epitaxial layer 3 was formed on the SiC substrate 2. The growth conditions of the SiC epitaxial layer 3 were different from those in Example 1. The defects on the surface of the SiC epitaxial layer 3 were observed using a photoluminescence method. The density of stacking faults in the SiC epitaxial layer 3 was 3.09 / cm. 2 The density of double Shockley-type stacking faults due to basal plane dislocations in the SiC epitaxial layer 3 was 0.72 / cm 2 The density of stacking faults other than double Shockley type stacking faults was 2.37 / cm 2 It was.

[0058] The SiC epitaxial wafer of Comparative Example 1 had a large number of stacking faults other than double-Shockley type stacking faults, and it was not possible to estimate the basal plane dislocations in the SiC substrate 2 unless the stacking faults were classified one by one. It took a long time to estimate the positions where many basal plane dislocations were concentrated and the number of basal plane dislocations in the SiC epitaxial wafer of Comparative Example 1. In addition, the SiC epitaxial wafer of Comparative Example 1 had a large number of other stacking faults, and the accuracy of estimating the positions where many basal plane dislocations were concentrated and the number of basal plane dislocations was also low. [Explanation of symbols]

[0059] 1. SiC epitaxial wafer 2. SiC substrate 3. SiC epitaxial layer 4 Notches

Claims

1. A SiC substrate; a SiC epitaxial layer formed on the SiC substrate; The SiC substrate has a basal plane dislocation density of 1 / cm ２ More than 3000 pieces / cm ２ is as follows: The SiC epitaxial layer has a double Shockley (2SSF) stacking fault density of 4 / cm ２ More than 10 pieces / cm ２ and the density of stacking faults other than the double Shockley (2SSF) type stacking faults is 2 / cm ２ The following is a SiC epitaxial wafer.

2. 2. The SiC epitaxial wafer of claim 1, having a diameter of 145 mm or more.

3. 2. The SiC epitaxial wafer of claim 1, having a diameter of 195 mm or more.

4. The density of the double Shockley (2SSF) type stacking faults is 6 / cm ２ More than 10 pieces / cm ２ 2. The SiC epitaxial wafer of claim 1 , wherein:

5. The density of the double Shockley (2SSF) type stacking faults is 8 / cm ２ More than 10 pieces / cm ２ 2. The SiC epitaxial wafer of claim 1 , wherein:

6. The density of the double Shockley (2SSF) type stacking faults is 4 / cm ２ 6 or more pieces / cm ２ 2. The SiC epitaxial wafer of claim 1 , wherein:

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