Electronic component built-in substrate and method for manufacturing electronic component built-in substrate

Abstract

To provide an electronic component built-in substrate which can suppress lowering of electric connection reliability.SOLUTION: An electronic component built-in substrate 1 has a first substrate 10 having a connection pad P3, a second substrate 20 having a connection pad P4 facing the connection pad P3, and a spacer member 40 for electrically connecting the connection pad P3 and the connection pad P4. The electronic component built-in substrate 1 has a semiconductor chip 30 which is arranged between the first substrate 10 and the second substrate 20, and is mounted on the first substrate 10, and a sealing resin 50 which is filled into a space between the first substrate 10 and the second substrate 20, and seals the semiconductor chip 30. The spacer member 40 has a spherical solder core ball 41, and a solder layer 42 coating the outer periphery of the solder core ball 41. The melting point of the solder layer 42 is lower than the melting point of the solder core ball 41.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a substrate with built-in electronic components and a method for manufacturing a substrate with built-in electronic components. [Background technology]

[0002] Conventionally, electronic component-embedded substrates in which electronic components are embedded between a lower substrate and an upper substrate have been proposed (see, for example, Patent Documents 1 and 2). In this type of electronic component-embedded substrate, the upper substrate is fixed to the lower substrate via a spacer member in order to maintain a gap between the lower substrate and the upper substrate. Then, a sealing resin is filled between the lower substrate and the upper substrate.

[0003] Copper core solder balls are used as spacer members in electronic component built-in substrates. Here, the copper core solder ball is a copper core ball covered with a solder layer. In the copper core solder ball, the copper core ball functions as a spacer, and the solder layer functions as a bonding material. Specifically, the connection pads of the upper substrate and the lower substrate are solder-bonded by reflowing the solder layer with the copper core solder ball sandwiched between the connection pads of the upper substrate and the connection pads of the lower substrate. At this time, the copper core ball in the solder layer functions as a spacer by being sandwiched between the connection pads of the upper substrate and the connection pads of the lower substrate. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2008-135781 A [Patent Document 2] JP 2008-10885 A Summary of the Invention [Problem to be solved by the invention]

[0005] However, in conventional electronic component built-in substrates, if the adhesion between the copper core ball and the solder layer in the spacer member is insufficient, cracks may occur at the interface between the copper core ball and the solder layer. If a crack occurs inside the spacer member, the reliability of the electrical connection between the lower substrate and the upper substrate decreases. [Means for solving the problem]

[0006] According to one aspect of the present invention, a semiconductor device includes a first substrate having a first connection pad, a second substrate having a second connection pad opposite the first connection pad, a spacer member electrically connecting the first connection pad and the second connection pad, an electronic component arranged between the first substrate and the second substrate and mounted on the first substrate, and a sealing resin filling the space between the first substrate and the second substrate and sealing the electronic component, wherein the spacer member has a spherical solder core ball and a solder layer covering the outer periphery of the solder core ball, and the melting point of the solder layer is lower than the melting point of the solder core ball. Effect of the Invention

[0007] Advantageous Effects of Invention According to one aspect of the present invention, an effect is achieved in that a decrease in reliability of electrical connection can be suppressed. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a schematic cross-sectional view showing an electronic component-embedded substrate according to one embodiment. [Diagram 2] FIG. 2 is a schematic cross-sectional view showing a method for manufacturing an electronic component-embedded substrate according to one embodiment. [Diagram 3] FIG. 3 is a schematic cross-sectional view showing a method for manufacturing an electronic component-embedded substrate according to one embodiment. [Figure 4] FIG. 4 is a schematic cross-sectional view showing a method for manufacturing an electronic component-embedded substrate according to one embodiment. [Diagram 5] FIG. 5 is a schematic cross-sectional view showing a method for manufacturing an electronic component-embedded substrate according to one embodiment. [Figure 6]FIG. 6 is a schematic cross-sectional view showing a method for manufacturing an electronic component-embedded substrate according to one embodiment. [Figure 7] FIG. 7 is a schematic cross-sectional view showing a modified example of an electronic component built-in substrate. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, an embodiment will be described with reference to the accompanying drawings. In addition, for convenience, the attached drawings may show characteristic parts in an enlarged manner to make the features easier to understand, and the dimensional ratios of each component may differ from drawing to drawing. In addition, in the cross-sectional views, in order to make the cross-sectional structure of each component easier to understand, the hatching of some components is shown instead of a matte pattern, and the hatching of some components is omitted. In this specification, "plan view" refers to viewing an object from a vertical direction (up and down in the figure) such as in FIG. 1, and "planar shape" refers to the shape of an object viewed from a vertical direction such as in FIG. 1. In this specification, "up and down direction" and "left and right direction" are directions when the direction in which the symbols indicating each component in each drawing can be correctly read is taken as the normal position. In this specification, "opposite" refers to surfaces or components being in front of each other, and includes not only the case where each is completely in front of the other, but also the case where each is partially in front of the other. In addition, in this specification, "opposite" includes both the case where a component other than the two parts is interposed between the two parts and the case where nothing is interposed between the two parts.

[0010] (Overall configuration of electronic component built-in substrate 1) As shown in FIG. 1, the electronic component built-in substrate 1 includes a first substrate 10, a second substrate 20, a semiconductor chip 30, an underfill resin 35, a spacer member 40, and a sealing resin 50.

[0011] (Configuration of first substrate 10) The first substrate 10 has a substrate body 11. A wiring layer 12 and a solder resist layer 13 are laminated in this order on the lower surface of the substrate body 11. A wiring layer 15 and a solder resist layer 16 are laminated in this order on the upper surface of the substrate body 11.

[0012] The substrate body 11 may be a wiring structure in which insulating resin layers and wiring layers are alternately laminated. The wiring structure may have, for example, a core substrate, or may not have a core substrate. The insulating resin layer may be made of, for example, a thermosetting insulating resin. The thermosetting insulating resin may be made of, for example, an insulating resin such as an epoxy resin, a polyimide resin, or a cyanate resin. The insulating resin layer may be made of, for example, an insulating resin mainly composed of a photosensitive resin such as a phenolic resin or a polyimide resin. The insulating resin layer may contain, for example, a filler such as silica or alumina.

[0013] The wiring layer of the substrate body 11 and the wiring layers 12 and 15 may be made of, for example, copper (Cu) or a copper alloy. The solder resist layers 13 and 16 may be made of, for example, an insulating resin mainly composed of a photosensitive resin such as a phenolic resin or a polyimide resin. The solder resist layers 13 and 16 may contain, for example, a filler such as silica or alumina.

[0014] The wiring layer 12 is formed on the lower surface of the substrate body 11. The wiring layer 12 is the lowermost wiring layer of the first substrate 10. Solder resist layer 13 is laminated on the lower surface of substrate body 11 so as to cover wiring layer 12. Solder resist layer 13 is an insulating layer that is the outermost layer (here, the bottom layer) of first substrate 10.

[0015] A plurality of openings 13X are formed in the solder resist layer 13 to expose parts of the lower surface of the wiring layer 12 as external connection pads P1. The external connection pads P1 are adapted to be connected to external connection terminals used when mounting the electronic component built-in substrate 1 on a mounting substrate such as a motherboard.

[0016] A surface treatment layer is formed on the lower surface of the wiring layer 12 exposed at the bottom of the opening 13X, as necessary. Examples of the surface treatment layer include a gold (Au) layer, a nickel (Ni) layer / Au layer (a metal layer in which a Ni layer and an Au layer are laminated in this order), and a Ni layer / palladium (Pd) layer / Au layer (a metal layer in which a Ni layer, a Pd layer, and an Au layer are laminated in this order). Other examples of the surface treatment layer include a Ni layer / Pd layer (a metal layer in which a Ni layer and a Pd layer are laminated in this order), and a Pd / Au layer (a metal layer in which a Pd layer and an Au layer are laminated in this order). Here, the Au layer is a metal layer made of Au or an Au alloy, the Ni layer is a metal layer made of Ni or an Ni alloy, and the Pd layer is a metal layer made of Pd or a Pd alloy. The Au layer, Ni layer, and Pd layer may be, for example, a metal layer (electroless plating layer) formed by electroless plating or a metal layer (electrolytic plating layer) formed by electrolytic plating. The surface treatment layer may be an OSP film formed by performing an anti-oxidation treatment such as an OSP (Organic Solderability Preservative) treatment on the lower surface of the wiring layer 12 exposed in the opening 13X. The OSP film may be, for example, an organic coating of an azole compound or an imidazole compound. When a surface treatment layer is formed on the lower surface of the wiring layer 12, the surface treatment layer functions as the external connection pad P1.

[0017] In this example, an external connection terminal is provided on the external connection pad P1, but the wiring layer 12 exposed in the opening 13X (or, if a surface treatment layer is formed on the wiring layer 12, the surface treatment layer) itself may be used as the external connection terminal.

[0018] The wiring layer 15 is provided on the mounting surface side (the upper surface side in FIG. 1) on which the semiconductor chip 30 is mounted. The wiring layer 15 is formed on the upper surface of the substrate body 11. The wiring layer 15 is electrically connected to the wiring layer 12 via a wiring layer and a through electrode in the substrate body 11.

[0019] The wiring layer 15 has a plurality of pads P2 for mounting electronic components, which are electrically connected to the bumps 31 of the semiconductor chip 30, and a plurality of connection pads P3 for electrically connecting between the first substrate 10 and the second substrate 20. Although a plan view is not shown, the plurality of pads P2 are arranged in a matrix in a plan view in a mounting region where the semiconductor chip 30 is mounted, for example, according to the arrangement of the bumps 31 of the semiconductor chip 30. The planar shape of each pad P2 is formed, for example, in a circular shape.

[0020] The multiple connection pads P3 are provided in an area outside the mounting area in a plan view. The multiple connection pads P3 are provided so as to surround the outer periphery of the semiconductor chip 30 in a plan view. Although the plan view is not shown, the multiple connection pads P3 are provided in multiple rows (two rows here) in an arrangement surrounding the outer periphery of the semiconductor chip 30. The planar shape of each connection pad P3 is formed, for example, in a circular shape.

[0021] Solder resist layer 16 is laminated on the upper surface of substrate body 11 so as to cover wiring layer 15. Solder resist layer 16 is an insulating layer that is the outermost layer (here, the uppermost layer) of first substrate .

[0022] The solder resist layer 16 is formed with a plurality of openings 16X for exposing a part of the upper surface of the wiring layer 15 as the pads P2, and a plurality of openings 16Y for exposing a part of the upper surface of the wiring layer 15 as the connection pads P3. On the wiring layer 15 exposed from these openings 16X and 16Y, that is, on the pads P2 and the connection pads P3, a surface treatment layer is formed as necessary. Examples of the surface treatment layer include a metal layer such as an Au layer, a Ni layer / Au layer, a Ni layer / Pd layer / Au layer, a Ni layer / Pd layer, or a Pd / Au layer, or an OSP film. When a surface treatment layer is formed on the upper surface of the wiring layer 15, the surface treatment layer functions as the pads P2 or the connection pads P3.

[0023] (Configuration of semiconductor chip 30) The semiconductor chip 30 has a plurality of bumps 31 formed on a circuit formation surface (here, the lower surface) of the semiconductor chip 30. The semiconductor chip 30 is mounted on the upper surface of the first substrate 10. The semiconductor chip 30 is flip-chip mounted on the upper surface of the first substrate 10. The semiconductor chip 30 is electrically connected to the pads P2 of the first substrate 10 via the bumps 31. As a result, the semiconductor chip 30 is electrically connected to the wiring layer 15 of the first substrate 10 via the bumps 31.

[0024] The semiconductor chip 30 may be, for example, a logic chip such as a CPU (Central Processing Unit) chip or a GPU (Graphics Processing Unit) chip. The semiconductor chip 30 may be, for example, a memory chip such as a DRAM (Dynamic Random Access Memory) chip, an SRAM (Static Random Access Memory) chip, or a flash memory chip. When multiple semiconductor chips 30 are mounted on the first substrate 10, a logic chip and a memory chip may be combined and mounted on the first substrate 10.

[0025] The semiconductor chip 30 has a rectangular planar shape, for example. The planar size of the semiconductor chip 30 may be, for example, about 3 mm×3 mm to 12 mm×12 mm. The thickness of the semiconductor chip 30 may be, for example, about 50 μm to 100 μm.

[0026] For example, a gold bump or a solder bump can be used as the bump 31. Materials for the solder bump include an alloy containing lead (Pb), an alloy of tin (Sn) and Au, an alloy of Sn and Cu, an alloy of Sn and silver (Ag), an alloy of Sn, Ag and Cu, etc. The thickness of the bump 31 can be, for example, about 20 μm to 70 μm.

[0027] The underfill resin 35 is provided so as to fill the gap between the upper surface of the first substrate 10 and the lower surface of the semiconductor chip 30. Note that as the material of the underfill resin 35, for example, an insulating resin such as an epoxy resin can be used.

[0028] (Configuration of second substrate 20) The second substrate 20 has a substrate body 21. A wiring layer 22 and a solder resist layer 23 are laminated in this order on the lower surface of the substrate body 21. A wiring layer 25 and a solder resist layer 26 are laminated in this order on the upper surface of the substrate body 21.

[0029] The substrate body 21 may be a wiring structure in which insulating resin layers and wiring layers are alternately laminated. The wiring structure may have, for example, a core substrate, or may not have a core substrate. The insulating resin layer may be made of, for example, a thermosetting insulating resin. The thermosetting insulating resin may be made of, for example, an insulating resin such as an epoxy resin, a polyimide resin, or a cyanate resin. The insulating resin layer may be made of, for example, an insulating resin mainly composed of a photosensitive resin such as a phenolic resin or a polyimide resin. The insulating resin layer may contain, for example, a filler such as silica or alumina.

[0030] The wiring layer of the substrate body 21 and the wiring layers 22 and 25 may be made of, for example, copper or a copper alloy. The solder resist layers 23 and 26 may be made of, for example, an insulating resin mainly composed of a photosensitive resin such as a phenolic resin or a polyimide resin. The solder resist layers 23 and 26 may contain a filler such as silica or alumina.

[0031] The wiring layer 22 is formed on the lower surface of the substrate main body 21 facing the first substrate 10. The wiring layer 22 is the bottommost wiring layer of the second substrate 20. The wiring layer 22 has a plurality of connection pads P4 for electrically connecting the first substrate 10 and the second substrate 20. Each connection pad P4 is electrically connected to each connection pad P3 provided on the first substrate 10 via a spacer member 40.

[0032] The multiple connection pads P4 are provided so as to face each of the multiple connection pads P3 provided on the first substrate 10. The multiple connection pads P4 are provided so as to surround the outer periphery of the semiconductor chip 30 in a plan view. Although the plan view is not shown, the multiple connection pads P4 are provided in multiple rows (two rows here) in an arrangement surrounding the outer periphery of the semiconductor chip 30. The planar shape of each connection pad P4 is formed, for example, in a circular shape.

[0033] The solder resist layer 23 is laminated on the lower surface of the substrate body 21 so as to cover the wiring layer 22. The solder resist layer 23 is an insulating layer that is the outermost layer of the second substrate 20 (here, the bottom layer).

[0034] The solder resist layer 23 has a plurality of openings 23X for exposing a part of the lower surface of the wiring layer 22 as the connection pads P4. A surface treatment layer is formed on the wiring layer 22 exposed from the openings 23X, i.e., on the connection pads P4, as necessary. Examples of the surface treatment layer include a metal layer such as an Au layer, a Ni layer / Au layer, a Ni layer / Pd layer / Au layer, a Ni layer / Pd layer, or a Pd / Au layer, or an OSP film. When a surface treatment layer is formed on the lower surface of the wiring layer 22, the surface treatment layer functions as the connection pads P4.

[0035] The wiring layer 25 is formed on the upper surface of the substrate body 21 on which electronic components other than the semiconductor chip 30 are mounted. The wiring layer 25 is electrically connected to the wiring layer 22 via a wiring layer and a through electrode in the substrate body 21.

[0036] The wiring layer 25 has component connection pads P5 electrically connected to electronic components such as a semiconductor chip other than the semiconductor chip 30 or a passive element. The planar shape of each component connection pad P5 is formed to be, for example, circular.

[0037] The solder resist layer 26 is laminated on the upper surface of the substrate body 21 so as to cover the wiring layer 25. The solder resist layer 26 is an insulating layer that is the outermost layer (here, the uppermost layer) of the second substrate 20.

[0038] The solder resist layer 26 has a plurality of openings 26X for exposing a part of the upper surface of the wiring layer 25 as the component connection pads P5. A surface treatment layer is formed on the wiring layer 25 exposed from the openings 26X, i.e., on the component connection pads P5, as necessary. Examples of the surface treatment layer include a metal layer such as an Au layer, a Ni layer / Au layer, a Ni layer / Pd layer / Au layer, a Ni layer / Pd layer, or a Pd / Au layer, or an OSP film. When a surface treatment layer is formed on the upper surface of the wiring layer 25, the surface treatment layer functions as the component connection pads P5.

[0039] (Configuration of Spacer Member 40) The spacer member 40 electrically connects the connection pads P3 of the first substrate 10 and the connection pads P4 of the second substrate 20 to each other. The spacer member 40 is bonded to the connection pads P3 and P4. Specifically, the spacer member 40 is provided between the first substrate 10 and the second substrate 20, with one end bonded to the connection pads P3 and the other end bonded to the connection pads P4. The spacer member 40 functions as a connection terminal that electrically connects the connection pads P3 and P4, and also functions as a spacer that maintains the distance between the first substrate 10 and the second substrate 20, i.e., the separation distance, at a specified value.

[0040] The spacer member 40 has a spherical solder core ball 41 and a solder layer 42 that covers the periphery of the solder core ball 41. The solder layer 42 is made of solder having a lower melting point than the solder core ball 41. The melting point of the low-melting-point solder layer 42 can be, for example, about 100°C to 200°C. The melting point of the solder layer 42 is 20°C or more lower than the melting point of the solder core ball 41. For example, Sn-bismuth (Bi)-based or Sn-indium (In)-based Pb-free solder can be used as the material of the solder layer 42. The solder core ball 41 is made of solder having a higher melting point than the solder layer 42. The melting point of the solder core ball 41 can be, for example, about 220°C to 280°C. For example, Sn-Ag-based or Sn-antimony (Sb)-based Pb-free solder can be used as the material of the solder core ball 41.

[0041] In the spacer member 40, the solder layer 42 functions as a bonding material. More specifically, the spacer member 40 is bonded to the connection pad P3 by the solder layer 42, and is also bonded to the connection pad P4 by the solder layer 42. The solder layer 42 is bonded to the connection pads P3, P4, for example, by being melted by a heat treatment during the manufacturing process and then solidified. The solder layer 42 is formed, for example, so as to fill the opening 16Y of the solder resist layer 16, and is also formed so as to fill the opening 23X of the solder resist layer 23.

[0042] In the spacer member 40, the solder core ball 41 functions as a spacer. The solder core ball 41 is not melted during, for example, a heat treatment in which the solder layer 42 is melted, and maintains a spherical state. Therefore, the height of the space between the first substrate 10 and the second substrate 20 is set by the height (diameter) of the solder core ball 41. The height of such a solder core ball 41 is set, for example, to be higher than the thickness of the semiconductor chip 30. Specifically, the height of the solder core ball 41 is set to be higher than the total thickness of the semiconductor chip 30 and the bump 31. The height of the solder core ball 41 can be, for example, about 100 μm to 200 μm.

[0043] (Configuration of sealing resin 50) The sealing resin 50 is filled in the space between the first substrate 10 and the second substrate 20. The sealing resin 50 is formed so as to seal the semiconductor chip 30 arranged between the first substrate 10 and the second substrate 20. The sealing resin 50 fixes the second substrate 20 to the first substrate 10 and seals the semiconductor chip 30. That is, the sealing resin 50 functions as an adhesive that bonds the first substrate 10 and the second substrate 20 together, and also functions as a protective layer that protects the semiconductor chip 30. Note that, for example, an insulating resin such as an epoxy resin or a polyimide resin can be used as the material for the sealing resin 50.

[0044] (Method of Manufacturing Electronic Component Built-in Substrate 1) Next, a method for manufacturing the electronic component built-in substrate 1 will be described. 2, a first substrate 10 is prepared, which includes a substrate body 11, a wiring layer 12 and a solder resist layer 13 laminated on the lower surface of the substrate body 11, and a wiring layer 15 and a solder resist layer 16 laminated on the upper surface of the substrate body 11. The first substrate 10 can be manufactured by a known manufacturing method, and therefore a detailed description thereof will be omitted here.

[0045] Next, the semiconductor chip 30 is flip-chip mounted on the upper surface of the first substrate 10. Specifically, the bumps 31 of the semiconductor chip 30 are flip-chip bonded to the pads P2 of the first substrate 10. After that, underfill resin 35 is filled between the upper surface of the first substrate 10, specifically the upper surface of the solder resist layer 16, and the lower surface of the semiconductor chip 30, and is cured.

[0046] 3, a second substrate 20 is prepared, which has a substrate body 21, a wiring layer 22 and a solder resist layer 23 laminated on the lower surface of the substrate body 21, and a wiring layer 25 and a solder resist layer 26 laminated on the upper surface of the substrate body 21. The second substrate 20 can be manufactured by a known manufacturing method, and therefore a detailed description thereof will be omitted here.

[0047] Next, a spacer member 40 having a solder core ball 41 and a solder layer 42 covering the outer periphery of the solder core ball 41 is mounted on the connection pad P4 of the second substrate 20. For example, the spacer member 40 is mounted after applying an appropriate amount of flux on the connection pad P4. Next, the solder layer 42 is bonded to the connection pad P4 by performing reflow at a first temperature (for example, about 200°C) that melts only the solder layer 42 in the spacer member 40. That is, after only the solder layer 42 is melted at a first temperature that is higher than the melting point of the solder layer 42 and lower than the melting point of the solder core ball 41, the solder layer 42 is solidified by cooling. As a result, the solder layer 42 is bonded to the connection pad P4. At this time, since the first temperature is lower than the melting point of the solder core ball 41, the solder core ball 41 does not melt, and only the solder layer 42 melts and solidifies.

[0048] Next, the second substrate 20 is disposed above the first substrate 10. At this time, the second substrate 20 is disposed so that the spacer member 40 faces the upper surface of the first substrate 10. Furthermore, the first substrate 10 and the second substrate 20 are positioned so that the connection pad P3 and the connection pad P4 face each other.

[0049] Next, in the process shown in FIG. 4, the spacer member 40 is bonded onto the connection pad P3. For example, after applying an appropriate amount of flux onto the connection pad P3, the second substrate 20 is placed on the first substrate 10 with the spacer member 40 sandwiched therebetween. Then, the spacer member 40 is interposed between the solder resist layer 16 of the first substrate 10 and the solder resist layer 23 of the second substrate 20, and a gap (space) is formed by the spacer member 40. Then, the first substrate 10 and the second substrate 20 that are superimposed as described above are reflowed at a first temperature (for example, about 200° C.) that melts only the solder layer 42 of the spacer member 40. At this time, since the first temperature is lower than the melting point of the solder core ball 41, the solder core ball 41 does not melt, and only the solder layer 42 melts and solidifies. As a result, the solder core ball 41 is maintained in a spherical state, and the solder layer 42 is bonded to the connection pads P3 and P4. In this way, the second substrate 20 is fixed to the first substrate 10 via the spacer member 40, and the connection pads P3 and P4 are electrically connected via the spacer member 40. Here, in this process, reflow is performed while pressing the second substrate 20 toward the first substrate 10. At this time, the solder core balls 41 of the spacer member 40 do not melt and maintain their spherical shape, so that the solder core balls 41 function as spacers. Therefore, the gap between the first substrate 10 and the second substrate 20 is maintained at a predetermined distance according to the diameter of the solder core balls 41.

[0050] 5, the sealing resin 50 is formed so as to fill the space between the first substrate 10 and the second substrate 20, that is, the space between the solder resist layer 16 and the solder resist layer 23. The sealing resin 50 is formed so as to seal the semiconductor chip 30 arranged between the first substrate 10 and the second substrate 20. The sealing resin 50 can be formed by, for example, a resin molding method. For example, when a thermosetting mold resin is used as the material of the sealing resin 50, the structure shown in FIG. 4 is accommodated in a metal mold, and the mold resin is fluidized by applying pressure (for example, 5 MPa to 10 MPa) into the metal mold. Thereafter, the mold resin is heated at a temperature of about 180° C. to harden it, thereby forming the sealing resin 50. Then, after the required sealing process is completed, the structure on which the sealing resin 50 is formed is taken out from the metal mold. In addition, as a method for filling the mold resin, for example, a transfer molding method, a compression molding method, an injection molding method, or the like can be used.

[0051] Here, the heating temperature in this process is set to a temperature lower than the melting point of the solder core balls 41. Therefore, in this process, the solder core balls 41 do not melt and are maintained in a spherical state. Therefore, in the spacer member 40 after this process, an interface exists between the solder core balls 41 and the solder layer 42.

[0052] Thereafter, the solder core ball 41 and the solder layer 42 are integrated by heating at a second temperature higher than the melting point of the solder core ball 41. That is, by heating the structure shown in FIG. 5 at a second temperature, both the solder core ball 41 and the solder layer 42 are melted, and the interface between the solder core ball 41 and the solder layer 42 is eliminated by blending the two types of solder. As a result, the solder core ball 41 and the solder layer 42 are integrated. That is, as shown in FIG. 6, a spacer member 40A made of a single layer is formed. In this process, the two types of solder, the solder core ball 41 and the solder layer 42 shown in FIG. 5, are blended, so that the occurrence of cracks inside the spacer member 40A can be suitably suppressed.

[0053] Next, the effects of this embodiment will be described. (1) The electronic component built-in substrate 1 includes a first substrate 10 having a connection pad P3, a second substrate 20 having a connection pad P4 facing the connection pad P3, and a spacer member 40 electrically connecting the connection pad P3 and the connection pad P4. The electronic component built-in substrate 1 includes a semiconductor chip 30 disposed between the first substrate 10 and the second substrate 20 and mounted on the first substrate 10, and a sealing resin 50 that fills the space between the first substrate 10 and the second substrate 20 and seals the semiconductor chip 30. The spacer member 40 includes a spherical solder core ball 41 and a solder layer 42 that covers the outer periphery of the solder core ball 41. The melting point of the solder layer 42 is lower than the melting point of the solder core ball 41.

[0054] According to this configuration, the spherical solder core balls 41 in the spacer member 40 function as a spacer that maintains the separation distance between the first substrate 10 and the second substrate 20 at a specified value. The solder layer 42 in the spacer member 40 functions as a bonding material that bonds the connection pads P3 and P4 to the spacer member 40. Here, due to manufacturing errors and manufacturing conditions when manufacturing the electronic component built-in substrate 1, cracks may occur at the interface between the solder core balls 41 and the solder layer 42. In contrast, the spacer member 40 of this embodiment is composed of two types of solder with different melting points, that is, the solder core balls 41 and the solder layer 42. Therefore, by heating at a second temperature higher than the melting point of the solder layer 42 and the melting point of the solder core balls 41, the two types of solder can be melted and blended together. Therefore, even if a crack occurs at the interface between the solder core ball 41 and the solder layer 42, the molten solder spreads to fill the crack and the crack disappears as the two types of solder blend together. This makes it possible to preferably prevent cracks from occurring inside the spacer member 40A after the solder core ball 41 and the solder layer 42 are integrated. As a result, it is possible to preferably prevent a decrease in the electrical reliability between the connection pads P3 and P4 electrically connected by the spacer member 40A.

[0055] (2) The melting point of the solder layer 42 is set to be at least 20° C. lower than the melting point of the solder core ball 41. With this configuration, even if the melting points of the solder core ball 41 and the solder layer 42 deviate slightly from the target values ​​due to manufacturing errors, only the solder layer 42 out of the solder core ball 41 and the solder layer 42 can be suitably melted during reflow at the first temperature.

[0056] (3) A process of joining the solder layer 42 to the connection pads P3, P4 by performing reflow at a first temperature that is higher than the melting point of the solder layer 42 and lower than the melting point of the solder core ball 41. With this configuration, the solder core ball 41 is not melted and is maintained in a spherical state during reflow at the first temperature. This allows the solder core ball 41 to function favorably as a spacer that maintains the separation distance between the first substrate 10 and the second substrate 20 at a specified value in the structure before the sealing resin 50 is formed.

[0057] (4) After the step of forming the sealing resin 50, the method includes a step of integrating the solder core ball 41 and the solder layer 42 by heating at a second temperature higher than the melting point of the solder core ball 41. According to this configuration, after the sealing resin 50 that fixes the first substrate 10 and the second substrate 20 and keeps the separation distance between the first substrate 10 and the second substrate 20 at a specified value is formed, the solder core ball 41 and the solder layer 42 are melted and integrated. Therefore, when the solder core ball 41 that functions as a spacer is melted, the sealing resin 50 that functions as a spacer is formed. Therefore, even when the solder core ball 41 is melted, the separation distance between the first substrate 10 and the second substrate 20 can be suitably kept at a specified value.

[0058] (Other embodiments) The above embodiment can be modified as follows: The above embodiment and the following modifications can be combined with each other to the extent that no technical contradiction occurs.

[0059] 7, the underfill resin 35 may be omitted, and the gap between the first substrate 10 and the semiconductor chip 30 may be sealed with a sealing resin 50. In this case, the gap between the first substrate 10 and the semiconductor chip 30 is filled with the sealing resin 50, and the bumps 31 are sealed with the sealing resin 50.

[0060] When the bumps 31 are made of solder, the melting point of the bumps 31 may be set to be the same as or higher than the melting point of the solder core balls 41. By setting the melting point in this way, it is possible to prevent the bumps 31 from melting when the solder layer 42 of the spacer member 40 is melted to connect the first substrate 10 and the second substrate 20. Therefore, even when the underfill resin 35 is omitted and the space between the first substrate 10 and the semiconductor chip 30 is sealed with the sealing resin 50 as in the modified example shown in FIG. 7, the electrical connection reliability between the bumps 31 and the pads P2 can be favorably maintained. As a result, the connection reliability of the semiconductor chip 30 can be favorably maintained.

[0061] The structure of the first substrate 10 in the above embodiment can be modified as appropriate. For example, the solder resist layer 13 may be omitted. For example, the solder resist layer 16 may be omitted. The structure of the second substrate 20 in the above embodiment can be modified as appropriate. For example, the solder resist layer 23 may be omitted. For example, the solder resist layer 26 may be omitted.

[0062] In the electronic component built-in substrate 1 of the above embodiment, a plurality of electronic components may be mounted on the first substrate 10. In the above embodiment, the semiconductor chip 30 is mounted on the first substrate 10, but this is not limiting. For example, other electronic components such as a capacitor or an inductor may be mounted on the first substrate 10.

[0063] In the above embodiment, the electronic component built-in substrate 1 is embodied in a structure in which two substrates, the first substrate 10 and the second substrate 20, are stacked on top of each other with the spacer member 40 interposed therebetween. However, the present invention is not limited to this, and the electronic component built-in substrate 1 may be embodied in a structure in which three or more substrates are stacked on top of each other with the spacer member 40 interposed therebetween. [Explanation of symbols]

[0064] 1. Electronic component embedded board 10 First board 15 wiring layer 20 Second board 22 wiring layer 30 Semiconductor chips (electronic components) 35 Underfill resin 40 Spacer member 40A Spacer member 41 Solder core ball 42 Solder layer 50 Sealing resin P3 connection pad (first connection pad) P4 connection pad (second connection pad)

Claims

1. a first substrate having a first connection pad; a second substrate having second connection pads opposite the first connection pads; a spacer member electrically connecting the first connection pad and the second connection pad; an electronic component disposed between the first substrate and the second substrate and mounted on the first substrate; a sealing resin that fills a space between the first substrate and the second substrate and seals the electronic components, The spacer member has a spherical solder core ball and a solder layer covering an outer periphery of the solder core ball, The solder layer has a melting point lower than a melting point of the solder core ball.

2. 2. The electronic component built-in substrate according to claim 1, wherein the melting point of the solder layer is lower than the melting point of the solder core ball by 20[deg.] C. or more.

3. Providing a first substrate having a first connection pad; Mounting electronic components on an upper surface of the first substrate; Providing a second substrate having a second connection pad; a step of mounting the second substrate on the first substrate in a state in which a spacer member having a spherical solder core ball and a solder layer covering an outer periphery of the solder core ball is interposed between the first connection pad and the second connection pad; bonding the solder layer to the first connection pad and the second connection pad by reflowing at a first temperature that melts only the solder layer on the spacer member; and forming a sealing resin that fills a space between the first substrate and the second substrate and seals the electronic components disposed between the first substrate and the second substrate, The melting point of the solder layer is lower than the melting point of the solder core ball, The method for manufacturing a substrate with built-in electronic components, wherein the first temperature is higher than a melting point of the solder layer and lower than a melting point of the solder core ball.

4. After the step of forming the sealing resin, 4. The method for manufacturing a substrate with built-in electronic components according to claim 3, further comprising the step of integrating the solder core ball and the solder layer by heating at a second temperature higher than a melting point of the solder core ball.

5. Before the step of mounting the second substrate on the first substrate, mounting the spacer member on the second connection pad; 4. The method for manufacturing a substrate with built-in electronic components according to claim 3, further comprising the step of: bonding the solder layer to the second connection pad by performing reflow at the first temperature.

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