Power finfet having alternative blocking region and integrated control electrode, and manufacturing method of them

Abstract

To provide a manufacturing method of a power FinFET, having an alternative blocking region and an integrated control electrode.SOLUTION: A manufacturing method of a power FinFET, contains: a step of generating a mask to which a first structuralization is made to a front surface of a semiconductor main body in a lithography step; a step of generating a first groove from the front surface of the semiconductor main body under a first open region to a drift layer; a step of generating a blocking region under the first groove by a first implantation processing; a step of executing an isotropic oxide layer to the front side of the semiconductor main body; a step of generating the mask to which a second structuralization is made; a step of generating a second groove from the front surface under a second open region into the drift layer; a step of arranging further the oxide layer by oxidizing the front surface; a step of generating a fin by expanding a with of the first and second grooves; a step of executing a polysilicon layer to the front surface of the semiconductor main body and embedding completely the first and second grooves; and a step of activating the blocking region with annealing.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a method for fabricating a power FinFET with alternating shield regions and integral control electrodes, and to a power FinFET with alternating shield regions and integral control electrodes. [Background technology]

[0002] In power electronics, semiconductors with large bandgaps, such as SiC or GaN, are applied, and in this respect power MOSFETs with vertical channel regions are typically used.

[0003] To increase the breakdown voltage of such power MOSFETs, shielding regions are arranged under the trenches, which can be connected to the source regions by contacts in the trenches, thus forming a two-part control electrode in the trenches, as shown, for example, in document DE10224201B4.

[0004] This may be disadvantageous, for example, because the grooves have to be designed very wide, which leads to large pitch dimensions and large on-resistance of the power MOSFET. The form factor may be large. Furthermore, the manufacturing method of the two-part control electrode may be cumbersome.

[0005] Between two adjacent trenches, a so-called JFET is formed between the shielding regions, which are usually p-doped, and serve to limit the current through the channel region in the event of a short circuit. For this purpose, the p-doped shielding regions are implanted using a lithographically structured mask.

[0006] In this regard, for example, it may be a disadvantage that the spacing between the two p-doped shielding regions is exposed to process variations, which have an effect on the short-circuit current limit. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] DE10224201B4 Summary of the Invention [Problem to be solved by the invention]

[0008] It is an object of the present invention to overcome these and other drawbacks. [Means for solving the problem]

[0009] The present invention provides a method for manufacturing a power FinFET with alternating shielding regions and integral control electrodes and a power FinFET with alternating shielding regions and integral control electrodes according to the independent claims.

[0010] Preferred embodiments are the subject of the respective dependent claims. According to a first aspect, the present invention relates to a method for manufacturing a power FinFET with an integral control electrode and a semiconductor body having a second terminal region and a drift layer, the second terminal region being on a front side of the semiconductor body, comprising the steps of: generating a first structured mask on the front side of the semiconductor body by a lithography step, the first mask having an oxide region and a first opening region exposing the front side of the semiconductor body, and generating a first trench from the front side of the semiconductor body into the drift layer under the first opening region by a first etching process. The method further comprises the step of generating a shielding region under the first trench by a first implantation process. The method includes the steps of applying an isotropic oxide layer to the front side of the semiconductor body, creating a second structured mask by a second etching process, whereby the isotropic oxide layer has second open areas, the second open areas exposing the front side of the semiconductor body, and creating second grooves from the front side into the drift layer under the second open areas by a third etching process, the second grooves being arranged substantially parallel to the first grooves and alternating between the first and second grooves, the second grooves having a smaller width than the first grooves. The method further includes the steps of oxidizing the front side, whereby a further oxide layer is arranged on the front side, and extending the width of the first and second grooves by a fourth etching process, whereby fins arise between the first and second grooves, the fins having a width of less than 500 nm. The method includes applying a polysilicon layer to a front side of the semiconductor body, whereby the first trench and the second trench are completely filled, and activating the shielded region by annealing.

[0011] In this regard, it may be advantageous that a short circuit current limiting effect occurs between the shielding region and the sidewall of the second trench, which allows process variations to be tolerated, and the spacing between the shielding regions may be further reduced.

[0012] In one variant, the first structured mask has nitride regions, in which case the oxide regions are arranged on the nitride regions. In this regard, it may be advantageous to prevent oxidation of the top surface of the fins.

[0013] In a further embodiment, the second implant process creates a widening region beneath the second trench, where the second implant energy has a value between 200 keV and 2500 keV.

[0014] In this regard, it may be an advantage that the on-resistance may be reduced. In one variation, the first etch process, the second etch process, and the third etch process are anisotropic plasma etch processes.

[0015] In this regard, it may be advantageous if the structured mask can be transferred to the underlying layer with minimal width expansion. In one form the first implantation process has a first implantation energy in the range of 30 keV to 2700 keV.

[0016] In this regard, it may be advantageous that a shielding region occurs below the gate oxide to be protected in the trench bottom, so that maximum shielding is achieved without loss of pitch. According to a second aspect, the present invention relates to a power FinFET with an integral control electrode and a semiconductor body having a drift layer and a second terminal region. The second terminal region is arranged on the drift layer and a first trench and a second trench extend from the second terminal region into the drift layer. The first trench and the second trench are arranged in sequence with respect to each other, whereby the second trench has a smaller width than the first trench and a shielding region is arranged below the first trench. The shielding region is directly adjacent to the first trench and the shielding regions are conductively connected to the source region, the conductive connection being not arranged in the first trench (206). A respective integral control electrode is arranged in the first trench, the respective integral control electrode being electrically insulated from the shielding region below the first trench. Fins are arranged between the first trench and the second trench, the fins having a width of at most 500 nm.

[0017] In this regard, it may be advantageous that the short circuit current may be limited by the space charge zones in the shielding region and the opposing trench walls of the second trench. It may further be advantageous that the effect of process variations on the short circuit current and on-resistance may be mitigated.

[0018] In one variation, a flaring region is disposed below the second groove. In this regard, it may be advantageous that current spreading may be increased and / or on-resistance may be reduced.

[0019] In a further embodiment, the shielding region is p-type doped and has an average doping ratio of at least 1E18 / cm 3 The dopant concentration is In this regard, it may be advantageous to be able to inexpensively place a high implant dose below the trench bottom.

[0020] In one form the semiconductor body comprises SiC. In this regard, it may be an advantage that easily activatable aluminum may be used for the implantation.

[0021] In a further form the semiconductor body comprises GaN. In this regard, it would be advantageous to be able to increase the critical electric field strength and electron mobility. Further advantages will be apparent from the following description of exemplary embodiments.

[0022] The present invention will be described below based on preferred embodiments and the accompanying drawings. [Brief description of the drawings]

[0023] [Figure 1] FIG. 1 is a flow diagram of a method for manufacturing a power FinFET with alternating shielding regions and integral control electrodes. [Diagram 2] FIG. 1 illustrates a power FinFET with alternating shielding regions and an integral control electrode. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0024] FIG. 1 illustrates a method for fabricating a power FinFET with alternating shielded regions and no split control electrode. The control electrodes are integrally formed. Typically, at least one control electrode may be integrally formed. The shielded regions of the power FinFET are connected to the source regions. These connections are not located within the trenches of the power FinFET. Instead, the source regions may be conductively connected, for example, by contacts at the edge of the cell array, or by deep terminal portions implanted at periodic intervals along the fin, for example.

[0025] The power FinFET includes a semiconductor body, for example comprising SiC or GaN, a second terminal region, and a drift layer, with the second terminal region being on the front side of the semiconductor body. The method may include a step 105 in which a first structured mask is produced on the front side of the semiconductor body by a lithography step. The first structured mask may have oxide regions and first open areas, which expose the front side of the semiconductor body.

[0026] In step 110, a first etching process may create a first trench from the front side of the semiconductor body into the drift layer beneath the first open area. In step 115, a shielding region can be created under the first trench by a first implantation process at a first implantation energy. The first implantation energy can be between 30 keV and 2700 keV. The shielding region can be p-type doped.

[0027] In step 120, an isotropic oxide layer may be applied to the front side of the semiconductor body. In step 125, a second etching process may be performed to create a second structured mask such that the isotropic oxide layer has second open areas, which expose the front side of the semiconductor body.

[0028] In step 130, a third etching process can create second trenches from the front side of the semiconductor body into the drift layer below the second open area. The second trenches are preferably arranged parallel to and alternated with the first trenches. The second trenches can have a smaller width than the first trenches.

[0029] In other words, a self-aligned mask can be produced in step 125, which can then be used to sublithographically create the second trench in step 130 by a mask reverse process, with the width or pitch of the mesa between the first and second trench being determined by the thickness of the isotropic oxide layer. A precise alignment between the shielding area under the first trench and the opposing sidewalls of the second trench is further possible, which allows optimal tuning of the on-resistance, short circuit current, and electric field in the oxide at the bottom of the second trench.

[0030] In step 135, the front side of the semiconductor body may be oxidized such that a further oxide layer is disposed on the front side of the semiconductor body, the further oxide layer having a thickness of at least 10 nm.

[0031] In step 140, a fourth etching process may expand the width of the first and second trenches, resulting in a fin between the first and second trenches, which may have a width of, for example, less than 500 nm, preferably in the range between 400 and 50 nm, and more preferably in the range between 200 and 50 nm. In this regard, the oxide from step 135 may be selectively wet-chemically etched.

[0032] Depending on the fin width to be reached, steps 135 and 140 can be performed periodically. In other words, the front side of the semiconductor body can be oxidized multiple times. An etching step can be performed between the oxidation steps. Thus, the trench width expansion can be performed without alignment, since the lateral oxidation rate exceeds the vertical oxidation rate by a factor of about two.

[0033] In step 145, a polysilicon layer may be applied to the front side of the semiconductor body to completely fill the first and second trenches, so that during a subsequent etch, not only will spacers remain on the trench sidewalls, but all of the first and second trenches will still be completely filled. Alternatively or additionally, the first and / or second trenches may be partially or completely filled in separate steps.

[0034] In a next step 150, the shielded regions may be activated by annealing, typically at 1700°C. By the method according to the invention, the shielding regions under the first trench are further away from each other than the shielding regions are from the facing trench wall or side wall of the second trench, so that the short circuit current is not limited by a collision of the space charge zones of the two shielding regions, but by the space charge zone of one p-doped shielding region in each case, which pushes or pushes the current towards the facing trench wall of the second trench. A low sensitivity to process variations is achieved, since the trench wall of each second trench forms an accumulation channel that cannot be dispelled by the space charge zone of the p-doped shielding region by a positive gate voltage in the event of a short circuit.

[0035] The first etching process, the second etching process, and / or the third etching process may be anisotropic etching processes. The fourth etching process may be isotropic. In this regard, the first and / or third etching process may be, in the case of a SiC semiconductor body, an isotropic etching process that separates SiC, which is etched, and SiO, which is not etched. 2 , SiN, and Si. The second etching process and / or the fourth etching process may select between SiO 2 to be etched in the case of a SiC semiconductor body. 2 and SiC, SiN, and Si, which are not etched.

[0036] In one exemplary embodiment, the first structured mask has nitride regions present between the front side and the oxide regions, which protect the front side or surface of the fins, thereby preventing oxidation of the top surface of the fins in step 135. The nitride regions may be removed in an intermediate step, not shown in FIG. 1, between steps 145 and 150.

[0037] In a further exemplary embodiment, the second implantation process can implant a spreading region under the second trench. The spreading region can be n-type doped and can have a higher doping than the n-type doped drift layer. This can enhance the current spreading effect under the second trench. The second implantation process can have a second implantation energy having a value between 200 keV and 2500 keV.

[0038] 2 shows a power FinFET 200 with alternating shielding regions and without a two-part control electrode 209. The control electrode 209 is integral. The power FinFET 200 has a semiconductor body 201 having a first terminal region 202, a drift layer 203, a channel region 204, and a second terminal region 205. The first terminal region 202 functions as a drain terminal and the second terminal region 205 functions as a source terminal. The drift layer 203 is disposed on the first terminal region 202, the channel region 204 is disposed on the drift layer 203, and the second terminal region 205 is disposed on the channel region 204. The second terminal region 205 functions as the front side of the semiconductor body 201.

[0039] From the front side of the semiconductor body 201, a first trench 206 and a second trench 207 extend into the drift layer 203, in which the second trench 207 has a smaller width than the first trench 206. The first trench 206 and the second trench 207 are arranged one after the other. A shielding region 211 is arranged below the first trench 206, which is preferably p-doped and directly adjoins the trench bottom of the first trench 206. The dopant concentration of the shielding region 211 is at least 1E18 / cm 3Shielding region 211 is conductively connected to source region 210, which is not located in a trench, for example by contacts at the edge of the cell array, or by deep terminal portions implanted at periodic intervals along the fin, as partially illustrated in FIG. 2. Control electrode 209 may function as a gate terminal. The division of control electrode 209 into two may be completely or at least partially eliminated, i.e. one, several or all control electrodes 209 may be integral. Control electrode 209 is electrically insulated from shielding region 211 by oxide layer 208. Between first trench 206 and second trench 207, fin 212 is arranged, which may have a width of, for example, less than 500 nm, preferably in the range between 400 and 50 nm, and more preferably in the range between 200 and 50 nm.

[0040] The semiconductor body 201 may include SiC and / or GaN. In one exemplary embodiment, a spreading region 213 is arranged below the second trench 207. The spreading region 213 may be n-type doped. The spreading region 213 may have a higher doping than the drift layer 203, which may also be n-type doped. The shielding regions 211 and the spreading regions 213 may be arranged in a sequential, in particular alternating, or periodic pattern. The spacing between directly adjacent shielding regions 211 may be in the range between 800 and 1000 nm, preferably in the range between 850 and 950 nm. It is further preferred that the spacing between directly adjacent shielding regions may be 900 nm.

[0041] Power FinFETs find application, for example, in DC / DC converters and inverters in electric powertrains of electric or hybrid vehicles, and in vehicle chargers. [Explanation of symbols]

[0042] 200 Power FinFET 201 Semiconductor body 202 First Terminal Area 203 Drift Layer 204 Channel Region 205 Second Terminal Area 206 First Groove 207 Second Groove 208 Oxide layer 209 Control Electrode 210 Source Region 211 Covered area 212 Finn 213 Spreading Area

Claims

1. A method (100) for manufacturing a power FinFET (200) with an integral control electrode, the power FinFET (200) comprising a semiconductor body (201) having a second terminal region (205) and a drift layer (203), the second terminal region (205) being on a front side of the semiconductor body (201), the method comprising the steps of: - generating (105) a first structured mask on the front side of the semiconductor body (201) by a lithography step, said first structured mask having oxide regions and first open regions, said first open regions exposing said front side of the semiconductor body (201); generating (110) a first trench (206) from the front side of the semiconductor body (201) into the drift layer (203) under the first open area by a first etching process; - creating (115) a shielding region (211) under said first trench by a first implantation process; - applying (120) an isotropic oxide layer to said front side of said semiconductor body (201); - generating (125) a second structured mask by a second etching process, whereby the isotropic oxide layer has second open areas, the second open areas exposing the front side of the semiconductor body (201); generating (130) second trenches (207) from the front side into the drift layer (203) under the second open areas by a third etching process, the second trenches (207) being arranged substantially parallel to the first trenches (206) and alternating between the first trenches (206) and the second trenches (207), the second trenches (207) having a smaller width than the first trenches (206); - oxidizing (135) said front side, whereby a further oxide layer is disposed on said front side; - expanding (140) the width of said first trench (206) and said second trench (207) by a fourth etching process, whereby a fin (212) is created between said first trench (206) and said second trench (207), said fin (212) having a width of less than 500 nm; applying (145) a polysilicon layer to said front side of said semiconductor body, whereby said first trench (206) and said second trench (207) are completely filled; - activating (150) said shielded regions (211) by annealing; The method (100),

2. 2. The method (100) of claim 1, wherein the first structured mask comprises a nitride region, and wherein the oxide region is disposed on the nitride region.

3. The method (100) of claim 1 or 2, wherein a second implantation process creates a widening region under the second trench, where the second implantation energy has a value between 200 keV and 2500 keV.

4. 4. The method of claim 1, wherein the first etching process, the second etching process, and the third etching process are anisotropic plasma etching processes.

5. The method of any one of claims 1 to 4, wherein the first implantation process has a first implantation energy in the range of 30 keV to 2700 keV.

6. A power FinFET (200) comprising a semiconductor body (201) having an integral control electrode, a drift layer (203) and a second terminal region (205), the second terminal region (205) is disposed on the drift layer (203), and a first groove (206) and a second groove (207) extend from the second terminal region (205) into the drift layer (203); a first groove (206) and a second groove (207) are arranged in sequence with respect to each other, wherein the second groove (207) has a smaller width than the first groove (206); a shielding region (211) is disposed below the first trench (206), the shielding region (211) is directly adjacent to the first trench (206), the shielding region (211) is conductively connected to a source region (210), the conductive connection being not disposed within the first trench (206); a respective integral control electrode (209) is disposed in each of the first grooves (206), the respective integral control electrode (209) being electrically insulated from the shielding area (211) below the first groove (206); and A fin (212) is disposed between the first trench (206) and the second trench (207), the fin (212) having a width of at most 500 nm.

7. The power FinFET (200) of claim 6, wherein a spreading region (213) is disposed beneath the second trench (207).

8. The shielding region is p-doped and has a density of at least 1E18 / cm ３ The power FinFET (200) of claim 6 or 7, having a dopant concentration of:

9. The power FinFET (200) of any one of claims 6 to 8, wherein the semiconductor body (201) comprises SiC.

10. The power FinFET (200) of any one of claims 6 to 8, wherein the semiconductor body (201) comprises GaN.

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