Semiconductor device

Abstract

To provide a semiconductor device capable of assuring a circuit operation voltage while improving ESD resistance of a circuit part which transmits / receives a signal across different power supplies.SOLUTION: A semiconductor device according to the present disclosure has a semiconductor chip including a first circuit region, a second circuit region having a ground voltage different from a ground voltage of the first circuit region, a first protection element, and a resistance circuit. The first circuit region includes: a first terminal to which a power supply voltage is supplied; a first circuit electrically connected to the first terminal; and a second circuit electrically connected to the first terminal and the first circuit, with smaller power consumption than the first circuit. The second circuit region includes a third circuit electrically connected to the second circuit. The first circuit and the third circuit mutually inputs / outputs a unidirectional or bidirectional signal through the second circuit. The first protection element is electrically connected to a first node which electrically connects the first terminal and the second node. The resistance circuit electrically connects the first node to the first terminal, the first circuit, and the second circuit, and is provided between itself and a second node located at upstream of the first node.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device, and particularly to a semiconductor device including a protection element.

Background Art

[0002] The CDM (Charged Device Model) test is a withstand voltage evaluation method using an electrostatic discharge model in a semiconductor chip. The CDM withstand voltage is evaluated by charging the entire semiconductor chip and then discharging it by contacting a test pin with a ground terminal (ground conductor).

[0003] In the semiconductor process, the thinning of the gate oxide film of MOS (Metal-Oxide-Semiconductor) transistors due to miniaturization is progressing, and the reduction of the gate breakdown voltage has become remarkable. Therefore, during an electrostatic breakdown test for evaluating ESD (Electro-Static Discharge) resistance (especially during a CDM test), gate breakdown of MOS transistors is likely to occur. This tendency is particularly prominent in MOS transistors that transmit and receive signals across different power supplies in a semiconductor chip where an analog circuit and a digital circuit are mixed and different power supplies are supplied to each.

[0004] Patent Document 1 discloses a semiconductor device in which a protection element is connected to an internal node between a bias circuit and a clock oscillator, and a protection resistor is inserted between the internal node and the power supply of an analog circuit.

[0005] Thereby, an ESD discharge path is formed, a part of the ESD current flows through the protection resistor, a voltage drop is generated between the power supply of the analog circuit and the internal node, and the ESD stress voltage applied to the signal line crossing between different power supplies is divided and reduced.

Prior Art Documents

Patent Documents

[0006]

Patent Document 1

SUMMARY OF THE INVENTION

PROBLEMS TO BE SOLVED BY THE INVENTION

[0007] In highly integrated semiconductor chips such as 3nm process products, when a protection resistor with a large resistance value is inserted, the PLL (Phase Locked Loop) may not be able to operate due to the requirements for increasing the clock frequency and the decrease in the power supply voltage of the analog circuit.

[0008] To solve this problem, it is necessary to increase the supply current to the oscillator. However, if the resistance value of the protection resistor is large, the voltage drop between the power supply of the analog circuit and the internal node during normal operation becomes large, so the voltage of the internal node decreases and the oscillator cannot operate.

[0009] With the reduction in the breakdown voltage of transistors due to process miniaturization, it is necessary to lower the power supply voltage of the analog circuit. Therefore, the margin of the voltage drop amount between the power supply of the analog circuit and the internal node becomes smaller than that of the prior art, and it has become difficult in circuit design to use a protection resistor with a large resistance value.

[0010] Other problems and novel features will become apparent from the description of this specification and the accompanying drawings.

MEANS FOR SOLVING THE PROBLEMS

[0011] The semiconductor device according to the present disclosure has a semiconductor chip including a first circuit region, a second circuit region having a ground voltage different from the ground voltage of the first circuit region, a first protection element, and a resistance circuit. The first circuit region includes a first terminal to which a power supply voltage is supplied, a first circuit electrically connected to the first terminal, and a second circuit electrically connected to the first terminal and the first circuit and having lower power consumption than the first circuit. The second circuit region includes a third circuit electrically connected to the second circuit. The first circuit and the third circuit input and output unidirectional or bidirectional signals to and from each other via the second circuit. The first protection element is electrically connected to a first node electrically connecting the first terminal and the second circuit. The resistance circuit is provided between the first node and a second node located upstream of the first node and electrically connecting the first terminal, the first circuit, and the second circuit.

Advantages of the Invention

[0012] According to the present disclosure, it is possible to provide a semiconductor device capable of ensuring a circuit operating voltage while enhancing the ESD resistance of a circuit section that transmits and receives signals across different power supplies.

Brief Description of the Drawings

[0013]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Embodiments for Carrying Out the Invention

[0014] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. In the specification and drawings, the same constituent elements or corresponding constituent elements are denoted by the same reference numerals, and redundant descriptions are omitted. In the drawings, for convenience of explanation, the configuration may be omitted or simplified. Also, at least a part of each embodiment may be arbitrarily combined with each other.

[0015] In the semiconductor device according to the present disclosure, a configuration in which the conductivity type (p-type or n-type) of a semiconductor substrate, a semiconductor layer, a diffusion layer (diffusion region), etc. is inverted may be adopted. Therefore, when one of the n-type and p-type conductivity types is defined as the first conductivity type and the other conductivity type is defined as the second conductivity type, the first conductivity type can be p-type and the second conductivity type can be n-type, or conversely, the first conductivity type can be n-type and the second conductivity type can be p-type.

[0016] Also, in the present disclosure, the expression "connect" shall include the meaning of "electrically connect" unless specifically described as "directly connect".

[0017] <Embodiment 1> Hereinafter, a configuration example of the semiconductor chip 1 included in the semiconductor device according to the present disclosure will be described with reference to FIG. 1. The semiconductor chip 1 shown in FIG. 1 includes at least a first circuit region 10, a second circuit region 20, and a first protection element 30. Also, the second circuit region 20 is driven at a ground voltage different from the ground voltage of the first circuit region 10.

[0018] The first circuit region 10 includes at least a first terminal 11, a first circuit 12, and a second circuit 13. The first terminal 11 is a terminal to which a power supply voltage is supplied from the outside. The first terminal 11 is electrically connected to the first circuit 12 and the second circuit 13 that consumes less power than the first circuit 12.

[0019] The second circuit region 20 includes at least the third circuit 21. The third circuit 21 is electrically connected to the second circuit 13. Thus, the first circuit 12 and the third circuit 21 are electrically connected to each other via the second circuit 13. Also, the first circuit 12 and the third circuit 21 perform input and output of unidirectional or bidirectional signals to each other via the second circuit 13.

[0020] The first protection element 30 is electrically connected to a first node 14 that electrically connects the first terminal 11 and the second circuit 13. Details of the first protection element 30 will be described later.

[0021] The resistance circuit 16 is provided between the first node 14 and a second node 15 that electrically connects the first terminal 11, the first circuit 12, and the second circuit 13 and is located upstream of the first node 14. Details of the resistance circuit 16 will also be described later.

[0022] With such a configuration, it is possible to provide a semiconductor device that can ensure the circuit operating voltage while enhancing the ESD resistance of a circuit section that transmits and receives signals across different power supplies.

[0023] Next, a configuration example of the semiconductor chip 1 will be described in detail with reference to FIG. 2.

[0024] Within the semiconductor chip 1, the second circuit region 20 has a larger area than the first circuit region 10. Also, the semiconductor device according to the present disclosure operates preferably when the areas of the wirings, wells, and diffusion layers to which the power supply voltage and the ground voltage of the second circuit region 20 are supplied are larger than those of the first circuit region 10.

[0025] For example, the first circuit region 10 is an analog circuit region, and the second circuit region 20 is a digital circuit region. Also, in another aspect of the present disclosure, the first circuit region 10 is a circuit region to which a power supply voltage and a ground voltage used exclusively for IP (Intellectual Property) are supplied, and the second circuit region 20 is a circuit region to which a power supply voltage and a ground voltage commonly used for the semiconductor chip are supplied.

[0026] An IP is a circuit function block with a specific role, and the circuit area (hereinafter referred to as the "IP dedicated area") to which the power supply voltage and ground voltage dedicated to the IP are supplied is a circuit area where analog IPs mainly processing analog signals are arranged.

[0027] Examples of analog IPs include PLL (Phase Locked Loop), TRNG (True Random Number Generator), oscillators, temperature sensors, Analog-to-Digital converters, and Digital-to-Analog converters. Since these circuits are easily affected by noise, it is necessary to provide dedicated power supply voltage and ground voltage to avoid noise propagation from the circuit area supplied with the power supply voltage and ground voltage commonly used for semiconductor chips.

[0028] The circuit area (hereinafter referred to as the "chip common circuit area") to which the power supply voltage and ground voltage commonly used for semiconductor chips are supplied is a circuit area where digital IPs mainly processing digital signals are arranged.

[0029] Examples of digital IPs include CPU (Central Processing Unit), SRAM (Static Random Access Memory), and flash memory. Since these circuits are less affected by noise compared to analog IPs, the chip common power supply voltage and ground voltage used by multiple IPs can be used.

[0030] The first terminal 11 in the first circuit area 10 is electrically connected to the first external terminal 111 to which the power supply voltage is supplied from the outside, and also functions as a test pin in the CDM test. Similarly, the second terminal 211 in the second circuit area 20 is electrically connected to a second external terminal 212 different from the first external terminal 111.

[0031] In addition to the above-described configuration, the first circuit region 10 further includes a bias circuit 41, a bias circuit 42, and a protection circuit 43. The bias circuit 41 is provided between the second node 15 and the first circuit 12, and the bias circuit 42 is provided between the resistance circuit 16 and the first node 14. Further, the protection circuit 43 is provided between the first terminal 11 connected to the power supply and the first ground 110.

[0032] The first circuit 12 and the third circuit 21 are electrically connected via the second circuit 13, and thus, input and output of unidirectional or bidirectional signals are performed with each other via the second circuit. In FIG. 2, the first signal 50 output from the first circuit 12 to the second circuit 13 is a signal that crosses between the same power supplies. The first signal 50 is processed so as to be converted into a second signal 60 that crosses between different power supplies in the second circuit 13, and is output to the third circuit 21.

[0033] Alternatively, a configuration may be adopted in which the first signal 50 is output from the third circuit 21 to the second circuit 13, the first signal 50 is processed into the second signal 60 in the second circuit 13, and the second signal 60 is output to the first circuit 12. This configuration will be described in Embodiment 3.

[0034] In addition to the configuration of Embodiment 1, the second circuit region 20 further includes a second terminal 211 to which a power supply voltage different from that of the first circuit region 10 (ground voltage supplied to the second circuit region 20) is supplied, and the third circuit 21 is provided between the second terminal 211 and the second ground 210.

[0035] Further, a protection circuit 44 is provided between the first ground 110 and the second ground 210. Thereby, a discharge path for ESD current is formed between the first ground 110 and the second ground 210.

[0036] When the second circuit region 20 has a larger area than the first circuit region 10, a large amount of charges accumulated in the second circuit region 20 flow into the first circuit region 10. As a result, a large ESD stress voltage is applied between the first circuit region 10 and the second circuit region 20, which becomes a cause of electrostatic breakdown.

[0037] Also, in the CDM negative polarity test where the semiconductor under test is charged with a negative charge and the charging charge is discharged from the test terminal, when the first terminal 11 is used as the test terminal, the CDM current entering from the first terminal 11 flows through the protection circuits 43 and 44 into the second circuit region 20. Therefore, a large ESD stress voltage equivalent to two stages of protection circuits is applied to the third circuit 21 that receives the second signal 60 (a signal crossing between different power supplies), which becomes a factor of electrostatic breakdown.

[0038] When the ESD stress voltage applied to the third circuit 21 cannot be suppressed below the breakdown voltage only by the protection circuits 43 and 44, a method of providing a discharge path through the resistance circuit 16 and the first protection element 30 to divide and reduce the ESD stress voltage of the first node 14 and the second signal 60 can be mentioned. However, for example, when the first circuit 12 is a circuit with a large consumption current during normal operation, such as an oscillator that generates a clock signal with a frequency of about several GHz, inserting a high-resistance resistance circuit 16 will increase the voltage drop applied across the first circuit 12 due to the circuit operating current flowing during normal operation. Therefore, there may be a case where the first circuit 12 cannot operate sufficiently.

[0039] Furthermore, as the breakdown voltage of the transistor decreases due to process miniaturization, it is necessary to lower the power supply voltage. Therefore, the margin of the voltage drop amount between the first terminal 11 and the node (the third node 17) between the first circuit 12 and the bias circuit 41 becomes smaller, and it is required in circuit design to lower the resistance values of the resistance circuit 16 and the first protection element 30.

[0040] The semiconductor device according to the present disclosure includes, in the first circuit region 10, a second circuit 13 that is a buffer circuit with lower power consumption than the first circuit 12, and a bias circuit 42 for the buffer circuit, and has a configuration that transmits a signal from the first circuit 12 to the second circuit region 20 via the second circuit 13.

[0041] Furthermore, the first protection element 30 is provided between the first node 14 and the second ground 210 of the second circuit region 20, and the resistance circuit 16 is preferably provided between the first node 14 and the second node 15 located upstream of the first node 14, which electrically connects the first terminal 11, the first circuit 12, and the second circuit 13. In the present disclosure, the expression "located upstream" means that when starting from the first terminal 11, the second node 15 is electrically closer to the first terminal 11 than the first node 14. Also, the first node 14 is preferably not connected to the third node 17 and is electrically separated.

[0042] With such a configuration, the voltage drop generated in the resistance circuit 16 during normal operation can be reduced, so it is not essential to lower the resistance value of the resistance circuit 16. Therefore, a semiconductor device can be provided that can ensure the circuit operating voltage while enhancing the ESD resistance of the signal portion across different power supplies.

[0043] Next, each component of the semiconductor device according to the present disclosure will be described. A specific example of the first circuit 12 is a ring oscillator composed of a multi-stage inverter circuit, and a specific example of the second circuit is an inverter circuit. Since the inverter circuit has fewer elements and a smaller element size than the ring oscillator, it consumes less power and is suitable for the semiconductor device according to the present disclosure.

[0044] The bias circuits 41 and 42 are circuits that generate a reference power supply and a reference current for the circuits (the first circuit 12 and the second circuit 13) located downstream of the bias circuits to operate properly.

[0045] The protection circuit 43 is provided between the first terminal 11 and the first ground 110. As an example, a GCNMOS (Gate Controlled Ntype Metal Oxide Semiconductor) with a channel width of 1000 to 10000 μm is used. The protection circuit 44 is provided between the first ground 110 and the second ground 210. As an example, a bidirectional diode with an anode-cathode facing length of 100 to 1000 μm is used. Each protection circuit forms a discharge path for the ESD current and has the role of discharging the ESD current to the external terminal. The impedance value of the discharge path formed by these protection circuits is about several milliohms to several ohms.

[0046] The first protection element 30 is preferably formed of a PMOS transistor or an NMOS transistor having a channel width of several μm to several tens of μm. Further, the first protection element 30 may be formed of a plurality of diodes having an opposing length of 1 to 100 μm.

[0047] The resistance circuit 16 is preferably formed of a resistor having a value of several tens to several thousands of ohms. The resistance circuit 16 is not limited to only the position shown in FIG. 2 and may be provided between the bias circuit 42 and the first node 14. The impedance value of the resistance circuit 16 is about several tens to several thousands of ohms, and the resistance circuit 16 may be formed of a transistor that can obtain a similar impedance value.

[0048] Also, as shown in FIG. 3, a protection circuit 45 serving as a second protection element may be connected between the first terminal 11 of the first circuit region 10 and the second ground 210 of the second circuit region 20 so as to be electrically short-circuited. By providing the protection circuit 45, the CDM current flowing in from the first terminal 11 can be dispersed into a discharge path passing through the protection circuits 43 and 44 and two discharge paths passing through the protection circuit 45. Therefore, it is possible to reduce the ESD stress voltage as compared with the case where only the discharge path passing through the protection circuits 43 and 44 is used.

[0049] Since the protection circuit 45 can use the same configuration as the protection circuit 43, the impedance of the discharge path formed by the protection circuit 45 is about several commas to several ohms. Therefore, the impedance value of the resistance circuit 16 is larger than that of the protection circuit 45 which serves as the second protection element.

[0050] By adopting such a configuration, it is possible to provide a semiconductor device that can enhance the ESD resistance of the circuit section for transmitting signals across different power supplies while ensuring the circuit operating voltage.

[0051] <Embodiment 2> In this embodiment, a modification of the semiconductor chip 1 included in the semiconductor device according to Embodiment 1 will be described in detail with reference to FIG. 4. Note that, in order to avoid redundant explanations, the description may be omitted for those that are the same as the configuration example of Embodiment 1.

[0052] The fourth circuit 114 included in the first circuit region 10 according to this embodiment is a regulator circuit for an analog circuit, the fifth circuit 115 is a unity gain buffer circuit, and the sixth circuit 116 is an analog circuit.

[0053] The fourth circuit 114, which is a regulator circuit, generates an internal voltage such as a secondary power supply and a reference voltage to be applied to the sixth circuit 116, which is an analog circuit. The fifth circuit 115, which is a unity gain buffer circuit, outputs the internal voltage input to the analog circuit to the second circuit region 20, which is a digital circuit region. Here, it is preferable that the fifth circuit 115, which is a unity gain buffer circuit, reduces the number of elements or the element size to reduce the current consumption compared to the fourth circuit 114, which is a regulator circuit.

[0054] In a configuration where the internal voltage generated in the analog circuit region is output to the digital circuit region, if the resistance circuit 16 is provided in the regulator circuit, when the current consumption of the regulator is large, a large voltage drop may occur in the resistance circuit 16, and the voltage level of the first signal may decrease, which is not preferable.

[0055] On the one hand, a semiconductor device capable of ensuring the circuit operating voltage while enhancing the ESD resistance of a circuit section that transmits a signal across different power supplies can be provided by a configuration in which a resistance circuit 16 is provided so as to be located upstream of the unity gain buffer circuit according to the present disclosure.

[0056] <Embodiment 3> In the present embodiment, a modification of the semiconductor chip 1 included in the semiconductor device according to Embodiments 1 and 2 will be described in detail with reference to FIG. 5. Note that, in order to avoid redundant explanations, the description may be omitted for those that are the same as the configuration examples of Embodiments 1 and 2.

[0057] A seventh circuit 117 included in the first circuit region 10 according to the present embodiment is a signal output circuit of a level shifter, an eighth circuit 118 is a buffer circuit, and a ninth circuit 219 included in the second circuit region 20 is a signal input circuit of a level shifter. Therefore, the semiconductor chip 1 according to the present embodiment has a configuration in which a signal is passed from the second circuit region 20, which is a digital circuit region, to the first circuit region 10, which is an analog circuit region.

[0058] The ninth circuit 219, which is a signal input circuit of the level shifter, is preferably composed of an inverter circuit.

[0059] The eighth circuit 118, which is a buffer circuit, is preferably composed of a plurality of stages of inverter circuits, and it is preferable to reduce the number of elements or reduce the element size to make the current consumption smaller than that of the seventh circuit 117, which is a signal output circuit of the level shifter. With such a configuration, a semiconductor device capable of ensuring the circuit operating voltage while enhancing the ESD resistance of a circuit section that transmits a signal across different power supplies can be provided.

[0060] As described above, the invention made by the present inventor has been specifically described based on the embodiments. However, it goes without saying that the present invention is not limited to the embodiments already described, and various modifications can be made without departing from the gist thereof.

Description of Reference Numerals

[0061] 1 Semiconductor chip 10 First circuit region 11 First terminal 12 First circuit 13 Second circuit 14 First node 15 Second node 16 Resistance circuit 17 Third node 20 Second circuit region 21 Third circuit 30 First protection element 41, 42 Bias circuit 43, 44, 45 Protection circuit 50 First signal 60 Second signal 110 First ground 111 First external terminal 114 Fourth circuit 115 Fifth circuit 116 Sixth circuit 117 Seventh circuit 118 Eighth circuit 210 Second ground 211 Second terminal 212 Second external terminal 219 Ninth circuit

Claims

1. a semiconductor chip including a first circuit area, a second circuit area having a ground voltage different from the ground voltage of the first circuit area, a first protection element, and a resistor circuit; The first circuit area includes: a first terminal to which a power supply voltage is supplied; a first circuit electrically connected to the first terminal; a second circuit electrically connected to the first terminal and the first circuit and consuming less power than the first circuit; the second circuit region includes a third circuit electrically connected to the second circuit; the first circuit and the third circuit perform unidirectional or bidirectional signal input / output between each other via the second circuit; the first protection element is electrically connected to a first node that electrically connects the first terminal and the second circuit; The resistor circuit is provided between the first node and a second node that electrically connects the first terminal, the first circuit, and the second circuit and is located upstream of the first node. Semiconductor device.

2. a second terminal to which a ground voltage of the second circuit area is supplied and which is electrically connected to the third circuit; a second protection element that connects the first terminal and the second terminal so as to electrically short-circuit the first terminal and the second terminal, The impedance value of the resistor circuit is greater than that of the second protection element. The semiconductor device according to claim 1 .

3. the first circuit area is an analog circuit area, The second circuit area is a digital circuit area. The semiconductor device according to claim 2 .

4. a first signal is output from the first circuit to the second circuit; The first signal is processed into a second signal by the second circuit and then output to the third circuit. The semiconductor device according to claim 3 .

5. the first circuit is a ring oscillator configured with a plurality of inverter circuits, The second circuit is an inverter circuit. The semiconductor device according to claim 4.

6. The first circuit area is a circuit area to which a power supply voltage and a ground voltage are supplied for exclusive use by an IP (Intellectual Property), The second circuit area is a circuit area to which a power supply voltage and a ground voltage that are commonly used in the semiconductor chip are supplied. The semiconductor device according to claim 2 .

7. The second circuit region has a larger area than that of the first circuit region, the area being determined by the wiring, the well, and the diffusion layer to which a power supply voltage and a ground voltage are supplied. The semiconductor device according to claim 2 .

8. a first signal is output from the third circuit to the second circuit; The first signal is processed by the second circuit to a second signal, and then output to the first circuit. The semiconductor device according to claim 3 .

9. the first circuit is a regulator circuit that outputs a given voltage; The second circuit is a unity gain buffer circuit. The semiconductor device according to claim 4.

10. the first circuit, the second circuit, and the third circuit constitute a level shifter; the first circuit is a signal output circuit of the level shifter, the second circuit is a multi-stage inverter circuit, The third circuit is a signal input circuit of the level shifter. The semiconductor device according to claim 8.

11. 2. The semiconductor device according to claim 1, wherein the resistance circuit is formed of a resistor.

12. 2. The semiconductor device according to claim 1, wherein the resistor circuit is formed of a transistor.

13. The semiconductor device according to claim 1 , wherein the first protection element is formed of a PMOS transistor or an NMOS transistor.

14. The semiconductor device according to claim 1 , wherein the first protection element is formed of a plurality of diodes.

15. the first terminal is electrically connected to a first external terminal; The second terminal is electrically connected to a second external terminal different from the first external terminal. The semiconductor device according to claim 2 .

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