Semiconductor package

Abstract

To provide a semiconductor package capable of implementing a stack of semiconductor chips having a bonding interfacial surface with excellent quality.SOLUTION: A semiconductor package includes: a first semiconductor chip including a first buffer layer 160 that is arranged on a first substrate 110, and surrounds a side surface of a first upper pad 150a of a first group, a first insulation layer 140 that surrounds a side surface of a first upper pad 150b of a second group and a side surface of the first upper pad 150a, a penetration electrode 130 penetrating the substrate; and a second semiconductor chip including a second buffer layer 260 that is arranged on the first semiconductor, is arranged under a second substrate 210, and surrounds a side surface of a second lower pad of the first group, and a second insulation layer 240 surrounding a side surface of a second lower pad 250b of the second group and a side surface of the second buffer layer. The first upper pad of the first group is in contact with the second lower pad, and the first upper pad of the second group is in contact with the second lower pad of the second group.SELECTED DRAWING: Figure 2a

Description

[Technical field]

[0001] The present invention relates to semiconductor packages. [Background technology]

[0002] As the demand for high capacity, thin and compact electronic products increases, various types of semiconductor packages are being developed. Recently, direct bonding technology has been developed to bond semiconductor chips without adhesive films (e.g. NCF) or connection bumps (e.g. solder balls) as a method to incorporate more components (e.g. semiconductor chips) into the package structure. Summary of the Invention [Problem to be solved by the invention]

[0003] One of the problems to be solved by the present invention is to provide a semiconductor package having improved reliability by realizing a stack of semiconductor chips having a bonding interface of excellent quality. [Means for solving the problem]

[0004] A semiconductor package according to an exemplary embodiment includes a first substrate, a first semiconductor chip disposed on the first substrate, the first semiconductor chip including a plurality of first upper pads including a first group and a second group of first upper pads, a first buffer layer surrounding side surfaces of the first upper pads of the first group, a first insulating layer surrounding side surfaces of the first upper pads of the second group and a side surface of the first buffer layer, and a plurality of through electrodes penetrating the first substrate and connected to the plurality of first upper pads; and a second substrate disposed on the first semiconductor chip, the first semiconductor chip including a second substrate and the first insulating layer. The second semiconductor chip includes a second substrate and includes a plurality of second lower pads including a first group and a second group of second lower pads, a second buffer layer surrounding side surfaces of the second lower pads of the first group, and a second insulating layer surrounding side surfaces of the second lower pads of the second group and side surfaces of the second buffer layer, wherein the first upper pads of the first group are in contact with the second lower pads of the first group, and the first upper pads of the second group are in contact with the second lower pads of the second group.

[0005] A semiconductor package according to an exemplary embodiment includes a first semiconductor chip and a second semiconductor chip stacked vertically, the first semiconductor chip including a first upper conductive layer and a first upper seed layer surrounding a side surface and a bottom surface of the first upper conductive layer, a first buffer layer extending around some of the first upper pads, a first insulating layer surrounding the remaining first upper pads of the first upper pads and the first buffer layer, the second semiconductor chip including a second lower conductive layer and a second lower seed layer surrounding a side surface and a top surface of the second lower conductive layer, a plurality of second lower pads electrically connected to the first upper pads, a second buffer layer extending around some of the second lower pads, and a second insulating layer surrounding the remaining second lower pads of the second lower pads and the second buffer layer, the first buffer layer and the second buffer layer may include a polymer or a porous metal.

[0006] A semiconductor package according to an exemplary embodiment includes a first semiconductor chip including a plurality of upper pads; and a second semiconductor chip including a plurality of lower pads including a first group and a second group of lower pads in contact with upper surfaces of the plurality of upper pads, a connecting conductor in contact with an upper surface of the lower pads of the first group, an inner insulating layer surrounding a side surface of the connecting conductor, a buffer insulating layer in contact with a side surface of the lower pads of the first group and an upper surface of the lower pads of the second group, and an outer insulating layer surrounding the side surface of the lower pads of the first group and a side surface of the lower pads of the second group under the buffer insulating layer, wherein the lower pads of the first group may include a layer portion surrounded by the outer insulating layer and an extension portion extending from an upper surface of the layer portion, penetrating the buffer insulating layer, and contacting a lower surface of the connecting conductor.

[0007] A semiconductor chip according to an exemplary embodiment may include a substrate; a plurality of upper pads disposed on the substrate, the plurality of upper pads including a first group and a second group of upper pads; a buffer layer covering sides of the first group of upper pads; and an insulating layer surrounding sides of the second group of upper pads and sides of the buffer layer on the substrate, the buffer layer including a first material having a first Young's modulus smaller than a second Young's modulus of a second material included in the plurality of upper pads. Effect of the Invention

[0008] According to an embodiment of the present invention, by introducing a buffer layer surrounding a portion of the pad, a stack of semiconductor chips can be achieved with a superior quality bonding interface, providing a semiconductor package with improved reliability. [Brief description of the drawings]

[0009] [Figure 1] 1 is a cross-sectional view showing a semiconductor package according to an embodiment of the present invention. [Figure 2a] FIG. 2 is a partially enlarged view showing area “A” of FIG. [Figure 2b]FIG. 2b is a plan view showing a cross section taken along line II' in FIG. 2a. [Diagram 3] FIG. 2b is a plan view showing a variation on region "A" of FIG. 2a. [Figure 4] FIG. 2b is a plan view showing a variation on region "A" of FIG. 2a. [Diagram 5] FIG. 2b is a plan view showing a variation on region "A" of FIG. 2a. [Figure 6] FIG. 2b is a plan view showing a variation on region "A" of FIG. 2a. [Figure 7] FIG. 2b is a plan view showing a variation on region "A" of FIG. 2a. [Figure 8] FIG. 2b is a plan view showing a variation on region "A" of FIG. 2a. [Figure 9] FIG. 2b is a plan view showing a variation on region "A" of FIG. 2a. [Figure 10] FIG. 2b is a plan view showing a variation on region "A" of FIG. 2a. [Figure 11] FIG. 2b is a plan view showing a variation on region "A" of FIG. 2a. [Figure 12] FIG. 2b is a plan view showing a variation on region "A" of FIG. 2a. [Figure 13] FIG. 2b is a plan view showing a variation on region "A" of FIG. 2a. [Figure 14] FIG. 2b is a plan view showing a variation on region "A" of FIG. 2a. [Figure 15] FIG. 2b is a plan view showing a variation on region "A" of FIG. 2a. [Figure 16a] FIG. 16 is a perspective view for explaining a modified example of FIGS. 14 and 15. [Figure 16b] FIG. 16 is a perspective view for explaining a modified example of FIGS. 14 and 15. [Figure 16c] 16 is a graph showing the experimental data of FIGS. 14 and 15. FIG. [Figure 17] FIG. 2b is a plan view showing a variation on region "A" of FIG. 2a. [Figure 18] FIG. 2b is a plan view showing a variation on region "A" of FIG. 2a. [Figure 19]1 is a cross-sectional view showing a semiconductor package according to an embodiment of the present invention. [Figure 20a] 1 is a plan view showing a semiconductor package according to an embodiment of the present invention; [Figure 20b] 20b is a cross-sectional view showing a section taken along line II-II' in FIG. 20a. [Figure 21a] 2b is a cross-sectional view showing a manufacturing process of the semiconductor package of FIG. 2a. [Figure 21b] 2b is a cross-sectional view showing a manufacturing process of the semiconductor package of FIG. 2a. [Figure 21c] 2b is a cross-sectional view showing a manufacturing process of the semiconductor package of FIG. 2a. [Figure 21d] 2b is a cross-sectional view showing a manufacturing process of the semiconductor package of FIG. 2a. [Figure 21e] 2b is a cross-sectional view showing a manufacturing process of the semiconductor package of FIG. 2a. [Figure 22a] 5A to 5C are cross-sectional views showing a manufacturing process of the semiconductor package of FIG. [Figure 22b] 5A to 5C are cross-sectional views showing a manufacturing process of the semiconductor package of FIG. [Figure 22c] 5A to 5C are cross-sectional views showing a manufacturing process of the semiconductor package of FIG. [Figure 23a] 15A to 15C are cross-sectional views showing a manufacturing process of the semiconductor package of FIG. 14. [Figure 23b] 15A to 15C are cross-sectional views showing a manufacturing process of the semiconductor package of FIG. 14. [Figure 23c] 15A to 15C are cross-sectional views showing a manufacturing process of the semiconductor package of FIG. 14. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Hereinafter, an embodiment of the present invention will be described with reference to the accompanying drawings. In the following, terms such as "top", "upper", "upper surface", "lower", "lower", "lower surface", "side" and the like are indicated by reference numerals and may be understood as being referred to with reference to the drawings unless otherwise specified.

[0011] Also, ordinal numbers such as "first," "second," "third," etc. may be used as labels of particular elements, stages, directions, etc. to distinguish various elements, stages, directions, etc. from one another. Terms not described herein with "first," "second," etc. may still be referred to as "first" or "second" in the claims. Furthermore, a term referenced by a particular ordinal number (e.g., "first" in a particular claim) may be described elsewhere by other ordinal numbers (e.g., "second" in the specification or other claims).

[0012] FIG. 1 is a cross-sectional view showing a semiconductor package 10 according to one embodiment of the present invention, FIG. 2a is a partially enlarged view showing area "A" in FIG. 1, and FIG. 2b is a plan view showing a cross section taken along line II' in FIG. 2a.

[0013] First, referring to FIG. 1, a semiconductor package 10 according to an embodiment may include a plurality of semiconductor chips, for example, a first semiconductor chip 100 and a second semiconductor chip 200, stacked in a vertical direction (Z-axis direction). The first semiconductor chip 100 and the second semiconductor chip 200 may be directly bonded and coupled (e.g., may be referred to as hybrid bonding, direct bonding, etc.) between an upper surface of the first semiconductor chip 100 and a lower surface of the second semiconductor chip 200 without a connecting member such as a metal bump. A first insulating layer 140 and a plurality of first upper pads 150 providing an upper surface of the first semiconductor chip 100 may be bonded and coupled to a second insulating layer 240 and a plurality of second lower pads 250 providing a lower surface of the second semiconductor chip 200, respectively. The first semiconductor chip 100 and the second semiconductor chip 200 may be electrically connected to each other through the plurality of first upper pads 150 and the plurality of second lower pads 250 directly bonded thereto.

[0014] Hereinafter, components of the first semiconductor chip 100 and the second semiconductor chip 200 will be described in detail with reference to FIGS. 2a and 2b.

[0015] Hereinafter, the "first insulating layer 140" may be referred to as a "first upper insulating layer" or a "first back insulating layer" respectively to distinguish the positions of components in the first semiconductor chip 100. The "second insulating layer 240" may be referred to as a "second lower insulating layer" or a "second front insulating layer" to distinguish the positions of components in the second semiconductor chip 200. Furthermore, the "first upper pad 150" may be referred to as a "first pad" or a "first back pad", and the "second lower pad 250" may be referred to as a "second pad" or a "second front pad".

[0016] The first semiconductor chip 100 may include a first substrate 110, a first circuit layer 120, a plurality of first through electrodes 130, a first insulating layer 140, a plurality of first upper pads 150, and a first buffer layer 160. The plurality of first upper pads 150 may include a first group of first upper pads 150A and a second group of first upper pads 150B.

[0017] The first substrate 110 may be a semiconductor wafer substrate having a front surface FR and a back surface BA facing each other. For example, the first substrate 110 may be a semiconductor wafer including a semiconductor element such as silicon or germanium, or a compound semiconductor such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP). The front surface FR may be an active surface having an active region doped with impurities, and the back surface BA may be an inactive surface located opposite the front surface FR.

[0018] The first circuit layer 120 may be disposed on the front surface FR of the first substrate 110 and may include a first wiring structure (not shown) connected to the active region and a first interlayer insulating layer (not shown) surrounding the first wiring structure. The first wiring structure (not shown) may form an integrated circuit together with individual elements formed on the active surface of the first substrate 110. A first lower pad 182 electrically connected to the wiring structure (not shown) may be disposed under the first circuit layer 120. The first lower pad 182 may be a pad structure electrically connected to the wiring structure (not shown). A connection bump 186 may be disposed under the first lower pad 182. The connection bump 186 may be a conductive bump structure including, for example, a solder ball or a copper (Cu) post. The first circuit layer 120 may have the same or similar structure as the second circuit layer 220 shown in FIG. 2a. Therefore, the above-mentioned first wiring structure, first interlayer insulating layer, and individual elements can be understood to have similar characteristics to the second wiring structure 225, second interlayer insulating layer 221, and individual elements 215 of the second circuit layer 220 described below.

[0019] The through electrodes 130 (or "first through electrodes") may penetrate the first substrate 110 to electrically connect the first upper pads 150 and the first lower pads 182. The through electrodes 130 may include, for example, tungsten (W), titanium (Ti), aluminum (Al), copper (Cu), titanium (Ti), titanium nitride (TiN), tantalum (Ta), or tantalum nitride (TaN), and may be formed by a plating process, a PVD process, or a CVD process. A side insulating film (not shown) including an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride (e.g., a High Aspect Ratio Process (HARP) oxide) may be formed between the through electrodes 130 and the first substrate 110.

[0020] The first insulating layer 140 (or "first upper insulating layer") may be disposed on the back surface BA of the first substrate 110. The first insulating layer 140 may include an insulating material that can be bonded and coupled to the second insulating layer 240 (or "second lower insulating layer") below the second semiconductor chip 200. For example, the first insulating layer 140 may include at least one of silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), and silicon carbonitride (SiCN). That is, at least a portion of the first insulating layer 140 may be bonded to the second insulating layer 240 to form a bonding interface that bonds and couples the first semiconductor chip 100 and the second semiconductor chip 200. In addition, the first insulating layer 140 may be formed to surround a plurality of first upper pads 150 disposed on an upper surface thereof. The upper surface of the first insulating layer 140 may be substantially coplanar with the upper surfaces of the plurality of first upper pads 150.

[0021] The first upper pads 150 are disposed on the back surface BA of the first substrate 110 and bonded to the second lower pads 250 of the second semiconductor chip 200 to physically and electrically couple the first semiconductor chip 100 and the second semiconductor chip 200. The first upper pads 150 may include a first group of first upper pads 150a and a second group of first upper pads 150b. In a direction parallel to the top surface of the first substrate 110 (e.g., the X direction or the Y direction), a first width W1 of the first upper pads 150a of the first group may be larger than a second width W2 of the first upper pads 150b of the second group. The side and bottom surfaces of the first upper pads 150a of the first group may be covered with the first buffer layer 160, and the side surfaces of the first upper pads 150b of the second group may be in direct contact with the first insulating layer 140. As shown in FIG. 2b, the multiple first upper pads 150 may have a circular shape on a plane (XY plane), and the first buffer layer 160 may be configured to surround the first group of first upper pads 150, but their shapes and arrangements are not limited to this and may be modified in various ways.

[0022] Each of the first upper pads 150 may include a first upper conductive layer 155a, 155b and a first seed layer 153a, 153b covering the side and bottom surfaces of the first upper conductive layer 155a, 155b. The first upper conductive layer 155a, 155b may include at least one of copper (Cu), nickel (Ni), gold (Au), and silver (Ag), and the first seed layer 153a, 153b may include at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN).

[0023] The first buffer layer 160 may cover the side and bottom surfaces of the first group of first upper pads 150a among the plurality of first upper pads 150. The first buffer layer 160 may mitigate the expansion of the first upper pads 150a of the first loop during a thermo-compression process for bonding and joining the first semiconductor chip 100 and the second semiconductor chip 200. If the first width W1 of the first upper pads 150a of the first group is larger than the second width W2 of the second upper pads 150b of the second group, the expansion of the first upper pads 150a of the first group may be larger than the expansion of the first upper pads 150b of the second group during the thermo-compression process. If there is a difference in the expansion of the plurality of first upper pads 150 during the bonding process, the reliability of direct bonding may be reduced. The first buffer layer 160 may mitigate the expansion of the first group of first upper pads 150a, which may have a larger expansion, and improve the reliability of direct bonding.

[0024] The first buffer layer 160 may include a material having a smaller Young's modulus than the material included in the first upper pads 150, or the Young's modulus of the first buffer layer 160 itself may be smaller than the Young's modulus of each of the first upper pads 150 (Young's modulus is a coefficient indicating how the relative length of a given elastic object changes with respect to stress, and is also called elastic modulus). For example, the first buffer layer 160 may include a porous metal. Porosity refers to a state in which a solid has a plurality of small voids inside or on the surface. Since a porous metal has a structure including a plurality of voids, it may have a smaller Young's modulus than a metal having a structure without voids. For example, when the first upper pad 150 includes copper (Cu) and the first buffer layer 160 is made of porous copper (Cu), the Young's modulus of the first buffer layer 160 may be smaller than that of the first upper pad 150 even if the first upper pad 150 and the first buffer layer 160 include the same material, copper (Cu). For convenience of explanation, a material called a "porous metal" may be described as having a smaller Young's modulus than a general "metal" material. For example, porous copper (Cu) may be described as having a smaller Young's modulus than copper (Cu). In one embodiment, the first buffer layer may include porous copper (Cu) or porous silver (Ag). Since the first buffer layer 160 includes a conductive material such as a porous metal, the first group of first upper pads 150a may be electrically connected to the through electrodes 130 via the first buffer layer 160.

[0025] The second semiconductor chip 200 is disposed on the first semiconductor chip 100 and may include a second substrate 210, a second circuit layer 220, a second insulating layer 240, and a plurality of second lower pads 250. The second semiconductor chip 200 may have a flat lower surface provided by the lower surface of the second insulating layer 240 and the lower surfaces of the plurality of second lower pads 250. For example, the lower surface of the second insulating layer 240 and the lower surface of the second lower pads 250 exposed from the second insulating layer 240 may be substantially coplanar. Since the first semiconductor chip 100 and the second semiconductor chip 200 may have substantially the same or similar structures, the same or similar components are represented by the same or similar reference numerals, and the repeated description of the same components will be omitted below. For example, the second substrate 210 may be understood to have substantially the same features as the first substrate 110 described above.

[0026] The second circuit layer 220 is disposed on the front or active surface of the second substrate 210 and may include a second wiring structure 225 connected to the active region and a second interlayer insulating layer 221 surrounding the second wiring structure 225.

[0027] The second interlayer insulating layer 221 may include FOX (Flowable Oxide), TOSZ (Tonen SilaZen), USG (Undoped Silica Glass), BSG (Borosilica Glass), PSG (PhosphoSilaca Glass), BPSG (BoroPhosphoSilica Glass), PETEOS (Plasma Enhanced Tetra Ethyl Ortho Silicate), FSG (Fluoride Silicate Glass), HDP (High Density Plasma) Oxide, PEOX (Plasma Enhanced Oxide), FCVD (Flowable CVD) oxide, or a combination thereof. At least a portion of the second interlayer insulating layer 221 surrounding the second wiring structure 225 may be composed of a low dielectric layer. The second interlayer insulating layer 221 may be formed using a chemical vapor deposition (CVD), a flowable-CVD process, or a spin coating process.

[0028] The second wiring structure 225 may be formed as a multi-layer structure including a wiring pattern and a via made of, for example, aluminum (Al), gold (Au), cobalt (Co), copper (Cu), nickel (Ni), lead (Pb), tantalum (Ta), tellurium (Te), titanium (Ti), tungsten (W), or a combination thereof. A barrier film (not shown) including titanium (Ti), titanium nitride (TiN), tantalum (Ta), or tantalum nitride (TaN) may be disposed between the wiring pattern and / or the via and the second interlayer insulating layer 221. On the front surface of the second substrate 210, a discrete element 215 constituting an integrated circuit may be disposed. In this case, the second wiring structure 225 may be electrically connected to the discrete element 215 by an interconnection portion (e.g., a contact plug). The individual elements 215 may include various active and / or passive elements such as FETs such as planar FETs and FinFETs, memory elements such as flash memory, DRAM, SRAM, EEPROM, PRAM, MRAM, FeRAM, and RRAM, logic elements such as AND, OR, and NOT, system LSIs, CIS, and MEMS.

[0029] The second insulating layer 240 (or "second lower insulating layer") may be disposed under the second substrate 210 or the second circuit layer 220 and may be formed to surround the plurality of second lower pads 250. The second insulating layer 240 may include an insulating material that can be bonded and bonded to the first insulating layer 140 of the first semiconductor chip 100. For example, the second insulating layer 240 may include silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), or silicon carbonitride (SiCN). That is, at least a portion of the second insulating layer 240 may be bonded to the first insulating layer 140 to form a bonding interface that allows the first semiconductor chip 100 and the second semiconductor chip 200 to be bonded and bonded to each other. The lower surface of the second insulating layer 240 may be substantially coplanar with the lower surfaces of the plurality of second lower pads 250. The second insulating layer 240 may have similar characteristics to the first insulating layer 140.

[0030] The second lower pads 250 may be bonded to the first upper pads 150 of the first semiconductor chip 100 to physically and electrically couple the first semiconductor chip 100 and the second semiconductor chip 200. The second lower pads 250 may include a first group of second lower pads 250a and a second group of second lower pads 250b. In a direction parallel to the top surface of the second substrate 210 (e.g., the X-direction or the Y-direction), the first group of second lower pads 250a may have substantially the same width as the first width W1 of the first upper pads 150a of the first group, and the second group of second lower pads 250b may have substantially the same width as the first upper pads 150b of the second group. The first width W1 of the first group of second lower pads 250a may be larger than the second width W2 of the second group of second lower pads 250b of the second group. The side and top of the first group of second lower pads 250a may be covered with the second buffer layer 260, and the side of the second group of second lower pads 250b may be in direct contact with the second insulating layer 240. Each second lower pad 250 may include a second lower conductive layer 253a, 253b and a second seed layer 253a, 253b covering the side and top of the second lower conductive layer 155a, 155b. The second lower conductive layer 255a, 255b may include at least one of copper (Cu), nickel (Ni), gold (Au), and silver (Ag), and the second seed layer 253a, 253b may include at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN). The second lower pads 250 may have similar characteristics to the first upper pads 150.

[0031] The second buffer layer 260 may cover the side and upper surfaces of the first group of second lower pads 250a among the plurality of second lower pads 150. The second buffer layer 260 may mitigate expansion of the first group of second lower pads 250a during a thermo-compression process for bonding and coupling the first semiconductor chip 100 and the second semiconductor chip 200. The second buffer layer 260 may mitigate the expansion of the first group of second lower pads 250a, thereby improving the reliability of direct bonding. The second buffer layer 260 may have the same or similar characteristics as the above-mentioned first buffer layer 160. The first group of second lower pads 250a may be electrically connected to the second wiring structure 225 through the second buffer layer 260.

[0032] The first semiconductor chip 100 and the second semiconductor chip 200 may be bonded and joined through the following process. First, a polishing process may be applied to the upper surface of the first insulating layer 140 and the lower surface of the second insulating layer 240 to form flat surfaces. The polishing process may include a chemical mechanical polishing (CMP) process. Then, the upper surface of the first insulating layer 140 and the lower surface of the second insulating layer 240 may be arranged to face each other, and then pressure may be applied to form a bond due to van der Waals attraction. Then, a low-temperature heat treatment process may be performed at, for example, about 100° C. to 200° C., but is not limited thereto. After a bond is formed between the upper surface of the first insulating layer 140 and the lower surface of the second insulating layer 240, the upper surfaces of the first upper pads 150 and the lower surfaces of the second lower pads 250 may be bonded through an interdiffusion phenomenon during a high-temperature heat treatment process. The high temperature heat treatment process may be performed at a temperature of about 200° C. to 400° C., but is not limited thereto.

[0033] Since the first group of first upper pads 150a and second lower pads 250a have a larger width than the second group of first upper pads 150b and second lower pads 250b, the first group of pads may have a larger expansion during a heat treatment process than the second group of pads, which may impair the stability of the bond. However, the present invention includes first and second buffer layers 160 and 260 surrounding the first group of pads, which can reduce the expansion of the first group of pads and allow for more reliable bonding.

[0034] Although FIG. 2a shows both the first buffer layer 160 and the second buffer layer 260 as being present, depending on the embodiment, only the first buffer layer 160 or only the second buffer layer 260 may be present.

[0035] After bonding, the interface between the first insulating layer 140 and the second insulating layer 240 may not be clearly distinguished, and the interface between the plurality of first upper pads 150 and the plurality of second lower pads 250 may not be clearly distinguished. Depending on the explanation method, the first insulating layer 140 and the second insulating layer 240, the plurality of first upper pads 150 and the plurality of second lower pads 150, the first buffer layer 160 and the second buffer layer 260 may each be explained as one configuration. For example, the first insulating layer 140 and the second insulating layer 240 may be referred to as one bonding insulating layer 140, 240, the plurality of first upper pads 150 and the plurality of second lower pads 250 may be referred to as a plurality of bonding pads 150, 250, and the first buffer layer 160 and the second buffer layer 260 may be referred to as a bonding buffer layer 160, 260.

[0036] 1 to 2b is an exemplary embodiment of a semiconductor package, and the number, shape, intervals, etc. of the plurality of first upper pads and the plurality of second lower pads 250 at the portion where the first semiconductor chip 100 and the second semiconductor chip 200 are bonded may be modified in various ways. The number, arrangement positions, etc. of the first group of first upper pads 150a and the first group of second lower pads 250a, and the second group of first upper pads 150b and the second group of second lower pads 250b may be modified in various ways, and some of these pads may be dummy pads that are not electrically connected to other components.

[0037] In the following description, descriptions that overlap with the contents described with reference to FIGS. 1 to 2b will be omitted.

[0038] 3 to 15 are plan views showing modified examples of the "A" region of FIG. 1. The description with reference to FIGS. 3 to 15 is related to an exemplary embodiment, and the manner in which the first semiconductor 100 and the second semiconductor 200 are joined and coupled may be modified in various ways. The manner in which the modified examples of FIGS. 3 to 15 are applied to the first semiconductor chip 100 and the second semiconductor chip 200 may be changed. For example, the "A" region on the top of the first semiconductor chip 100 may have the form of FIG. 4, and the "A" region on the bottom of the second semiconductor chip 200 may have the form of FIG. 5. That is, several modified examples may be mixed in the first semiconductor chip 100 and the second semiconductor chip 200 within a compatible range.

[0039] 3, a bonding film BF may be present between the first insulating layer 140 and the second insulating layer 240. The bonding film BF may include a material that facilitates bonding and coupling between the first semiconductor chip 100 and the second semiconductor chip 200. The bonding film BF may include a material that is the same as or different from the material included in the first and second insulating layers 140, 240. For example, the bonding film BF may include silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), or silicon carbonitride (SiCN).

[0040] Referring to FIG. 4, the first buffer layer 160 may surround the side of the first group of first upper pads 150a, and the lower surface of the first group of first upper pads 150a may be in direct contact with the through electrode 130. As described with reference to FIG. 2, the first buffer layer 160 may cover the side of the first group of first upper pads 150a, thereby reducing the expansion of the first group of first upper pads 150a during heat treatment. When the first group of first upper pads 150a is in direct contact with the through electrode 130 as in the present embodiment, the first buffer layer 160 may use an insulating material such as a polymer as well as a porous metal. The polymer contained in the first buffer layer 160 may have a smaller Young's modulus than the conductive material contained in the first upper pads 150a. Similarly, the second buffer layer 260 may surround the side of the first group of second lower pads 250a. The top surfaces of the first group of second lower pads 250 a may be in direct contact with the second circuit layer 220 and may be directly electrically connected to the second wiring structure 225 .

[0041] 5, the first buffer layer 160 covers the side and lower surfaces of the first group of first upper pads 150a, and the first group of first upper pads 150a may be directly in contact with the through electrodes 130 through the lower surface of the first buffer layer 160 and be electrically connected thereto. The first buffer layer 160 may include an insulating material such as a polymer as well as a conductive material such as a porous metal. Similarly, the first group of second lower pads 250a may be directly in contact with the second circuit layer 220 through the upper surface of the second buffer layer 260 and be electrically connected thereto.

[0042] 6, the first upper pads 150 and the second lower pads 250 may be in contact with each other so as to be offset from each other. For example, the second lower pads 250 may be arranged to be offset from each other by a predetermined distance L in a horizontal direction (e.g., the X direction). At least a portion of an upper surface of the first upper pad 150 may be in contact with at least a portion of a lower surface of the second lower pad 250.

[0043] 7, the first semiconductor chip 100 may further include a first connection conductor 170. The first connection conductor 170 may be located between the first upper pads 150 and the first substrate 110 in the first insulating layer 140. The first connection conductor 170 may be in direct contact with the upper surface (or the back surface BA, see FIG. 1) of the first substrate 110 and may electrically connect the through electrodes 130 and the first upper pads 150. In this case, the first buffer layer 160 also reduces the expansibility of the first upper pads 150a of the first group during bonding, thereby enabling reliable bonding to be performed even when the first width W1 of the first upper pads 150a of the first group is greater than the second width W2 of the first upper pads 150b of the second group. The width of the first connection conductor 170 in the horizontal direction (e.g., X direction) may be greater than the first width W1 and the second width W2. The first connecting conductor 170 may include, but is not limited to, at least one of aluminum (Al), copper (Cu), or an alloy thereof. The second semiconductor chip 200 may include a second connecting conductor 270 contacting upper surfaces of the second lower pads 250 under the second substrate 210. According to an embodiment, the second connecting conductor 270 may be present only on the first group of second lower pads 250a or only on the second group of second lower pads 250b. The second connecting conductor 270 may have the same or similar characteristics as the first connecting conductor 170 of the first semiconductor chip 100. The second connecting conductor 270 may be located between the second lower pads 250 and the second circuit layer 220 in the second insulating layer 240. The second connecting conductor 270 may be in direct contact with the lower surface of the second circuit layer 220 and may electrically connect the second wiring structure 225 and the second lower pad 250.

[0044] 8, the first upper pad 150b of the second group and the second lower pad 250b of the second group may be dummy pads that are not electrically connected to the surrounding components. The first connection conductor 170 may be directly connected to the through electrode 130 under the first upper pad 150a of the first group, and the second connection conductor 270 may be directly connected to the second wiring structure 225 on the second lower pad 250a of the first group. The first connection conductor 170 may increase the expansibility of the adjacent first upper pad 150a of the first group during bonding. Thus, even if the first width W1 of the first upper pad 150a of the first group is substantially the same as the second width W2 of the second upper pad 250a of the second group, the expansibility of the first upper pad 150a of the first group may be larger. The first buffer layer 160 covering the side and bottom surfaces of the first upper pads 150a of the first group can reduce the expansion of the first upper pads 150a of the first group, thereby improving the reliability of bonding. Similarly, the second buffer layer 260 can reduce the expansion of the adjacent second lower pads 250a of the first group, thereby improving the reliability of bonding.

[0045] 9, the first group of first upper pads 150a may penetrate the first buffer layer 160 and directly contact the first connecting conductor 170. Thus, the first buffer layer 160 may include not only a conductive material but also an insulating material. The first group of second lower pads 250a may penetrate the second buffer layer 260 and directly contact the second connecting conductor 270, and the second buffer layer 260 may include not only a conductive material but also an insulating material. Each configuration of FIG. 9 may have the same or similar features as the corresponding configuration described with reference to FIG. 8.

[0046] 8 and 9, the first buffer layer 160 may cover the side surfaces of the first group of first upper pads 150a, and the lower surfaces of the first group of first upper pads 150a may be in direct contact with the first connecting conductor 170. Similarly, the second buffer layer 260 may cover the side surfaces of the first group of second lower pads 250a, and the upper surfaces of the first group of second lower pads 250a may be in direct contact with the lower surface of the second circuit layer 220 to be electrically connected to the second wiring structure 225.

[0047] 11, the first buffer layer 160 may cover the side surfaces of the first upper pads 150a of the first group as well as the first upper pads 150b of the second group. The first buffer layer 160 may reduce the expansion during bonding of the adjacent first upper pads 150, thereby improving the reliability of bonding. The second buffer layer 260 may also cover the side surfaces of the second lower pads 250b of the second group as well as the second lower pads 250a of the first group, thereby improving the reliability of bonding. The form in which the first and second buffer layers 160 and 260 cover the first upper pads 150 and the second lower pads 250 is not limited thereto, and may be modified in various ways as in the above-described embodiment.

[0048] 12, the second group of first upper pads 150b may have the same or similar features as the embodiment of FIG. 8, except that the second group of first upper pads 150b are spaced from the top surface of the first substrate 110 by the thickness of the first connecting conductor 170, and the second group of second lower pads 250b are spaced from the second circuit layer 220 by the thickness of the second connecting conductor 270.

[0049] 13, unlike the embodiment of FIG. 12, the second width W2 of the first upper pads 150b of the second group may be greater than the first width W1 of the first upper pads 150a of the first group. The first buffer layer 160 may cover the sides of the first upper pads 150b of the second group as well as the first upper pads 150a of the first group. The first buffer layer 160 adjacent to the first upper pads 150a of the first group may mitigate the increased expansion of the first upper pads 150a of the first group caused by the first connecting conductor 170, and the first buffer layer 160 adjacent to the first upper pads 150b of the second group may mitigate the increased expansion of the first upper pads 150b of the second group having the second width W2. The widths of the buffer layer 160 covering the first upper pads 150a of the first group and the buffer layer 160 covering the second upper pads 150b of the second group may be the same or different from each other depending on the embodiment. For example, if the expansibility of the first upper pads 150a of the first group needs to be further reduced, the width of the buffer layer 160 in contact with the first upper pads 150a of the first group may be greater than the width of the buffer layer 160 in contact with the first upper pads 150b of the second group. The second buffer layer 260 of the second semiconductor chip 200 may have the same or similar characteristics as the first buffer layer 160 of the first semiconductor chip 100.

[0050] 14, the first semiconductor chip 100 may include a first buffer insulating layer 165 dividing the first insulating layer 140 into a first inner insulating layer 140_1 and a first outer insulating layer 140_2. The first inner insulating layer 140_1 may surround a side of the first connecting conductor 170 on the first substrate 110. The first buffer insulating layer 165 may be disposed on the first inner insulating layer 140_1 and the first connecting conductor 170, and may contact a side of the first upper pad 150a of the first group and a lower surface of the first upper pad 150b of the second group. The first upper pad 150a of the first group may include a first layer portion 150aL on the first buffer insulating layer 175 and an extension portion 150aV extending from the lower surface of the first layer portion 150aL and contacting the first connecting conductor 170 through the first buffer insulating layer 165. The first outer insulating layer 140_2 may surround the first layer portion 150aL on the first buffer insulating layer 165. Since the first layer portion 150aL is spaced apart from the first connecting conductor 170, the expansion of the first group of first upper pads 150a increased by the first connecting conductor 170 may be alleviated, and the reliability of bonding may be improved. The second semiconductor chip 200 may include a second connecting conductor 270 having similar properties to the first connecting conductor 170 and a second buffer insulating layer 265 having similar characteristics to the first buffer insulating layer 165. The second connecting conductor 270 may contact the upper surface of the first group of second lower pads 250a under the second circuit layer 220. The second inner insulating layer 240_1 may surround the side of the second lower pad 250a. The second buffer insulating layer 265 may surround the first group of second lower pads 250a under the second inner insulating layer 240_1 and contact the upper surfaces of the second group of second lower pads 250b. The second outer insulating layer 240_2 may surround the first group of second lower pads 250a and the second group of second lower pads 250b under the second buffer insulating layer 265.

[0051] 15, the first semiconductor chip 100 may further include a first buffer layer 160 covering the side surfaces of the first group of first upper pads 150a. As a result, even if the first width W1 of the first group of first upper pads 150a in contact with the first connecting conductor 170 is greater than the second width W2 of the second group of second upper pads 150b, the expansion of the first group of first upper pads 150a may be mitigated, improving bonding reliability. The second semiconductor chip 200 may include a second buffer layer 260, and a duplicated description will be omitted.

[0052] Figures 16a to 16c are perspective views and graphs showing experimental data for explaining modifications of Figures 14 and 15. Figures 16a to 16c will be described with reference to Figures 14 to 15.

[0053] FIG. 16a shows a conductive structure including a layer portion and an extension portion, and UBM1, UBM2, and LB in FIG. 16a can be understood as corresponding to each of the configurations in FIG. 14 to FIG. 15. UBM1 can be understood as corresponding to the first extension portion 150aV or the second extension portion 250aV, UBM2 can be understood as corresponding to the first layer portion 150aL or the second layer portion 250aL, and LB can be understood as corresponding to the first connection conductor 170 or the second connection conductor 270. FIG. 16b shows that as the thickness h of UBM1 gradually decreases from 2.8 μm to 0.5 μm, UBM2 expands more during heat treatment. Similarly, the graph in FIG. 16c shows the average expansion value of UBM2 due to temperature increase when the thickness of UBM1 is changed from 0.5 μm to 2.8 μm.

[0054] The UBM2 electrically connected to the LB has a larger expansion during the heat treatment for bonding. The expansion is reduced as the thickness of the UBM1 is larger, that is, the distance between the UBM2 and the LB is larger. For example, when the UBM1 is 0.5 μm thick during heat treatment at 300° C., the average expansion value of the UBM2 is between 220 Å and 240 Å, whereas the average expansion value of the UBM2 is between 160 Å and 180 Å when the UBM1 is 2.8 μm thick. Although the first upper pads 150a of the first group have a tendency to expand more during the heat treatment than the first upper pads 150b of the second group due to contact with the first connecting conductor 170, the expansion of the first layer portion 150aL can be reduced by ensuring a sufficient thickness of the first extension portion 150aV. 15, the first buffer layer 160 in contact with the first layer portion 150aL can further reduce the expansibility of the first layer portion 150aL, and the hybrid bonding by the heat treatment can be stably performed. The description of the overlapping first group second lower pad 150a, second connecting conductor 270, second buffer layer 260, etc. will be omitted.

[0055] Referring to FIG. 17, the first group of first upper pads 150a surrounded by the first buffer layer 160 may be dummy pads that are not electrically connected to other components. A first width W1 of the first group of first upper pads 150a that are dummy pads may be greater than a first width W2 of the second group of second upper pads 150b that are electrically connected to other components. The first buffer layer 160 may surround at least a portion of the side and lower surface of the first group of first upper pads 150a. The first buffer layer 160 may include an insulating material such as a polymer in addition to a conductive material such as a porous metal. The first group of second lower pads 250a surrounded by the second buffer layer 260 may have the same or similar characteristics as the first group of first upper pads 150a. The second buffer layer 260 may cover at least a portion of the side and top surfaces of the first group of second lower pads 250 a and may have the same or similar characteristics as the first buffer layer 160 .

[0056] 18, the first group of first upper pads 150a and the second group of first upper pads 150b may be dummy pads that are not electrically connected to other components. In an area not shown in the "A" area of ​​FIG. 18, a third group of pads may be present that electrically connect the first semiconductor chip 100 and the second semiconductor chip 200. In a direction perpendicular to the top surface of the first substrate 110 (e.g., Z direction), the first thickness H1 of the first group of first upper pads 150a may be greater than the second thickness H2 of the second group of second upper pads 150b. Even if the first width W1 of the first group of first upper pads 150a is substantially the same as the second width W2 of the second group of first upper pads 150b, the expansion of the first group of first upper pads 150a may be greater than the expansion of the second group of first upper pads 150b during bonding. The first buffer layer 160 surrounds at least a portion of the side and lower surface of the first group of first upper pads 150a and can reduce the expansibility of the first group of first upper pads 150a. The first group of second lower pads 150a, the second group of second lower pads 150b, and the second buffer layer 260 can have the same or similar characteristics as the first group of first upper pads 150a, the second group of first upper pads 150b, and the first buffer layer 150b, respectively.

[0057] Referring to Figure 19, a semiconductor package 10B of one embodiment may have the same or similar features as those described with reference to Figures 1 to 18, except that it includes multiple second semiconductor chips 200A, 200B, 200C, 200D stacked in a vertical direction (Z-axis direction) on a first semiconductor chip 100, and a molding member 290.

[0058] For example, the first semiconductor chip 100 may include a plurality of first upper pads 150, and the plurality of first upper pads 150 may include a first group of first upper pads 150a and a second group of first upper pads 150b described with reference to Figures 2a to 18. The plurality of second semiconductor chips 200A, 200B, 200C, and 200D may each include a plurality of second lower pads 250, and the plurality of second lower pads 250 may include a first group of second lower pads 250a and a second group of second lower pads 250b described with reference to Figures 2a to 18. The plurality of second semiconductor chips 200A, 200B, 200C, and 200D may each include a plurality of second upper pads 255 and a second upper insulating layer 245, which may have the same or similar features as the plurality of first upper pads 150 and the first insulating layer 140, respectively.

[0059] A bonding interface may be formed between the second semiconductor chips 200A, 200B, 200C, and 200D, in which the second lower insulating layer 240 and the second upper insulating layer 245, the second lower pads 250, and the second upper pads 255 are bonded to each other. The second semiconductor chips 200A, 200B, 200C, and 200D may be electrically connected to each other through the second lower pads 250 and the second upper pads 255. Among the second semiconductor chips 200A, 200B, 200C, and 200D, the bottom second semiconductor chip 200A may be electrically connected to the first semiconductor chip 100 through the second lower pads 250 and the first upper pads 150 of the first semiconductor chip 100, which are bonded to each other.

[0060] The second semiconductor chips 200A, 200B, 200C, and 200D may have the same or similar features as the second semiconductor chip 200 described with reference to FIGS. 1 to 18, except that the second semiconductor chips 200A, 200B, 200C, and 200D further include second through electrodes 230 for forming electrical connection paths between the second semiconductor chips 200A, 200B, 200C, and 200D. However, the second semiconductor chip 200D arranged at the top may not include the second through electrodes 230, and may have a relatively large thickness according to an embodiment. According to an embodiment, more or less semiconductor chips than those shown in the drawings may be stacked on the first semiconductor chip 100. For example, three or less or five or more semiconductor chips may be stacked on the first semiconductor chip 100.

[0061] As an example, the first semiconductor chip 100 may be a buffer chip or a control chip including a number of logic elements and / or memory elements. The first semiconductor chip 100 may transmit signals from the second semiconductor chips 200A, 200B, 200C, and 200D stacked thereon to the outside, and transmit signals and power from the outside to the second semiconductor chips 200A, 200B, 200C, and 200D. The second semiconductor chips 200A, 200B, 200C, and 200D may be memory chips including volatile memory elements such as DRAM and SRAM, or non-volatile memory elements such as PRAM, MRAM, FeRAM, or RRAM.

[0062] The molding member 290 is disposed on the first semiconductor chip 100 and can encapsulate at least a portion of each of the plurality of second semiconductor chips 200A, 200B, 200C, and 200D. The molding member 290 can be formed to expose an upper surface of the uppermost second semiconductor chip 200D. However, according to an embodiment, the molding member 290 can be formed to cover an upper surface of the uppermost second semiconductor chip 200D. The molding member 290 can include, for example, EMC (Epoxy Mold Compound), but the material of the molding member 290 is not particularly limited.

[0063] FIG. 20a is a plan view showing a semiconductor package according to one embodiment of the present invention, and FIG. 20b is a cross-sectional view showing a cut surface taken along line II-II' in FIG. 20a.

[0064] 20a and 20b, a semiconductor package 10C according to an embodiment may include a package substrate 600, an interposer substrate 700, and at least one package structure PS. The semiconductor package 10C may further include a logic chip (or a processor chip) 800 disposed adjacent to the package structure PS on the interposer substrate 700. The package structure PS may have the same or similar features as the semiconductor packages described with reference to FIGS. 1 to 18. The package structure PS is shown in the form of a semiconductor package 10B shown in FIG. 19, but is not limited thereto.

[0065] The package substrate 600 is a support substrate on which the interposer substrate 700, the logic chip 800, and the package structure PS are mounted, and may be a substrate for a semiconductor package including a printed circuit board (PCB), a ceramic substrate, a glass substrate, a tape wiring substrate, etc. The package substrate 600 may include a lower pad 612, an upper pad 611, and a wiring circuit 613 that electrically connects the lower pad 612 and the upper pad 611. The body of the package substrate 600 may include different materials depending on the type of substrate. For example, when the package substrate 600 is a printed circuit board, A wiring layer may be further laminated on a cross-section or both sides of the copper foil laminate. The upper pad 611, the lower pad 612, and the wiring circuit 613 may form an electrical path connecting the lower surface and the upper surface of the package substrate 600. External connection bumps 620 connected to the lower pads 612 may be disposed on the lower surface of the package substrate 600. The external connection bumps 620 may include, for example, solder balls.

[0066] The interposer substrate 700 may include a substrate 701, a lower protective layer 703, a lower pad 705, an interconnect structure 710, a conductive bump 720, and a through via 730. The package structure PS and the processor chip 800 may be stacked on the package substrate 600 via the interposer substrate 700. The interposer substrate 700 may electrically connect the package structure PS and the processor chip 800 to each other.

[0067] The substrate 701 may be formed of, for example, any one of a silicon, organic, plastic, and glass substrate. If the substrate 701 is a silicon substrate, the interposer substrate 700 may be called a silicon interposer. If the substrate 701 is an organic substrate, as opposed to what is shown in the figure, the interposer substrate 700 may be called a panel interposer.

[0068] A lower protective layer 703 may be disposed on the lower surface of the substrate 701, and a lower pad 705 may be disposed on the lower protective layer 703. The lower pad 705 may be connected to a through via 730. The package structure PS and the processor chip 800 may be electrically connected to the package substrate 600 through a conductive bump 720 disposed on the lower pad 705.

[0069] The interconnect structure 710 is disposed on the upper surface of the substrate 701 and may include an interlayer insulating layer 711 and a single-layer or multi-layer wiring structure 712. When the interconnect structure 710 is composed of a multi-layer wiring structure, wiring patterns of different layers may be connected to each other through contact vias. An upper pad 704 connected to the wiring structure 712 may be disposed on the interconnect structure 710. The package structure PS and the processor chip 800 may be connected to the upper pad 704 through connection bumps 139.

[0070] The through vias 730 may extend from the top surface of the substrate 701 to the bottom surface thereof, penetrating the substrate 701. As an example, the through vias 730 may extend into the interconnect structure 710 and be electrically connected to the wiring of the interconnect structure 710. When the substrate 701 is silicon, the through vias 730 may be referred to as TSVs.

[0071] The interposer substrate 700 may be used for converting or transmitting input electrical signals between the package substrate 600 and the package structure PS or the processor chip 800. Thus, the interposer substrate 700 may not include elements such as active elements or passive elements. According to an embodiment, the interconnect structure 710 may be disposed on the bottom of the substrate 701.

[0072] The conductive bumps 720 may be disposed on the lower surface of the interposer substrate 700 and electrically connected to the wiring of the interconnect structure 710. The interposer substrate 700 may be mounted on the package substrate 600 via the conductive bumps 720. As an example, some of the lower pads 705 used for power or ground may be integrated and connected to the conductive bumps 720, so that the number of the lower pads 705 may be greater than the number of the conductive bumps 720.

[0073] The logic chip or processor chip 800 may include, for example, a central processor (CPU), a graphics processor (GPU), a field programmable gate array (FPGA), a digital signal processor (DSP), a cryptographic processor, a microprocessor, a microcontroller, an analog-to-digital converter, an application specific semiconductor (ASIC), etc. Depending on the type of integrated circuit included inside the logic chip 800, the semiconductor package 10B may be referred to as a semiconductor package for a server, a semiconductor package for a mobile device, etc. According to an embodiment, the logic chip 800 and / or the package structure PS mounted on the interposer substrate 700 may be provided in a greater or lesser number than shown in the figure.

[0074] 21a to 21e are diagrams showing a manufacturing method for a portion of the first semiconductor chip 100 shown in FIG. 2a in the order of steps.

[0075] 21a, a plurality of recess regions RS1, RS2 having different widths may be formed in a first insulating layer 140 on a first substrate 110. The plurality of recess regions RS1, RS2 may be formed using a photosensitive material layer and a photolithography process. The width of the first recess region RS1 may be greater than the width of the second recess region RS2.

[0076] 21b, a preliminary first buffer layer 160' may be formed to cover the upper surface of the first insulating layer 140, the side surfaces of the first insulating layer 140 exposed by the recess regions RS1 and RS2, the upper surface of the first substrate 110, and the upper surface of the through electrode 130. The preliminary first buffer layer 160' may include a porous metal and may be formed using a plating process. The voids included in the porous metal of the preliminary first buffer layer 160' may be formed, for example, by forming a mixed metal of copper (Cu) and zinc (Zn) using a plating process and selectively etching only the zinc (Zn).

[0077] 21c, the first buffer layer 160' may be formed by removing the remaining portion of the preliminary first buffer layer 160' except for the portion formed in the first recess region RS1. The removal of the preliminary first buffer layer 160' may be performed using, for example, a photolithography process. After the first buffer layer 160' is formed, the first width W1 of the first recess region RS1 may be larger than the second width W2 of the second recess region RS2.

[0078] 21d, a preliminary first seed layer 153′ may be formed to cover the first insulating layer 140, the first buffer layer 160, the upper surface of the first substrate 110 exposed by the second recess region RS2, and the upper surface of the through electrode 130. The preliminary first seed layer 153′ may be formed using, for example, a plating process, a physical vapor deposition (PVD) process, or a chemical vapor deposition (CVD) process.

[0079] Referring to FIG. 21e, a preliminary first upper conductive layer 155' may be formed on the preliminary first seed layer 153'. The preliminary first upper conductive layer 155' may be formed by, for example, a plating process, a physical vapor deposition (PVD) process, or a chemical vapor deposition (CVD) process. Then, referring to FIG. 2a, the preliminary first upper conductive layer 155' and the preliminary first seed layer 153' that are at a level higher than the top surface of the first insulating layer 140 may be removed by a planarization process to form a plurality of first upper pads 150. The manufacturing process described with reference to FIGS. 21a to 21e may be similarly applied to the second insulating layer 240 and the plurality of second lower pads 250 of the second semiconductor chip 200.

[0080] In the following description of the manufacturing method, descriptions overlapping with those in FIGS. 21a to 21e will be omitted.

[0081] 22a to 22c are diagrams showing a manufacturing method for a portion of the first semiconductor chip 100 shown in FIG. 4 in the order of steps.

[0082] Referring to FIG. 22a, the first insulating layer 140 may be patterned to form a plurality of recess regions RS1 and RS2 to form a preliminary first buffer layer 160'. The preliminary first buffer layer 160' may include a polymer as well as a porous metal. When the preliminary first buffer layer 160' includes a polymer, the preliminary first buffer layer 160' may be formed using, for example, a physical vapor deposition (PVD) process or a chemical vapor deposition (CVD) process. When the preliminary first buffer layer 160' includes a porous metal, the preliminary first buffer layer 160' may be formed in a manner similar to the method described with reference to FIG. 21b.

[0083] Referring to FIG. 22b, the preliminary first buffer layer 160′ may be formed by removing the remaining portions except for the side portions of the first buffer layer 160 exposed by the first recess region RS1.

[0084] 22c, a preliminary first seed layer 153' may be formed to cover the first insulating layer 140, the first buffer layer 160, and the upper surface of the first substrate 110 exposed by the recess regions RS1 and RS2, and the upper surface of the through electrode 130. A preliminary first upper conductive layer 155' may be formed on the preliminary first seed layer 153'. Then, referring to FIG. 4, the preliminary first upper conductive layer 155' and the preliminary first seed layer 153' at a level higher than the upper surface of the first insulating layer 140 may be removed to form a plurality of first upper pads 150.

[0085] 23a to 23c are diagrams showing a manufacturing method for a partial configuration of first semiconductor chip 100 shown in FIG. 14 in the order of steps.

[0086] 23a, a first connecting conductor 170 in contact with the through electrode 130 and a first inner insulating layer 140_1 surrounding a side surface of the first connecting conductor 170 may be formed on a first substrate 110. Then, a first buffer insulating layer 165 may be formed on the first inner insulating layer 140_1, and a first outer insulating layer 140_2 may be formed on the first buffer insulating layer 165. The first buffer insulating layer 165 and the first outer insulating layer 140_2 may be formed using, for example, a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, or a spin coating process.

[0087] 23b, a first recess region RS1 may be formed by etching a portion of the first outer insulating layer 140_2 and the first buffer insulating layer 165 to expose a portion of an upper surface of the first connecting conductor 170. Then, a second recess region RS2 having a second width W2 substantially equal to the first width W1 of the first recess region RS1 may be formed.

[0088] 23c, a preliminary first seed layer 153' may be formed to cover the upper surface of the first outer insulating layer 140_2 and portions exposed by the plurality of recess regions RS1, RS2, and a preliminary first upper conductive layer 155' may be formed on the preliminary first seed layer 153'. Then, referring to FIG. 14, the preliminary first upper conductive layer 155' and the preliminary first seed layer 153' at a level higher than the upper surface of the first outer insulating layer 140_2 may be removed to form a plurality of first upper pads 150.

[0089] The present invention is not limited by the above-described embodiments and the accompanying drawings, but is limited by the scope of the accompanying claims. Therefore, various substitutions, modifications and changes can be made by a person having ordinary knowledge in the art without departing from the technical idea of ​​the present invention described in the claims, and these also belong to the scope of the present invention. [Explanation of symbols]

[0090] 100: First semiconductor chip 110: First substrate 120: 1st circuit layer 130:Through electrode 140: First insulating layer 150: A plurality of first upper pads 150a: First upper pad of the first group 150b: 1st upper pad of 2nd group 160: First buffer layer 165: First buffer insulating layer 200: Second semiconductor chip 210: Second substrate 220: 2nd circuit layer 240: Second insulating layer 250: Multiple secondary lower pads 250a: 2nd lower pad of 1st group 250b: Second lower pad of second group 260: Second buffer layer 265: Second buffer insulating layer

Claims

1. a first semiconductor chip including: a first substrate; a plurality of first upper pads disposed on the first substrate, the first upper pads including a first group and a second group; a first buffer layer surrounding side surfaces of the first upper pads of the first substrate; a first insulating layer surrounding side surfaces of the first upper pads of the second substrate and a side surface of the first buffer layer; and a plurality of through electrodes passing through the first substrate and connected to the plurality of first upper pads; a second semiconductor chip disposed on the first semiconductor chip, the second semiconductor chip including a second substrate, a plurality of second lower pads disposed under the second substrate, the second lower pads including a first group and a second group of second lower pads, a second buffer layer surrounding side surfaces of the second lower pads of the first group, and a second insulating layer surrounding side surfaces of the second lower pads of the second group and a side surface of the second buffer layer; the first upper pads of the first group contact the second lower pads of the first group; The first upper pads of the second group contact the second lower pads of the second group.

2. the first buffer layer includes a first material having a first Young's modulus that is less than a second Young's modulus of a second material included in the first plurality of upper pads; 2 . The semiconductor package of claim 1 , wherein the second buffer layer comprises a third material having a third Young's modulus less than a fourth Young's modulus of a fourth material included in the second plurality of lower pads.

3. 2. The semiconductor package of claim 1, wherein a first width of the first upper pads of the first group is greater than a second width of the first upper pads of the second group in a direction parallel to a top surface of the first semiconductor chip.

4. 2. The semiconductor package of claim 1, wherein a first thickness of the first upper pads of the first group is greater than a second thickness of the first upper pads of the second group in a direction perpendicular to a top surface of the first semiconductor chip.

5. The semiconductor package of claim 1 , further comprising a bonding film disposed between the first insulating layer and the second insulating layer.

6. 2. The semiconductor package of claim 1, further comprising a second connecting conductor contacting upper surfaces of the second lower pads of the first group below the second substrate.

7. a second buffer insulating layer dividing the second insulating layer into a second inner insulating layer and a second outer insulating layer; the second inner insulating layer surrounds a side surface of the second connecting conductor under the second substrate; the second buffer insulating layer contacts a side surface of the second lower pad of the first group and a top surface of the second lower pad of the second group under the second internal insulating layer and the second connecting conductor; 7. The semiconductor package of claim 6, wherein the second outer insulating layer surrounds sides of the second lower pads of the first group and sides of the second lower pads of the second group under the second buffer insulating layer.

8. 8. The semiconductor package of claim 7, wherein the second lower pads of the first group include a second layer portion below the second buffer insulating layer and a second extension portion extending from an upper surface of the second layer portion, penetrating the second buffer insulating layer, and contacting the second connecting conductor.

9. The semiconductor package of claim 8 , wherein the second extension portion has a width that decreases toward the second connection conductor.

10. 8. The semiconductor package of claim 7, wherein the second buffer insulating layer comprises at least one of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbonitride.

11. The semiconductor package of claim 6 , wherein the second connection conductor comprises at least one of aluminum (Al), copper (Cu), or an alloy thereof.

12. the first buffer layer comprises a polymer or a porous metal; The semiconductor package of claim 1 , wherein the second buffer layer comprises the polymer or the porous metal.

13. 2 . The semiconductor package of claim 1 , wherein the first insulating layer and the second insulating layer include at least one of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbonitride.

14. The semiconductor device includes a first semiconductor chip and a second semiconductor chip that are stacked vertically, The first semiconductor chip is a first upper conductive layer and a first upper seed layer surrounding a side surface and a bottom surface of the first upper conductive layer; a first buffer layer extending around and along some of the first upper pads of the plurality of first upper pads; a first insulating layer surrounding the remaining first upper pads of the plurality of first upper pads and the first buffer layer; The second semiconductor chip is a second lower conductive layer and a second lower seed layer surrounding a side surface and an upper surface of the second lower conductive layer, the second lower pads being electrically connected to the first upper pads; a second buffer layer extending around and along some of the second lower pads among the plurality of second lower pads; a second insulating layer surrounding the remaining second lower pads of the plurality of second lower pads and the second buffer layer; The first buffer layer and the second buffer layer comprise a polymer or a porous metal.

15. The semiconductor package of claim 14 , wherein the portion of the first upper pads directly contact the portion of the second lower pads.

16. the first upper conductive layer and the second lower conductive layer include copper (Cu); 15. The semiconductor package of claim 14, wherein the first upper seed layer and the second lower seed layer comprise at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN).

17. a first semiconductor chip including a plurality of upper pads; and a second semiconductor chip including a plurality of lower pads including a first group and a second group of lower pads in contact with upper surfaces of the plurality of upper pads, a connecting conductor in contact with upper surfaces of the first group of lower pads, an inner insulating layer surrounding side surfaces of the connecting conductor, a buffer insulating layer in contact with side surfaces of the first group of lower pads and upper surfaces of the second group of lower pads, and an outer insulating layer surrounding the side surfaces of the first group of lower pads and the side surfaces of the second group of lower pads under the buffer insulating layer, A semiconductor package, wherein the lower pads of the first group include a layer portion surrounded by the outer insulating layer and an extension portion extending from an upper surface of the layer portion, penetrating the buffer insulating layer, and contacting a lower surface of the connecting conductor.

18. 20. The semiconductor package of claim 17, wherein the buffer insulating layer comprises at least one of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbonitride.

19. The semiconductor package of claim 17 , further comprising a buffer layer covering the layer portion within the outer insulating layer.

20. 20. The semiconductor package of claim 19, wherein a thickness of the lower pads of the first group is greater than a thickness of the lower pads of the second group in a direction perpendicular to a lower surface of the connecting conductor.

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