Semiconductor device

Abstract

To provide a semiconductor device with good electric characteristics and stable electric characteristics.SOLUTION: A semiconductor device comprises: a first insulation layer; a second insulation layer; a third insulation layer; a fourth insulation layer; a semiconductor layer; and a first conductive layer. The second insulation layer is positioned on the first insulation layer, and an island-shaped semiconductor layer is positioned on the second insulation layer. The second insulation layer includes an island-shape having an end part on the side outward from a region overlapped with the semiconductor layer. The fourth insulation layer covers the second insulation layer, the semiconductor layer, the third insulation layer, and the first conductive layer, is contacted to one part of an upper surface of the semiconductor layer, and is contacted to the first insulation layer on the side outward from the end part of the second insulation layer. The semiconductor layer contains a metal oxide, the second and third insulation layers contain an oxide, the first insulation layer contains the metal oxide or nitride, and the fourth insulation layer contains a metal nitride.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] One embodiment of the present invention relates to a semiconductor device. One embodiment of the present invention relates to a display device. One embodiment relates to a method for manufacturing a semiconductor device or a display device.

[0002] Note that one embodiment of the present invention is not limited to the above technical fields. The technical field of one embodiment of the present invention is a semiconductor device, a display device, a light-emitting device, a power storage device, a storage device, and a , electronic device, lighting device, input device, input / output device, driving method thereof, or manufacturing method thereof A semiconductor device functions by utilizing the semiconductor properties. This refers to all devices that can do this. [Background technology]

[0003] Oxide semiconductors using metal oxides are attracting attention as semiconductor materials that can be used for transistors. For example, in Patent Document 1, a plurality of oxide semiconductor layers are stacked, and the plurality of oxide semiconductor layers are Among the oxide semiconductor layers, an oxide semiconductor layer serving as a channel contains indium and gallium, and By increasing the ratio of indium to that of gallium, the field effect mobility (simply called the mobility A semiconductor device having improved mobility, or μFE, is disclosed.

[0004] Metal oxides that can be used for the semiconductor layer can be formed by using a sputtering method or the like. Therefore, it can be used for the semiconductor layer of a transistor that constitutes a large display device. The company plans to improve some of its production facilities for transistors using polycrystalline silicon and amorphous silicon. In addition, it is possible to reduce capital investment by using metal oxides. The transistor has a higher field effect mobility than amorphous silicon, so it can be driven A highly functional display device having a circuit can be realized.

[0005] In addition, Patent Document 2 discloses that aluminum, boron, and gallium are added to the source and drain regions. The group consisting of lithium, indium, titanium, silicon, germanium, tin, and lead. An oxide semiconductor film having a low-resistance region containing at least one of these as a dopant is used. A thin film transistor having the same structure is disclosed. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] JP 2014-7399 A [Patent Document 2] JP 2011-228622 A Summary of the Invention [Problem to be solved by the invention]

[0007] An object of one embodiment of the present invention is to provide a semiconductor device with favorable electrical characteristics. Another object of the present invention is to provide a semiconductor device having stable electrical characteristics. An object of one embodiment of the present invention is to provide a highly reliable display device.

[0008] The description of these problems does not preclude the existence of other problems. It is not necessary for one embodiment to solve all of these problems. The subject matter can be extracted from descriptions in the specification, drawings, claims, etc. [Means for solving the problem]

[0009] One aspect of the present invention is a semiconductor device comprising a first insulating layer, a second insulating layer, a third insulating layer, and a fourth insulating layer. The semiconductor device has a first insulating layer, a semiconductor layer, and a first conductive layer. The semiconductor layer is located on the second insulating layer and has an island shape. The third insulating layer and the first conductive layer are stacked on the semiconductor layer. The second insulating layer is The fourth insulating layer has an island shape having an end portion on the outer side of the region overlapping with the semiconductor layer. A second insulating layer, a semiconductor layer, a third insulating layer, and a first conductive layer are covered, and a second insulating layer is formed on the semiconductor layer. The second insulating layer is in contact with a portion of the surface and is in contact with the first insulating layer outside the end portion of the second insulating layer. The semiconductor layer includes a metal oxide, the second insulating layer and the third insulating layer include an oxide, and the first insulating layer includes a metal oxide. The edge layer comprises a metal oxide or nitride, and the fourth insulating layer comprises a metal nitride.

[0010] In the above, the fourth insulating layer preferably contains aluminum.

[0011] In the above, the first insulating layer is made of at least one of aluminum and hafnium. and oxygen.

[0012] In the above, the second insulating layer and the semiconductor layer may have substantially the same top surface shape. preferable.

[0013] In the above, the second insulating layer has an end portion outside the area where the end portion overlaps with the first conductive layer. It is preferred that the moiety be located at

[0014] In the above, the second insulating layer is located in a region where an end portion overlaps with the first conductive layer. It is preferred to have a moiety.

[0015] In the above, a second conductive layer is provided below the first insulating layer, and the second conductive layer is It is preferable that the second conductive layer has a region overlapping both the semiconductor layer and the first conductive layer.

[0016] In the above, the second insulating layer is formed outside a region where an end portion of the second insulating layer overlaps with the second conductive layer. Alternatively, the second insulating layer preferably has a portion located on the second side. It is preferable that the conductive layer has a portion located in an area overlapping the conductive layer. Effect of the Invention

[0017] According to one embodiment of the present invention, a semiconductor device having favorable electrical characteristics can be provided. It is possible to provide a semiconductor device having stable properties, or a display device having high reliability.

[0018] The description of these effects does not preclude the existence of other effects. An embodiment does not necessarily have to have all of these effects. can be extracted from descriptions in the specification, drawings, claims, etc. [Brief description of the drawings]

[0019] [Figure 1] An example of a transistor configuration. [Diagram 2] An example of a transistor configuration. [Diagram 3] An example of a transistor configuration. [Figure 4] An example of a transistor configuration. [Diagram 5] An example of a transistor configuration. [Figure 6] An example of pixel configuration. [Figure 7] 1A to 1C illustrate a method for manufacturing a transistor. [Figure 8] 1A to 1C illustrate a method for manufacturing a transistor. [Figure 9]1A to 1C illustrate a method for manufacturing a transistor. [Figure 10] FIG. [Figure 11] FIG. [Figure 12] FIG. [Figure 13] FIG. [Figure 14] FIG. [Figure 15] FIG. [Figure 16] 1A and 1B are a block diagram and a circuit diagram of a display device. [Figure 17] FIG. [Figure 18] 1 shows an example of a display module configuration. [Figure 19] Example of electronic device configuration. [Figure 20] Example of electronic device configuration. [Figure 21] Example of electronic device configuration. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0020] Hereinafter, the embodiments will be described with reference to the drawings. The present invention may be embodied in various different forms without departing from its spirit and scope. It will be readily understood by those skilled in the art that various modifications and changes may be made to the embodiments and details of the present invention. However, the present invention should not be construed as being limited to the description of the following embodiments.

[0021] In addition, in each figure described in this specification, the size, layer thickness, or area of ​​each component is May be exaggerated for clarity.

[0022] In addition, the ordinal numbers "first," "second," and "third" used in this specification refer to the components of the This is added to avoid confusion and is not intended to limit the number.

[0023] In addition, in this specification, the words "above" and "below" indicating the position of the components are used. The positional relationship is used for convenience in describing the drawings. The relationship changes depending on the direction in which each component is depicted. The above words and phrases are not limited to those used above, but can be rephrased appropriately depending on the situation.

[0024] In this specification, the functions of the source and drain of a transistor are different. When using polarity transistors, or when the direction of current changes during circuit operation, etc. For this reason, the terms source and drain are often used interchangeably. It is possible to do so.

[0025] In addition, in this specification, "electrically connected" means "something that has some kind of electrical effect." This includes cases where the device is connected via a "device having some electrical function." "of" is not subject to any particular restrictions as long as it enables the transmission and reception of electrical signals between connected objects. For example, "something that has an electrical effect" includes electrodes, wiring, and transistors. These devices have various functions such as switching elements, resistor elements, inductors, capacitors, etc. This includes elements such as:

[0026] In addition, in this specification and the like, the terms "film" and "layer" are interchangeable. For example, the terms "conductive layer" and "insulating layer" can be interchanged with "conductive film" and The term "insulating film" may sometimes be used interchangeably.

[0027] In this specification and the like, unless otherwise specified, the off-state current refers to the current that occurs when a transistor is off. This refers to the drain current when the device is in a non-conducting state (also called a cut-off state). Unless otherwise specified, for n-channel transistors, V is the voltage between the gate and source gs is lower than the threshold voltage Vth (for p-channel transistors, Vth is higher (i) This refers to a state of being.

[0028] In this specification, a display panel, which is one aspect of a display device, displays (outputs) images on a display surface. Therefore, the display panel is one aspect of an output device.

[0029] In the present specification, the substrate of the display panel is provided with, for example, an FPC (Flexible Printed Circuit). inted Circuit) or TCP (Tape Carrier Packa ge) or other connectors attached to the board, or COG (Chip On Gauge) Display module is a device that has ICs mounted using a method such as display glass. It may be called a display panel, a display unit, or simply a display panel.

[0030] In this specification and the like, a touch panel, which is one aspect of a display device, is a device for displaying images, etc. on a display surface. The function of displaying information and detecting when a detectable object such as a finger or stylus touches, presses, or approaches the display surface. The touch panel also functions as a touch sensor that detects the touch of the touch panel. A card is one form of input / output device.

[0031] The touch panel is, for example, a display panel (or display device) with a touch sensor, A touch panel can also be called a display panel (or display device) with touch function. A display panel and a touch sensor panel may be used. It may also be configured to have a touch sensor function inside or on its surface.

[0032] In addition, in this specification, a touch panel substrate on which a connector or IC is mounted is referred to as a touch panel. It may be called a touch panel module, a display module, or simply a touch panel. be.

[0033] (Embodiment 1) In this embodiment, a semiconductor device, a display device, and a manufacturing method thereof according to one embodiment of the present invention will be described. He explains.

[0034] One embodiment of the present invention is a semiconductor layer in which a channel is formed on a formation surface, and a gate insulating film on the semiconductor layer. A transistor having a gate insulating layer (also called a third insulating layer) and a gate electrode on the gate insulating layer. The semiconductor layer is a metal oxide (hereinafter referred to as an oxide semiconductor) that exhibits semiconductor properties. It is preferable that the composition includes (c).

[0035] It is preferable that the gate electrode and the gate insulating layer have substantially the same top surface shape. In other words, the gate electrode and the gate insulating layer are processed so that their sides are continuous. For example, it is preferable to laminate an insulating film that will be a gate insulating layer and a conductive film that will be a gate electrode. After that, the same etching mask is used to continue the processing. Alternatively, the gate electrode processed previously can be used as a hard mask to process the insulating film. An insulating layer may be formed.

[0036] The semiconductor layer includes a channel forming region where a channel can be formed, a source region, and a drain region. The channel formation region is a pair of low resistance regions which function as an in-region. The low resistance region is a region that overlaps with the gate electrode. It is a certain area.

[0037] An insulating layer containing a metal nitride (also called a fourth insulating layer) is formed on the surface of the low resistance region of the semiconductor layer. By providing an insulating layer containing a metal nitride in contact with the semiconductor layer, a low resistance The insulating film containing the metal nitride in contact with the semiconductor layer has an effect of increasing the electrical conductivity of the region. It is preferable to perform heat treatment in this state, since this promotes a further reduction in resistance.

[0038] It is particularly preferable that the metal nitride contains aluminum. For example, aluminum The sputtering was carried out by reactive sputtering using a nitrogen-containing gas as the deposition gas. The aluminum nitride film formed by the deposition method is By properly controlling the flow rate, it has extremely high insulation and extremely high blocking properties against hydrogen and oxygen. Therefore, it is possible to obtain a film that has both anti-reflection and anti-static properties. By providing an insulating film, including a gate insulating film, in contact with the semiconductor layer, the resistance of the semiconductor layer can be reduced, and the semiconductor layer can be made It is possible to effectively prevent oxygen from being released from the conductor layer and hydrogen from diffusing into the semiconductor layer. can.

[0039] When aluminum nitride is used as the metal nitride, the insulating material containing the aluminum nitride It is preferable that the thickness of the film is 5 nm or more. Even with such a thin film, hydrogen and oxygen This allows the compound to have both high blocking properties against elements and a function of reducing the resistance of the semiconductor layer. The thickness of the insulating layer may be any thickness, but in consideration of productivity, it is preferably 500 nm or less. It is preferable that the thickness is 200 nm or less, and more preferably 50 nm or less.

[0040] In addition, an insulating layer (also referred to as a second insulating layer) containing oxide is provided in contact with the lower surface of the semiconductor layer. By providing a second insulating layer containing an oxide in contact with the semiconductor layer, Oxygen released by heating is effectively supplied to the semiconductor layer, compensating for oxygen deficiencies in the semiconductor layer. It is possible.

[0041] In one embodiment of the present invention, the second insulating layer has an island shape. Under the edge layer, there is an insulating layer (called the first insulating layer) that has high blocking properties against water, hydrogen, and oxygen. Furthermore, the upper surface and the side surface of the end of the second insulating layer contain the metal nitride. The insulating layer (fourth insulating layer) is configured to cover the insulating layer. In the region on the side of the first insulating layer, the first insulating layer and the fourth insulating layer are in contact with each other, so that the second insulating layer and The semiconductor layer and the like may be surrounded (sealed) by the first insulating layer and the fourth insulating layer. This effectively prevents oxygen from being released from the second insulating layer to the outside. Therefore, most of the oxygen can be supplied to the semiconductor layer.

[0042] If an extremely excessive amount of oxygen is supplied to the semiconductor layer, it may adversely affect the transistor characteristics. However, in this configuration, the area of ​​the second insulating layer processed into an island shape is changed. By doing so, it becomes possible to control the amount of oxygen that can be supplied to the semiconductor layer. is the amount of oxygen that the second insulating layer can release, the area of ​​the semiconductor layer that overlaps the second insulating layer, or It is possible to appropriately design the second insulating layer depending on the thickness and the like.

[0043] By adopting the above-mentioned configuration, a semiconductor device having excellent electrical characteristics and high reliability can be realized. This can be done.

[0044] A more specific example will be described below with reference to the drawings.

[0045] [Configuration example 1] FIG. 1A is a top view of a transistor 100, and FIG. 1B is a top view of the transistor 100 shown in FIG. FIG. 1C is a cross-sectional view taken along the dashed line A1-A2 shown in FIG. It corresponds to a cross-sectional view taken along the dashed line B1-B2. Some of the components of the transistor 100 (such as a gate insulating layer) are omitted in the figure. The dashed line A1-A2 direction is the channel length direction, and the dashed line B1-B2 direction is the channel width direction. In addition, the top view of a transistor may be referred to as a As in 1(A), some of the components may be omitted in the illustration.

[0046] The transistor 100 is provided on a substrate 102, an insulating layer 103, an insulating layer 104, a semiconductor 1. Conductive layer 108, insulating layer 110, metal oxide layer 114, conductive layer 112, insulating layer 116, insulating layer The insulating layer 104 is provided on the insulating layer 103, and the semiconductor layer 108 is provided on the insulating layer The insulating layer 110, the metal oxide layer 114, and the conductive layer 112 are provided on the The insulating layer 116 is laminated on the upper and side surfaces of the insulating layer 104. , the top and side surfaces of the semiconductor layer 108, the side surfaces of the insulating layer 110, the side surfaces of the metal oxide layer 114, and The insulating layer 118 is provided to cover the upper and side surfaces of the insulating layer 116 and the conductive layer 112. It is installed covering the.

[0047] A portion of the conductive layer 112 functions as a gate electrode. A portion of the insulating layer 110 functions as a gate insulator. The transistor 100 includes a gate electrode provided on the semiconductor layer 108. This is a so-called top-gate transistor.

[0048] The semiconductor layer 108 preferably comprises a metal oxide.

[0049] For example, the semiconductor layer 108 may be made of indium and M (where M is gallium, aluminum, or silicon). Boron, Yttrium, Tin, Copper, Vanadium, Beryllium, Titanium, Iron, Nickel , Germanium, Zirconium, Molybdenum, Lanthanum, Cerium, Neodymium, Hafnium one or more selected from the group consisting of aluminum, tantalum, tungsten, and magnesium; and zinc. In particular, M is aluminum, gallium, yttrium, or Tin is preferred.

[0050] In particular, the semiconductor layer 108 is made of an oxide containing indium, gallium, and zinc. It is preferred.

[0051] The semiconductor layer 108 may be a layer having a different composition, a layer having a different crystallinity, or a layer having a different impurity concentration. Alternatively, a laminate structure in which different layers are laminated may be used.

[0052] The semiconductor layer 108 has a region overlapping with the conductive layer 112 and a low-resistance region 10 The region 108n is provided with an insulating layer 116 in contact therewith. The region of 08 overlapping with the conductive layer 112 is used as a channel formation region of the transistor 100. On the other hand, region 108n functions as a source region or a drain region of transistor 100. It functions as:

[0053] As shown in FIGS. 1A and 1B, the transistor 100 is formed on an insulating layer 118. The conductive layer 120a and the conductive layer 120b may be included. The conductive layer 120a and the conductive layer 120b function as a source electrode or a drain electrode. are the openings 141a and 141b provided in the insulating layer 118 and the insulating layer 116, respectively. It is electrically connected to region 108n via 41b.

[0054] The conductive layer 112, the metal oxide layer 114, and the insulating layer 110 have top surface shapes that are generally aligned with each other. is doing.

[0055] In this specification, the term "approximately coincident upper surface shapes" means that there is at least a slight difference between the layers. For example, the upper and lower layers have the same mask pattern. This includes cases where the entire surface is processed using the same mask pattern, or where a part of the surface is processed using the same mask pattern. The shells do not overlap, and the upper layer is located inside the lower layer, or the upper layer is located outside the lower layer. In this case too, it is said that "the top surface shapes roughly match."

[0056] The metal oxide layer 114 located between the insulating layer 110 and the conductive layer 112 is It functions as a barrier film that prevents oxygen contained in the metal oxide from diffusing to the conductive layer 112 side. Layer 114 is preferably made of a material that is at least less permeable to oxygen than insulating layer 110. can be done.

[0057] The metal oxide layer 114 makes it easier for the conductive layer 112 to absorb oxygen, such as aluminum or copper. Even when a thin metal is used, oxygen is prevented from diffusing from the insulating layer 110 to the conductive layer 112. Even if the conductive layer 112 contains hydrogen, the conductive layer 112 can be prevented from The supply of hydrogen to the semiconductor layer 108 through the insulating layer 110 is suppressed. As a result, The carrier density in the channel formation region of the semiconductor layer 108 can be made extremely low. .

[0058] The metal oxide layer 114 can be made of an insulating material or a conductive material. If the metal oxide layer 114 has insulating properties, it functions as a part of the gate insulating layer. If the metal oxide layer 114 is conductive, it functions as a part of the gate electrode.

[0059] In particular, the metal oxide layer 114 is made of an insulating material having a higher dielectric constant than silicon oxide. In particular, an aluminum oxide film, a hafnium oxide film, or a hafnium a It is preferable to use a laminate film or the like.

[0060] The metal oxide layer 114 is preferably formed using a sputtering apparatus. For example, when an aluminum oxide film is formed using a sputtering apparatus, the atmosphere is preferably oxygen gas. By forming the insulating layer 110 and the semiconductor layer 108 under atmospheric conditions, oxygen can be suitably added to the insulating layer 110 and the semiconductor layer 108. In addition, when an aluminum oxide film is formed using a sputtering device, the film is highly dense. This is preferable because it can increase the degree of adhesion.

[0061] The insulating layer 116 can be an insulating film containing a metal nitride. Metallic elements such as aluminum, titanium, tantalum, tungsten, chromium, and ruthenium It is preferable that the film contains at least one of the above and nitrogen. In particular, the film contains aluminum and nitrogen. is preferably used since it has extremely high insulating properties.

[0062] When an aluminum nitride film is used for the insulating layer 116, the composition formula is AlN x (x is greater than 0 A membrane is used that satisfies the following: x is a real number less than or equal to 2, preferably, x is a real number greater than 0.5 and less than or equal to 1.5. This makes it possible to obtain a film having excellent insulating properties and excellent thermal conductivity. Therefore, it is possible to improve the dissipation of heat generated when the transistor 100 is driven. do.

[0063] Alternatively, an aluminum titanium nitride film, a titanium nitride film, or the like is used as the insulating layer 116. It is possible.

[0064] The region 108n is a part of the semiconductor layer 108 and has a lower resistance than the channel formation region. It is.

[0065] Here, when a metal oxide film containing indium is used as the semiconductor layer 108, the region 1 In the vicinity of the interface of the insulating layer 116 of the 08n, there is a region where metallic indium is precipitated or In some cases, regions with high silicide concentrations are formed. Such regions can be detected by, for example, X-ray photoelectron Spectroscopy (XPS: X-ray Photoelectron Spectroscopy) ) may be observed using analytical methods such as

[0066] The region 108n has a higher carrier density than the channel formation region, and a lower oxygen vacancy density than the channel formation region. These regions can also be referred to as regions with high n-type charge.

[0067] In addition, the insulating layer 104 and the insulating layer 110 in contact with the channel formation region of the semiconductor layer 108 are It is preferable to use an oxide film. For example, a silicon oxide film, a silicon oxynitride film, an oxide An oxide film such as an aluminum film can be used. The oxide desorbed from the insulating layer 104 or the insulating layer 110 due to heat treatment in the manufacturing process. The oxygen vacancies in the semiconductor layer 108 are reduced by supplying oxygen to the channel formation region of the semiconductor layer 108. It is possible.

[0068] The insulating layer 103 provided below the insulating layer 104 (on the substrate 102 side) is made of oxygen and It is preferable to use an insulating film that is difficult to diffuse hydrogen. It is preferable to use a metal oxide film such as a hafnium film or a hafnium aluminate film. I wish.

[0069] The aluminum oxide film, the hafnium oxide film, the hafnium aluminate film, etc. have a thickness of Even if it is thin, it has extremely high barrier properties. Therefore, the thickness is set to 0.5 nm or more and 50 nm or less. m or less, preferably 1 nm or more and 40 nm or less, and more preferably 2 nm or more and 30 nm or less. In particular, the aluminum oxide film has a high barrier property against hydrogen and the like. Therefore, even if it is extremely thin (for example, 0.5 nm to 1.5 nm), sufficient effect can be obtained. Such films can be formed, for example, by sputtering or atomic layer deposition (ALD). It can be formed by a film formation method such as the Omic Layer Deposition method. Cut.

[0070] Here, the semiconductor layer 108 and the insulating layer 104 are each processed into an island shape. In A), the outline of the insulating layer 104 is indicated by a dashed line. The insulating layer 104 is formed so as to at least include the semiconductor layer 108. The end of the semiconductor layer 108 is processed so as to be located outside the region where the semiconductor layer 108 overlaps. As will be described later, the semiconductor layer 108 and the insulating layer 104 are formed using the same etching mask. In that case, the semiconductor layer 108 and the insulating layer 104 may be formed on the upper surface thereof. The shapes are roughly the same.

[0071] As shown in FIGS. 1B and 1C, in the region outside the end of the insulating layer 104, Thus, the insulating layer 103 and the insulating layer 116 are provided in contact with each other. and insulating layer 104, etc. can be sealed with insulating layer 103 and insulating layer 116. With this structure, the semiconductor layer 108 and the insulating layer 104 of the transistor 100 can be Hydrogen diffuses from the outside, and oxygen in the semiconductor layer 108 and the insulating layer 104 diffuses to the outside. Therefore, the dispersion of the particles can be effectively suppressed.

[0072] In addition, the insulating layer 118 may contain hydrogen, but the oxide layer in contact with the semiconductor layer 108 may contain hydrogen. The insulating layer 104 and the insulating layer 110, which include a film, are not in contact with the insulating layer 118 due to the insulating layer 116. Therefore, even if hydrogen is contained in the insulating layer 118, The hydrogen is absorbed into the insulating layer 104 and the insulating film 105 by heat or the like applied during the manufacturing process of the transistor 100. Diffusion into the semiconductor layer 108 through the edge layer 110 can be effectively prevented.

[0073] Here, the semiconductor layer 108 and oxygen vacancies that may be formed in the semiconductor layer 108 will be described. Do the following.

[0074] The oxygen vacancies formed in the semiconductor layer 108 are problematic because they affect the transistor characteristics. For example, when oxygen vacancies are formed in the semiconductor layer 108, hydrogen bonds to the oxygen vacancies. When a carrier source is generated in the semiconductor layer 108, This causes a change in the electrical characteristics of the transistor 100, typically a shift in the threshold voltage. In addition, it is preferable that the semiconductor layer 108 have fewer oxygen vacancies.

[0075] Therefore, in one aspect of the present invention, the insulating film near the semiconductor layer 108, specifically, the semiconductor The insulating layer 110 above the dielectric layer 108 and the insulating layer 104 below are made of oxide. The insulating layer 104 and the insulating layer 110 are formed by heat or the like applied during the manufacturing process. By transferring oxygen from the semiconductor layer 108 to the semiconductor layer 108, oxygen vacancies in the semiconductor layer 108 can be reduced. This makes it possible.

[0076] In addition, the semiconductor layer 108 preferably has a region in which the atomic ratio of In is greater than the atomic ratio of M. The higher the atomic ratio of In, the more the field effect mobility of the transistor can be improved. Cut.

[0077] In the case of metal oxides containing In, Ga, and Zn, the bonding strength between In and oxygen is greater than that between Ga and oxygen. Since the bonding strength is weaker than that of the element, when the atomic ratio of In is large, oxygen deficiency occurs in the metal oxide film. The same problem occurs when the metal element M is used instead of Ga. If there are many oxygen vacancies in the metal oxide film, the electrical characteristics of the transistor tend to deteriorate. This can result in degradation and reduced reliability.

[0078] However, in one embodiment of the present invention, the semiconductor layer 108 containing a metal oxide contains a very large amount of Since oxygen can be supplied, it is possible to use metal oxide materials with a high In atomic ratio. This allows the device to have extremely high field-effect mobility, stable electrical characteristics, and high reliability. It is possible to realize a transistor having such a structure.

[0079] For example, the atomic ratio of In is 1.5 times or more, or 2 times or more, or Preferably, the metal oxide has a concentration of 1000 or more times the surface area of ​​the metal oxide, 3 times or more, 3.5 times or more, or 4 times or more. It is possible.

[0080] In particular, the atomic ratio of In, M, and Zn in the semiconductor layer 108 is In:M:Zn=5:1. : 6 or close thereto (when In is 5, M is 0.5 or more and 1.5 or less, and Zn is 5 or more, including 7 or less). Alternatively, the ratio of the numbers of In, M, and Zn atoms is It is preferable that the composition ratio of In:M:Zn is 4:2:3 or in the vicinity thereof. As for the composition, the ratio of the number of In, M, and Zn atoms in the semiconductor layer 108 may be approximately equal. That is, the ratio of the numbers of In, M, and Zn atoms is In:M:Zn=1:1:1 or It may also include nearby materials.

[0081] For example, the above-mentioned high field effect mobility transistor is used as a gate driver for generating a gate signal. By using this in a driver, it is possible to provide a display device with a narrow frame width (also called a narrow frame). In addition, the above-mentioned high field effect mobility transistor is used as a source driver (especially the source It can be used for a demultiplexer connected to the output terminal of a shift register of a driver. As a result, it is possible to provide a display device having a small number of wires connected to the display device.

[0082] Even if the semiconductor layer 108 has a region in which the atomic ratio of In is greater than the atomic ratio of M, However, when the crystallinity of the semiconductor layer 108 is high, the field effect mobility may be reduced. The crystallinity of 108 can be measured, for example, by X-ray diffraction (XRD). Analyze using a transmission electron microscope (TEM) or This can be analyzed using a 3D electron microscope.

[0083] Here, impurities such as hydrogen or moisture that are mixed into the semiconductor layer 108 may affect the transistor characteristics. Therefore, in the semiconductor layer 108, hydrogen or water The fewer the impurities such as fluorine, the better. By using a thin film, a transistor having excellent electrical characteristics can be fabricated. The low impurity concentration and low defect level density (reduced oxygen vacancies) allow the The carrier density can be reduced. The electrical characteristics of a transistor are such that the threshold voltage is negative (also called normally-on). In addition, a transistor using such a metal oxide film has a significantly low off-state current. Therefore, extremely small characteristics can be obtained.

[0084] The semiconductor layer 108 may have a stacked structure of two or more layers.

[0085] For example, the semiconductor layer 108 may be formed by stacking two or more metal oxide films having different compositions. For example, when In-Ga-Zn oxide is used, the atomic numbers of In, M, and Zn are The ratio of In:M:Zn=5:1:6, In:M:Zn=4:2:3, In:M:Zn= 1:1:1, In:M:Zn=2:2:1, In:M:Zn=1:3:4, In:M:Z The pore size of the film formed with a sputtering target having n=1:3:2 or a value close to that range It is preferable to use two or more layers in a laminate.

[0086] In addition, the semiconductor layer 108 may be formed by stacking two or more metal oxide films having different crystallinity. In this case, the same oxide target can be used, but the deposition conditions can be changed to reduce the exposure to air. It is preferable that they are formed continuously and without touching.

[0087] For example, the oxygen flow rate during deposition of the first metal oxide film is set to be equal to or lower than the oxygen flow rate during deposition of the second metal oxide film. The oxygen flow rate ratio is set to be smaller than that during deposition of the first metal oxide film. During the film formation, oxygen is not allowed to flow. This prevents oxygen from being introduced during the formation of the second metal oxide film. In addition, the first metal oxide film is more effective in supplying the element than the second metal oxide film. The film has lower crystallinity and higher electrical conductivity than the first film. The second metal oxide film is made to have higher crystallinity than the first metal oxide film, so that the semiconductor layer 1 Damage during processing of 08 and during deposition of the insulating layer 110 can be suppressed.

[0088] More specifically, the oxygen flow rate ratio during the formation of the first metal oxide film is set to 0% or more and less than 50%. Preferably, it is 0% or more and 30% or less, more preferably, it is 0% or more and 20% or less, typically, it is 10%. The oxygen flow rate during the formation of the second metal oxide film is set to 50% or more and 100% or less. Preferably, the ratio is 60% or more and 100% or less, more preferably, 80% or more and 100% or less, and even more preferably, The ratio is preferably 90% or more and 100% or less, and typically 100%. The first and second metal oxide films may be formed under different conditions such as pressure, temperature, and power. By keeping all other conditions the same except for the oxygen flow rate, the time required for the film formation process can be shortened. This is preferable.

[0089] By adopting such a configuration, the transistor 100 has excellent electrical characteristics and high reliability. This can be achieved.

[0090] The above is a description of configuration example 1.

[0091] [Variation 1] A modification of the above configuration example 1 will be described below.

[0092] [Variation 1-1] In FIGS. 2A and 2B, the insulating layer 104 and the semiconductor layer 108 are etched using the same etching mask. In other words, the insulating layer 104 and the semiconductor layer 105 are processed into islands. It can be said that the top surface shape of the insulating layer 104 is roughly the same as that of the insulating layer 104. It can also be said that the side surfaces of the semiconductor layer 108 at the respective ends are continuous. Cut.

[0093] With this configuration, the step of processing the insulating layer 104 can be omitted. This makes it possible to improve yields and reduce manufacturing costs.

[0094] [Variation 1-2] FIG. 2C shows a state where the end of the insulating layer 104 is located outside the semiconductor layer 108 and is conductive. The insulating layer 110 is formed on the insulating layer 112. The insulating layer 110 is formed on the insulating layer 112. The insulating layer 110 is formed on the insulating layer 110. This is an example of the case where the insulating layer 104 is processed. FIG. 2(C) shows a cross section in the channel width direction. is.

[0095] In the modified example 1-1 and the modified example 1-2, the area of ​​the insulating layer 104 is smaller than that of the above-mentioned configuration example 1. In this way, by changing the pattern and the method of forming the insulating layer 104, This makes it possible to optimize the amount of oxygen supplied from the insulating layer 104 to the semiconductor layer 108.

[0096] The above is the explanation of the first modification example.

[0097] [Configuration example 2] Hereinafter, a configuration example of a transistor having a partly different configuration from the above configuration example 1 will be described. In the following, explanations of parts that overlap with the above-mentioned configuration example 1 may be omitted. In the drawings shown below, parts having the same functions as the above configuration example are shown with hatched patterns. In some cases, the lines are the same and no code is added.

[0098] FIG. 3A is a top view of a transistor 100A, and FIG. 3B is a top view of a transistor 100B. 3(C) is a cross-sectional view of the channel length direction of transistor 100A, and FIG. 3(D) is a cross-sectional view of the channel width direction of transistor 100A. 4 is a cross-sectional view in the direction.

[0099] The transistor 100A has a conductive layer 106 between the substrate 102 and the insulating layer 103. The main difference from the configuration example 1 is that the conductive layer 106 is formed by interposing the insulating layer 104 and the insulating layer 103. The conductive layer 112 and the semiconductor layer 108 overlap each other.

[0100] In the transistor 100A, the conductive layer 106 is a first gate electrode (bottom gate electrode). The conductive layer 112 functions as a second gate electrode (also called a top gate electrode). In addition, a part of the insulating layer 103 and the insulating layer 104 functions as a first electrode. A portion of the insulating layer 110 serves as the first gate insulating layer, and a portion of the insulating layer 110 serves as the second gate insulating layer. do.

[0101] A portion of the semiconductor layer 108 overlapping with at least one of the conductive layer 112 and the conductive layer 106 In the following description, for ease of explanation, the semiconductor layer 1 The portion of the conductive layer 112 of the insulating film 08 that overlaps with the conductive layer 112 is sometimes called a channel formation region. In the portion that does not overlap with the conductive layer 112 but overlaps with the conductive layer 106 (portion including the region 108n), Channels may form.

[0102] As shown in FIG. 3C, the conductive layer 106 includes a metal oxide layer 114 and an insulating layer 110. The conductive layer 112 and the insulating layer 103 are electrically connected to each other through an opening 142 provided in the insulating layer 104 and the insulating layer 103. In this way, the conductive layer 106 and the conductive layer 112 are electrically connected to each other. can be given.

[0103] The conductive layer 106 may be made of the same material as the conductive layer 112, the conductive layer 120a, or the conductive layer 120b. In particular, the conductive layer 106 can be formed of a material containing copper, which can reduce resistance. This is preferable because it can reduce the resistance.

[0104] As shown in FIGS. 3A and 3C, the conductive layer 112 and It is preferable that the conductive layer 106 protrudes outward beyond the end of the semiconductor layer 108. At this time, as shown in FIG. 3C, the entire semiconductor layer 108 in the channel width direction is covered with the insulating layer 11. 0 and insulating layer 104, and is covered with conductive layer 112 and conductive layer 106.

[0105] With this configuration, the semiconductor layer 108 is subjected to an electric field generated by a pair of gate electrodes. In this case, the conductive layer 106 and the conductive layer 112 are electrically surrounded by the same material. It is preferable to apply a potential to the semiconductor layer 108 in order to induce a channel in the semiconductor layer 108. Since the electric field can be effectively applied, the on-current of the transistor 100A can be increased. This also makes it possible to miniaturize the transistor 100A.

[0106] The conductive layer 112 and the conductive layer 106 may not be connected to each other. A constant potential is applied to one of the gate electrodes of the transistor 100A, and a signal for driving the transistor 100A is applied to the other gate electrode. In this case, the transistor 100A may be turned on by applying a potential to one electrode. It is also possible to control the threshold voltage when driving the device with one electrode.

[0107] The above is an explanation of configuration example 2.

[0108] [Variation 2] A modification of the above configuration example 2 will be described below.

[0109] [Variation 2-1] 4A and 4B show the insulating layer 104 and the semiconductor layer 108 etched using the same etching mask. This shows an example of processing into a more island-like shape.

[0110] At this time, as shown in FIG. 4B, the conductive layer 112 and the conductive layer 106 are formed as a metal oxide layer. 114, the insulating layer 110, and the insulating layer 103 are electrically connected through an opening 142 provided therein. The structure is such that it continues.

[0111] [Variation 2-2] FIG. 5A shows an example where an end of an insulating layer 104 is connected to a semiconductor layer 108, a conductive layer 112, and a metal oxide layer 113. 114, and a layer located outside the insulating layer 110 and inside the conductive layer 106. This is an example in which the insulating layer 104 is processed so as to be

[0112] [Modification 2-3] 5B and 5C show that the end of the insulating layer 104 is located outside the semiconductor layer 108. and the conductive layer 112, the metal oxide layer 114, the insulating layer 110, and the conductive layer 106. This is an example of the case where the slit is located on the inner side.

[0113] FIG. 5B shows an example in which an opening 142 is provided in a position where the insulating layer 104 does not exist. On the other hand, in FIG. 5C, an opening 142 is provided at the position where the insulating layer 104 is present. This is an example of a case where

[0114] In the configuration shown in FIG. 4B (Modification 2-1) and FIG. 5B and FIG. 5C (Modification 2-3), In the channel width direction of the transistor, the conductive layer 11 on the outer side of the end of the insulating layer 104 2 is located below the semiconductor layer 108. The semiconductor layer 108 is more effectively electrically surrounded by the electric field generated by the pair of gate electrodes. This makes it possible to increase the on-state current of the transistor.

[0115] The above is an explanation of the second modification.

[0116] [Application example] An example in which the above transistor is applied to a pixel of a display device will be described below.

[0117] FIG. 6A is a schematic top view of a display device in which a plurality of sub-pixels are arranged in a matrix. A subpixel includes at least a transistor 100 and a transistor electrically connected to the transistor 100. The conductive layer 131 functions as a pixel electrode. Although the pixel configuration is shown, other transistors and capacitors may be used depending on the display element applied to the subpixel. Quantitative elements and the like can be provided as appropriate.

[0118] In FIG. 6A, the conductive layer 112 functions as a gate line (also called a scan line) and The layer 120a functions as a source line (also called a signal line or a video signal line), and the conductive layer 120 The region b functions as a wiring that electrically connects the transistor 100 and the conductive layer 131 .

[0119] In FIG. 6A, an insulating layer 104 having an island shape is provided for each transistor. That is, one insulating layer 104 is provided on one semiconductor layer 10. It can also be said to be a configuration that overlaps with 8.

[0120] In FIGS. 6B and 6C, one insulating layer 104 overlaps two or more semiconductor layers 108. 1 shows an example configuration.

[0121] FIG. 6B shows the extension of the gate line (conductive layer 112) in the display area 130 of the display device. In FIG. 6B, the insulating layer 104 is disposed in the display area 13. It is processed to cross 0.

[0122] FIG. 6C shows a portion including the entire display area 130 of the display device. In the example shown in FIG. 1, a single insulating layer 104 is formed so as to cover the entire display area 130. In other words, the insulating layer 104 is formed on all the semiconductor layers provided in the display area 130. It is stacked on top of 108.

[0123] As shown in FIGS. 6B and 6C, the insulating layer 104 can be shared between two or more sub-pixels. This makes it easy to achieve high resolution.

[0124] The configuration of the insulating layer 104 is not limited to the above, and may be for each pixel or for a block of several pixels. Alternatively, one insulating layer 104 may be disposed for each subpixel. When a transistor is included, one insulating layer may be disposed for each sub-pixel.

[0125] The transistor of one embodiment of the present invention can be applied not only to a display device but also to various circuits and devices. For example, it can be used in the arithmetic circuits, memory circuits, drive circuits, etc. of IC chips mounted on electronic devices. Various circuits such as operating circuits and interface circuits, or liquid crystal elements and organic EL elements It is suitable for display devices in which the above-mentioned is applied, and for driving circuits in various sensor devices. It can be used appropriately.

[0126] At this time, for example, a block including one or more transistors 100 (for example, each circuit, A single insulating layer 104 is provided so as to cover each of the semiconductor devices (e.g., each chip), and an insulating layer 11 is provided around the insulating layer 104. By providing an area where the insulating layer 103 contacts the transistors in the block, The insulating layer 103 and the insulating layer 116 can seal the semiconductor device 100. Therefore, hydrogen is diffused from the outside into the semiconductor layer 108 of the transistor 100, and the semiconductor layer The oxygen in the 108 is effectively prevented from diffusing to the outside, resulting in a highly reliable device. do.

[0127] The above is a description of the application example.

[0128] [Components of Semiconductor Devices] Next, components included in the semiconductor device of this embodiment will be described in detail.

[0129] 〔substrate〕 There is no particular restriction on the material of the substrate 102, but it should be strong enough to withstand the subsequent heat treatment. For example, single crystals made of silicon or silicon carbide are Semiconductor substrates, polycrystalline semiconductor substrates, compound semiconductor substrates such as silicon germanium, SOI substrates A plate, a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, etc. are used as the substrate 102. In addition, the substrate 102 may be a substrate on which a semiconductor element is provided. It may be used.

[0130] In addition, a flexible substrate is used as the substrate 102, and the transistor 10 is directly formed on the flexible substrate. Alternatively, a peeling layer may be provided between the substrate 102 and the transistor 100, etc. The release layer may be removed from the substrate 102 after a semiconductor device is partially or completely completed thereon. The transistor 10 can be separated from the semiconductor device 10 and transferred to another substrate. 0 etc. can be transferred to substrates with poor heat resistance or flexible substrates.

[0131] [Insulating layer 104] The insulating layer 104 can be formed by sputtering, CVD, vapor deposition, pulsed laser deposition ( The insulating layer 104 can be formed by using a suitable method such as a photo-induced laser diode (PLD) method. The insulating film can be formed as a single layer or a stack of an oxide insulating film or a nitride insulating film. In order to improve the interface characteristics with the semiconductor layer 108, at least the semiconductor A region in contact with the insulating layer 108 is preferably formed using an oxide insulating film. It is preferable to use a film that releases oxygen when heated.

[0132] The insulating layer 104 may be, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, or nitrogen. Silicon oxide, aluminum oxide, hafnium oxide, gallium oxide or Ga-Zn oxide The above may be used, and the layer may be formed as a single layer or a multilayer.

[0133] In addition, the insulating layer 104 may have a film other than an oxide film such as a silicon nitride film on the side in contact with the semiconductor layer 108. When the above-mentioned film is used, a pretreatment such as an oxygen plasma treatment is performed on the surface in contact with the semiconductor layer 108. and oxidizing the surface or the vicinity of the surface.

[0134] [Conductive Film] The conductive layer 112 and the conductive layer 106 function as a gate electrode, and a source electrode or drain electrode. A conductive layer 120a serving as one of the drain electrodes and a conductive layer 120b serving as the other drain electrode are provided. b: chromium, copper, aluminum, gold, silver, zinc, molybdenum, tantalum, titanium tungsten, manganese, nickel, iron, cobalt, or any of the above. The alloys are made of the above metal elements or alloys combining the above metal elements. Each of them can be formed.

[0135] The conductive layer 112, the conductive layer 106, the conductive layer 120a, and the conductive layer 120b are made of In. -Sn oxide, In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti -Sn oxide, In-Zn oxide, In-Sn-Si oxide, In-Ga-Zn oxide, etc. Alternatively, an oxide conductor or a metal oxide film may be used.

[0136] Here, we will explain about oxide conductors (OC). For example, oxygen vacancies are formed in a metal oxide having semiconductor properties, and hydrogen is added to the oxygen vacancies. Then, a donor level is formed near the conduction band. As a result, the metal oxide has high electrical conductivity. The metal oxide that has been made conductive can be called an oxide conductor.

[0137] In addition, as the conductive layer 112, etc., a conductive film containing the oxide conductor (metal oxide) and a metal Alternatively, a laminated structure of a conductive film containing a metal or an alloy may be used. In this case, the insulating film that functions as a gate insulating film is It is preferable to apply a conductive film containing an oxide conductor to the side in contact with the edge layer.

[0138] The conductive layer 112, the conductive layer 106, the conductive layer 120a, and the conductive layer 120b are made of the above-mentioned gold. Among the group elements, titanium, tungsten, tantalum, and molybdenum are particularly preferred. It is preferable to use one or more of the above. In particular, it is preferable to use a tantalum nitride film. The tantalum nitride film has electrical conductivity and has the following properties with respect to copper, oxygen, and hydrogen: Since the barrier layer 104 has a high barrier property and releases little hydrogen from itself, it is preferable that the barrier layer 104 is in contact with the semiconductor layer 108. It can be suitably used as a conductive film or a conductive film in the vicinity of the semiconductor layer 108 .

[0139] [Insulating layer 110] The insulating layer 110, which functions as a gate insulating film for the transistor 100, etc., is formed by PECVD. The insulating layer 110 can be formed by a sputtering method or the like. Silicon oxide film, silicon nitride film, silicon nitride film, aluminum oxide film, hafnium oxide film tungsten oxide film, yttrium oxide film, zirconium oxide film, gallium oxide film, tantalum oxide film, Magnesium oxide film, lanthanum oxide film, cerium oxide film, and neodymium oxide film, or more The insulating layer 110 may have a laminated structure of two layers or three or more layers. The above laminated structure may also be used.

[0140] The insulating layer 110 in contact with the semiconductor layer 108 is preferably an oxide insulating film. It is more preferable to have a region containing oxygen in excess of the stoichiometric composition. The insulating layer 110 is an insulating film capable of releasing oxygen. For example, The insulating layer 110 is formed by the above-mentioned method, and the insulating layer 110 after the film formation is subjected to a heat treatment in an oxygen atmosphere. Alternatively, an oxide film is formed on the insulating layer 110 in an oxygen atmosphere. Oxygen can also be supplied into the insulating layer 110 by, for example, forming a film therein.

[0141] In addition, the insulating layer 110 is made of a material having a higher dielectric constant than silicon oxide or silicon oxynitride. Materials such as hafnium oxide can also be used. This allows the thickness of the insulating layer 110 to be increased. It is possible to suppress leakage current caused by tunnel current. In particular, hafnium oxide, which has crystallinity, is It is preferable because it has a higher relative dielectric constant than crystalline hafnium oxide.

[0142] [Semiconductor Layer] When the semiconductor layer 108 is an In-M-Zn oxide, in order to form an In-M-Zn oxide film, The sputtering target used in the present invention must have an atomic ratio of In equal to or greater than that of M. The atomic ratio of the metal elements in such a sputtering target is preferably In:M :Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=2:1:3, In:M:Zn=3:1:2, In:M:Zn=4:2:4.1, In:M:Zn=5: 1:6, In:M:Zn=5:1:7, In:M:Zn=5:1:8, In:M:Zn= 6:1:6, In:M:Zn=5:2:5, etc.

[0143] In addition, a target containing a polycrystalline oxide is used as the sputtering target. This is preferable because the semiconductor layer 108 having crystallinity can be easily formed. The atomic ratio of the semiconductor layer 108 is determined by the atomic ratio of the metal elements contained in the sputtering target. For example, the sputtering used for the semiconductor layer 108 may vary by ±40%. When the composition of the ring target is In:Ga:Zn=4:2:4.1 [atomic ratio], the film is formed. The composition of the semiconductor layer 108 is approximately In:Ga:Zn=4:2:3 [atomic ratio]. There may be cases where this occurs.

[0144] In addition, when the atomic ratio is described as In:Ga:Zn=4:2:3 or in the vicinity, When the atomic ratio of Ga is 4, the atomic ratio of Ga is 1 to 3, and the atomic ratio of Zn is 2. The atomic ratio of In:Ga:Zn is 5:1:6 or less. When describing it as being in the vicinity of , when the atomic ratio of In is 5, the atomic ratio of Ga is 0. The atomic ratio of Zn is greater than 1 and less than 2, and includes the case where the atomic ratio of Zn is greater than 5 and less than 7. When describing that the atomic ratio of In:Ga:Zn is 1:1:1 or close to that, When the atomic ratio of Ga is 1, the atomic ratio of Zn is 0.1 or more and 2 or less. This includes cases where the numerical ratio is greater than 0.1 and less than 2.

[0145] The semiconductor layer 108 has an energy gap of 2 eV or more, preferably 2.5 eV or more. In this way, by using metal oxides with a wider energy gap than silicon, As a result, the off-state current of the transistor can be reduced.

[0146] In addition, the semiconductor layer 108 preferably has a non-single crystal structure. The non-single crystal structure is, for example, This includes the CAAC structure, polycrystalline structure, microcrystalline structure, and amorphous structure described below. In the structure, the amorphous structure has the highest defect level density, and the CAAC structure has the lowest defect level density. low.

[0147] Below, we explain about CAAC (c-axis aligned crystal). CAAC represents an example of a crystal structure.

[0148] The CAAC structure has multiple nanocrystals (crystalline regions with a maximum diameter of less than 10 nm). It is one of the crystal structures of thin films, etc., and each nanocrystal has a c-axis oriented in a specific direction and a-axis and The b-axis and b-axis do not have any orientation, and the nanocrystals are continuously connected without forming grain boundaries. In particular, thin films with CAAC structure have the following characteristics: The c-axis of the thin film is oriented in the thickness direction, the normal direction to the surface on which the film is formed, or the normal direction to the surface of the thin film. It has the characteristic of being easy to use.

[0149] CAAC-OS (Oxide Semiconductor) is a highly crystalline oxide semiconductor. On the other hand, since no clear crystal grain boundaries can be identified in CAAC-OS, It can be said that the decrease in electron mobility caused by the grain boundaries is unlikely to occur. The crystallinity may be reduced by the inclusion of impurities or the generation of defects. It can be said that CAAC- is an oxide semiconductor with few impurities and defects (such as oxygen vacancies). The physical properties of an oxide semiconductor having an OS are stable. The oxide semiconductor used is heat resistant and highly reliable.

[0150] In crystallography, the three axes that make up a unit cell, the a-axis, the b-axis, and the c-axis (crystal It is common to take a unit cell with a specific axis as the c-axis for the lattice. In a crystal with this structure, the two axes parallel to the plane direction of the layers are the a-axis and the b-axis, and the axis that intersects the layers is the Generally, the c-axis is taken as the c-axis. A typical example of a crystal with such a layered structure is Graphite is classified as a hexagonal crystal, and the a- and b-axes of the unit cell are parallel to the cleavage plane. The c-axis is perpendicular to the cleavage plane. For example, the layered structure YbFe 2 O 4 Crystal structure of the type InGaZnO 4 The crystal of this system can be classified as a hexagonal system, and the a-axis and The a- and b-axes are parallel to the plane of the layer, and the c-axis is perpendicular to the layers (i.e., the a- and b-axes).

[0151] An example of the crystal structure of a metal oxide will be described. In the following, In-Ga-Zn oxide Sputtering was performed using a Zn oxide target (In:Ga:Zn=4:2:4.1 [atomic ratio]). A metal oxide film formed by the ring method will be described as an example. Metal oxide formed by sputtering at a plate temperature of 100°C to 130°C is either nc (nano crystal) or CAAC crystal structure, or On the other hand, the substrate temperature is set to room temperature (RT), and the Metal oxides formed by the deposition method tend to have an nc crystal structure. Room temperature (RT) includes the temperature at which the substrate is not intentionally heated.

[0152] [Example of manufacturing method] An example of a method for manufacturing a transistor of one embodiment of the present invention will be described below. The transistor 100A illustrated in the second configuration example will be described as an example.

[0153] The thin films (insulating film, semiconductor film, conductive film, etc.) constituting the semiconductor device are formed by sputtering. Chemical Vapor Deposition (CVD) method , vacuum deposition, pulsed laser deposition (PLD) ion) method, Atomic Layer Deposition (ALD) The CVD method can be a plasma-enhanced chemical vapor deposition (PEC) method. There are methods such as the VD (Plasma Enhanced CVD) method and the thermal CVD method. One of the thermal CVD methods is metal organic chemical vapor deposition (MOCVD). c CVD) method.

[0154] In addition, thin films (insulating films, semiconductor films, conductive films, etc.) that constitute semiconductor devices are formed by spin coating, Dip, spray application, inkjet, dispensing, screen printing, offset Printing, doctor knife, slit coat, roll coat, curtain coat, knife coat It can be formed by the above method.

[0155] In addition, when processing the thin films that constitute the semiconductor device, photolithography and other methods are used. In addition, nanoimprinting, sandblasting, lift-off, The thin film may be processed by a method such as a masking method using a metal mask. The island-shaped thin film may be directly formed by the film method.

[0156] There are two typical photolithography methods. A resist mask is formed on the thin film to be processed by etching or the like. The other method is to remove the mask after forming a photosensitive thin film. Then, development is performed to process the thin film into a desired shape.

[0157] In the photolithography method, the light used for exposure is, for example, i-line (wavelength 365 nm), Using g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture of these. In addition, ultraviolet light, KrF laser light, ArF laser light, etc. can be used. The exposure may be performed by immersion lithography. Using extreme ultraviolet (EUV) and X-rays, Also, instead of light for exposure, an electron beam can be used. The use of light, X-rays or electron beams is preferable because it allows extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, the photomask is It is not necessary.

[0158] There are three methods for etching thin films: dry etching, wet etching, and sandblasting. Methods such as the above can be used.

[0159] 7 to 9 show the channel configurations of the transistor 100A at various stages in the manufacturing process. 4 shows cross sections in the channel length direction and the channel width direction side by side.

[0160] [Formation of Conductive Layer 106] A conductive film is formed on the substrate 102 and processed by etching to form a gate electrode. A functional conductive layer 106 is formed (FIG. 7(A)).

[0161] [Formation of insulating layers 103 and 104] Next, insulating layers 103 and 104 are laminated to cover the substrate 102 and the conductive layer 106. (FIG. 7(B)). The insulating layer 103 and the insulating layer 104 are formed by the PECVD method, The film can be formed by using an ALD method, a sputtering method, or the like.

[0162] For example, the insulating layer 103 is formed by using an ALD method or a sputtering method, and the insulating layer 10 4 can be formed using a PECVD method or a sputtering method.

[0163] Next, a part of the insulating layer 104 is removed by etching and processed into an island shape (FIG. 7(C) ).

[0164] [Formation of Semiconductor Layer 108] Next, a metal oxide film is formed on the insulating layer 104 and the insulating layer 103, and then processed. Thus, the semiconductor layer 108 is formed.

[0165] The metal oxide film is formed by a sputtering method using a metal oxide target. is preferred.

[0166] In addition, when forming a metal oxide film, in addition to oxygen gas, an inert gas (e.g., helium Gas such as argon gas, xenon gas, etc. may be mixed. The higher the ratio of oxygen gas in the total deposition gas (hereinafter referred to as the oxygen flow ratio), the better the deposition efficiency. This can improve the crystallinity of the metal oxide film, resulting in highly reliable transistors. On the other hand, the lower the oxygen flow rate ratio, the lower the crystallinity of the metal oxide film, and the higher the on-current. The transistor may be a transistor having a gate insulating film.

[0167] The metal oxide film is formed under the following conditions: the substrate temperature is equal to or higher than room temperature and lower than 200° C. For example, the film formation temperature may be set to be between room temperature and 140° C. If the temperature is less than 100° C., the productivity is increased, which is preferable. By forming the metal oxide film without heating, the crystallinity can be reduced.

[0168] In addition, before the metal oxide film is formed, water, hydrogen, and organic matter adsorbed on the surface of the insulating layer 104 are removed. It is preferable to perform a treatment for removing the above-mentioned elements and a treatment for supplying oxygen into the insulating layer 104. For example, heat treatment can be performed at a temperature of 70°C to 200°C in a reduced pressure atmosphere. Alternatively, plasma treatment may be performed in an atmosphere containing oxygen. 2 O When plasma processing is performed in an atmosphere containing a gas, organic matter on the surface of the insulating layer 104 is preferably removed. After such a treatment, the surface of the insulating layer 104 is exposed to the atmosphere. It is preferable to form the metal oxide film continuously without a step.

[0169] Metal oxide films are processed using either wet etching or dry etching. In this case, the part of the insulating layer 104 that does not overlap with the semiconductor layer 108 may be used. The part may be etched and thinned.

[0170] After the metal oxide film is formed or processed into the semiconductor layer 108, the metal oxide film or Alternatively, heat treatment may be performed in order to remove hydrogen or water from the semiconductor layer 108. The temperature is typically 150° C. or higher but lower than the strain point of the substrate, or 250° C. or higher but lower than 450° C. or 300°C or higher and 450°C or lower.

[0171] The heat treatment can be performed in an atmosphere containing a rare gas or nitrogen. After heating in the atmosphere, heating in an oxygen-containing atmosphere may be performed. It is preferable that the gas does not contain hydrogen, water, etc. The heat treatment is carried out in an electric furnace, RTA (Repetitive Thermal Atomic Energy Acoustic Current) or the like. A RTA device can be used. This allows the heat treatment time to be shortened.

[0172] [Formation of insulating film 110f and metal oxide film 114f] Next, the insulating layer 110 is formed to cover the insulating layer 103, the insulating layer 104, and the semiconductor layer 108. The insulating film 110f and the metal oxide film 114f that will become the metal oxide layer 114 are laminated to form the film. do.

[0173] The insulating film 110f is, for example, an oxide film such as a silicon oxide film or a silicon oxynitride film. The deposition of the film is performed using a plasma enhanced chemical vapor deposition (PECVD) system, or simply a plasma CVD system. It is preferable to form the insulating film by using a PECVD method using microwaves. It may be formed by

[0174] The metal oxide film 114f is preferably formed in an atmosphere containing oxygen, for example. It is preferable to form the film by sputtering in an atmosphere containing oxygen. Oxygen can be supplied to the insulating film 110f during the formation of the metal oxide film 114f.

[0175] For example, the deposition conditions for the metal oxide film 114f are as follows: oxygen is used as the deposition gas; It is preferable to form the metal oxide film by a reactive sputtering method using gold. When aluminum is used as the metal target, for example, an aluminum oxide film is formed. It is possible.

[0176] When the metal oxide film 114f is formed, the total flow rate of the film formation gas introduced into the film formation chamber of the film formation apparatus is The higher the oxygen flow rate ratio to the total oxygen flow rate (oxygen flow rate ratio) or the oxygen partial pressure in the deposition chamber, the greater the insulating film thickness. The oxygen supplied during 10f can be increased. The oxygen flow ratio or oxygen partial pressure can be increased, for example, by 50% or more and 100% or less, preferably 65% ​​or more and 100% or less, more preferably 80% or more The oxygen flow rate ratio is preferably 100% or more, and more preferably 90% or more and 100% or less. It is preferable to set the oxygen partial pressure at 100% and to make the oxygen partial pressure as close to 100% as possible.

[0177] In this manner, the metal oxide film 114f is formed by the sputtering method in an atmosphere containing oxygen. By forming the metal oxide film 114f, oxygen is supplied to the insulating film 110f during the formation of the metal oxide film 114f. At the same time, oxygen can be prevented from being released from the insulating film 110f. It is possible to trap a large amount of oxygen in the film 110f. As a result, a large amount of oxygen can be supplied to the semiconductor layer 108. This reduces oxygen vacancies and realizes a highly reliable transistor.

[0178] Next, after the metal oxide film 114f is formed, the metal oxide film 114f, the insulating film 110f, The insulating layer 104 and a part of the insulating layer 103 are etched to reach the conductive layer 106. An opening is formed. This allows the conductive layer 112 and the conductive layer 106 to be formed later to pass through the opening. The electrical connection can be made via.

[0179] A schematic cross-sectional view at this stage corresponds to FIG. 8(B).

[0180] [Formation of Conductive Layer 112, Metal Oxide Layer 114, and Insulating Layer 110] Then, a conductive film that will become the conductive layer 112 is formed on the metal oxide film 114f. The film is formed by sputtering using a metal or alloy sputtering target. It is preferable to do so.

[0181] Next, the conductive film, the metal oxide film 114f, and a part of the insulating film 110f are etched. (FIG. 8(C)). The conductive film, the metal oxide film 114f, and the insulating film 110f are It is preferable to process the conductive layer 1 after etching using the same resist mask. 12 as a hard mask, the metal oxide film 114f and the insulating film 110f are etched. You may also search for

[0182] As a result, the conductive layer 112, the metal oxide layer 114, and the like, which are islands with roughly the same top surface shape, are formed. An insulating layer 110 may be formed.

[0183] When the conductive film, the metal oxide film 114f, and the insulating film 110f are etched, the insulating layer The semiconductor layer 108 not covered by 110 may also be etched and thinned.

[0184] [Formation of insulating layer 116] Next, the insulating layer 104, the semiconductor layer 108, the side surface of the insulating layer 110, and the metal oxide layer 114 are An insulating layer 116 is formed to cover the side surfaces and the conductive layer 112. Outside the end of 04, a region where the insulating layer 103 and the insulating layer 116 are in contact with each other is formed. (Figure 9(A)).

[0185] The insulating layer 116 is formed by sputtering a target containing the above-mentioned metal element with nitrogen gas. The reactive sputtering method uses a mixture of rare gases, which is a dilution gas, as the deposition gas. In this way, the insulating layer can be formed by controlling the flow rate ratio of the deposition gas. This makes it easier to control the film quality of 116.

[0186] For example, the insulating layer 116 is formed by reactive sputtering using an aluminum target. When using an aluminum nitride film formed by the above method, the flow rate of nitrogen gas relative to the total flow rate of the deposition gas is The amount is 30% or more and 100% or less, preferably 40% or more and 100% or less, more preferably 50 It is preferable that the ratio is 100% or more and 100% or less.

[0187] When the insulating layer 116 is formed, the interface between the semiconductor layer 108 and the insulating layer 116 and the interface A low resistance region 108n is formed in the adjacent region.

[0188] [First heat treatment] Subsequently, it is preferable to perform a heat treatment. This can further promote the reduction in the resistance of 8n.

[0189] The heat treatment is preferably carried out in an atmosphere of an inert gas such as nitrogen or a rare gas. The higher the processing temperature, the more preferable. However, the heat resistance of the substrate 102, the conductive layer 106, the conductive layer 112, etc. For example, the temperature can be set to 120° C. or higher and 500° C. or lower, preferably 1 50°C or higher and 450°C or lower, more preferably 200°C or higher and 400°C or lower, and further preferably The temperature can be 250° C. or more and 400° C. or less. For example, the heat treatment temperature can be 350° C. By keeping the size to about 100mm, it is possible to produce semiconductor devices with a high yield rate using production equipment that uses large glass substrates. It is possible.

[0190] The heat treatment may be performed at any stage after the insulating layer 116 is formed. This may also be combined with heat treatment.

[0191] For example, oxygen in the semiconductor layer 108 is extracted to the insulating layer 116 side by heat treatment. The oxygen vacancies are generated by the above-mentioned oxidation, and hydrogen contained in the semiconductor layer 108 is bonded to the oxygen vacancies. By bonding, the carrier concentration increases, and the resistance of the portion in contact with the insulating layer 116 can be reduced. .

[0192] Alternatively, the metal element contained in the semiconductor layer 108 may be removed by the heat treatment at the interface with the insulating layer 116. The metal element diffuses toward the surrounding area, forming a region with a high concentration of the metal element, forming an insulating layer. In some cases, the resistance of the portion in contact with the semiconductor layer 116 is reduced. When a metal oxide film containing indium is used, the region with a high indium concentration is formed in the insulating layer of the semiconductor layer 108. It may be observed near the interface with 116.

[0193] The region 108n, which has been made low-resistance by such a complex action, has an extremely stable low resistance. The region 108n thus formed is a region to which oxygen is supplied in a later process, for example. Even if treatment is performed, the resistance is unlikely to increase again.

[0194] [Formation of insulating layer 118] Subsequently, an insulating layer 118 is formed covering the insulating layer 116. The insulating layer 118 is made of, for example, PE It can be formed by a CVD method.

[0195] [Formation of openings 141a and 141b] Next, the insulating layer 118 and a part of the insulating layer 116 are etched to form the region 108n The openings 141a and 141b are formed so as to reach the

[0196] [Formation of conductive layers 120a, 120b] Next, a conductive film is formed on the insulating layer 118 so as to cover the openings 141a and 141b. The conductive film is then processed into a desired shape to form the conductive layers 120a and 120b. (Figure 9(B)).

[0197] Through the above steps, the transistor 100A can be manufactured.

[0198] In addition, when the configurations illustrated in Configuration Example 1 and Modification Example 1 are used, In this case, the step of forming the conductive layer 106 and the step of forming the opening 142 may be omitted.

[0199] The above is an explanation of the example of the manufacturing method.

[0200] The configuration examples and manufacturing method examples illustrated in this embodiment and the corresponding drawings, etc. Also, parts of the present invention may be implemented in appropriate combination with other configuration examples, manufacturing method examples, drawings, etc. can be done.

[0201] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0202] (Embodiment 2) In this embodiment, a display device including the transistor described in the above embodiment will be An example will be described.

[0203] [Configuration example] FIG. 10A shows a top view of a display device 700. The display device 700 includes a sealant 712. The first substrate 701 and the second substrate 705 are bonded together by a bonding wire. 01, the second substrate 705, and the area sealed by the sealant 712, the first substrate 7 01, a pixel section 702, a source driver circuit section 704, and a gate driver circuit section 706 The pixel portion 702 is provided with a plurality of display elements.

[0204] In addition, an FPC 716 (FP C: Flexible printed circuit) is connected to the FPC terminal 7 The FPC terminal portion 708 and the signal line 710 are connected by the FPC 716. Through the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 Various signals are supplied to each of these.

[0205] A plurality of gate driver circuit sections 706 may be provided. The path portion 706 and the source driver circuit portion 704 are separately formed on a semiconductor substrate or the like. The IC chip may be in the form of a packaged IC chip. The IC chip may be mounted on the first substrate 70. 1, or can be mounted on FPC716.

[0206] The pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 have The transistor can be a transistor that is a semiconductor device of one embodiment of the present invention. do.

[0207] Examples of the display element provided in the pixel portion 702 include a liquid crystal element and a light emitting element. The liquid crystal elements used include transmissive liquid crystal elements, reflective liquid crystal elements, and semi-transmissive liquid crystal elements. In addition, the light emitting element can be LED (Light Emitting Diode). iode), OLED (Organic LED), QLED (Quantum-dot) Examples of self-luminous light-emitting elements include LEDs and semiconductor lasers. MEMS (Micro Electro Mechanical Systems) using the optical interference method Systems), microcapsule type, electrophoretic type, electrowet type Use display elements that use the electronic powder method or electronic liquid powder method. It is also possible.

[0208] The display device 700A shown in FIG. 10B is suitable for use in electronic devices having a large screen. The display device 700A is, for example, a television device, a monitor device, equipment, personal computers (including notebook and desktop computers), tablet devices , and can be suitably used for digital signage.

[0209] The display device 700A includes a plurality of source driver ICs 721 and a pair of gate driver circuits. The sensor 722 has a first section 722.

[0210] The source driver ICs 721 are each attached to an FPC 723. In addition, the plurality of FPCs 723 are arranged such that one terminal is connected to the first board 701 and the other terminal is connected to the printed board. The FPC 723 is bent to connect the printed circuit board 7 24 can be disposed on the back side of the pixel section 702 and mounted on the electronic device, thereby reducing the space required for the electronic device. It is possible to pace things.

[0211] On the other hand, the gate driver circuit section 722 is formed on the first substrate 701. This makes it possible to realize electronic devices with narrow frames.

[0212] With this configuration, a large-sized and high-resolution display device can be realized. The surface size is 30 inches or more, 40 inches or more, 50 inches or more, or 60 inches or more diagonally. It can also be applied to the above display devices. Alternatively, it is possible to realize extremely high-resolution display devices such as 8K4K.

[0213] [Cross-section example] In the following, a configuration in which a liquid crystal element and an EL element are used as a display element will be described with reference to FIGS. 11 to 13 are respectively the chain diagrams shown in FIG. 11 and 12 are cross-sectional views taken along the line QR. FIG. 13 shows a configuration using an EL element.

[0214] [Description of common parts of the display device] A display device 700 shown in FIGS. 11 to 13 includes a wiring portion 711 and a pixel portion 702. , a source driver circuit section 704, and an FPC terminal section 708. 11 includes a signal line 710. The pixel portion 702 includes a transistor 750 and a capacitor 79. 0. The source driver circuit portion 704 includes a transistor 752.

[0215] The transistor 750 and the transistor 752 are the transistors exemplified in the first embodiment. can be applied.

[0216] The transistor used in this embodiment is made of a highly purified oxide film in which the formation of oxygen vacancies is suppressed. The transistor has a semiconductor film. The off-state current of the transistor can be reduced. This allows the retention time of electrical signals such as signals to be extended, and the writing interval of image signals etc. can also be set longer. This allows the frequency of refresh operations to be reduced, resulting in reduced power consumption. This has the effect of reducing

[0217] In addition, the transistor used in this embodiment has a relatively high field-effect mobility. For example, a transistor capable of such high speed operation can be used for a display device. By using this in a device, the switching transistor in the pixel section and the driver circuit section In other words, a separate driver circuit can be formed on the same substrate. Since there is no need to use semiconductor devices formed from silicon wafers, etc., The number of points can be reduced. Also, in the pixel area, transistors that can be driven at high speed can be used. By using this, high quality images can be provided.

[0218] The capacitor 790 is formed by processing the same film as the semiconductor layer of the transistor 750. The lower electrode is processed to have a low resistance, and the same conductive film as the source electrode or drain electrode is processed. and an upper electrode formed by the transistor. In other words, the capacitor 790 is formed by insulating a pair of electrodes. It has a laminated structure in which an insulating film that functions as a dielectric film is sandwiched between the insulating film and the gate electrode.

[0219] In addition, a planarization insulating layer is formed on the transistor 750, the transistor 752, and the capacitor 790. A veneer 770 is provided.

[0220] A transistor 750 included in the pixel portion 702 and a transistor 751 included in the source driver circuit portion 704 A transistor having a structure different from that of the transistor 752 may be used. A top-gate transistor is applied to one side, and a bottom-gate transistor is applied to the other side. The source driver circuit section 704 may be replaced with a gate driver circuit. It may also be read as "road section."

[0221] The signal line 710 is the same as the source and drain electrodes of the transistors 750 and 752. In this case, if a low-resistance material such as a material containing copper is used, the wiring This is preferable because it reduces signal delays caused by line resistance and enables display on a large screen.

[0222] The FPC terminal portion 708 includes wiring 760, a part of which functions as a connection electrode, and an anisotropic conductive film 78. The wiring 760 is connected to the FPC 716 via an anisotropic conductive film. Here, the wiring 760 is electrically connected to the terminals of the transistors 750 and 752. The source electrode and drain electrode of the second transistor are formed of the same conductive film.

[0223] The first substrate 701 and the second substrate 705 are, for example, a glass substrate or a plastic substrate. A flexible substrate such as a plastic substrate can be used.

[0224] In addition, the structure 778 between the first substrate 701 and the second substrate 705 is The spacers function as columnar spacers to control the distance (cell gap) between the first substrate 705 and the second substrate 705. The structure 778 may be formed on the second substrate 705 side, or a spherical spacer may be used. It's fine.

[0225] On the second substrate 705 side, a light-shielding film 738, a colored film 736, and insulating films in contact with these are provided. A border membrane 734 is provided.

[0226] [Example of the configuration of a display device using a liquid crystal element] The display device 700 shown in FIG. 11 includes a liquid crystal element 775. The liquid crystal element 775 includes a conductive film A second conductive film 774 is disposed between the first conductive film 772 and the second conductive film 774, and a liquid crystal layer 776 is disposed between the first conductive film 772 and the second conductive film 774. The conductive film 772 is provided on the substrate 705 side and functions as a common electrode. The conductive film is electrically connected to a source electrode or a drain electrode of the transistor 750. A pixel electrode 772 is formed on the planarization insulating film 770 and functions as a pixel electrode.

[0227] The conductive film 772 is made of a material that transmits visible light or a material that reflects visible light. Examples of the light-transmitting material include indium, zinc, tin, etc. The reflective material may be, for example, an oxide material containing aluminum, silver, etc. It is advisable to use materials that

[0228] When a reflective material is used for the conductive film 772, the display device 700 becomes a reflective liquid crystal display device. On the other hand, when a light-transmitting material is used for the conductive film 772, the liquid crystal display device becomes a transmissive type. In the case of a liquid crystal display device of the transmission type, a polarizing plate is provided on the viewing side. A pair of polarizing plates is provided to sandwich the liquid crystal element.

[0229] The display device 700 shown in FIG. 12 includes a liquid crystal element 77 of a horizontal electric field type (for example, an FFS mode). 5 is disposed on a conductive film 772 with an insulating film 773 interposed therebetween, the conductive film 772 serving as a common electrode. A conductive film 774 is provided. An electric field generated between the conductive film 772 and the conductive film 774 causes The alignment state of the liquid crystal layer 776 can be controlled.

[0230] Although not shown in FIGS. 11 and 12, an alignment film is provided in contact with the liquid crystal layer 776. In addition, optical members such as a polarizing member, a phase difference member, and an anti-reflection member (optical substrate) may be used. A display panel, and light sources such as a backlight and a sidelight can be provided as appropriate.

[0231] The liquid crystal layer 776 may include a thermotropic liquid crystal, a low molecular weight liquid crystal, a high molecular weight liquid crystal, a polymer dispersion liquid, etc. Liquid crystals, polymer network type liquid crystals, ferroelectric liquid crystals, antiferroelectric liquid crystals, etc. can be used. In addition, when the in-plane switching method is adopted, liquid crystals exhibiting a blue phase without using an alignment film may be used. stomach.

[0232] The liquid crystal element modes are Twisted Nematic (TN) mode, VA (Vertical Alignment) mode, IPS (In-Plane-S witching) mode, FFS(Fringe Field Switching) mode, ASM (Axially Symmetric aligned Micro- cell) mode, OCB (Optical Compensated Birefri) ngence) mode, ECB (Electrically Controlled B irefringence mode, guest-host mode, etc. can be used.

[0233] [Display device using light-emitting element] The display device 700 shown in FIG. 13 includes a light-emitting element 782. The light-emitting element 782 is a conductive film The EL layer 786 includes an organic compound, has inorganic compounds such as quantum dots.

[0234] Examples of materials that can be used for the organic compound include fluorescent materials and phosphorescent materials. In addition, materials that can be used for quantum dots include colloidal quantum dots. materials, alloy type quantum dot materials, core-shell type quantum dot materials, core type quantum dot materials, etc.

[0235] In the display device 700 shown in FIG. An insulating film 730 is provided. Here, the light-emitting element 782 has a light-transmitting conductive film 788. The light-emitting element 782 is a top-emission type light-emitting element. A bottom emission structure that emits light from the bottom and a conductive film 788 side that emits light from the bottom are also available. A dual emission structure may be used.

[0236] The colored film 736 is provided at a position overlapping the light emitting element 782, and the light shielding film 738 is an insulating film. 730, the lead wiring portion 711, and the source driver circuit portion 704. The colored film 736 and the light-shielding film 738 are covered with an insulating film 734. The space between the light emitting element 782 and the insulating film 734 is filled with a sealing film 732. 86 is formed in an island shape for each pixel or in a stripe shape for each pixel row, that is, by painting. In some cases, the colored film 736 may not be provided.

[0237] [Example of configuration in which an input device is provided on a display device] An input device may be provided in the display device 700 shown in FIGS. An example of the device is a touch sensor.

[0238] 14 and 13 show a configuration in which a touch panel 791 is provided on the display device 700 shown in FIG. FIG. 15 shows a configuration in which a touch panel 791 is provided on a display device 700.

[0239] The touch panel 791 shown in FIG. 14 and FIG. 15 is made of a second substrate 705 and a colored film 736. The touch panel 791 is provided between the second substrate 731 and the colored film 736. The touch panel 791 is formed on the second substrate 705 and the first substrate 701. Since it is provided between the display and the LCD, it can also be called an in-cell type touch panel.

[0240] The touch panel 791 has an insulating film 792 covering the light-shielding film 738 and an insulating layer 797 between which an electric field is formed. The electrode 793, the electrode 794, the insulating film 795, and the electrode 796 are included. A change in capacitance between the electrodes 793 and 794 that may occur when a detection object such as a mouse approaches. can be detected.

[0241] Also, the intersection of the electrode 793 and the electrode 794 is shown in the portion overlapping the light-shielding film 738. The electrode 796 is formed by sandwiching the electrode 794 between two electrodes through an opening provided in the insulating film 795. The crossing portion is electrically connected to the electrode 793. etc.

[0242] The electrodes 793 and 794 are disposed in a region that does not overlap with the light-emitting element 782 or the liquid crystal element 775, e.g. For example, it is preferable to provide the electrode 793 and the light shielding film 738 in a portion overlapping the electrode 793. The pole 794 can be shaped like a mesh. This allows the light emitting element 782 to emit light. The touch panel can be configured so as not to block light coming through the liquid crystal element 775 or light passing through the liquid crystal element 775. The decrease in brightness caused by the placement of the LED 791 is suppressed, and the visibility is high and the power consumption is low. Further, at this time, the electrodes 793 and 794 are provided with low resistance. Therefore, compared with the case where a transparent conductive material is used, This can improve the sensor sensitivity of the touch panel.

[0243] The configuration of the touch panel is not limited to the in-cell type, and an input device may be provided on the display device 700. A so-called on-cell type touch panel or an input device is attached to the display device 700. A so-called out-cell type touch panel may be used.

[0244] The configuration examples exemplified in this embodiment and the corresponding drawings are at least partially The above can be implemented in appropriate combination with other configuration examples or drawings, etc.

[0245] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0246] (Embodiment 3) In this embodiment, a display device including a semiconductor device of one embodiment of the present invention will be described with reference to FIG. This will be used to explain.

[0247] The display device shown in FIG. 16A includes a pixel portion 502, a driver circuit portion 504, and a protection circuit 505. 6 and a terminal portion 507. Note that the protection circuit 506 may be omitted. .

[0248] The transistors in the pixel portion 502 and the driver circuit portion 504 are the transistors of one embodiment of the present invention. In addition, the protection circuit 506 can also use the transistor of one embodiment of the present invention. may be applied.

[0249] The pixel section 502 is a multi-layered pixel array arranged in X rows and Y columns (X and Y are each independently a natural number of 2 or more). The pixel circuit 501 includes a number of pixel circuits 501 for driving a number of display elements.

[0250] The driving circuit unit 504 includes a gate driver that outputs scanning signals to the gate lines GL_1 to GL_X. a source driver 504a, which supplies data signals to the data lines DL_1 to DL_Y; The gate driver 504a includes at least a shift register The source driver 504b may be, for example, a plurality of analog switches. Also, the source driver 504 is configured using a shift register, etc. b may be constructed.

[0251] The terminal unit 507 is used to input power, control signals, and image signals from an external circuit to the display device. This refers to the part where terminals are provided for connecting the power supply to the power source.

[0252] When a potential outside a certain range is applied to the wiring to which the protection circuit 506 is connected, the protection circuit The protection circuit 506 shown in FIG. For example, the scanning line GL, which is the wiring between the gate driver 504a and the pixel circuit 501, Various wiring such as the data line DL, which is the wiring between the source driver 504b and the pixel circuit 501, Connected.

[0253] The gate driver 504a and the source driver 504b are connected to the pixel section 502 and The gate driver circuit or the source driver circuit may be provided on the same substrate. A separately formed substrate (for example, a driving circuit formed of a single crystal semiconductor film or a polycrystalline semiconductor film) The circuit board is bonded to the board by COG or TAB (Tape Automated Bonding). It may also be configured to be mounted on a substrate.

[0254] Here, FIG. 17 shows a configuration different from that of FIG. 16(A). In FIG. 17, A pair of source lines (for example, source line DLa1 and source line DLb1) is arranged. In addition, two adjacent gate lines (for example, gate line GL_1 and the gate line GL_2) are electrically connected.

[0255] In addition, the pixels connected to the gate line GL_1 are connected to one of the source lines (source line DLa1, The pixels connected to the gate line GL_1 are connected to the other source line DLa2, etc. (source line DLb1, source line DLb2, etc.).

[0256] With this configuration, two gate lines can be selected at the same time. As a result, the length of one horizontal period can be doubled compared to the configuration shown in FIG. This makes it easy to realize a display device with high resolution and a large screen.

[0257] In addition, the pixel circuits 501 shown in FIG. 16(A) and FIG. 17 may be, for example, The configuration shown in FIG.

[0258] The pixel circuit 501 shown in FIG. 16B includes a liquid crystal element 570, a transistor 550, and a capacitor. The pixel circuit 501 also includes a data line DL_n, a scanning line GL_ m, a potential supply line VL, etc. are connected.

[0259] The potential of one of the pair of electrodes of the liquid crystal element 570 is appropriately set according to the specifications of the pixel circuit 501. The alignment state of the liquid crystal element 570 is set by the written data. A common potential is applied to one of a pair of electrodes of the liquid crystal element 570 in each of the pixel circuits 501. A common potential may be applied to the pair of liquid crystal elements 570 of the pixel circuits 501 in each row. A different potential may be applied to one of the electrodes.

[0260] The pixel circuit 501 shown in FIG. 16C includes transistors 552 and 554 and a capacitance element. The pixel circuit 501 includes a data line DL_n , the scanning line GL_m, the potential supply line VL_a, the power supply line VL_b, etc. are connected to the pixel electrodes GL_m, GL_m.

[0261] A high power supply potential VDD is applied to one of the potential supply lines VL_a and VL_b. and the other is supplied with a low power supply potential VSS.

[0262] The configuration examples exemplified in this embodiment and the corresponding drawings are at least partially The above can be implemented in appropriate combination with other configuration examples or drawings, etc.

[0263] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0264] (Embodiment 4) In this embodiment, a display module that can be manufactured using one embodiment of the present invention will be described. I will explain it below.

[0265] The display module 6000 shown in FIG. 18(A) includes an upper cover 6001 and a lower cover 6002. A display device 6006, a frame 6009, and a printer 6002 are connected to the FPC 6005. The semiconductor device has a support substrate 6010 and a battery 6011.

[0266] For example, a display device manufactured according to one embodiment of the present invention can be used as the display device 6006. The display device 6006 realizes a display module with extremely low power consumption. It is possible.

[0267] The upper cover 6001 and the lower cover 6002 are adapted to the size of the display device 6006. The shape and dimensions can be changed as appropriate.

[0268] The display device 6006 may have a function as a touch panel.

[0269] The frame 6009 has a function of protecting the display device 6006 and a function of preventing the display device 6006 from being damaged by the operation of the printed circuit board 6010. The insulating film may have a function of blocking electromagnetic waves generated by the insulating film, a function as a heat sink, etc.

[0270] The printed circuit board 6010 includes a power supply circuit, a signal circuit for outputting a video signal, and a clock signal. It has a signal processing circuit, a battery control circuit, etc.

[0271] FIG. 18B is a schematic cross-sectional view of a display module 6000 equipped with an optical touch sensor. It is.

[0272] The display module 6000 includes a light emitting section 6015 and a receiving section 6016 provided on a printed circuit board 6010. The optical unit 6016 is surrounded by an upper cover 6001 and a lower cover 6002. The region has a pair of light guiding portions (light guiding portion 6017a, light guiding portion 6017b).

[0273] The display device 6006 is connected to a printed circuit board 6010 and a battery via a frame 6009. The display device 6006 and the frame 6009 are disposed on top of the light guide unit 6011. 017a and fixed to light guiding portion 6017b.

[0274] Light 6018 emitted from the light emitting portion 6015 is guided to the display device 600 by the light guiding portion 6017a. 6, and reaches the light receiving part 6016 through the light guiding part 6017b. A touch operation is detected when the light 6018 is blocked by a detection object such as an illustration. It is possible.

[0275] A plurality of light emitting sections 6015 are provided along two adjacent sides of the display device 6006, for example. A plurality of light receiving sections 6016 are provided at positions facing the light emitting sections 6015. It is possible to obtain information on the position where the touch operation was performed.

[0276] The light emitting unit 6015 may be a light source such as an LED element, and in particular, may be a light source that emits infrared rays. It is preferable to use a light source that emits light. The light receiving unit 6016 receives the light emitted by the light emitting unit 6015. A photoelectric element that can receive light and convert it into an electrical signal can be used. A photodiode such as a photodiode can be used.

[0277] The light guiding portion 6017a and the light guiding portion 6017b transmit light 6018. The light receiving unit 6016 can be disposed under the display device 6006, and external light is received by the light receiving unit 601. 6, which prevents the touch sensor from malfunctioning. By using a resin that allows wires to pass through, malfunction of the touch sensor can be more effectively prevented.

[0278] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0279] (Embodiment 5) In this embodiment, an electronic device including a display device manufactured according to one embodiment of the present invention will be described. I will explain this in more detail.

[0280] FIG. 19A shows the appearance of the camera 8000 with the viewfinder 8100 attached. This is a diagram.

[0281] The camera 8000 includes a housing 8001, a display unit 8002, an operation button 8003, and a shutter. The camera 8000 has a button 8004 and the like. The camera 8000 also has a detachable lens 8006. It is attached.

[0282] In addition, the camera 8000 may have the lens 8006 and the housing integrated together.

[0283] The camera 8000 can be operated by pressing the shutter button 8004 or by using a touch panel. By touching the display portion 8002, an image can be captured.

[0284] The housing 8001 has a mount having electrodes, and is equipped with a finder 8100 and a strobe. It is possible to connect devices such as a

[0285] The finder 8100 includes a housing 8101, a display unit 8102, a button 8103, and the like. .

[0286] The housing 8101 is attached to the camera 8000 by a mount that engages with the mount of the camera 8000. The Finder 8100 is attached to the Camera 8000. The information can be displayed on the display unit 8102 .

[0287] The button 8103 has a function such as a power button.

[0288] The display unit 8002 of the camera 8000 and the display unit 8102 of the viewfinder 8100 are The display device according to one embodiment of the present invention can be applied to a camera having a built-in viewfinder. It may be La 8000.

[0289] FIG. 19B is a diagram showing the external appearance of the head mounted display 8200.

[0290] The head mounted display 8200 includes a mounting part 8201, a lens 8202, and a main body 82 8203, a display unit 8204, a cable 8205, etc. It has a built-in 8206 battery.

[0291] A cable 8205 supplies power from a battery 8206 to the main body 8203. 203 is equipped with a wireless receiver and the like, and can display received video information on a display unit 8204. The main body 8203 is also equipped with a camera, and can input information on the movements of the user's eyes and eyelids. It can be used as a step.

[0292] In addition, the attachment part 8201 is provided with a flow sensor that flows in accordance with the movement of the user's eyeball at a position where the attachment part 8201 touches the user. A plurality of electrodes capable of detecting a current passing through the sensor may be provided, and the sensor may have a function of recognizing the line of sight. In addition, the device may have a function of monitoring the pulse rate of the user by measuring the current flowing through the electrodes. In addition, the mounting part 8201 has various sensors such as a temperature sensor, a pressure sensor, and an acceleration sensor. The display unit 8204 may have a function to display the user's biological information, and the head of the user may have a function to display the user's biological information on the display unit 8204. The display portion 8204 may have a function of changing an image displayed on the display portion 8204 in accordance with the user's movement.

[0293] The display device of one embodiment of the present invention can be applied to the display portion 8204.

[0294] 19(C), (D), and (E) are diagrams showing the appearance of the head mounted display 8300. The head mounted display 8300 includes a housing 8301, a display unit 8302, and a backlight. The optical element has a band-shaped fixture 8304 and a pair of lenses 8305.

[0295] A user can view the display on the display unit 8302 through the lens 8305 . If the display unit 8302 is curved, the user can feel a high sense of presence. In addition, it is preferable to display different images in different areas of the display unit 8302 through the lens 8304. By viewing through 305, it is possible to perform a three-dimensional display using parallax. The present invention is not limited to a configuration in which one display unit 8302 is provided, but may be configured in such a way that two display units 8302 are provided and one of the display units is One display unit may be arranged for each eye.

[0296] Note that the display device of one embodiment of the present invention can be applied to the display portion 8302. A display device including the semiconductor device of one embodiment of the present invention has extremely high definition. Even if the image is magnified using the lens 8305, the pixels are not visible to the user, and the image is more This makes it possible to display images with a higher sense of reality.

[0297] The electronic device shown in FIG. 20A to FIG. 20G includes a housing 9000, a display portion 9001, a switch A speaker 9003, an operation key 9005 (including a power switch or an operation switch), a connection terminal Child 9006, sensor 9007 (force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, Light, liquid, magnetism, temperature, chemicals, sound, time, hardness, electric field, current, voltage, power, radiation, (including functions for measuring flow rate, humidity, gradient, vibration, odor, or infrared rays), 9008, etc.

[0298] The electronic devices shown in FIGS. 20A to 20G have various functions. Function to display various information (still images, videos, text images, etc.) on the display unit, touch panel function , calendar, date or time display functions, various software (programs) a function for controlling processing by a wireless communication function, a program recorded on a recording medium, or The electronic device can have the function of reading and processing data, etc. The electronic device may have a variety of functions, but is not limited to these. Also, a camera or the like may be provided in the electronic device to take still images or videos and store them on a recording medium (external It has the functions of storing the captured image on a memory card (built into the camera or the internal memory) and displaying the captured image on the display. It is okay to do so.

[0299] The electronic devices shown in FIGS. 20A to 20G will be described in detail below.

[0300] FIG. 20A is a perspective view showing a television device 9100. 100 is a display unit 9001 with a large screen, for example, 50 inches or more or 100 inches or more It is possible to incorporate.

[0301] FIG. 20B is a perspective view showing a portable information terminal 9101. For example, the mobile information terminal 9101 can be used as a smartphone. A speaker 9003, a connection terminal 9006, a sensor 9007, etc. may be provided. The terminal 9101 can display text and image information on multiple surfaces. In the example shown in FIG. 9, three icons 9050 are displayed. 051 can be displayed on another surface of the display unit 9001. , email, SNS message, phone call, etc., email and SNS message notifications The subject or sender name of the message, date and time, battery level, antenna reception strength, etc. Or, the icon 9050 is displayed at the position where the information 9051 is displayed. You may do so.

[0302] FIG. 20C is a perspective view showing a portable information terminal 9102. , and has a function of displaying information on three or more faces of the display unit 9001. An example in which information 9053 and information 9054 are displayed on different sides is shown. The person holds the mobile information terminal 9102 in the breast pocket of his / her clothes. The user can also check information 9053 displayed in a position that can be observed from above 2. The display can be checked without taking the mobile information terminal 9102 out of a pocket, and for example, a telephone call can be made. You can decide whether to accept it or not.

[0303] 20(D) is a perspective view showing a wristwatch-type portable information terminal 9200. The display unit 9001 can be used as a smart watch, for example. The display surface is curved, and the display can be performed along the curved display surface. In addition, the mobile information terminal 9200 can be made to communicate with, for example, a wireless headset. In addition, the mobile information terminal 9200 can also be connected to The terminal 9006 can be used to transmit data to and from other information terminals and can also be used for charging. The charging operation may be performed by wireless power supply.

[0304] 20(E), (F), and (G) are perspective views showing a foldable portable information terminal 9201. FIG. 20E shows the portable information terminal 9201 in an unfolded state, and FIG. 20G shows the portable information terminal 9201 in a folded state. Figure 20(F) shows the state where the two are changing from Figure 20(E) to Figure 20(G). The portable information terminal 9201 is highly portable when folded and is unfolded and is in a perspective view. When the display is turned on, the seamless, wide display area provides excellent visibility of the display. The display unit 9001 of the display device 9001 is made up of three housings 9000 connected by hinges 9055. For example, the display unit 9001 is curved with a radius of curvature of 1 mm or more and 150 mm or less. It can be done.

[0305] The electronic devices exemplified below include a display device according to one embodiment of the present invention in a display portion. Therefore, it is an electronic device that has achieved high resolution. Also, high resolution and large screen It is possible to provide an electronic device that is compatible with both.

[0306] The display unit of the electronic device according to one embodiment of the present invention may be a display device that supports, for example, full high definition, 4K2K, 8K4 It can display images with resolutions of 16K, 16K, 8K, or higher.

[0307] Examples of electronic devices include television sets, notebook personal computers, Equipped with relatively large screens such as monitor devices, digital signage, pachinko machines, and game machines In addition to electronic devices that can be used for personal computers, digital cameras, digital video cameras, digital photo frames, mobile phones, etc. Examples of the portable electronic device include mobile phones, portable game machines, portable information terminals, and audio playback devices.

[0308] The electronic device or lighting device to which one embodiment of the present invention is applied is installed on the inner or outer wall of a house or a building. The sensor can be installed along flat or curved surfaces of the interior or exterior of an automobile or the like.

[0309] FIG. 21A shows an example of a television device. A television device 7100 includes a housing 7 A display unit 7500 is built into the housing 7101. 101 is shown as a supported configuration.

[0310] The television device 7100 shown in FIG. 21A is operated by an operation switch provided in a housing 7101. This can be done by a separate remote control 7111 or a display unit 75 A touch panel is applied to the television device 7100, and the television device 7100 can be operated by touching the touch panel. The remote control operation device 7111 may have a display unit in addition to the operation buttons.

[0311] The television device 7100 may be a television broadcast receiver or a network connection device. The communication device may include:

[0312] FIG. 21B shows a notebook personal computer 7200. The mobile computer 7200 includes a housing 7211, a keyboard 7212, a pointing device, The display unit 7500 is assembled in the housing 7211. It is embedded in the

[0313] Figure 21 (C) and (D) show digital signage. An example of a sub-sign is shown below.

[0314] The digital signage 7300 shown in FIG. 21C includes a housing 7301, a display unit 7500, and a speaker 7303. In addition, LED lamps, operation keys (power switch, It may have a variety of functions, including a control switch, connection terminals, various sensors, a microphone, etc. Cut.

[0315] FIG. 21(D) shows a digital signage 740 attached to a cylindrical pillar 7401. The digital signage 7400 is a display unit provided along the curved surface of a pillar 7401. It has 7500.

[0316] The larger the display 7500, the more information can be provided at once, and the closer it is to the human eye. Since it is easy to attach to the skin, it has the effect of increasing the effectiveness of advertising, for example.

[0317] It is preferable that a touch panel be applied to the display unit 7500 so that a user can operate it. This will enable the use of the information not only for advertising purposes, but also for route information, traffic information, and commercial facility guidance information. It can also be used to provide users with information they are looking for.

[0318] Also, as shown in FIG. 21(C) and (D), the digital signage 7300 or the digital The signage 7400 is connected wirelessly to an information terminal 7311 such as a smartphone carried by a user. For example, the advertisement displayed on the display unit 7500 may be The information is displayed on the screen of the information terminal 7311, and the information terminal 7311 is operated. In this way, the display on the display unit 7500 can be switched.

[0319] In addition, the Digital Signage 7300 or Digital Signage 7400 can be equipped with an information terminal. It is also possible to run games using the 7311 as an operating means (controller). This allows an unspecified number of users to participate in and enjoy the game at the same time.

[0320] The display device of one embodiment of the present invention is applied to the display portion 7500 in FIGS. It is possible.

[0321] Although the electronic device of the present embodiment has a display unit, the present invention can be applied to electronic devices that do not have a display unit. One embodiment of the present invention can also be applied to the above-mentioned semiconductor device.

[0322] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination. [Explanation of symbols]

[0323] 100, 100A: transistor, 102: substrate, 103, 104, 110, 116, 1 18: insulating layer, 106, 112, 120a, 120b, 131: conductive layer, 108: semiconductor layer, 108n: region, 110f: insulating film, 114: metal oxide layer, 114f: metal oxide Membrane, 130: Display area, 141a, 141b, 142: Opening

Claims

1. a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, a semiconductor layer, and a first conductive layer; the second insulating layer is located on the first insulating layer; the semiconductor layer is located on the second insulating layer and has an island shape; the third insulating layer and the first conductive layer are stacked on the semiconductor layer, the second insulating layer has an island shape having an end portion on the outer side of a region overlapping with the semiconductor layer, the fourth insulating layer covers the second insulating layer, the semiconductor layer, the third insulating layer, and the first conductive layer, contacts a part of an upper surface of the semiconductor layer, and contacts the first insulating layer on an outer side of the end of the second insulating layer; the semiconductor layer comprises a metal oxide; the second insulating layer and the third insulating layer include an oxide; the first insulating layer comprises a metal oxide or a metal nitride; the fourth insulating layer includes a metal nitride; Semiconductor device.

2. In claim 1, the fourth insulating layer includes aluminum; Semiconductor device.

3. In claim 1 or 2, The first insulating layer comprises at least one of aluminum and hafnium, and oxygen. Semiconductor device.

4. In any one of claims 1 to 3, The second insulating layer and the semiconductor layer have substantially the same top surface shape. Semiconductor device.

5. In any one of claims 1 to 4, the second insulating layer has a portion located outside a region where the end portion overlaps with the first conductive layer; Semiconductor device.

6. In any one of claims 1 to 4, the second insulating layer has a portion located in a region where the end overlaps with the first conductive layer; Semiconductor device.

7. In any one of claims 1 to 6, a second conductive layer below the first insulating layer; the second conductive layer has an area overlapping both the semiconductor layer and the first conductive layer; Semiconductor device.

8. In claim 7, the second insulating layer has a portion located outside a region where the end portion overlaps with the second conductive layer; Semiconductor device.

9. In claim 7, the second insulating layer has a portion located in a region where the end overlaps with the second conductive layer; Semiconductor device.

Images